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OMAP4: DSS2: HDMI: Move HDMI IP independent generic header
[deliverable/linux.git] / drivers / video / omap2 / dss / dss.h
CommitLineData
559d6701
TV		 1/*
2 * linux/drivers/video/omap2/dss/dss.h
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#ifndef __OMAP2_DSS_H
24#define __OMAP2_DSS_H
25
26#ifdef CONFIG_OMAP2_DSS_DEBUG_SUPPORT
27#define DEBUG
28#endif
29
30#ifdef DEBUG
31extern unsigned int dss_debug;
32#ifdef DSS_SUBSYS_NAME
33#define DSSDBG(format, ...) \
34 if (dss_debug) \
35 printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME ": " format, \
36 ## __VA_ARGS__)
37#else
38#define DSSDBG(format, ...) \
39 if (dss_debug) \
40 printk(KERN_DEBUG "omapdss: " format, ## __VA_ARGS__)
41#endif
42
43#ifdef DSS_SUBSYS_NAME
44#define DSSDBGF(format, ...) \
45 if (dss_debug) \
46 printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME \
47 ": %s(" format ")\n", \
48 __func__, \
49 ## __VA_ARGS__)
50#else
51#define DSSDBGF(format, ...) \
52 if (dss_debug) \
53 printk(KERN_DEBUG "omapdss: " \
54 ": %s(" format ")\n", \
55 __func__, \
56 ## __VA_ARGS__)
57#endif
58
59#else /* DEBUG */
60#define DSSDBG(format, ...)
61#define DSSDBGF(format, ...)
62#endif
63
64
65#ifdef DSS_SUBSYS_NAME
66#define DSSERR(format, ...) \
67 printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
68 ## __VA_ARGS__)
69#else
70#define DSSERR(format, ...) \
71 printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
72#endif
73
74#ifdef DSS_SUBSYS_NAME
75#define DSSINFO(format, ...) \
76 printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
77 ## __VA_ARGS__)
78#else
79#define DSSINFO(format, ...) \
80 printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
81#endif
82
83#ifdef DSS_SUBSYS_NAME
84#define DSSWARN(format, ...) \
85 printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
86 ## __VA_ARGS__)
87#else
88#define DSSWARN(format, ...) \
89 printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
90#endif
91
92/* OMAP TRM gives bitfields as start:end, where start is the higher bit
93 number. For example 7:0 */
94#define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
95#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
96#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
97#define FLD_MOD(orig, val, start, end) \
98 (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
99
569969d6
AT		 100enum dss_io_pad_mode {
101 DSS_IO_PAD_MODE_RESET,
102 DSS_IO_PAD_MODE_RFBI,
103 DSS_IO_PAD_MODE_BYPASS,
559d6701
TV		 104};
105
7ed024aa
M		 106enum dss_hdmi_venc_clk_source_select {
107 DSS_VENC_TV_CLK = 0,
108 DSS_HDMI_M_PCLK = 1,
109};
110
6ff8aa31
AT		 111enum dss_dsi_content_type {
112 DSS_DSI_CONTENT_DCS,
113 DSS_DSI_CONTENT_GENERIC,
114};
115
559d6701
TV		 116struct dss_clock_info {
117 /* rates that we get with dividers below */
118 unsigned long fck;
119
120 /* dividers */
121 u16 fck_div;
122};
123
124struct dispc_clock_info {
125 /* rates that we get with dividers below */
126 unsigned long lck;
127 unsigned long pck;
128
129 /* dividers */
130 u16 lck_div;
131 u16 pck_div;
132};
133
134struct dsi_clock_info {
135 /* rates that we get with dividers below */
136 unsigned long fint;
137 unsigned long clkin4ddr;
138 unsigned long clkin;
ea75159e
TA		 139 unsigned long dsi_pll_hsdiv_dispc_clk; /* OMAP3: DSI1_PLL_CLK
140 * OMAP4: PLLx_CLK1 */
141 unsigned long dsi_pll_hsdiv_dsi_clk; /* OMAP3: DSI2_PLL_CLK
142 * OMAP4: PLLx_CLK2 */
559d6701
TV		 143 unsigned long lp_clk;
144
145 /* dividers */
146 u16 regn;
147 u16 regm;
ea75159e
TA		 148 u16 regm_dispc; /* OMAP3: REGM3
149 * OMAP4: REGM4 */
150 u16 regm_dsi; /* OMAP3: REGM4
151 * OMAP4: REGM5 */
559d6701
TV		 152 u16 lp_clk_div;
153
154 u8 highfreq;
1bb47835 155 bool use_sys_clk;
559d6701
TV		 156};
157
158struct seq_file;
159struct platform_device;
160
161/* core */
559d6701 162struct bus_type *dss_get_bus(void);
8a2cfea8
TV		 163struct regulator *dss_get_vdds_dsi(void);
164struct regulator *dss_get_vdds_sdi(void);
559d6701
TV		 165
166/* display */
167int dss_suspend_all_devices(void);
168int dss_resume_all_devices(void);
169void dss_disable_all_devices(void);
170
171void dss_init_device(struct platform_device *pdev,
172 struct omap_dss_device *dssdev);
173void dss_uninit_device(struct platform_device *pdev,
174 struct omap_dss_device *dssdev);
175bool dss_use_replication(struct omap_dss_device *dssdev,
176 enum omap_color_mode mode);
177void default_get_overlay_fifo_thresholds(enum omap_plane plane,
5ed8cf5b 178 u32 fifo_size, u32 burst_size,
559d6701
TV		 179 u32 *fifo_low, u32 *fifo_high);
180
181/* manager */
182int dss_init_overlay_managers(struct platform_device *pdev);
183void dss_uninit_overlay_managers(struct platform_device *pdev);
184int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl);
185void dss_setup_partial_planes(struct omap_dss_device *dssdev,
26a8c250
TV		 186 u16 *x, u16 *y, u16 *w, u16 *h,
187 bool enlarge_update_area);
559d6701
TV		 188void dss_start_update(struct omap_dss_device *dssdev);
189
190/* overlay */
191void dss_init_overlays(struct platform_device *pdev);
192void dss_uninit_overlays(struct platform_device *pdev);
193int dss_check_overlay(struct omap_overlay *ovl, struct omap_dss_device *dssdev);
194void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
195#ifdef L4_EXAMPLE
196void dss_overlay_setup_l4_manager(struct omap_overlay_manager *mgr);
197#endif
198void dss_recheck_connections(struct omap_dss_device *dssdev, bool force);
199
200/* DSS */
96c401bc
SG		 201int dss_init_platform_driver(void);
202void dss_uninit_platform_driver(void);
559d6701 203
4fbafaf3
TV		 204int dss_runtime_get(void);
205void dss_runtime_put(void);
206
7ed024aa 207void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
89a35e51 208const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
8b9cb3a8 209void dss_dump_clocks(struct seq_file *s);
559d6701
TV		 210
211void dss_dump_regs(struct seq_file *s);
8b9cb3a8
SG		 212#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
213void dss_debug_dump_clocks(struct seq_file *s);
214#endif
559d6701
TV		 215
216void dss_sdi_init(u8 datapairs);
217int dss_sdi_enable(void);
218void dss_sdi_disable(void);
219
89a35e51 220void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src);
5a8b572d
AT		 221void dss_select_dsi_clk_source(int dsi_module,
222 enum omap_dss_clk_source clk_src);
ea75159e 223void dss_select_lcd_clk_source(enum omap_channel channel,
89a35e51
AT		 224 enum omap_dss_clk_source clk_src);
225enum omap_dss_clk_source dss_get_dispc_clk_source(void);
5a8b572d 226enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module);
89a35e51 227enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
2f18c4d8 228
559d6701
TV		 229void dss_set_venc_output(enum omap_dss_venc_type type);
230void dss_set_dac_pwrdn_bgz(bool enable);
231
232unsigned long dss_get_dpll4_rate(void);
233int dss_calc_clock_rates(struct dss_clock_info *cinfo);
234int dss_set_clock_div(struct dss_clock_info *cinfo);
235int dss_get_clock_div(struct dss_clock_info *cinfo);
236int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
237 struct dss_clock_info *dss_cinfo,
238 struct dispc_clock_info *dispc_cinfo);
239
240/* SDI */
368a148e 241#ifdef CONFIG_OMAP2_DSS_SDI
42c9dee8 242int sdi_init(void);
559d6701
TV		 243void sdi_exit(void);
244int sdi_init_display(struct omap_dss_device *display);
368a148e 245#else
42c9dee8 246static inline int sdi_init(void)
368a148e
JN		 247{
248 return 0;
249}
250static inline void sdi_exit(void)
251{
252}
253#endif
559d6701
TV		 254
255/* DSI */
368a148e 256#ifdef CONFIG_OMAP2_DSS_DSI
5a8b572d
AT		 257
258struct dentry;
259struct file_operations;
260
c8aac01b
SG		 261int dsi_init_platform_driver(void);
262void dsi_uninit_platform_driver(void);
559d6701 263
4fbafaf3
TV		 264int dsi_runtime_get(struct platform_device *dsidev);
265void dsi_runtime_put(struct platform_device *dsidev);
266
559d6701 267void dsi_dump_clocks(struct seq_file *s);
5a8b572d
AT		 268void dsi_create_debugfs_files_irq(struct dentry *debugfs_dir,
269 const struct file_operations *debug_fops);
270void dsi_create_debugfs_files_reg(struct dentry *debugfs_dir,
271 const struct file_operations *debug_fops);
559d6701 272
559d6701
TV		 273int dsi_init_display(struct omap_dss_device *display);
274void dsi_irq_handler(void);
a3b3cc2b
AT		 275u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt);
276
a72b64b9
AT		 277unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev);
278int dsi_pll_set_clock_div(struct platform_device *dsidev,
279 struct dsi_clock_info *cinfo);
280int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft,
281 unsigned long req_pck, struct dsi_clock_info *cinfo,
559d6701 282 struct dispc_clock_info *dispc_cinfo);
a72b64b9
AT		 283int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
284 bool enable_hsdiv);
285void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes);
559d6701 286void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
5ed8cf5b 287 u32 fifo_size, u32 burst_size,
559d6701 288 u32 *fifo_low, u32 *fifo_high);
a72b64b9
AT		 289void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev);
290void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev);
291struct platform_device *dsi_get_dsidev_from_id(int module);
368a148e 292#else
c8aac01b 293static inline int dsi_init_platform_driver(void)
368a148e
JN		 294{
295 return 0;
296}
c8aac01b 297static inline void dsi_uninit_platform_driver(void)
368a148e
JN		 298{
299}
4fbafaf3
TV		 300static inline int dsi_runtime_get(struct platform_device *dsidev)
301{
302 return 0;
303}
304static inline void dsi_runtime_put(struct platform_device *dsidev)
305{
306}
a3b3cc2b
AT		 307static inline u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
308{
309 WARN("%s: DSI not compiled in, returning pixel_size as 0\n", __func__);
310 return 0;
311}
a72b64b9 312static inline unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
66534e8e
TA		 313{
314 WARN("%s: DSI not compiled in, returning rate as 0\n", __func__);
315 return 0;
316}
943e4457
TV		 317static inline int dsi_pll_set_clock_div(struct platform_device *dsidev,
318 struct dsi_clock_info *cinfo)
319{
320 WARN("%s: DSI not compiled in\n", __func__);
321 return -ENODEV;
322}
323static inline int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev,
324 bool is_tft, unsigned long req_pck,
325 struct dsi_clock_info *dsi_cinfo,
326 struct dispc_clock_info *dispc_cinfo)
327{
328 WARN("%s: DSI not compiled in\n", __func__);
329 return -ENODEV;
330}
331static inline int dsi_pll_init(struct platform_device *dsidev,
332 bool enable_hsclk, bool enable_hsdiv)
333{
334 WARN("%s: DSI not compiled in\n", __func__);
335 return -ENODEV;
336}
337static inline void dsi_pll_uninit(struct platform_device *dsidev,
338 bool disconnect_lanes)
339{
340}
a72b64b9 341static inline void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
e406f907
TV		 342{
343}
a72b64b9 344static inline void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
e406f907
TV		 345{
346}
a72b64b9
AT		 347static inline struct platform_device *dsi_get_dsidev_from_id(int module)
348{
349 WARN("%s: DSI not compiled in, returning platform device as NULL\n",
350 __func__);
351 return NULL;
352}
368a148e 353#endif
559d6701
TV		 354
355/* DPI */
368a148e 356#ifdef CONFIG_OMAP2_DSS_DPI
277b2881 357int dpi_init(void);
559d6701
TV		 358void dpi_exit(void);
359int dpi_init_display(struct omap_dss_device *dssdev);
368a148e 360#else
277b2881 361static inline int dpi_init(void)
368a148e
JN		 362{
363 return 0;
364}
365static inline void dpi_exit(void)
366{
367}
368#endif
559d6701
TV		 369
370/* DISPC */
060b6d9c
SG		 371int dispc_init_platform_driver(void);
372void dispc_uninit_platform_driver(void);
559d6701 373void dispc_dump_clocks(struct seq_file *s);
dfc0fd8d 374void dispc_dump_irqs(struct seq_file *s);
559d6701
TV		 375void dispc_dump_regs(struct seq_file *s);
376void dispc_irq_handler(void);
377void dispc_fake_vsync_irq(void);
378
4fbafaf3
TV		 379int dispc_runtime_get(void);
380void dispc_runtime_put(void);
559d6701
TV		 381
382void dispc_enable_sidle(void);
383void dispc_disable_sidle(void);
384
385void dispc_lcd_enable_signal_polarity(bool act_high);
386void dispc_lcd_enable_signal(bool enable);
387void dispc_pck_free_enable(bool enable);
559d6701 388void dispc_set_digit_size(u16 width, u16 height);
cd295aeb
TV		 389void dispc_enable_fifomerge(bool enable);
390void dispc_enable_gamma_table(bool enable);
391void dispc_set_loadmode(enum omap_dss_load_mode mode);
392
393bool dispc_lcd_timings_ok(struct omap_video_timings *timings);
394unsigned long dispc_fclk_rate(void);
395void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
396 struct dispc_clock_info *cinfo);
397int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
398 struct dispc_clock_info *cinfo);
399
400
f0e5caab
TV		 401u32 dispc_ovl_get_fifo_size(enum omap_plane plane);
402void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
f0e5caab 403u32 dispc_ovl_get_burst_size(enum omap_plane plane);
f0e5caab 404int dispc_ovl_setup(enum omap_plane plane,
559d6701
TV		 405 u32 paddr, u16 screen_width,
406 u16 pos_x, u16 pos_y,
407 u16 width, u16 height,
408 u16 out_width, u16 out_height,
409 enum omap_color_mode color_mode,
410 bool ilace,
411 enum omap_dss_rotation_type rotation_type,
412 u8 rotation, bool mirror,
18faa1b6 413 u8 global_alpha, u8 pre_mult_alpha,
0d66cbb5
AJ		 414 enum omap_channel channel,
415 u32 puv_addr);
cd295aeb
TV		 416int dispc_ovl_enable(enum omap_plane plane, bool enable);
417void dispc_ovl_enable_replication(enum omap_plane plane, bool enable);
559d6701 418
cd295aeb
TV		 419
420void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable);
421void dispc_mgr_set_lcd_size(enum omap_channel channel, u16 width, u16 height);
422void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable);
423void dispc_mgr_set_cpr_coef(enum omap_channel channel,
424 struct omap_dss_cpr_coefs *coefs);
26d9dd0d
TV		 425bool dispc_mgr_go_busy(enum omap_channel channel);
426void dispc_mgr_go(enum omap_channel channel);
427void dispc_mgr_enable(enum omap_channel channel, bool enable);
428bool dispc_mgr_is_channel_enabled(enum omap_channel channel);
569969d6
AT		 429void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode);
430void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable);
26d9dd0d
TV		 431void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines);
432void dispc_mgr_set_lcd_display_type(enum omap_channel channel,
64ba4f74 433 enum omap_lcd_display_type type);
26d9dd0d
TV		 434void dispc_mgr_set_default_color(enum omap_channel channel, u32 color);
435u32 dispc_mgr_get_default_color(enum omap_channel channel);
436void dispc_mgr_set_trans_key(enum omap_channel ch,
559d6701
TV		 437 enum omap_dss_trans_key_type type,
438 u32 trans_key);
26d9dd0d 439void dispc_mgr_get_trans_key(enum omap_channel ch,
559d6701
TV		 440 enum omap_dss_trans_key_type *type,
441 u32 *trans_key);
26d9dd0d
TV		 442void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable);
443void dispc_mgr_enable_alpha_blending(enum omap_channel ch, bool enable);
444bool dispc_mgr_trans_key_enabled(enum omap_channel ch);
445bool dispc_mgr_alpha_blending_enabled(enum omap_channel ch);
26d9dd0d 446void dispc_mgr_set_lcd_timings(enum omap_channel channel,
64ba4f74 447 struct omap_video_timings *timings);
26d9dd0d 448void dispc_mgr_set_pol_freq(enum omap_channel channel,
ff1b2cde 449 enum omap_panel_config config, u8 acbi, u8 acb);
cd295aeb
TV		 450unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
451unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
26d9dd0d 452int dispc_mgr_set_clock_div(enum omap_channel channel,
ff1b2cde 453 struct dispc_clock_info *cinfo);
26d9dd0d 454int dispc_mgr_get_clock_div(enum omap_channel channel,
ff1b2cde 455 struct dispc_clock_info *cinfo);
559d6701 456
559d6701 457/* VENC */
368a148e 458#ifdef CONFIG_OMAP2_DSS_VENC
30ea50c9
SG		 459int venc_init_platform_driver(void);
460void venc_uninit_platform_driver(void);
559d6701
TV		 461void venc_dump_regs(struct seq_file *s);
462int venc_init_display(struct omap_dss_device *display);
368a148e 463#else
30ea50c9 464static inline int venc_init_platform_driver(void)
368a148e
JN		 465{
466 return 0;
467}
30ea50c9 468static inline void venc_uninit_platform_driver(void)
368a148e
JN		 469{
470}
471#endif
559d6701 472
c3198a5e
M		 473/* HDMI */
474#ifdef CONFIG_OMAP4_DSS_HDMI
475int hdmi_init_platform_driver(void);
476void hdmi_uninit_platform_driver(void);
477int hdmi_init_display(struct omap_dss_device *dssdev);
478#else
479static inline int hdmi_init_display(struct omap_dss_device *dssdev)
480{
481 return 0;
482}
483static inline int hdmi_init_platform_driver(void)
484{
485 return 0;
486}
487static inline void hdmi_uninit_platform_driver(void)
488{
489}
490#endif
491int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev);
492void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev);
493void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev);
494int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
495 struct omap_video_timings *timings);
70be8323
M		 496int hdmi_panel_init(void);
497void hdmi_panel_exit(void);
c3198a5e 498
559d6701 499/* RFBI */
368a148e 500#ifdef CONFIG_OMAP2_DSS_RFBI
3448d500
SG		 501int rfbi_init_platform_driver(void);
502void rfbi_uninit_platform_driver(void);
559d6701 503void rfbi_dump_regs(struct seq_file *s);
559d6701 504int rfbi_init_display(struct omap_dss_device *display);
368a148e 505#else
3448d500 506static inline int rfbi_init_platform_driver(void)
368a148e
JN		 507{
508 return 0;
509}
3448d500 510static inline void rfbi_uninit_platform_driver(void)
368a148e
JN		 511{
512}
513#endif
559d6701 514
dfc0fd8d
TV		 515
516#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
517static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
518{
519 int b;
520 for (b = 0; b < 32; ++b) {
521 if (irqstatus & (1 << b))
522 irq_arr[b]++;
523 }
524}
525#endif
526
559d6701 527#endif
Linux kernel - Deliverables
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