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OMAPDSS: clean up the omapdss platform data mess
[deliverable/linux.git] / drivers / video / omap2 / dss / hdmi.c
CommitLineData
c3198a5e
M		 1/*
2 * hdmi.c
3 *
4 * HDMI interface DSS driver setting for TI's OMAP4 family of processor.
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
6 * Authors: Yong Zhi
7 * Mythri pk <mythripk@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#define DSS_SUBSYS_NAME "HDMI"
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/err.h>
27#include <linux/io.h>
28#include <linux/interrupt.h>
29#include <linux/mutex.h>
30#include <linux/delay.h>
31#include <linux/string.h>
24e6289c 32#include <linux/platform_device.h>
4fbafaf3
TV		 33#include <linux/pm_runtime.h>
34#include <linux/clk.h>
a0b38cc4 35#include <video/omapdss.h>
ad44cc32
RN		 36#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
37 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
38#include <sound/soc.h>
39#include <sound/pcm_params.h>
7334167b 40#include "ti_hdmi_4xxx_ip.h"
ad44cc32 41#endif
c3198a5e 42
94c52987 43#include "ti_hdmi.h"
c3198a5e 44#include "dss.h"
ad44cc32 45#include "dss_features.h"
c3198a5e 46
95a8aeb6
M		 47#define HDMI_WP 0x0
48#define HDMI_CORE_SYS 0x400
49#define HDMI_CORE_AV 0x900
50#define HDMI_PLLCTRL 0x200
51#define HDMI_PHY 0x300
52
7c1f1eca
M		 53/* HDMI EDID Length move this */
54#define HDMI_EDID_MAX_LENGTH 256
55#define EDID_TIMING_DESCRIPTOR_SIZE 0x12
56#define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36
57#define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80
58#define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4
59#define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4
60
b44e4582 61#define HDMI_DEFAULT_REGN 16
8d88767a
TV		 62#define HDMI_DEFAULT_REGM2 1
63
c3198a5e
M		 64static struct {
65 struct mutex lock;
c3198a5e 66 struct platform_device *pdev;
95a8aeb6 67 struct hdmi_ip_data ip_data;
4fbafaf3
TV		 68
69 struct clk *sys_clk;
c3198a5e
M		 70} hdmi;
71
72/*
73 * Logic for the below structure :
74 * user enters the CEA or VESA timings by specifying the HDMI/DVI code.
75 * There is a correspondence between CEA/VESA timing and code, please
76 * refer to section 6.3 in HDMI 1.3 specification for timing code.
77 *
78 * In the below structure, cea_vesa_timings corresponds to all OMAP4
79 * supported CEA and VESA timing values.code_cea corresponds to the CEA
80 * code, It is used to get the timing from cea_vesa_timing array.Similarly
81 * with code_vesa. Code_index is used for back mapping, that is once EDID
82 * is read from the TV, EDID is parsed to find the timing values and then
83 * map it to corresponding CEA or VESA index.
84 */
85
46095b2d 86static const struct hdmi_config cea_timings[] = {
a05ce78f
M		 87{ {640, 480, 25200, 96, 16, 48, 2, 10, 33, 0, 0, 0}, {1, HDMI_HDMI} },
88{ {720, 480, 27027, 62, 16, 60, 6, 9, 30, 0, 0, 0}, {2, HDMI_HDMI} },
89{ {1280, 720, 74250, 40, 110, 220, 5, 5, 20, 1, 1, 0}, {4, HDMI_HDMI} },
90{ {1920, 540, 74250, 44, 88, 148, 5, 2, 15, 1, 1, 1}, {5, HDMI_HDMI} },
91{ {1440, 240, 27027, 124, 38, 114, 3, 4, 15, 0, 0, 1}, {6, HDMI_HDMI} },
92{ {1920, 1080, 148500, 44, 88, 148, 5, 4, 36, 1, 1, 0}, {16, HDMI_HDMI} },
93{ {720, 576, 27000, 64, 12, 68, 5, 5, 39, 0, 0, 0}, {17, HDMI_HDMI} },
94{ {1280, 720, 74250, 40, 440, 220, 5, 5, 20, 1, 1, 0}, {19, HDMI_HDMI} },
95{ {1920, 540, 74250, 44, 528, 148, 5, 2, 15, 1, 1, 1}, {20, HDMI_HDMI} },
96{ {1440, 288, 27000, 126, 24, 138, 3, 2, 19, 0, 0, 1}, {21, HDMI_HDMI} },
97{ {1440, 576, 54000, 128, 24, 136, 5, 5, 39, 0, 0, 0}, {29, HDMI_HDMI} },
98{ {1920, 1080, 148500, 44, 528, 148, 5, 4, 36, 1, 1, 0}, {31, HDMI_HDMI} },
99{ {1920, 1080, 74250, 44, 638, 148, 5, 4, 36, 1, 1, 0}, {32, HDMI_HDMI} },
100{ {2880, 480, 108108, 248, 64, 240, 6, 9, 30, 0, 0, 0}, {35, HDMI_HDMI} },
101{ {2880, 576, 108000, 256, 48, 272, 5, 5, 39, 0, 0, 0}, {37, HDMI_HDMI} },
46095b2d
M		 102};
103static const struct hdmi_config vesa_timings[] = {
a05ce78f
M		 104/* VESA From Here */
105{ {640, 480, 25175, 96, 16, 48, 2 , 11, 31, 0, 0, 0}, {4, HDMI_DVI} },
106{ {800, 600, 40000, 128, 40, 88, 4 , 1, 23, 1, 1, 0}, {9, HDMI_DVI} },
107{ {848, 480, 33750, 112, 16, 112, 8 , 6, 23, 1, 1, 0}, {0xE, HDMI_DVI} },
108{ {1280, 768, 79500, 128, 64, 192, 7 , 3, 20, 1, 0, 0}, {0x17, HDMI_DVI} },
109{ {1280, 800, 83500, 128, 72, 200, 6 , 3, 22, 1, 0, 0}, {0x1C, HDMI_DVI} },
110{ {1360, 768, 85500, 112, 64, 256, 6 , 3, 18, 1, 1, 0}, {0x27, HDMI_DVI} },
111{ {1280, 960, 108000, 112, 96, 312, 3 , 1, 36, 1, 1, 0}, {0x20, HDMI_DVI} },
112{ {1280, 1024, 108000, 112, 48, 248, 3 , 1, 38, 1, 1, 0}, {0x23, HDMI_DVI} },
113{ {1024, 768, 65000, 136, 24, 160, 6, 3, 29, 0, 0, 0}, {0x10, HDMI_DVI} },
114{ {1400, 1050, 121750, 144, 88, 232, 4, 3, 32, 1, 0, 0}, {0x2A, HDMI_DVI} },
115{ {1440, 900, 106500, 152, 80, 232, 6, 3, 25, 1, 0, 0}, {0x2F, HDMI_DVI} },
116{ {1680, 1050, 146250, 176 , 104, 280, 6, 3, 30, 1, 0, 0}, {0x3A, HDMI_DVI} },
117{ {1366, 768, 85500, 143, 70, 213, 3, 3, 24, 1, 1, 0}, {0x51, HDMI_DVI} },
118{ {1920, 1080, 148500, 44, 148, 80, 5, 4, 36, 1, 1, 0}, {0x52, HDMI_DVI} },
119{ {1280, 768, 68250, 32, 48, 80, 7, 3, 12, 0, 1, 0}, {0x16, HDMI_DVI} },
120{ {1400, 1050, 101000, 32, 48, 80, 4, 3, 23, 0, 1, 0}, {0x29, HDMI_DVI} },
121{ {1680, 1050, 119000, 32, 48, 80, 6, 3, 21, 0, 1, 0}, {0x39, HDMI_DVI} },
122{ {1280, 800, 79500, 32, 48, 80, 6, 3, 14, 0, 1, 0}, {0x1B, HDMI_DVI} },
123{ {1280, 720, 74250, 40, 110, 220, 5, 5, 20, 1, 1, 0}, {0x55, HDMI_DVI} }
c3198a5e
M		 124};
125
4fbafaf3
TV		 126static int hdmi_runtime_get(void)
127{
128 int r;
129
130 DSSDBG("hdmi_runtime_get\n");
131
a247ce78
AT		 132 /*
133 * HACK: Add dss_runtime_get() to ensure DSS clock domain is enabled.
134 * This should be removed later.
135 */
136 r = dss_runtime_get();
137 if (r < 0)
138 goto err_get_dss;
139
4fbafaf3
TV		 140 r = pm_runtime_get_sync(&hdmi.pdev->dev);
141 WARN_ON(r < 0);
a247ce78
AT		 142 if (r < 0)
143 goto err_get_hdmi;
144
145 return 0;
146
147err_get_hdmi:
148 dss_runtime_put();
149err_get_dss:
150 return r;
4fbafaf3
TV		 151}
152
153static void hdmi_runtime_put(void)
154{
155 int r;
156
157 DSSDBG("hdmi_runtime_put\n");
158
0eaf9f52 159 r = pm_runtime_put_sync(&hdmi.pdev->dev);
4fbafaf3 160 WARN_ON(r < 0);
a247ce78
AT		 161
162 /*
163 * HACK: This is added to complement the dss_runtime_get() call in
164 * hdmi_runtime_get(). This should be removed later.
165 */
166 dss_runtime_put();
4fbafaf3
TV		 167}
168
c3198a5e
M		 169int hdmi_init_display(struct omap_dss_device *dssdev)
170{
171 DSSDBG("init_display\n");
172
60634a28 173 dss_init_hdmi_ip_ops(&hdmi.ip_data);
c3198a5e
M		 174 return 0;
175}
176
46095b2d
M		 177static const struct hdmi_config *hdmi_find_timing(
178 const struct hdmi_config *timings_arr,
179 int len)
c3198a5e 180{
46095b2d 181 int i;
c3198a5e 182
46095b2d 183 for (i = 0; i < len; i++) {
9e4ed603 184 if (timings_arr[i].cm.code == hdmi.ip_data.cfg.cm.code)
46095b2d
M		 185 return &timings_arr[i];
186 }
187 return NULL;
188}
c3198a5e 189
46095b2d
M		 190static const struct hdmi_config *hdmi_get_timings(void)
191{
192 const struct hdmi_config *arr;
193 int len;
194
9e4ed603 195 if (hdmi.ip_data.cfg.cm.mode == HDMI_DVI) {
46095b2d
M		 196 arr = vesa_timings;
197 len = ARRAY_SIZE(vesa_timings);
198 } else {
199 arr = cea_timings;
200 len = ARRAY_SIZE(cea_timings);
201 }
202
203 return hdmi_find_timing(arr, len);
204}
205
206static bool hdmi_timings_compare(struct omap_video_timings *timing1,
207 const struct hdmi_video_timings *timing2)
208{
209 int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync;
210
211 if ((timing2->pixel_clock == timing1->pixel_clock) &&
212 (timing2->x_res == timing1->x_res) &&
213 (timing2->y_res == timing1->y_res)) {
c3198a5e 214
46095b2d
M		 215 timing2_hsync = timing2->hfp + timing2->hsw + timing2->hbp;
216 timing1_hsync = timing1->hfp + timing1->hsw + timing1->hbp;
217 timing2_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
218 timing1_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
219
220 DSSDBG("timing1_hsync = %d timing1_vsync = %d"\
221 "timing2_hsync = %d timing2_vsync = %d\n",
222 timing1_hsync, timing1_vsync,
223 timing2_hsync, timing2_vsync);
224
225 if ((timing1_hsync == timing2_hsync) &&
226 (timing1_vsync == timing2_vsync)) {
227 return true;
228 }
c3198a5e 229 }
46095b2d 230 return false;
c3198a5e
M		 231}
232
233static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing)
234{
46095b2d 235 int i;
c3198a5e
M		 236 struct hdmi_cm cm = {-1};
237 DSSDBG("hdmi_get_code\n");
238
46095b2d
M		 239 for (i = 0; i < ARRAY_SIZE(cea_timings); i++) {
240 if (hdmi_timings_compare(timing, &cea_timings[i].timings)) {
241 cm = cea_timings[i].cm;
242 goto end;
243 }
244 }
245 for (i = 0; i < ARRAY_SIZE(vesa_timings); i++) {
246 if (hdmi_timings_compare(timing, &vesa_timings[i].timings)) {
247 cm = vesa_timings[i].cm;
248 goto end;
c3198a5e
M		 249 }
250 }
251
46095b2d 252end: return cm;
c3198a5e 253
c3198a5e
M		 254}
255
c3dc6a7a
AT		 256unsigned long hdmi_get_pixel_clock(void)
257{
258 /* HDMI Pixel Clock in Mhz */
a05ce78f 259 return hdmi.ip_data.cfg.timings.pixel_clock * 1000;
c3dc6a7a
AT		 260}
261
6cb07b25
AT		 262static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
263 struct hdmi_pll_info *pi)
c3198a5e 264{
6cb07b25 265 unsigned long clkin, refclk;
c3198a5e
M		 266 u32 mf;
267
4fbafaf3 268 clkin = clk_get_rate(hdmi.sys_clk) / 10000;
c3198a5e
M		 269 /*
270 * Input clock is predivided by N + 1
271 * out put of which is reference clk
272 */
8d88767a
TV		 273 if (dssdev->clocks.hdmi.regn == 0)
274 pi->regn = HDMI_DEFAULT_REGN;
275 else
276 pi->regn = dssdev->clocks.hdmi.regn;
277
b44e4582 278 refclk = clkin / pi->regn;
c3198a5e 279
8d88767a
TV		 280 if (dssdev->clocks.hdmi.regm2 == 0)
281 pi->regm2 = HDMI_DEFAULT_REGM2;
282 else
283 pi->regm2 = dssdev->clocks.hdmi.regm2;
c3198a5e 284
dd2116a3
M		 285 /*
286 * multiplier is pixel_clk/ref_clk
287 * Multiplying by 100 to avoid fractional part removal
288 */
289 pi->regm = phy * pi->regm2 / refclk;
290
c3198a5e
M		 291 /*
292 * fractional multiplier is remainder of the difference between
293 * multiplier and actual phy(required pixel clock thus should be
294 * multiplied by 2^18(262144) divided by the reference clock
295 */
dd2116a3
M		 296 mf = (phy - pi->regm / pi->regm2 * refclk) * 262144;
297 pi->regmf = pi->regm2 * mf / refclk;
c3198a5e
M		 298
299 /*
300 * Dcofreq should be set to 1 if required pixel clock
301 * is greater than 1000MHz
302 */
303 pi->dcofreq = phy > 1000 * 100;
b44e4582 304 pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10;
c3198a5e 305
7b27da54
M		 306 /* Set the reference clock to sysclk reference */
307 pi->refsel = HDMI_REFSEL_SYSCLK;
308
c3198a5e
M		 309 DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
310 DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
311}
312
c3198a5e
M		 313static int hdmi_power_on(struct omap_dss_device *dssdev)
314{
46095b2d
M		 315 int r;
316 const struct hdmi_config *timing;
c3198a5e 317 struct omap_video_timings *p;
6cb07b25 318 unsigned long phy;
c3198a5e 319
4fbafaf3
TV		 320 r = hdmi_runtime_get();
321 if (r)
322 return r;
c3198a5e 323
7797c6da 324 dss_mgr_disable(dssdev->manager);
c3198a5e
M		 325
326 p = &dssdev->panel.timings;
327
328 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n",
329 dssdev->panel.timings.x_res,
330 dssdev->panel.timings.y_res);
331
46095b2d
M		 332 timing = hdmi_get_timings();
333 if (timing == NULL) {
334 /* HDMI code 4 corresponds to 640 * 480 VGA */
9e4ed603 335 hdmi.ip_data.cfg.cm.code = 4;
46095b2d 336 /* DVI mode 1 corresponds to HDMI 0 to DVI */
9e4ed603 337 hdmi.ip_data.cfg.cm.mode = HDMI_DVI;
46095b2d
M		 338 hdmi.ip_data.cfg = vesa_timings[0];
339 } else {
340 hdmi.ip_data.cfg = *timing;
341 }
c3198a5e
M		 342 phy = p->pixel_clock;
343
7b27da54 344 hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data);
c3198a5e 345
60634a28 346 hdmi.ip_data.ops->video_enable(&hdmi.ip_data, 0);
c3198a5e 347
95a8aeb6 348 /* config the PLL and PHY hdmi_set_pll_pwrfirst */
60634a28 349 r = hdmi.ip_data.ops->pll_enable(&hdmi.ip_data);
c3198a5e
M		 350 if (r) {
351 DSSDBG("Failed to lock PLL\n");
352 goto err;
353 }
354
60634a28 355 r = hdmi.ip_data.ops->phy_enable(&hdmi.ip_data);
c3198a5e
M		 356 if (r) {
357 DSSDBG("Failed to start PHY\n");
358 goto err;
359 }
360
60634a28 361 hdmi.ip_data.ops->video_configure(&hdmi.ip_data);
c3198a5e
M		 362
363 /* Make selection of HDMI in DSS */
364 dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
365
366 /* Select the dispc clock source as PRCM clock, to ensure that it is not
367 * DSI PLL source as the clock selected by DSI PLL might not be
368 * sufficient for the resolution selected / that can be changed
369 * dynamically by user. This can be moved to single location , say
370 * Boardfile.
371 */
6cb07b25 372 dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
c3198a5e
M		 373
374 /* bypass TV gamma table */
375 dispc_enable_gamma_table(0);
376
377 /* tv size */
41721163 378 dss_mgr_set_timings(dssdev->manager, &dssdev->panel.timings);
c3198a5e 379
60634a28 380 hdmi.ip_data.ops->video_enable(&hdmi.ip_data, 1);
c3198a5e 381
33ca237f
TV		 382 r = dss_mgr_enable(dssdev->manager);
383 if (r)
384 goto err_mgr_enable;
3870c909 385
c3198a5e 386 return 0;
33ca237f
TV		 387
388err_mgr_enable:
389 hdmi.ip_data.ops->video_enable(&hdmi.ip_data, 0);
390 hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
391 hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
c3198a5e 392err:
4fbafaf3 393 hdmi_runtime_put();
c3198a5e
M		 394 return -EIO;
395}
396
397static void hdmi_power_off(struct omap_dss_device *dssdev)
398{
7797c6da 399 dss_mgr_disable(dssdev->manager);
c3198a5e 400
60634a28
M		 401 hdmi.ip_data.ops->video_enable(&hdmi.ip_data, 0);
402 hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
403 hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
4fbafaf3 404 hdmi_runtime_put();
c3198a5e
M		 405}
406
407int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
408 struct omap_video_timings *timings)
409{
410 struct hdmi_cm cm;
411
412 cm = hdmi_get_code(timings);
413 if (cm.code == -1) {
c3198a5e
M		 414 return -EINVAL;
415 }
416
417 return 0;
418
419}
420
421void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev)
422{
423 struct hdmi_cm cm;
424
c3198a5e 425 cm = hdmi_get_code(&dssdev->panel.timings);
9e4ed603
M		 426 hdmi.ip_data.cfg.cm.code = cm.code;
427 hdmi.ip_data.cfg.cm.mode = cm.mode;
fa70dc5f
TV		 428
429 if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
430 int r;
431
432 hdmi_power_off(dssdev);
433
434 r = hdmi_power_on(dssdev);
435 if (r)
436 DSSERR("failed to power on device\n");
fcc36619
AT		 437 } else {
438 dss_mgr_set_timings(dssdev->manager, &dssdev->panel.timings);
fa70dc5f 439 }
c3198a5e
M		 440}
441
162874d5
M		 442void hdmi_dump_regs(struct seq_file *s)
443{
444 mutex_lock(&hdmi.lock);
445
446 if (hdmi_runtime_get())
447 return;
448
449 hdmi.ip_data.ops->dump_wrapper(&hdmi.ip_data, s);
450 hdmi.ip_data.ops->dump_pll(&hdmi.ip_data, s);
451 hdmi.ip_data.ops->dump_phy(&hdmi.ip_data, s);
452 hdmi.ip_data.ops->dump_core(&hdmi.ip_data, s);
453
454 hdmi_runtime_put();
455 mutex_unlock(&hdmi.lock);
456}
457
47024565
TV		 458int omapdss_hdmi_read_edid(u8 *buf, int len)
459{
460 int r;
461
462 mutex_lock(&hdmi.lock);
463
464 r = hdmi_runtime_get();
465 BUG_ON(r);
466
467 r = hdmi.ip_data.ops->read_edid(&hdmi.ip_data, buf, len);
468
469 hdmi_runtime_put();
470 mutex_unlock(&hdmi.lock);
471
472 return r;
473}
474
759593ff
TV		 475bool omapdss_hdmi_detect(void)
476{
477 int r;
478
479 mutex_lock(&hdmi.lock);
480
481 r = hdmi_runtime_get();
482 BUG_ON(r);
483
484 r = hdmi.ip_data.ops->detect(&hdmi.ip_data);
485
486 hdmi_runtime_put();
487 mutex_unlock(&hdmi.lock);
488
489 return r == 1;
490}
491
c3198a5e
M		 492int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev)
493{
c49d005b 494 struct omap_dss_hdmi_data *priv = dssdev->data;
c3198a5e
M		 495 int r = 0;
496
497 DSSDBG("ENTER hdmi_display_enable\n");
498
499 mutex_lock(&hdmi.lock);
500
05e1d606
TV		 501 if (dssdev->manager == NULL) {
502 DSSERR("failed to enable display: no manager\n");
503 r = -ENODEV;
504 goto err0;
505 }
506
c49d005b
TV		 507 hdmi.ip_data.hpd_gpio = priv->hpd_gpio;
508
c3198a5e
M		 509 r = omap_dss_start_device(dssdev);
510 if (r) {
511 DSSERR("failed to start device\n");
512 goto err0;
513 }
514
515 if (dssdev->platform_enable) {
516 r = dssdev->platform_enable(dssdev);
517 if (r) {
518 DSSERR("failed to enable GPIO's\n");
519 goto err1;
520 }
521 }
522
523 r = hdmi_power_on(dssdev);
524 if (r) {
525 DSSERR("failed to power on device\n");
526 goto err2;
527 }
528
529 mutex_unlock(&hdmi.lock);
530 return 0;
531
532err2:
533 if (dssdev->platform_disable)
534 dssdev->platform_disable(dssdev);
535err1:
536 omap_dss_stop_device(dssdev);
537err0:
538 mutex_unlock(&hdmi.lock);
539 return r;
540}
541
542void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev)
543{
544 DSSDBG("Enter hdmi_display_disable\n");
545
546 mutex_lock(&hdmi.lock);
547
548 hdmi_power_off(dssdev);
549
550 if (dssdev->platform_disable)
551 dssdev->platform_disable(dssdev);
552
553 omap_dss_stop_device(dssdev);
554
555 mutex_unlock(&hdmi.lock);
556}
557
82335c4c
RN		 558#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
559 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
ad44cc32 560
edefcdad
RN		 561static int hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd,
562 struct snd_soc_dai *dai)
563{
564 struct snd_soc_pcm_runtime *rtd = substream->private_data;
565 struct snd_soc_codec *codec = rtd->codec;
566 struct platform_device *pdev = to_platform_device(codec->dev);
567 struct hdmi_ip_data *ip_data = snd_soc_codec_get_drvdata(codec);
568 int err = 0;
569
570 if (!(ip_data->ops) && !(ip_data->ops->audio_enable)) {
571 dev_err(&pdev->dev, "Cannot enable/disable audio\n");
572 return -ENODEV;
573 }
574
575 switch (cmd) {
576 case SNDRV_PCM_TRIGGER_START:
577 case SNDRV_PCM_TRIGGER_RESUME:
578 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
579 ip_data->ops->audio_enable(ip_data, true);
580 break;
581 case SNDRV_PCM_TRIGGER_STOP:
582 case SNDRV_PCM_TRIGGER_SUSPEND:
583 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
584 ip_data->ops->audio_enable(ip_data, false);
585 break;
586 default:
587 err = -EINVAL;
588 }
589 return err;
590}
591
284cb318 592static int hdmi_audio_hw_params(struct snd_pcm_substream *substream,
ad44cc32
RN		 593 struct snd_pcm_hw_params *params,
594 struct snd_soc_dai *dai)
595{
284cb318
RN		 596 struct snd_soc_pcm_runtime *rtd = substream->private_data;
597 struct snd_soc_codec *codec = rtd->codec;
598 struct hdmi_ip_data *ip_data = snd_soc_codec_get_drvdata(codec);
ad44cc32
RN		 599 struct hdmi_audio_format audio_format;
600 struct hdmi_audio_dma audio_dma;
601 struct hdmi_core_audio_config core_cfg;
602 struct hdmi_core_infoframe_audio aud_if_cfg;
603 int err, n, cts;
604 enum hdmi_core_audio_sample_freq sample_freq;
605
606 switch (params_format(params)) {
607 case SNDRV_PCM_FORMAT_S16_LE:
608 core_cfg.i2s_cfg.word_max_length =
609 HDMI_AUDIO_I2S_MAX_WORD_20BITS;
610 core_cfg.i2s_cfg.word_length = HDMI_AUDIO_I2S_CHST_WORD_16_BITS;
611 core_cfg.i2s_cfg.in_length_bits =
612 HDMI_AUDIO_I2S_INPUT_LENGTH_16;
613 core_cfg.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_LEFT;
614 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES;
615 audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS;
616 audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT;
617 audio_dma.transfer_size = 0x10;
618 break;
619 case SNDRV_PCM_FORMAT_S24_LE:
620 core_cfg.i2s_cfg.word_max_length =
621 HDMI_AUDIO_I2S_MAX_WORD_24BITS;
622 core_cfg.i2s_cfg.word_length = HDMI_AUDIO_I2S_CHST_WORD_24_BITS;
623 core_cfg.i2s_cfg.in_length_bits =
624 HDMI_AUDIO_I2S_INPUT_LENGTH_24;
625 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_ONESAMPLE;
626 audio_format.sample_size = HDMI_AUDIO_SAMPLE_24BITS;
627 audio_format.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
628 core_cfg.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
629 audio_dma.transfer_size = 0x20;
630 break;
631 default:
632 return -EINVAL;
633 }
634
635 switch (params_rate(params)) {
636 case 32000:
637 sample_freq = HDMI_AUDIO_FS_32000;
638 break;
639 case 44100:
640 sample_freq = HDMI_AUDIO_FS_44100;
641 break;
642 case 48000:
643 sample_freq = HDMI_AUDIO_FS_48000;
644 break;
645 default:
646 return -EINVAL;
647 }
648
95a8aeb6 649 err = hdmi_config_audio_acr(ip_data, params_rate(params), &n, &cts);
ad44cc32
RN		 650 if (err < 0)
651 return err;
652
653 /* Audio wrapper config */
654 audio_format.stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL;
655 audio_format.active_chnnls_msk = 0x03;
656 audio_format.type = HDMI_AUDIO_TYPE_LPCM;
657 audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
658 /* Disable start/stop signals of IEC 60958 blocks */
659 audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF;
660
661 audio_dma.block_size = 0xC0;
662 audio_dma.mode = HDMI_AUDIO_TRANSF_DMA;
663 audio_dma.fifo_threshold = 0x20; /* in number of samples */
664
95a8aeb6
M		 665 hdmi_wp_audio_config_dma(ip_data, &audio_dma);
666 hdmi_wp_audio_config_format(ip_data, &audio_format);
ad44cc32
RN		 667
668 /*
669 * I2S config
670 */
671 core_cfg.i2s_cfg.en_high_bitrate_aud = false;
672 /* Only used with high bitrate audio */
673 core_cfg.i2s_cfg.cbit_order = false;
674 /* Serial data and word select should change on sck rising edge */
675 core_cfg.i2s_cfg.sck_edge_mode = HDMI_AUDIO_I2S_SCK_EDGE_RISING;
676 core_cfg.i2s_cfg.vbit = HDMI_AUDIO_I2S_VBIT_FOR_PCM;
677 /* Set I2S word select polarity */
678 core_cfg.i2s_cfg.ws_polarity = HDMI_AUDIO_I2S_WS_POLARITY_LOW_IS_LEFT;
679 core_cfg.i2s_cfg.direction = HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST;
680 /* Set serial data to word select shift. See Phillips spec. */
681 core_cfg.i2s_cfg.shift = HDMI_AUDIO_I2S_FIRST_BIT_SHIFT;
682 /* Enable one of the four available serial data channels */
683 core_cfg.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN;
684
685 /* Core audio config */
686 core_cfg.freq_sample = sample_freq;
687 core_cfg.n = n;
688 core_cfg.cts = cts;
689 if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) {
690 core_cfg.aud_par_busclk = 0;
691 core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_SW;
f15511e2 692 core_cfg.use_mclk = dss_has_feature(FEAT_HDMI_AUDIO_USE_MCLK);
ad44cc32
RN		 693 } else {
694 core_cfg.aud_par_busclk = (((128 * 31) - 1) << 8);
695 core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_HW;
696 core_cfg.use_mclk = true;
ad44cc32 697 }
f15511e2
RN		 698
699 if (core_cfg.use_mclk)
700 core_cfg.mclk_mode = HDMI_AUDIO_MCLK_128FS;
ad44cc32
RN		 701 core_cfg.layout = HDMI_AUDIO_LAYOUT_2CH;
702 core_cfg.en_spdif = false;
703 /* Use sample frequency from channel status word */
704 core_cfg.fs_override = true;
705 /* Enable ACR packets */
706 core_cfg.en_acr_pkt = true;
707 /* Disable direct streaming digital audio */
708 core_cfg.en_dsd_audio = false;
709 /* Use parallel audio interface */
710 core_cfg.en_parallel_aud_input = true;
711
95a8aeb6 712 hdmi_core_audio_config(ip_data, &core_cfg);
ad44cc32
RN		 713
714 /*
715 * Configure packet
716 * info frame audio see doc CEA861-D page 74
717 */
718 aud_if_cfg.db1_coding_type = HDMI_INFOFRAME_AUDIO_DB1CT_FROM_STREAM;
719 aud_if_cfg.db1_channel_count = 2;
720 aud_if_cfg.db2_sample_freq = HDMI_INFOFRAME_AUDIO_DB2SF_FROM_STREAM;
721 aud_if_cfg.db2_sample_size = HDMI_INFOFRAME_AUDIO_DB2SS_FROM_STREAM;
722 aud_if_cfg.db4_channel_alloc = 0x00;
723 aud_if_cfg.db5_downmix_inh = false;
724 aud_if_cfg.db5_lsv = 0;
725
95a8aeb6 726 hdmi_core_audio_infoframe_config(ip_data, &aud_if_cfg);
ad44cc32
RN		 727 return 0;
728}
729
ad44cc32
RN		 730static int hdmi_audio_startup(struct snd_pcm_substream *substream,
731 struct snd_soc_dai *dai)
732{
9e4ed603 733 if (!hdmi.ip_data.cfg.cm.mode) {
ad44cc32
RN		 734 pr_err("Current video settings do not support audio.\n");
735 return -EIO;
736 }
737 return 0;
738}
739
b17ce117
RN		 740static int hdmi_audio_codec_probe(struct snd_soc_codec *codec)
741{
742 struct hdmi_ip_data *priv = &hdmi.ip_data;
743
744 snd_soc_codec_set_drvdata(codec, priv);
745 return 0;
746}
747
ad44cc32 748static struct snd_soc_codec_driver hdmi_audio_codec_drv = {
b17ce117 749 .probe = hdmi_audio_codec_probe,
ad44cc32
RN		 750};
751
752static struct snd_soc_dai_ops hdmi_audio_codec_ops = {
753 .hw_params = hdmi_audio_hw_params,
754 .trigger = hdmi_audio_trigger,
755 .startup = hdmi_audio_startup,
756};
757
758static struct snd_soc_dai_driver hdmi_codec_dai_drv = {
759 .name = "hdmi-audio-codec",
760 .playback = {
761 .channels_min = 2,
762 .channels_max = 2,
763 .rates = SNDRV_PCM_RATE_32000 |
764 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
765 .formats = SNDRV_PCM_FMTBIT_S16_LE |
766 SNDRV_PCM_FMTBIT_S24_LE,
767 },
768 .ops = &hdmi_audio_codec_ops,
769};
82335c4c
RN		 770#endif
771
4fbafaf3
TV		 772static int hdmi_get_clocks(struct platform_device *pdev)
773{
774 struct clk *clk;
775
776 clk = clk_get(&pdev->dev, "sys_clk");
777 if (IS_ERR(clk)) {
778 DSSERR("can't get sys_clk\n");
779 return PTR_ERR(clk);
780 }
781
782 hdmi.sys_clk = clk;
783
4fbafaf3
TV		 784 return 0;
785}
786
787static void hdmi_put_clocks(void)
788{
789 if (hdmi.sys_clk)
790 clk_put(hdmi.sys_clk);
4fbafaf3
TV		 791}
792
c3198a5e
M		 793/* HDMI HW IP initialisation */
794static int omapdss_hdmihw_probe(struct platform_device *pdev)
795{
796 struct resource *hdmi_mem;
4fbafaf3 797 int r;
c3198a5e 798
c3198a5e
M		 799 hdmi.pdev = pdev;
800
801 mutex_init(&hdmi.lock);
802
803 hdmi_mem = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0);
804 if (!hdmi_mem) {
805 DSSERR("can't get IORESOURCE_MEM HDMI\n");
806 return -EINVAL;
807 }
808
809 /* Base address taken from platform */
95a8aeb6
M		 810 hdmi.ip_data.base_wp = ioremap(hdmi_mem->start,
811 resource_size(hdmi_mem));
812 if (!hdmi.ip_data.base_wp) {
c3198a5e
M		 813 DSSERR("can't ioremap WP\n");
814 return -ENOMEM;
815 }
816
4fbafaf3
TV		 817 r = hdmi_get_clocks(pdev);
818 if (r) {
95a8aeb6 819 iounmap(hdmi.ip_data.base_wp);
4fbafaf3
TV		 820 return r;
821 }
822
823 pm_runtime_enable(&pdev->dev);
824
95a8aeb6
M		 825 hdmi.ip_data.core_sys_offset = HDMI_CORE_SYS;
826 hdmi.ip_data.core_av_offset = HDMI_CORE_AV;
827 hdmi.ip_data.pll_offset = HDMI_PLLCTRL;
828 hdmi.ip_data.phy_offset = HDMI_PHY;
829
c3198a5e
M		 830 hdmi_panel_init();
831
ad44cc32
RN		 832#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
833 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
834
835 /* Register ASoC codec DAI */
4fbafaf3 836 r = snd_soc_register_codec(&pdev->dev, &hdmi_audio_codec_drv,
ad44cc32 837 &hdmi_codec_dai_drv, 1);
4fbafaf3 838 if (r) {
ad44cc32 839 DSSERR("can't register ASoC HDMI audio codec\n");
4fbafaf3 840 return r;
ad44cc32
RN		 841 }
842#endif
c3198a5e
M		 843 return 0;
844}
845
846static int omapdss_hdmihw_remove(struct platform_device *pdev)
847{
848 hdmi_panel_exit();
849
ad44cc32
RN		 850#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
851 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
852 snd_soc_unregister_codec(&pdev->dev);
853#endif
854
4fbafaf3
TV		 855 pm_runtime_disable(&pdev->dev);
856
857 hdmi_put_clocks();
858
95a8aeb6 859 iounmap(hdmi.ip_data.base_wp);
c3198a5e
M		 860
861 return 0;
862}
863
4fbafaf3
TV		 864static int hdmi_runtime_suspend(struct device *dev)
865{
4fbafaf3
TV		 866 clk_disable(hdmi.sys_clk);
867
868 dispc_runtime_put();
869 dss_runtime_put();
870
871 return 0;
872}
873
874static int hdmi_runtime_resume(struct device *dev)
875{
876 int r;
877
878 r = dss_runtime_get();
879 if (r < 0)
880 goto err_get_dss;
881
882 r = dispc_runtime_get();
883 if (r < 0)
884 goto err_get_dispc;
885
886
887 clk_enable(hdmi.sys_clk);
4fbafaf3
TV		 888
889 return 0;
890
891err_get_dispc:
892 dss_runtime_put();
893err_get_dss:
894 return r;
895}
896
897static const struct dev_pm_ops hdmi_pm_ops = {
898 .runtime_suspend = hdmi_runtime_suspend,
899 .runtime_resume = hdmi_runtime_resume,
900};
901
c3198a5e
M		 902static struct platform_driver omapdss_hdmihw_driver = {
903 .probe = omapdss_hdmihw_probe,
904 .remove = omapdss_hdmihw_remove,
905 .driver = {
906 .name = "omapdss_hdmi",
907 .owner = THIS_MODULE,
4fbafaf3 908 .pm = &hdmi_pm_ops,
c3198a5e
M		 909 },
910};
911
912int hdmi_init_platform_driver(void)
913{
914 return platform_driver_register(&omapdss_hdmihw_driver);
915}
916
917void hdmi_uninit_platform_driver(void)
918{
919 return platform_driver_unregister(&omapdss_hdmihw_driver);
920}
Linux kernel - Deliverables
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