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OMAPDSS: HDMI: Split audio_enable into audio_enable/disable
[deliverable/linux.git] / drivers / video / omap2 / dss / hdmi.c
CommitLineData
c3198a5e
M		 1/*
2 * hdmi.c
3 *
4 * HDMI interface DSS driver setting for TI's OMAP4 family of processor.
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
6 * Authors: Yong Zhi
7 * Mythri pk <mythripk@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#define DSS_SUBSYS_NAME "HDMI"
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/err.h>
27#include <linux/io.h>
28#include <linux/interrupt.h>
29#include <linux/mutex.h>
30#include <linux/delay.h>
31#include <linux/string.h>
24e6289c 32#include <linux/platform_device.h>
4fbafaf3
TV		 33#include <linux/pm_runtime.h>
34#include <linux/clk.h>
a0b38cc4 35#include <video/omapdss.h>
ad44cc32
RN		 36#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
37 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
38#include <sound/soc.h>
39#include <sound/pcm_params.h>
7334167b 40#include "ti_hdmi_4xxx_ip.h"
ad44cc32 41#endif
c3198a5e 42
94c52987 43#include "ti_hdmi.h"
c3198a5e 44#include "dss.h"
ad44cc32 45#include "dss_features.h"
c3198a5e 46
95a8aeb6
M		 47#define HDMI_WP 0x0
48#define HDMI_CORE_SYS 0x400
49#define HDMI_CORE_AV 0x900
50#define HDMI_PLLCTRL 0x200
51#define HDMI_PHY 0x300
52
7c1f1eca
M		 53/* HDMI EDID Length move this */
54#define HDMI_EDID_MAX_LENGTH 256
55#define EDID_TIMING_DESCRIPTOR_SIZE 0x12
56#define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36
57#define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80
58#define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4
59#define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4
60
b44e4582 61#define HDMI_DEFAULT_REGN 16
8d88767a
TV		 62#define HDMI_DEFAULT_REGM2 1
63
c3198a5e
M		 64static struct {
65 struct mutex lock;
c3198a5e 66 struct platform_device *pdev;
95a8aeb6 67 struct hdmi_ip_data ip_data;
4fbafaf3
TV		 68
69 struct clk *sys_clk;
c3198a5e
M		 70} hdmi;
71
72/*
73 * Logic for the below structure :
74 * user enters the CEA or VESA timings by specifying the HDMI/DVI code.
75 * There is a correspondence between CEA/VESA timing and code, please
76 * refer to section 6.3 in HDMI 1.3 specification for timing code.
77 *
78 * In the below structure, cea_vesa_timings corresponds to all OMAP4
79 * supported CEA and VESA timing values.code_cea corresponds to the CEA
80 * code, It is used to get the timing from cea_vesa_timing array.Similarly
81 * with code_vesa. Code_index is used for back mapping, that is once EDID
82 * is read from the TV, EDID is parsed to find the timing values and then
83 * map it to corresponding CEA or VESA index.
84 */
85
46095b2d 86static const struct hdmi_config cea_timings[] = {
a05ce78f
M		 87{ {640, 480, 25200, 96, 16, 48, 2, 10, 33, 0, 0, 0}, {1, HDMI_HDMI} },
88{ {720, 480, 27027, 62, 16, 60, 6, 9, 30, 0, 0, 0}, {2, HDMI_HDMI} },
89{ {1280, 720, 74250, 40, 110, 220, 5, 5, 20, 1, 1, 0}, {4, HDMI_HDMI} },
90{ {1920, 540, 74250, 44, 88, 148, 5, 2, 15, 1, 1, 1}, {5, HDMI_HDMI} },
91{ {1440, 240, 27027, 124, 38, 114, 3, 4, 15, 0, 0, 1}, {6, HDMI_HDMI} },
92{ {1920, 1080, 148500, 44, 88, 148, 5, 4, 36, 1, 1, 0}, {16, HDMI_HDMI} },
93{ {720, 576, 27000, 64, 12, 68, 5, 5, 39, 0, 0, 0}, {17, HDMI_HDMI} },
94{ {1280, 720, 74250, 40, 440, 220, 5, 5, 20, 1, 1, 0}, {19, HDMI_HDMI} },
95{ {1920, 540, 74250, 44, 528, 148, 5, 2, 15, 1, 1, 1}, {20, HDMI_HDMI} },
96{ {1440, 288, 27000, 126, 24, 138, 3, 2, 19, 0, 0, 1}, {21, HDMI_HDMI} },
97{ {1440, 576, 54000, 128, 24, 136, 5, 5, 39, 0, 0, 0}, {29, HDMI_HDMI} },
98{ {1920, 1080, 148500, 44, 528, 148, 5, 4, 36, 1, 1, 0}, {31, HDMI_HDMI} },
99{ {1920, 1080, 74250, 44, 638, 148, 5, 4, 36, 1, 1, 0}, {32, HDMI_HDMI} },
100{ {2880, 480, 108108, 248, 64, 240, 6, 9, 30, 0, 0, 0}, {35, HDMI_HDMI} },
101{ {2880, 576, 108000, 256, 48, 272, 5, 5, 39, 0, 0, 0}, {37, HDMI_HDMI} },
46095b2d
M		 102};
103static const struct hdmi_config vesa_timings[] = {
a05ce78f
M		 104/* VESA From Here */
105{ {640, 480, 25175, 96, 16, 48, 2 , 11, 31, 0, 0, 0}, {4, HDMI_DVI} },
106{ {800, 600, 40000, 128, 40, 88, 4 , 1, 23, 1, 1, 0}, {9, HDMI_DVI} },
107{ {848, 480, 33750, 112, 16, 112, 8 , 6, 23, 1, 1, 0}, {0xE, HDMI_DVI} },
108{ {1280, 768, 79500, 128, 64, 192, 7 , 3, 20, 1, 0, 0}, {0x17, HDMI_DVI} },
109{ {1280, 800, 83500, 128, 72, 200, 6 , 3, 22, 1, 0, 0}, {0x1C, HDMI_DVI} },
110{ {1360, 768, 85500, 112, 64, 256, 6 , 3, 18, 1, 1, 0}, {0x27, HDMI_DVI} },
111{ {1280, 960, 108000, 112, 96, 312, 3 , 1, 36, 1, 1, 0}, {0x20, HDMI_DVI} },
112{ {1280, 1024, 108000, 112, 48, 248, 3 , 1, 38, 1, 1, 0}, {0x23, HDMI_DVI} },
113{ {1024, 768, 65000, 136, 24, 160, 6, 3, 29, 0, 0, 0}, {0x10, HDMI_DVI} },
114{ {1400, 1050, 121750, 144, 88, 232, 4, 3, 32, 1, 0, 0}, {0x2A, HDMI_DVI} },
115{ {1440, 900, 106500, 152, 80, 232, 6, 3, 25, 1, 0, 0}, {0x2F, HDMI_DVI} },
116{ {1680, 1050, 146250, 176 , 104, 280, 6, 3, 30, 1, 0, 0}, {0x3A, HDMI_DVI} },
117{ {1366, 768, 85500, 143, 70, 213, 3, 3, 24, 1, 1, 0}, {0x51, HDMI_DVI} },
118{ {1920, 1080, 148500, 44, 148, 80, 5, 4, 36, 1, 1, 0}, {0x52, HDMI_DVI} },
119{ {1280, 768, 68250, 32, 48, 80, 7, 3, 12, 0, 1, 0}, {0x16, HDMI_DVI} },
120{ {1400, 1050, 101000, 32, 48, 80, 4, 3, 23, 0, 1, 0}, {0x29, HDMI_DVI} },
121{ {1680, 1050, 119000, 32, 48, 80, 6, 3, 21, 0, 1, 0}, {0x39, HDMI_DVI} },
122{ {1280, 800, 79500, 32, 48, 80, 6, 3, 14, 0, 1, 0}, {0x1B, HDMI_DVI} },
123{ {1280, 720, 74250, 40, 110, 220, 5, 5, 20, 1, 1, 0}, {0x55, HDMI_DVI} }
c3198a5e
M		 124};
125
4fbafaf3
TV		 126static int hdmi_runtime_get(void)
127{
128 int r;
129
130 DSSDBG("hdmi_runtime_get\n");
131
132 r = pm_runtime_get_sync(&hdmi.pdev->dev);
133 WARN_ON(r < 0);
a247ce78 134 if (r < 0)
852f0838 135 return r;
a247ce78
AT		 136
137 return 0;
4fbafaf3
TV		 138}
139
140static void hdmi_runtime_put(void)
141{
142 int r;
143
144 DSSDBG("hdmi_runtime_put\n");
145
0eaf9f52 146 r = pm_runtime_put_sync(&hdmi.pdev->dev);
4fbafaf3
TV		 147 WARN_ON(r < 0);
148}
149
9d8232a7 150static int __init hdmi_init_display(struct omap_dss_device *dssdev)
c3198a5e
M		 151{
152 DSSDBG("init_display\n");
153
60634a28 154 dss_init_hdmi_ip_ops(&hdmi.ip_data);
c3198a5e
M		 155 return 0;
156}
157
46095b2d
M		 158static const struct hdmi_config *hdmi_find_timing(
159 const struct hdmi_config *timings_arr,
160 int len)
c3198a5e 161{
46095b2d 162 int i;
c3198a5e 163
46095b2d 164 for (i = 0; i < len; i++) {
9e4ed603 165 if (timings_arr[i].cm.code == hdmi.ip_data.cfg.cm.code)
46095b2d
M		 166 return &timings_arr[i];
167 }
168 return NULL;
169}
c3198a5e 170
46095b2d
M		 171static const struct hdmi_config *hdmi_get_timings(void)
172{
173 const struct hdmi_config *arr;
174 int len;
175
9e4ed603 176 if (hdmi.ip_data.cfg.cm.mode == HDMI_DVI) {
46095b2d
M		 177 arr = vesa_timings;
178 len = ARRAY_SIZE(vesa_timings);
179 } else {
180 arr = cea_timings;
181 len = ARRAY_SIZE(cea_timings);
182 }
183
184 return hdmi_find_timing(arr, len);
185}
186
187static bool hdmi_timings_compare(struct omap_video_timings *timing1,
188 const struct hdmi_video_timings *timing2)
189{
190 int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync;
191
192 if ((timing2->pixel_clock == timing1->pixel_clock) &&
193 (timing2->x_res == timing1->x_res) &&
194 (timing2->y_res == timing1->y_res)) {
c3198a5e 195
46095b2d
M		 196 timing2_hsync = timing2->hfp + timing2->hsw + timing2->hbp;
197 timing1_hsync = timing1->hfp + timing1->hsw + timing1->hbp;
198 timing2_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
199 timing1_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
200
201 DSSDBG("timing1_hsync = %d timing1_vsync = %d"\
202 "timing2_hsync = %d timing2_vsync = %d\n",
203 timing1_hsync, timing1_vsync,
204 timing2_hsync, timing2_vsync);
205
206 if ((timing1_hsync == timing2_hsync) &&
207 (timing1_vsync == timing2_vsync)) {
208 return true;
209 }
c3198a5e 210 }
46095b2d 211 return false;
c3198a5e
M		 212}
213
214static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing)
215{
46095b2d 216 int i;
c3198a5e
M		 217 struct hdmi_cm cm = {-1};
218 DSSDBG("hdmi_get_code\n");
219
46095b2d
M		 220 for (i = 0; i < ARRAY_SIZE(cea_timings); i++) {
221 if (hdmi_timings_compare(timing, &cea_timings[i].timings)) {
222 cm = cea_timings[i].cm;
223 goto end;
224 }
225 }
226 for (i = 0; i < ARRAY_SIZE(vesa_timings); i++) {
227 if (hdmi_timings_compare(timing, &vesa_timings[i].timings)) {
228 cm = vesa_timings[i].cm;
229 goto end;
c3198a5e
M		 230 }
231 }
232
46095b2d 233end: return cm;
c3198a5e 234
c3198a5e
M		 235}
236
c3dc6a7a
AT		 237unsigned long hdmi_get_pixel_clock(void)
238{
239 /* HDMI Pixel Clock in Mhz */
a05ce78f 240 return hdmi.ip_data.cfg.timings.pixel_clock * 1000;
c3dc6a7a
AT		 241}
242
6cb07b25
AT		 243static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
244 struct hdmi_pll_info *pi)
c3198a5e 245{
6cb07b25 246 unsigned long clkin, refclk;
c3198a5e
M		 247 u32 mf;
248
4fbafaf3 249 clkin = clk_get_rate(hdmi.sys_clk) / 10000;
c3198a5e
M		 250 /*
251 * Input clock is predivided by N + 1
252 * out put of which is reference clk
253 */
8d88767a
TV		 254 if (dssdev->clocks.hdmi.regn == 0)
255 pi->regn = HDMI_DEFAULT_REGN;
256 else
257 pi->regn = dssdev->clocks.hdmi.regn;
258
b44e4582 259 refclk = clkin / pi->regn;
c3198a5e 260
8d88767a
TV		 261 if (dssdev->clocks.hdmi.regm2 == 0)
262 pi->regm2 = HDMI_DEFAULT_REGM2;
263 else
264 pi->regm2 = dssdev->clocks.hdmi.regm2;
c3198a5e 265
dd2116a3
M		 266 /*
267 * multiplier is pixel_clk/ref_clk
268 * Multiplying by 100 to avoid fractional part removal
269 */
270 pi->regm = phy * pi->regm2 / refclk;
271
c3198a5e
M		 272 /*
273 * fractional multiplier is remainder of the difference between
274 * multiplier and actual phy(required pixel clock thus should be
275 * multiplied by 2^18(262144) divided by the reference clock
276 */
dd2116a3
M		 277 mf = (phy - pi->regm / pi->regm2 * refclk) * 262144;
278 pi->regmf = pi->regm2 * mf / refclk;
c3198a5e
M		 279
280 /*
281 * Dcofreq should be set to 1 if required pixel clock
282 * is greater than 1000MHz
283 */
284 pi->dcofreq = phy > 1000 * 100;
b44e4582 285 pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10;
c3198a5e 286
7b27da54
M		 287 /* Set the reference clock to sysclk reference */
288 pi->refsel = HDMI_REFSEL_SYSCLK;
289
c3198a5e
M		 290 DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
291 DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
292}
293
c3198a5e
M		 294static int hdmi_power_on(struct omap_dss_device *dssdev)
295{
46095b2d
M		 296 int r;
297 const struct hdmi_config *timing;
c3198a5e 298 struct omap_video_timings *p;
6cb07b25 299 unsigned long phy;
c3198a5e 300
4fbafaf3
TV		 301 r = hdmi_runtime_get();
302 if (r)
303 return r;
c3198a5e 304
7797c6da 305 dss_mgr_disable(dssdev->manager);
c3198a5e
M		 306
307 p = &dssdev->panel.timings;
308
309 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n",
310 dssdev->panel.timings.x_res,
311 dssdev->panel.timings.y_res);
312
46095b2d
M		 313 timing = hdmi_get_timings();
314 if (timing == NULL) {
315 /* HDMI code 4 corresponds to 640 * 480 VGA */
9e4ed603 316 hdmi.ip_data.cfg.cm.code = 4;
46095b2d 317 /* DVI mode 1 corresponds to HDMI 0 to DVI */
9e4ed603 318 hdmi.ip_data.cfg.cm.mode = HDMI_DVI;
46095b2d
M		 319 hdmi.ip_data.cfg = vesa_timings[0];
320 } else {
321 hdmi.ip_data.cfg = *timing;
322 }
c3198a5e
M		 323 phy = p->pixel_clock;
324
7b27da54 325 hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data);
c3198a5e 326
60634a28 327 hdmi.ip_data.ops->video_enable(&hdmi.ip_data, 0);
c3198a5e 328
95a8aeb6 329 /* config the PLL and PHY hdmi_set_pll_pwrfirst */
60634a28 330 r = hdmi.ip_data.ops->pll_enable(&hdmi.ip_data);
c3198a5e
M		 331 if (r) {
332 DSSDBG("Failed to lock PLL\n");
333 goto err;
334 }
335
60634a28 336 r = hdmi.ip_data.ops->phy_enable(&hdmi.ip_data);
c3198a5e
M		 337 if (r) {
338 DSSDBG("Failed to start PHY\n");
339 goto err;
340 }
341
60634a28 342 hdmi.ip_data.ops->video_configure(&hdmi.ip_data);
c3198a5e
M		 343
344 /* Make selection of HDMI in DSS */
345 dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
346
347 /* Select the dispc clock source as PRCM clock, to ensure that it is not
348 * DSI PLL source as the clock selected by DSI PLL might not be
349 * sufficient for the resolution selected / that can be changed
350 * dynamically by user. This can be moved to single location , say
351 * Boardfile.
352 */
6cb07b25 353 dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
c3198a5e
M		 354
355 /* bypass TV gamma table */
356 dispc_enable_gamma_table(0);
357
358 /* tv size */
41721163 359 dss_mgr_set_timings(dssdev->manager, &dssdev->panel.timings);
c3198a5e 360
60634a28 361 hdmi.ip_data.ops->video_enable(&hdmi.ip_data, 1);
c3198a5e 362
33ca237f
TV		 363 r = dss_mgr_enable(dssdev->manager);
364 if (r)
365 goto err_mgr_enable;
3870c909 366
c3198a5e 367 return 0;
33ca237f
TV		 368
369err_mgr_enable:
370 hdmi.ip_data.ops->video_enable(&hdmi.ip_data, 0);
371 hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
372 hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
c3198a5e 373err:
4fbafaf3 374 hdmi_runtime_put();
c3198a5e
M		 375 return -EIO;
376}
377
378static void hdmi_power_off(struct omap_dss_device *dssdev)
379{
7797c6da 380 dss_mgr_disable(dssdev->manager);
c3198a5e 381
60634a28
M		 382 hdmi.ip_data.ops->video_enable(&hdmi.ip_data, 0);
383 hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
384 hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
4fbafaf3 385 hdmi_runtime_put();
c3198a5e
M		 386}
387
388int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
389 struct omap_video_timings *timings)
390{
391 struct hdmi_cm cm;
392
393 cm = hdmi_get_code(timings);
394 if (cm.code == -1) {
c3198a5e
M		 395 return -EINVAL;
396 }
397
398 return 0;
399
400}
401
402void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev)
403{
404 struct hdmi_cm cm;
405
c3198a5e 406 cm = hdmi_get_code(&dssdev->panel.timings);
9e4ed603
M		 407 hdmi.ip_data.cfg.cm.code = cm.code;
408 hdmi.ip_data.cfg.cm.mode = cm.mode;
fa70dc5f
TV		 409
410 if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
411 int r;
412
413 hdmi_power_off(dssdev);
414
415 r = hdmi_power_on(dssdev);
416 if (r)
417 DSSERR("failed to power on device\n");
fcc36619
AT		 418 } else {
419 dss_mgr_set_timings(dssdev->manager, &dssdev->panel.timings);
fa70dc5f 420 }
c3198a5e
M		 421}
422
e40402cf 423static void hdmi_dump_regs(struct seq_file *s)
162874d5
M		 424{
425 mutex_lock(&hdmi.lock);
426
427 if (hdmi_runtime_get())
428 return;
429
430 hdmi.ip_data.ops->dump_wrapper(&hdmi.ip_data, s);
431 hdmi.ip_data.ops->dump_pll(&hdmi.ip_data, s);
432 hdmi.ip_data.ops->dump_phy(&hdmi.ip_data, s);
433 hdmi.ip_data.ops->dump_core(&hdmi.ip_data, s);
434
435 hdmi_runtime_put();
436 mutex_unlock(&hdmi.lock);
437}
438
47024565
TV		 439int omapdss_hdmi_read_edid(u8 *buf, int len)
440{
441 int r;
442
443 mutex_lock(&hdmi.lock);
444
445 r = hdmi_runtime_get();
446 BUG_ON(r);
447
448 r = hdmi.ip_data.ops->read_edid(&hdmi.ip_data, buf, len);
449
450 hdmi_runtime_put();
451 mutex_unlock(&hdmi.lock);
452
453 return r;
454}
455
759593ff
TV		 456bool omapdss_hdmi_detect(void)
457{
458 int r;
459
460 mutex_lock(&hdmi.lock);
461
462 r = hdmi_runtime_get();
463 BUG_ON(r);
464
465 r = hdmi.ip_data.ops->detect(&hdmi.ip_data);
466
467 hdmi_runtime_put();
468 mutex_unlock(&hdmi.lock);
469
470 return r == 1;
471}
472
c3198a5e
M		 473int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev)
474{
c49d005b 475 struct omap_dss_hdmi_data *priv = dssdev->data;
c3198a5e
M		 476 int r = 0;
477
478 DSSDBG("ENTER hdmi_display_enable\n");
479
480 mutex_lock(&hdmi.lock);
481
05e1d606
TV		 482 if (dssdev->manager == NULL) {
483 DSSERR("failed to enable display: no manager\n");
484 r = -ENODEV;
485 goto err0;
486 }
487
c49d005b
TV		 488 hdmi.ip_data.hpd_gpio = priv->hpd_gpio;
489
c3198a5e
M		 490 r = omap_dss_start_device(dssdev);
491 if (r) {
492 DSSERR("failed to start device\n");
493 goto err0;
494 }
495
496 if (dssdev->platform_enable) {
497 r = dssdev->platform_enable(dssdev);
498 if (r) {
499 DSSERR("failed to enable GPIO's\n");
500 goto err1;
501 }
502 }
503
504 r = hdmi_power_on(dssdev);
505 if (r) {
506 DSSERR("failed to power on device\n");
507 goto err2;
508 }
509
510 mutex_unlock(&hdmi.lock);
511 return 0;
512
513err2:
514 if (dssdev->platform_disable)
515 dssdev->platform_disable(dssdev);
516err1:
517 omap_dss_stop_device(dssdev);
518err0:
519 mutex_unlock(&hdmi.lock);
520 return r;
521}
522
523void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev)
524{
525 DSSDBG("Enter hdmi_display_disable\n");
526
527 mutex_lock(&hdmi.lock);
528
529 hdmi_power_off(dssdev);
530
531 if (dssdev->platform_disable)
532 dssdev->platform_disable(dssdev);
533
534 omap_dss_stop_device(dssdev);
535
536 mutex_unlock(&hdmi.lock);
537}
538
82335c4c
RN		 539#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
540 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
ad44cc32 541
edefcdad
RN		 542static int hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd,
543 struct snd_soc_dai *dai)
544{
545 struct snd_soc_pcm_runtime *rtd = substream->private_data;
546 struct snd_soc_codec *codec = rtd->codec;
547 struct platform_device *pdev = to_platform_device(codec->dev);
548 struct hdmi_ip_data *ip_data = snd_soc_codec_get_drvdata(codec);
549 int err = 0;
550
551 if (!(ip_data->ops) && !(ip_data->ops->audio_enable)) {
552 dev_err(&pdev->dev, "Cannot enable/disable audio\n");
553 return -ENODEV;
554 }
555
556 switch (cmd) {
557 case SNDRV_PCM_TRIGGER_START:
558 case SNDRV_PCM_TRIGGER_RESUME:
559 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
027bdc85 560 ip_data->ops->audio_enable(ip_data);
edefcdad
RN		 561 break;
562 case SNDRV_PCM_TRIGGER_STOP:
563 case SNDRV_PCM_TRIGGER_SUSPEND:
564 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
027bdc85 565 ip_data->ops->audio_disable(ip_data);
edefcdad
RN		 566 break;
567 default:
568 err = -EINVAL;
569 }
570 return err;
571}
572
284cb318 573static int hdmi_audio_hw_params(struct snd_pcm_substream *substream,
ad44cc32
RN		 574 struct snd_pcm_hw_params *params,
575 struct snd_soc_dai *dai)
576{
284cb318
RN		 577 struct snd_soc_pcm_runtime *rtd = substream->private_data;
578 struct snd_soc_codec *codec = rtd->codec;
579 struct hdmi_ip_data *ip_data = snd_soc_codec_get_drvdata(codec);
ad44cc32
RN		 580 struct hdmi_audio_format audio_format;
581 struct hdmi_audio_dma audio_dma;
582 struct hdmi_core_audio_config core_cfg;
583 struct hdmi_core_infoframe_audio aud_if_cfg;
584 int err, n, cts;
585 enum hdmi_core_audio_sample_freq sample_freq;
586
587 switch (params_format(params)) {
588 case SNDRV_PCM_FORMAT_S16_LE:
589 core_cfg.i2s_cfg.word_max_length =
590 HDMI_AUDIO_I2S_MAX_WORD_20BITS;
591 core_cfg.i2s_cfg.word_length = HDMI_AUDIO_I2S_CHST_WORD_16_BITS;
592 core_cfg.i2s_cfg.in_length_bits =
593 HDMI_AUDIO_I2S_INPUT_LENGTH_16;
594 core_cfg.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_LEFT;
595 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES;
596 audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS;
597 audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT;
598 audio_dma.transfer_size = 0x10;
599 break;
600 case SNDRV_PCM_FORMAT_S24_LE:
601 core_cfg.i2s_cfg.word_max_length =
602 HDMI_AUDIO_I2S_MAX_WORD_24BITS;
603 core_cfg.i2s_cfg.word_length = HDMI_AUDIO_I2S_CHST_WORD_24_BITS;
604 core_cfg.i2s_cfg.in_length_bits =
605 HDMI_AUDIO_I2S_INPUT_LENGTH_24;
606 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_ONESAMPLE;
607 audio_format.sample_size = HDMI_AUDIO_SAMPLE_24BITS;
608 audio_format.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
609 core_cfg.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
610 audio_dma.transfer_size = 0x20;
611 break;
612 default:
613 return -EINVAL;
614 }
615
616 switch (params_rate(params)) {
617 case 32000:
618 sample_freq = HDMI_AUDIO_FS_32000;
619 break;
620 case 44100:
621 sample_freq = HDMI_AUDIO_FS_44100;
622 break;
623 case 48000:
624 sample_freq = HDMI_AUDIO_FS_48000;
625 break;
626 default:
627 return -EINVAL;
628 }
629
95a8aeb6 630 err = hdmi_config_audio_acr(ip_data, params_rate(params), &n, &cts);
ad44cc32
RN		 631 if (err < 0)
632 return err;
633
634 /* Audio wrapper config */
635 audio_format.stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL;
636 audio_format.active_chnnls_msk = 0x03;
637 audio_format.type = HDMI_AUDIO_TYPE_LPCM;
638 audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
639 /* Disable start/stop signals of IEC 60958 blocks */
640 audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF;
641
642 audio_dma.block_size = 0xC0;
643 audio_dma.mode = HDMI_AUDIO_TRANSF_DMA;
644 audio_dma.fifo_threshold = 0x20; /* in number of samples */
645
95a8aeb6
M		 646 hdmi_wp_audio_config_dma(ip_data, &audio_dma);
647 hdmi_wp_audio_config_format(ip_data, &audio_format);
ad44cc32
RN		 648
649 /*
650 * I2S config
651 */
652 core_cfg.i2s_cfg.en_high_bitrate_aud = false;
653 /* Only used with high bitrate audio */
654 core_cfg.i2s_cfg.cbit_order = false;
655 /* Serial data and word select should change on sck rising edge */
656 core_cfg.i2s_cfg.sck_edge_mode = HDMI_AUDIO_I2S_SCK_EDGE_RISING;
657 core_cfg.i2s_cfg.vbit = HDMI_AUDIO_I2S_VBIT_FOR_PCM;
658 /* Set I2S word select polarity */
659 core_cfg.i2s_cfg.ws_polarity = HDMI_AUDIO_I2S_WS_POLARITY_LOW_IS_LEFT;
660 core_cfg.i2s_cfg.direction = HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST;
661 /* Set serial data to word select shift. See Phillips spec. */
662 core_cfg.i2s_cfg.shift = HDMI_AUDIO_I2S_FIRST_BIT_SHIFT;
663 /* Enable one of the four available serial data channels */
664 core_cfg.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN;
665
666 /* Core audio config */
667 core_cfg.freq_sample = sample_freq;
668 core_cfg.n = n;
669 core_cfg.cts = cts;
670 if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) {
671 core_cfg.aud_par_busclk = 0;
672 core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_SW;
f15511e2 673 core_cfg.use_mclk = dss_has_feature(FEAT_HDMI_AUDIO_USE_MCLK);
ad44cc32
RN		 674 } else {
675 core_cfg.aud_par_busclk = (((128 * 31) - 1) << 8);
676 core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_HW;
677 core_cfg.use_mclk = true;
ad44cc32 678 }
f15511e2
RN		 679
680 if (core_cfg.use_mclk)
681 core_cfg.mclk_mode = HDMI_AUDIO_MCLK_128FS;
ad44cc32
RN		 682 core_cfg.layout = HDMI_AUDIO_LAYOUT_2CH;
683 core_cfg.en_spdif = false;
684 /* Use sample frequency from channel status word */
685 core_cfg.fs_override = true;
686 /* Enable ACR packets */
687 core_cfg.en_acr_pkt = true;
688 /* Disable direct streaming digital audio */
689 core_cfg.en_dsd_audio = false;
690 /* Use parallel audio interface */
691 core_cfg.en_parallel_aud_input = true;
692
95a8aeb6 693 hdmi_core_audio_config(ip_data, &core_cfg);
ad44cc32
RN		 694
695 /*
696 * Configure packet
697 * info frame audio see doc CEA861-D page 74
698 */
699 aud_if_cfg.db1_coding_type = HDMI_INFOFRAME_AUDIO_DB1CT_FROM_STREAM;
700 aud_if_cfg.db1_channel_count = 2;
701 aud_if_cfg.db2_sample_freq = HDMI_INFOFRAME_AUDIO_DB2SF_FROM_STREAM;
702 aud_if_cfg.db2_sample_size = HDMI_INFOFRAME_AUDIO_DB2SS_FROM_STREAM;
703 aud_if_cfg.db4_channel_alloc = 0x00;
704 aud_if_cfg.db5_downmix_inh = false;
705 aud_if_cfg.db5_lsv = 0;
706
95a8aeb6 707 hdmi_core_audio_infoframe_config(ip_data, &aud_if_cfg);
ad44cc32
RN		 708 return 0;
709}
710
ad44cc32
RN		 711static int hdmi_audio_startup(struct snd_pcm_substream *substream,
712 struct snd_soc_dai *dai)
713{
9e4ed603 714 if (!hdmi.ip_data.cfg.cm.mode) {
ad44cc32
RN		 715 pr_err("Current video settings do not support audio.\n");
716 return -EIO;
717 }
718 return 0;
719}
720
b17ce117
RN		 721static int hdmi_audio_codec_probe(struct snd_soc_codec *codec)
722{
723 struct hdmi_ip_data *priv = &hdmi.ip_data;
724
725 snd_soc_codec_set_drvdata(codec, priv);
726 return 0;
727}
728
ad44cc32 729static struct snd_soc_codec_driver hdmi_audio_codec_drv = {
b17ce117 730 .probe = hdmi_audio_codec_probe,
ad44cc32
RN		 731};
732
733static struct snd_soc_dai_ops hdmi_audio_codec_ops = {
734 .hw_params = hdmi_audio_hw_params,
735 .trigger = hdmi_audio_trigger,
736 .startup = hdmi_audio_startup,
737};
738
739static struct snd_soc_dai_driver hdmi_codec_dai_drv = {
740 .name = "hdmi-audio-codec",
741 .playback = {
742 .channels_min = 2,
743 .channels_max = 2,
744 .rates = SNDRV_PCM_RATE_32000 |
745 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
746 .formats = SNDRV_PCM_FMTBIT_S16_LE |
747 SNDRV_PCM_FMTBIT_S24_LE,
748 },
749 .ops = &hdmi_audio_codec_ops,
750};
82335c4c
RN		 751#endif
752
4fbafaf3
TV		 753static int hdmi_get_clocks(struct platform_device *pdev)
754{
755 struct clk *clk;
756
757 clk = clk_get(&pdev->dev, "sys_clk");
758 if (IS_ERR(clk)) {
759 DSSERR("can't get sys_clk\n");
760 return PTR_ERR(clk);
761 }
762
763 hdmi.sys_clk = clk;
764
4fbafaf3
TV		 765 return 0;
766}
767
768static void hdmi_put_clocks(void)
769{
770 if (hdmi.sys_clk)
771 clk_put(hdmi.sys_clk);
4fbafaf3
TV		 772}
773
38f3daf6
TV		 774static void __init hdmi_probe_pdata(struct platform_device *pdev)
775{
776 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
777 int r, i;
778
779 for (i = 0; i < pdata->num_devices; ++i) {
780 struct omap_dss_device *dssdev = pdata->devices[i];
781
782 if (dssdev->type != OMAP_DISPLAY_TYPE_HDMI)
783 continue;
784
785 r = hdmi_init_display(dssdev);
786 if (r) {
787 DSSERR("device %s init failed: %d\n", dssdev->name, r);
788 continue;
789 }
790
791 r = omap_dss_register_device(dssdev, &pdev->dev, i);
792 if (r)
793 DSSERR("device %s register failed: %d\n",
794 dssdev->name, r);
795 }
796}
797
c3198a5e 798/* HDMI HW IP initialisation */
6e7e8f06 799static int __init omapdss_hdmihw_probe(struct platform_device *pdev)
c3198a5e
M		 800{
801 struct resource *hdmi_mem;
38f3daf6 802 int r;
c3198a5e 803
c3198a5e
M		 804 hdmi.pdev = pdev;
805
806 mutex_init(&hdmi.lock);
807
808 hdmi_mem = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0);
809 if (!hdmi_mem) {
810 DSSERR("can't get IORESOURCE_MEM HDMI\n");
811 return -EINVAL;
812 }
813
814 /* Base address taken from platform */
95a8aeb6
M		 815 hdmi.ip_data.base_wp = ioremap(hdmi_mem->start,
816 resource_size(hdmi_mem));
817 if (!hdmi.ip_data.base_wp) {
c3198a5e
M		 818 DSSERR("can't ioremap WP\n");
819 return -ENOMEM;
820 }
821
4fbafaf3
TV		 822 r = hdmi_get_clocks(pdev);
823 if (r) {
95a8aeb6 824 iounmap(hdmi.ip_data.base_wp);
4fbafaf3
TV		 825 return r;
826 }
827
828 pm_runtime_enable(&pdev->dev);
829
95a8aeb6
M		 830 hdmi.ip_data.core_sys_offset = HDMI_CORE_SYS;
831 hdmi.ip_data.core_av_offset = HDMI_CORE_AV;
832 hdmi.ip_data.pll_offset = HDMI_PLLCTRL;
833 hdmi.ip_data.phy_offset = HDMI_PHY;
834
c3198a5e
M		 835 hdmi_panel_init();
836
e40402cf
TV		 837 dss_debugfs_create_file("hdmi", hdmi_dump_regs);
838
38f3daf6 839 hdmi_probe_pdata(pdev);
35deca3d 840
ad44cc32
RN		 841#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
842 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
843
844 /* Register ASoC codec DAI */
4fbafaf3 845 r = snd_soc_register_codec(&pdev->dev, &hdmi_audio_codec_drv,
ad44cc32 846 &hdmi_codec_dai_drv, 1);
4fbafaf3 847 if (r) {
ad44cc32 848 DSSERR("can't register ASoC HDMI audio codec\n");
4fbafaf3 849 return r;
ad44cc32
RN		 850 }
851#endif
c3198a5e
M		 852 return 0;
853}
854
6e7e8f06 855static int __exit omapdss_hdmihw_remove(struct platform_device *pdev)
c3198a5e 856{
35deca3d
TV		 857 omap_dss_unregister_child_devices(&pdev->dev);
858
c3198a5e
M		 859 hdmi_panel_exit();
860
ad44cc32
RN		 861#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
862 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
863 snd_soc_unregister_codec(&pdev->dev);
864#endif
865
4fbafaf3
TV		 866 pm_runtime_disable(&pdev->dev);
867
868 hdmi_put_clocks();
869
95a8aeb6 870 iounmap(hdmi.ip_data.base_wp);
c3198a5e
M		 871
872 return 0;
873}
874
4fbafaf3
TV		 875static int hdmi_runtime_suspend(struct device *dev)
876{
4fbafaf3
TV		 877 clk_disable(hdmi.sys_clk);
878
879 dispc_runtime_put();
4fbafaf3
TV		 880
881 return 0;
882}
883
884static int hdmi_runtime_resume(struct device *dev)
885{
886 int r;
887
4fbafaf3
TV		 888 r = dispc_runtime_get();
889 if (r < 0)
852f0838 890 return r;
4fbafaf3
TV		 891
892 clk_enable(hdmi.sys_clk);
4fbafaf3
TV		 893
894 return 0;
4fbafaf3
TV		 895}
896
897static const struct dev_pm_ops hdmi_pm_ops = {
898 .runtime_suspend = hdmi_runtime_suspend,
899 .runtime_resume = hdmi_runtime_resume,
900};
901
c3198a5e 902static struct platform_driver omapdss_hdmihw_driver = {
6e7e8f06 903 .remove = __exit_p(omapdss_hdmihw_remove),
c3198a5e
M		 904 .driver = {
905 .name = "omapdss_hdmi",
906 .owner = THIS_MODULE,
4fbafaf3 907 .pm = &hdmi_pm_ops,
c3198a5e
M		 908 },
909};
910
6e7e8f06 911int __init hdmi_init_platform_driver(void)
c3198a5e 912{
61055d4b 913 return platform_driver_probe(&omapdss_hdmihw_driver, omapdss_hdmihw_probe);
c3198a5e
M		 914}
915
6e7e8f06 916void __exit hdmi_uninit_platform_driver(void)
c3198a5e 917{
04c742c3 918 platform_driver_unregister(&omapdss_hdmihw_driver);
c3198a5e 919}
Linux kernel - Deliverables
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