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OMAP: DSS2: check for manager when enabling display
[deliverable/linux.git] / drivers / video / omap2 / dss / hdmi.c
CommitLineData
c3198a5e
M		 1/*
2 * hdmi.c
3 *
4 * HDMI interface DSS driver setting for TI's OMAP4 family of processor.
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
6 * Authors: Yong Zhi
7 * Mythri pk <mythripk@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#define DSS_SUBSYS_NAME "HDMI"
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/err.h>
27#include <linux/io.h>
28#include <linux/interrupt.h>
29#include <linux/mutex.h>
30#include <linux/delay.h>
31#include <linux/string.h>
24e6289c 32#include <linux/platform_device.h>
4fbafaf3
TV		 33#include <linux/pm_runtime.h>
34#include <linux/clk.h>
a0b38cc4 35#include <video/omapdss.h>
ad44cc32
RN		 36#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
37 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
38#include <sound/soc.h>
39#include <sound/pcm_params.h>
40#endif
c3198a5e
M		 41
42#include "dss.h"
43#include "hdmi.h"
ad44cc32 44#include "dss_features.h"
c3198a5e
M		 45
46static struct {
47 struct mutex lock;
48 struct omap_display_platform_data *pdata;
49 struct platform_device *pdev;
50 void __iomem *base_wp; /* HDMI wrapper */
51 int code;
52 int mode;
53 u8 edid[HDMI_EDID_MAX_LENGTH];
54 u8 edid_set;
55 bool custom_set;
56 struct hdmi_config cfg;
4fbafaf3
TV		 57
58 struct clk *sys_clk;
59 struct clk *hdmi_clk;
c3198a5e
M		 60} hdmi;
61
62/*
63 * Logic for the below structure :
64 * user enters the CEA or VESA timings by specifying the HDMI/DVI code.
65 * There is a correspondence between CEA/VESA timing and code, please
66 * refer to section 6.3 in HDMI 1.3 specification for timing code.
67 *
68 * In the below structure, cea_vesa_timings corresponds to all OMAP4
69 * supported CEA and VESA timing values.code_cea corresponds to the CEA
70 * code, It is used to get the timing from cea_vesa_timing array.Similarly
71 * with code_vesa. Code_index is used for back mapping, that is once EDID
72 * is read from the TV, EDID is parsed to find the timing values and then
73 * map it to corresponding CEA or VESA index.
74 */
75
76static const struct hdmi_timings cea_vesa_timings[OMAP_HDMI_TIMINGS_NB] = {
77 { {640, 480, 25200, 96, 16, 48, 2, 10, 33} , 0 , 0},
78 { {1280, 720, 74250, 40, 440, 220, 5, 5, 20}, 1, 1},
79 { {1280, 720, 74250, 40, 110, 220, 5, 5, 20}, 1, 1},
80 { {720, 480, 27027, 62, 16, 60, 6, 9, 30}, 0, 0},
81 { {2880, 576, 108000, 256, 48, 272, 5, 5, 39}, 0, 0},
82 { {1440, 240, 27027, 124, 38, 114, 3, 4, 15}, 0, 0},
83 { {1440, 288, 27000, 126, 24, 138, 3, 2, 19}, 0, 0},
84 { {1920, 540, 74250, 44, 528, 148, 5, 2, 15}, 1, 1},
85 { {1920, 540, 74250, 44, 88, 148, 5, 2, 15}, 1, 1},
86 { {1920, 1080, 148500, 44, 88, 148, 5, 4, 36}, 1, 1},
87 { {720, 576, 27000, 64, 12, 68, 5, 5, 39}, 0, 0},
88 { {1440, 576, 54000, 128, 24, 136, 5, 5, 39}, 0, 0},
89 { {1920, 1080, 148500, 44, 528, 148, 5, 4, 36}, 1, 1},
90 { {2880, 480, 108108, 248, 64, 240, 6, 9, 30}, 0, 0},
91 { {1920, 1080, 74250, 44, 638, 148, 5, 4, 36}, 1, 1},
92 /* VESA From Here */
93 { {640, 480, 25175, 96, 16, 48, 2 , 11, 31}, 0, 0},
94 { {800, 600, 40000, 128, 40, 88, 4 , 1, 23}, 1, 1},
95 { {848, 480, 33750, 112, 16, 112, 8 , 6, 23}, 1, 1},
96 { {1280, 768, 79500, 128, 64, 192, 7 , 3, 20}, 1, 0},
97 { {1280, 800, 83500, 128, 72, 200, 6 , 3, 22}, 1, 0},
98 { {1360, 768, 85500, 112, 64, 256, 6 , 3, 18}, 1, 1},
99 { {1280, 960, 108000, 112, 96, 312, 3 , 1, 36}, 1, 1},
100 { {1280, 1024, 108000, 112, 48, 248, 3 , 1, 38}, 1, 1},
101 { {1024, 768, 65000, 136, 24, 160, 6, 3, 29}, 0, 0},
102 { {1400, 1050, 121750, 144, 88, 232, 4, 3, 32}, 1, 0},
103 { {1440, 900, 106500, 152, 80, 232, 6, 3, 25}, 1, 0},
104 { {1680, 1050, 146250, 176 , 104, 280, 6, 3, 30}, 1, 0},
105 { {1366, 768, 85500, 143, 70, 213, 3, 3, 24}, 1, 1},
106 { {1920, 1080, 148500, 44, 148, 80, 5, 4, 36}, 1, 1},
107 { {1280, 768, 68250, 32, 48, 80, 7, 3, 12}, 0, 1},
108 { {1400, 1050, 101000, 32, 48, 80, 4, 3, 23}, 0, 1},
109 { {1680, 1050, 119000, 32, 48, 80, 6, 3, 21}, 0, 1},
110 { {1280, 800, 79500, 32, 48, 80, 6, 3, 14}, 0, 1},
111 { {1280, 720, 74250, 40, 110, 220, 5, 5, 20}, 1, 1}
112};
113
114/*
115 * This is a static mapping array which maps the timing values
116 * with corresponding CEA / VESA code
117 */
118static const int code_index[OMAP_HDMI_TIMINGS_NB] = {
119 1, 19, 4, 2, 37, 6, 21, 20, 5, 16, 17, 29, 31, 35, 32,
120 /* <--15 CEA 17--> vesa*/
121 4, 9, 0xE, 0x17, 0x1C, 0x27, 0x20, 0x23, 0x10, 0x2A,
122 0X2F, 0x3A, 0X51, 0X52, 0x16, 0x29, 0x39, 0x1B
123};
124
125/*
126 * This is reverse static mapping which maps the CEA / VESA code
127 * to the corresponding timing values
128 */
129static const int code_cea[39] = {
130 -1, 0, 3, 3, 2, 8, 5, 5, -1, -1,
131 -1, -1, -1, -1, -1, -1, 9, 10, 10, 1,
132 7, 6, 6, -1, -1, -1, -1, -1, -1, 11,
133 11, 12, 14, -1, -1, 13, 13, 4, 4
134};
135
136static const int code_vesa[85] = {
137 -1, -1, -1, -1, 15, -1, -1, -1, -1, 16,
138 -1, -1, -1, -1, 17, -1, 23, -1, -1, -1,
139 -1, -1, 29, 18, -1, -1, -1, 32, 19, -1,
140 -1, -1, 21, -1, -1, 22, -1, -1, -1, 20,
141 -1, 30, 24, -1, -1, -1, -1, 25, -1, -1,
142 -1, -1, -1, -1, -1, -1, -1, 31, 26, -1,
143 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
144 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
145 -1, 27, 28, -1, 33};
146
147static const u8 edid_header[8] = {0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0};
148
149static inline void hdmi_write_reg(const struct hdmi_reg idx, u32 val)
150{
151 __raw_writel(val, hdmi.base_wp + idx.idx);
152}
153
154static inline u32 hdmi_read_reg(const struct hdmi_reg idx)
155{
156 return __raw_readl(hdmi.base_wp + idx.idx);
157}
158
159static inline int hdmi_wait_for_bit_change(const struct hdmi_reg idx,
160 int b2, int b1, u32 val)
161{
162 u32 t = 0;
163 while (val != REG_GET(idx, b2, b1)) {
164 udelay(1);
165 if (t++ > 10000)
166 return !val;
167 }
168 return val;
169}
170
4fbafaf3
TV		 171static int hdmi_runtime_get(void)
172{
173 int r;
174
175 DSSDBG("hdmi_runtime_get\n");
176
177 r = pm_runtime_get_sync(&hdmi.pdev->dev);
178 WARN_ON(r < 0);
179 return r < 0 ? r : 0;
180}
181
182static void hdmi_runtime_put(void)
183{
184 int r;
185
186 DSSDBG("hdmi_runtime_put\n");
187
188 r = pm_runtime_put(&hdmi.pdev->dev);
189 WARN_ON(r < 0);
190}
191
c3198a5e
M		 192int hdmi_init_display(struct omap_dss_device *dssdev)
193{
194 DSSDBG("init_display\n");
195
196 return 0;
197}
198
199static int hdmi_pll_init(enum hdmi_clk_refsel refsel, int dcofreq,
200 struct hdmi_pll_info *fmt, u16 sd)
201{
202 u32 r;
203
204 /* PLL start always use manual mode */
205 REG_FLD_MOD(PLLCTRL_PLL_CONTROL, 0x0, 0, 0);
206
207 r = hdmi_read_reg(PLLCTRL_CFG1);
208 r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */
209 r = FLD_MOD(r, fmt->regn, 8, 1); /* CFG1_PLL_REGN */
210
211 hdmi_write_reg(PLLCTRL_CFG1, r);
212
213 r = hdmi_read_reg(PLLCTRL_CFG2);
214
215 r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */
216 r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */
217 r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */
218
219 if (dcofreq) {
220 /* divider programming for frequency beyond 1000Mhz */
221 REG_FLD_MOD(PLLCTRL_CFG3, sd, 17, 10);
222 r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */
223 } else {
224 r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */
225 }
226
227 hdmi_write_reg(PLLCTRL_CFG2, r);
228
229 r = hdmi_read_reg(PLLCTRL_CFG4);
230 r = FLD_MOD(r, fmt->regm2, 24, 18);
231 r = FLD_MOD(r, fmt->regmf, 17, 0);
232
233 hdmi_write_reg(PLLCTRL_CFG4, r);
234
235 /* go now */
236 REG_FLD_MOD(PLLCTRL_PLL_GO, 0x1, 0, 0);
237
238 /* wait for bit change */
239 if (hdmi_wait_for_bit_change(PLLCTRL_PLL_GO, 0, 0, 1) != 1) {
240 DSSERR("PLL GO bit not set\n");
241 return -ETIMEDOUT;
242 }
243
244 /* Wait till the lock bit is set in PLL status */
245 if (hdmi_wait_for_bit_change(PLLCTRL_PLL_STATUS, 1, 1, 1) != 1) {
246 DSSWARN("cannot lock PLL\n");
247 DSSWARN("CFG1 0x%x\n",
248 hdmi_read_reg(PLLCTRL_CFG1));
249 DSSWARN("CFG2 0x%x\n",
250 hdmi_read_reg(PLLCTRL_CFG2));
251 DSSWARN("CFG4 0x%x\n",
252 hdmi_read_reg(PLLCTRL_CFG4));
253 return -ETIMEDOUT;
254 }
255
256 DSSDBG("PLL locked!\n");
257
258 return 0;
259}
260
261/* PHY_PWR_CMD */
262static int hdmi_set_phy_pwr(enum hdmi_phy_pwr val)
263{
264 /* Command for power control of HDMI PHY */
265 REG_FLD_MOD(HDMI_WP_PWR_CTRL, val, 7, 6);
266
267 /* Status of the power control of HDMI PHY */
268 if (hdmi_wait_for_bit_change(HDMI_WP_PWR_CTRL, 5, 4, val) != val) {
269 DSSERR("Failed to set PHY power mode to %d\n", val);
270 return -ETIMEDOUT;
271 }
272
273 return 0;
274}
275
276/* PLL_PWR_CMD */
277static int hdmi_set_pll_pwr(enum hdmi_pll_pwr val)
278{
279 /* Command for power control of HDMI PLL */
280 REG_FLD_MOD(HDMI_WP_PWR_CTRL, val, 3, 2);
281
282 /* wait till PHY_PWR_STATUS is set */
283 if (hdmi_wait_for_bit_change(HDMI_WP_PWR_CTRL, 1, 0, val) != val) {
284 DSSERR("Failed to set PHY_PWR_STATUS\n");
285 return -ETIMEDOUT;
286 }
287
288 return 0;
289}
290
291static int hdmi_pll_reset(void)
292{
293 /* SYSRESET controlled by power FSM */
294 REG_FLD_MOD(PLLCTRL_PLL_CONTROL, 0x0, 3, 3);
295
296 /* READ 0x0 reset is in progress */
297 if (hdmi_wait_for_bit_change(PLLCTRL_PLL_STATUS, 0, 0, 1) != 1) {
298 DSSERR("Failed to sysreset PLL\n");
299 return -ETIMEDOUT;
300 }
301
302 return 0;
303}
304
305static int hdmi_phy_init(void)
306{
307 u16 r = 0;
308
309 r = hdmi_set_phy_pwr(HDMI_PHYPWRCMD_LDOON);
310 if (r)
311 return r;
312
313 r = hdmi_set_phy_pwr(HDMI_PHYPWRCMD_TXON);
314 if (r)
315 return r;
316
317 /*
318 * Read address 0 in order to get the SCP reset done completed
319 * Dummy access performed to make sure reset is done
320 */
321 hdmi_read_reg(HDMI_TXPHY_TX_CTRL);
322
323 /*
324 * Write to phy address 0 to configure the clock
325 * use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field
326 */
327 REG_FLD_MOD(HDMI_TXPHY_TX_CTRL, 0x1, 31, 30);
328
329 /* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */
330 hdmi_write_reg(HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000);
331
332 /* Setup max LDO voltage */
333 REG_FLD_MOD(HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0);
334
335 /* Write to phy address 3 to change the polarity control */
336 REG_FLD_MOD(HDMI_TXPHY_PAD_CFG_CTRL, 0x1, 27, 27);
337
338 return 0;
339}
340
c3198a5e
M		 341static int hdmi_pll_program(struct hdmi_pll_info *fmt)
342{
343 u16 r = 0;
344 enum hdmi_clk_refsel refsel;
345
c3198a5e
M		 346 r = hdmi_set_pll_pwr(HDMI_PLLPWRCMD_ALLOFF);
347 if (r)
348 return r;
349
350 r = hdmi_set_pll_pwr(HDMI_PLLPWRCMD_BOTHON_ALLCLKS);
351 if (r)
352 return r;
353
354 r = hdmi_pll_reset();
355 if (r)
356 return r;
357
358 refsel = HDMI_REFSEL_SYSCLK;
359
360 r = hdmi_pll_init(refsel, fmt->dcofreq, fmt, fmt->regsd);
361 if (r)
362 return r;
363
364 return 0;
365}
366
367static void hdmi_phy_off(void)
368{
369 hdmi_set_phy_pwr(HDMI_PHYPWRCMD_OFF);
370}
371
372static int hdmi_core_ddc_edid(u8 *pedid, int ext)
373{
374 u32 i, j;
375 char checksum = 0;
376 u32 offset = 0;
377
378 /* Turn on CLK for DDC */
379 REG_FLD_MOD(HDMI_CORE_AV_DPD, 0x7, 2, 0);
380
381 /*
382 * SW HACK : Without the Delay DDC(i2c bus) reads 0 values /
383 * right shifted values( The behavior is not consistent and seen only
384 * with some TV's)
385 */
386 usleep_range(800, 1000);
387
388 if (!ext) {
389 /* Clk SCL Devices */
390 REG_FLD_MOD(HDMI_CORE_DDC_CMD, 0xA, 3, 0);
391
392 /* HDMI_CORE_DDC_STATUS_IN_PROG */
393 if (hdmi_wait_for_bit_change(HDMI_CORE_DDC_STATUS,
394 4, 4, 0) != 0) {
395 DSSERR("Failed to program DDC\n");
396 return -ETIMEDOUT;
397 }
398
399 /* Clear FIFO */
400 REG_FLD_MOD(HDMI_CORE_DDC_CMD, 0x9, 3, 0);
401
402 /* HDMI_CORE_DDC_STATUS_IN_PROG */
403 if (hdmi_wait_for_bit_change(HDMI_CORE_DDC_STATUS,
404 4, 4, 0) != 0) {
405 DSSERR("Failed to program DDC\n");
406 return -ETIMEDOUT;
407 }
408
409 } else {
410 if (ext % 2 != 0)
411 offset = 0x80;
412 }
413
414 /* Load Segment Address Register */
415 REG_FLD_MOD(HDMI_CORE_DDC_SEGM, ext/2, 7, 0);
416
417 /* Load Slave Address Register */
418 REG_FLD_MOD(HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1);
419
420 /* Load Offset Address Register */
421 REG_FLD_MOD(HDMI_CORE_DDC_OFFSET, offset, 7, 0);
422
423 /* Load Byte Count */
424 REG_FLD_MOD(HDMI_CORE_DDC_COUNT1, 0x80, 7, 0);
425 REG_FLD_MOD(HDMI_CORE_DDC_COUNT2, 0x0, 1, 0);
426
427 /* Set DDC_CMD */
428 if (ext)
429 REG_FLD_MOD(HDMI_CORE_DDC_CMD, 0x4, 3, 0);
430 else
431 REG_FLD_MOD(HDMI_CORE_DDC_CMD, 0x2, 3, 0);
432
433 /* HDMI_CORE_DDC_STATUS_BUS_LOW */
434 if (REG_GET(HDMI_CORE_DDC_STATUS, 6, 6) == 1) {
435 DSSWARN("I2C Bus Low?\n");
436 return -EIO;
437 }
438 /* HDMI_CORE_DDC_STATUS_NO_ACK */
439 if (REG_GET(HDMI_CORE_DDC_STATUS, 5, 5) == 1) {
440 DSSWARN("I2C No Ack\n");
441 return -EIO;
442 }
443
444 i = ext * 128;
445 j = 0;
446 while (((REG_GET(HDMI_CORE_DDC_STATUS, 4, 4) == 1) ||
447 (REG_GET(HDMI_CORE_DDC_STATUS, 2, 2) == 0)) &&
448 j < 128) {
449
450 if (REG_GET(HDMI_CORE_DDC_STATUS, 2, 2) == 0) {
451 /* FIFO not empty */
452 pedid[i++] = REG_GET(HDMI_CORE_DDC_DATA, 7, 0);
453 j++;
454 }
455 }
456
457 for (j = 0; j < 128; j++)
458 checksum += pedid[j];
459
460 if (checksum != 0) {
461 DSSERR("E-EDID checksum failed!!\n");
462 return -EIO;
463 }
464
465 return 0;
466}
467
468static int read_edid(u8 *pedid, u16 max_length)
469{
470 int r = 0, n = 0, i = 0;
471 int max_ext_blocks = (max_length / 128) - 1;
472
473 r = hdmi_core_ddc_edid(pedid, 0);
474 if (r) {
475 return r;
476 } else {
477 n = pedid[0x7e];
478
479 /*
480 * README: need to comply with max_length set by the caller.
481 * Better implementation should be to allocate necessary
482 * memory to store EDID according to nb_block field found
483 * in first block
484 */
485 if (n > max_ext_blocks)
486 n = max_ext_blocks;
487
488 for (i = 1; i <= n; i++) {
489 r = hdmi_core_ddc_edid(pedid, i);
490 if (r)
491 return r;
492 }
493 }
494 return 0;
495}
496
497static int get_timings_index(void)
498{
499 int code;
500
501 if (hdmi.mode == 0)
502 code = code_vesa[hdmi.code];
503 else
504 code = code_cea[hdmi.code];
505
506 if (code == -1) {
507 /* HDMI code 4 corresponds to 640 * 480 VGA */
508 hdmi.code = 4;
509 /* DVI mode 1 corresponds to HDMI 0 to DVI */
510 hdmi.mode = HDMI_DVI;
511
512 code = code_vesa[hdmi.code];
513 }
514 return code;
515}
516
517static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing)
518{
519 int i = 0, code = -1, temp_vsync = 0, temp_hsync = 0;
520 int timing_vsync = 0, timing_hsync = 0;
521 struct omap_video_timings temp;
522 struct hdmi_cm cm = {-1};
523 DSSDBG("hdmi_get_code\n");
524
525 for (i = 0; i < OMAP_HDMI_TIMINGS_NB; i++) {
526 temp = cea_vesa_timings[i].timings;
527 if ((temp.pixel_clock == timing->pixel_clock) &&
528 (temp.x_res == timing->x_res) &&
529 (temp.y_res == timing->y_res)) {
530
531 temp_hsync = temp.hfp + temp.hsw + temp.hbp;
532 timing_hsync = timing->hfp + timing->hsw + timing->hbp;
533 temp_vsync = temp.vfp + temp.vsw + temp.vbp;
534 timing_vsync = timing->vfp + timing->vsw + timing->vbp;
535
536 DSSDBG("temp_hsync = %d , temp_vsync = %d"
537 "timing_hsync = %d, timing_vsync = %d\n",
538 temp_hsync, temp_hsync,
539 timing_hsync, timing_vsync);
540
541 if ((temp_hsync == timing_hsync) &&
542 (temp_vsync == timing_vsync)) {
543 code = i;
544 cm.code = code_index[i];
545 if (code < 14)
546 cm.mode = HDMI_HDMI;
547 else
548 cm.mode = HDMI_DVI;
549 DSSDBG("Hdmi_code = %d mode = %d\n",
550 cm.code, cm.mode);
551 break;
552 }
553 }
554 }
555
556 return cm;
557}
558
559static void get_horz_vert_timing_info(int current_descriptor_addrs, u8 *edid ,
560 struct omap_video_timings *timings)
561{
562 /* X and Y resolution */
563 timings->x_res = (((edid[current_descriptor_addrs + 4] & 0xF0) << 4) |
564 edid[current_descriptor_addrs + 2]);
565 timings->y_res = (((edid[current_descriptor_addrs + 7] & 0xF0) << 4) |
566 edid[current_descriptor_addrs + 5]);
567
568 timings->pixel_clock = ((edid[current_descriptor_addrs + 1] << 8) |
569 edid[current_descriptor_addrs]);
570
571 timings->pixel_clock = 10 * timings->pixel_clock;
572
573 /* HORIZONTAL FRONT PORCH */
574 timings->hfp = edid[current_descriptor_addrs + 8] |
575 ((edid[current_descriptor_addrs + 11] & 0xc0) << 2);
576 /* HORIZONTAL SYNC WIDTH */
577 timings->hsw = edid[current_descriptor_addrs + 9] |
578 ((edid[current_descriptor_addrs + 11] & 0x30) << 4);
579 /* HORIZONTAL BACK PORCH */
580 timings->hbp = (((edid[current_descriptor_addrs + 4] & 0x0F) << 8) |
581 edid[current_descriptor_addrs + 3]) -
582 (timings->hfp + timings->hsw);
583 /* VERTICAL FRONT PORCH */
584 timings->vfp = ((edid[current_descriptor_addrs + 10] & 0xF0) >> 4) |
585 ((edid[current_descriptor_addrs + 11] & 0x0f) << 2);
586 /* VERTICAL SYNC WIDTH */
587 timings->vsw = (edid[current_descriptor_addrs + 10] & 0x0F) |
588 ((edid[current_descriptor_addrs + 11] & 0x03) << 4);
589 /* VERTICAL BACK PORCH */
590 timings->vbp = (((edid[current_descriptor_addrs + 7] & 0x0F) << 8) |
591 edid[current_descriptor_addrs + 6]) -
592 (timings->vfp + timings->vsw);
593
594}
595
596/* Description : This function gets the resolution information from EDID */
597static void get_edid_timing_data(u8 *edid)
598{
599 u8 count;
600 u16 current_descriptor_addrs;
601 struct hdmi_cm cm;
602 struct omap_video_timings edid_timings;
603
25985edc 604 /* search block 0, there are 4 DTDs arranged in priority order */
c3198a5e
M		 605 for (count = 0; count < EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR; count++) {
606 current_descriptor_addrs =
607 EDID_DESCRIPTOR_BLOCK0_ADDRESS +
608 count * EDID_TIMING_DESCRIPTOR_SIZE;
609 get_horz_vert_timing_info(current_descriptor_addrs,
610 edid, &edid_timings);
611 cm = hdmi_get_code(&edid_timings);
612 DSSDBG("Block0[%d] value matches code = %d , mode = %d\n",
613 count, cm.code, cm.mode);
614 if (cm.code == -1) {
615 continue;
616 } else {
617 hdmi.code = cm.code;
618 hdmi.mode = cm.mode;
619 DSSDBG("code = %d , mode = %d\n",
620 hdmi.code, hdmi.mode);
621 return;
622 }
623 }
624 if (edid[0x7e] != 0x00) {
625 for (count = 0; count < EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR;
626 count++) {
627 current_descriptor_addrs =
628 EDID_DESCRIPTOR_BLOCK1_ADDRESS +
629 count * EDID_TIMING_DESCRIPTOR_SIZE;
630 get_horz_vert_timing_info(current_descriptor_addrs,
631 edid, &edid_timings);
632 cm = hdmi_get_code(&edid_timings);
633 DSSDBG("Block1[%d] value matches code = %d, mode = %d",
634 count, cm.code, cm.mode);
635 if (cm.code == -1) {
636 continue;
637 } else {
638 hdmi.code = cm.code;
639 hdmi.mode = cm.mode;
640 DSSDBG("code = %d , mode = %d\n",
641 hdmi.code, hdmi.mode);
642 return;
643 }
644 }
645 }
646
647 DSSINFO("no valid timing found , falling back to VGA\n");
648 hdmi.code = 4; /* setting default value of 640 480 VGA */
649 hdmi.mode = HDMI_DVI;
650}
651
652static void hdmi_read_edid(struct omap_video_timings *dp)
653{
654 int ret = 0, code;
655
656 memset(hdmi.edid, 0, HDMI_EDID_MAX_LENGTH);
657
658 if (!hdmi.edid_set)
659 ret = read_edid(hdmi.edid, HDMI_EDID_MAX_LENGTH);
660
661 if (!ret) {
662 if (!memcmp(hdmi.edid, edid_header, sizeof(edid_header))) {
663 /* search for timings of default resolution */
664 get_edid_timing_data(hdmi.edid);
665 hdmi.edid_set = true;
666 }
667 } else {
668 DSSWARN("failed to read E-EDID\n");
669 }
670
671 if (!hdmi.edid_set) {
672 DSSINFO("fallback to VGA\n");
673 hdmi.code = 4; /* setting default value of 640 480 VGA */
674 hdmi.mode = HDMI_DVI;
675 }
676
677 code = get_timings_index();
678
679 *dp = cea_vesa_timings[code].timings;
680}
681
682static void hdmi_core_init(struct hdmi_core_video_config *video_cfg,
683 struct hdmi_core_infoframe_avi *avi_cfg,
684 struct hdmi_core_packet_enable_repeat *repeat_cfg)
685{
686 DSSDBG("Enter hdmi_core_init\n");
687
688 /* video core */
689 video_cfg->ip_bus_width = HDMI_INPUT_8BIT;
690 video_cfg->op_dither_truc = HDMI_OUTPUTTRUNCATION_8BIT;
691 video_cfg->deep_color_pkt = HDMI_DEEPCOLORPACKECTDISABLE;
692 video_cfg->pkt_mode = HDMI_PACKETMODERESERVEDVALUE;
693 video_cfg->hdmi_dvi = HDMI_DVI;
694 video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK;
695
696 /* info frame */
697 avi_cfg->db1_format = 0;
698 avi_cfg->db1_active_info = 0;
699 avi_cfg->db1_bar_info_dv = 0;
700 avi_cfg->db1_scan_info = 0;
701 avi_cfg->db2_colorimetry = 0;
702 avi_cfg->db2_aspect_ratio = 0;
703 avi_cfg->db2_active_fmt_ar = 0;
704 avi_cfg->db3_itc = 0;
705 avi_cfg->db3_ec = 0;
706 avi_cfg->db3_q_range = 0;
707 avi_cfg->db3_nup_scaling = 0;
708 avi_cfg->db4_videocode = 0;
709 avi_cfg->db5_pixel_repeat = 0;
710 avi_cfg->db6_7_line_eoftop = 0 ;
711 avi_cfg->db8_9_line_sofbottom = 0;
712 avi_cfg->db10_11_pixel_eofleft = 0;
713 avi_cfg->db12_13_pixel_sofright = 0;
714
715 /* packet enable and repeat */
716 repeat_cfg->audio_pkt = 0;
717 repeat_cfg->audio_pkt_repeat = 0;
718 repeat_cfg->avi_infoframe = 0;
719 repeat_cfg->avi_infoframe_repeat = 0;
720 repeat_cfg->gen_cntrl_pkt = 0;
721 repeat_cfg->gen_cntrl_pkt_repeat = 0;
722 repeat_cfg->generic_pkt = 0;
723 repeat_cfg->generic_pkt_repeat = 0;
724}
725
726static void hdmi_core_powerdown_disable(void)
727{
728 DSSDBG("Enter hdmi_core_powerdown_disable\n");
729 REG_FLD_MOD(HDMI_CORE_CTRL1, 0x0, 0, 0);
730}
731
732static void hdmi_core_swreset_release(void)
733{
734 DSSDBG("Enter hdmi_core_swreset_release\n");
735 REG_FLD_MOD(HDMI_CORE_SYS_SRST, 0x0, 0, 0);
736}
737
738static void hdmi_core_swreset_assert(void)
739{
740 DSSDBG("Enter hdmi_core_swreset_assert\n");
741 REG_FLD_MOD(HDMI_CORE_SYS_SRST, 0x1, 0, 0);
742}
743
744/* DSS_HDMI_CORE_VIDEO_CONFIG */
745static void hdmi_core_video_config(struct hdmi_core_video_config *cfg)
746{
747 u32 r = 0;
748
749 /* sys_ctrl1 default configuration not tunable */
750 r = hdmi_read_reg(HDMI_CORE_CTRL1);
751 r = FLD_MOD(r, HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC, 5, 5);
752 r = FLD_MOD(r, HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC, 4, 4);
753 r = FLD_MOD(r, HDMI_CORE_CTRL1_BSEL_24BITBUS, 2, 2);
754 r = FLD_MOD(r, HDMI_CORE_CTRL1_EDGE_RISINGEDGE, 1, 1);
755 hdmi_write_reg(HDMI_CORE_CTRL1, r);
756
757 REG_FLD_MOD(HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6);
758
759 /* Vid_Mode */
760 r = hdmi_read_reg(HDMI_CORE_SYS_VID_MODE);
761
762 /* dither truncation configuration */
763 if (cfg->op_dither_truc > HDMI_OUTPUTTRUNCATION_12BIT) {
764 r = FLD_MOD(r, cfg->op_dither_truc - 3, 7, 6);
765 r = FLD_MOD(r, 1, 5, 5);
766 } else {
767 r = FLD_MOD(r, cfg->op_dither_truc, 7, 6);
768 r = FLD_MOD(r, 0, 5, 5);
769 }
770 hdmi_write_reg(HDMI_CORE_SYS_VID_MODE, r);
771
772 /* HDMI_Ctrl */
773 r = hdmi_read_reg(HDMI_CORE_AV_HDMI_CTRL);
774 r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6);
775 r = FLD_MOD(r, cfg->pkt_mode, 5, 3);
776 r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0);
777 hdmi_write_reg(HDMI_CORE_AV_HDMI_CTRL, r);
778
779 /* TMDS_CTRL */
780 REG_FLD_MOD(HDMI_CORE_SYS_TMDS_CTRL,
781 cfg->tclk_sel_clkmult, 6, 5);
782}
783
784static void hdmi_core_aux_infoframe_avi_config(
785 struct hdmi_core_infoframe_avi info_avi)
786{
787 u32 val;
788 char sum = 0, checksum = 0;
789
790 sum += 0x82 + 0x002 + 0x00D;
791 hdmi_write_reg(HDMI_CORE_AV_AVI_TYPE, 0x082);
792 hdmi_write_reg(HDMI_CORE_AV_AVI_VERS, 0x002);
793 hdmi_write_reg(HDMI_CORE_AV_AVI_LEN, 0x00D);
794
795 val = (info_avi.db1_format << 5) |
796 (info_avi.db1_active_info << 4) |
797 (info_avi.db1_bar_info_dv << 2) |
798 (info_avi.db1_scan_info);
799 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(0), val);
800 sum += val;
801
802 val = (info_avi.db2_colorimetry << 6) |
803 (info_avi.db2_aspect_ratio << 4) |
804 (info_avi.db2_active_fmt_ar);
805 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(1), val);
806 sum += val;
807
808 val = (info_avi.db3_itc << 7) |
809 (info_avi.db3_ec << 4) |
810 (info_avi.db3_q_range << 2) |
811 (info_avi.db3_nup_scaling);
812 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(2), val);
813 sum += val;
814
815 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(3), info_avi.db4_videocode);
816 sum += info_avi.db4_videocode;
817
818 val = info_avi.db5_pixel_repeat;
819 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(4), val);
820 sum += val;
821
822 val = info_avi.db6_7_line_eoftop & 0x00FF;
823 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(5), val);
824 sum += val;
825
826 val = ((info_avi.db6_7_line_eoftop >> 8) & 0x00FF);
827 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(6), val);
828 sum += val;
829
830 val = info_avi.db8_9_line_sofbottom & 0x00FF;
831 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(7), val);
832 sum += val;
833
834 val = ((info_avi.db8_9_line_sofbottom >> 8) & 0x00FF);
835 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(8), val);
836 sum += val;
837
838 val = info_avi.db10_11_pixel_eofleft & 0x00FF;
839 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(9), val);
840 sum += val;
841
842 val = ((info_avi.db10_11_pixel_eofleft >> 8) & 0x00FF);
843 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(10), val);
844 sum += val;
845
846 val = info_avi.db12_13_pixel_sofright & 0x00FF;
847 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(11), val);
848 sum += val;
849
850 val = ((info_avi.db12_13_pixel_sofright >> 8) & 0x00FF);
851 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(12), val);
852 sum += val;
853
854 checksum = 0x100 - sum;
855 hdmi_write_reg(HDMI_CORE_AV_AVI_CHSUM, checksum);
856}
857
858static void hdmi_core_av_packet_config(
859 struct hdmi_core_packet_enable_repeat repeat_cfg)
860{
861 /* enable/repeat the infoframe */
862 hdmi_write_reg(HDMI_CORE_AV_PB_CTRL1,
863 (repeat_cfg.audio_pkt << 5) |
864 (repeat_cfg.audio_pkt_repeat << 4) |
865 (repeat_cfg.avi_infoframe << 1) |
866 (repeat_cfg.avi_infoframe_repeat));
867
868 /* enable/repeat the packet */
869 hdmi_write_reg(HDMI_CORE_AV_PB_CTRL2,
870 (repeat_cfg.gen_cntrl_pkt << 3) |
871 (repeat_cfg.gen_cntrl_pkt_repeat << 2) |
872 (repeat_cfg.generic_pkt << 1) |
873 (repeat_cfg.generic_pkt_repeat));
874}
875
876static void hdmi_wp_init(struct omap_video_timings *timings,
877 struct hdmi_video_format *video_fmt,
878 struct hdmi_video_interface *video_int)
879{
880 DSSDBG("Enter hdmi_wp_init\n");
881
882 timings->hbp = 0;
883 timings->hfp = 0;
884 timings->hsw = 0;
885 timings->vbp = 0;
886 timings->vfp = 0;
887 timings->vsw = 0;
888
889 video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444;
890 video_fmt->y_res = 0;
891 video_fmt->x_res = 0;
892
893 video_int->vsp = 0;
894 video_int->hsp = 0;
895
896 video_int->interlacing = 0;
897 video_int->tm = 0; /* HDMI_TIMING_SLAVE */
898
899}
900
901static void hdmi_wp_video_start(bool start)
902{
903 REG_FLD_MOD(HDMI_WP_VIDEO_CFG, start, 31, 31);
904}
905
906static void hdmi_wp_video_init_format(struct hdmi_video_format *video_fmt,
907 struct omap_video_timings *timings, struct hdmi_config *param)
908{
909 DSSDBG("Enter hdmi_wp_video_init_format\n");
910
911 video_fmt->y_res = param->timings.timings.y_res;
912 video_fmt->x_res = param->timings.timings.x_res;
913
914 timings->hbp = param->timings.timings.hbp;
915 timings->hfp = param->timings.timings.hfp;
916 timings->hsw = param->timings.timings.hsw;
917 timings->vbp = param->timings.timings.vbp;
918 timings->vfp = param->timings.timings.vfp;
919 timings->vsw = param->timings.timings.vsw;
920}
921
922static void hdmi_wp_video_config_format(
923 struct hdmi_video_format *video_fmt)
924{
925 u32 l = 0;
926
927 REG_FLD_MOD(HDMI_WP_VIDEO_CFG, video_fmt->packing_mode, 10, 8);
928
929 l |= FLD_VAL(video_fmt->y_res, 31, 16);
930 l |= FLD_VAL(video_fmt->x_res, 15, 0);
931 hdmi_write_reg(HDMI_WP_VIDEO_SIZE, l);
932}
933
934static void hdmi_wp_video_config_interface(
935 struct hdmi_video_interface *video_int)
936{
937 u32 r;
938 DSSDBG("Enter hdmi_wp_video_config_interface\n");
939
940 r = hdmi_read_reg(HDMI_WP_VIDEO_CFG);
941 r = FLD_MOD(r, video_int->vsp, 7, 7);
942 r = FLD_MOD(r, video_int->hsp, 6, 6);
943 r = FLD_MOD(r, video_int->interlacing, 3, 3);
944 r = FLD_MOD(r, video_int->tm, 1, 0);
945 hdmi_write_reg(HDMI_WP_VIDEO_CFG, r);
946}
947
948static void hdmi_wp_video_config_timing(
949 struct omap_video_timings *timings)
950{
951 u32 timing_h = 0;
952 u32 timing_v = 0;
953
954 DSSDBG("Enter hdmi_wp_video_config_timing\n");
955
956 timing_h |= FLD_VAL(timings->hbp, 31, 20);
957 timing_h |= FLD_VAL(timings->hfp, 19, 8);
958 timing_h |= FLD_VAL(timings->hsw, 7, 0);
959 hdmi_write_reg(HDMI_WP_VIDEO_TIMING_H, timing_h);
960
961 timing_v |= FLD_VAL(timings->vbp, 31, 20);
962 timing_v |= FLD_VAL(timings->vfp, 19, 8);
963 timing_v |= FLD_VAL(timings->vsw, 7, 0);
964 hdmi_write_reg(HDMI_WP_VIDEO_TIMING_V, timing_v);
965}
966
967static void hdmi_basic_configure(struct hdmi_config *cfg)
968{
969 /* HDMI */
970 struct omap_video_timings video_timing;
971 struct hdmi_video_format video_format;
972 struct hdmi_video_interface video_interface;
973 /* HDMI core */
974 struct hdmi_core_infoframe_avi avi_cfg;
975 struct hdmi_core_video_config v_core_cfg;
976 struct hdmi_core_packet_enable_repeat repeat_cfg;
977
978 hdmi_wp_init(&video_timing, &video_format,
979 &video_interface);
980
981 hdmi_core_init(&v_core_cfg,
982 &avi_cfg,
983 &repeat_cfg);
984
985 hdmi_wp_video_init_format(&video_format,
986 &video_timing, cfg);
987
988 hdmi_wp_video_config_timing(&video_timing);
989
990 /* video config */
991 video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
992
993 hdmi_wp_video_config_format(&video_format);
994
995 video_interface.vsp = cfg->timings.vsync_pol;
996 video_interface.hsp = cfg->timings.hsync_pol;
997 video_interface.interlacing = cfg->interlace;
998 video_interface.tm = 1 ; /* HDMI_TIMING_MASTER_24BIT */
999
1000 hdmi_wp_video_config_interface(&video_interface);
1001
1002 /*
1003 * configure core video part
1004 * set software reset in the core
1005 */
1006 hdmi_core_swreset_assert();
1007
1008 /* power down off */
1009 hdmi_core_powerdown_disable();
1010
1011 v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL;
1012 v_core_cfg.hdmi_dvi = cfg->cm.mode;
1013
1014 hdmi_core_video_config(&v_core_cfg);
1015
1016 /* release software reset in the core */
1017 hdmi_core_swreset_release();
1018
1019 /*
1020 * configure packet
1021 * info frame video see doc CEA861-D page 65
1022 */
1023 avi_cfg.db1_format = HDMI_INFOFRAME_AVI_DB1Y_RGB;
1024 avi_cfg.db1_active_info =
1025 HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF;
1026 avi_cfg.db1_bar_info_dv = HDMI_INFOFRAME_AVI_DB1B_NO;
1027 avi_cfg.db1_scan_info = HDMI_INFOFRAME_AVI_DB1S_0;
1028 avi_cfg.db2_colorimetry = HDMI_INFOFRAME_AVI_DB2C_NO;
1029 avi_cfg.db2_aspect_ratio = HDMI_INFOFRAME_AVI_DB2M_NO;
1030 avi_cfg.db2_active_fmt_ar = HDMI_INFOFRAME_AVI_DB2R_SAME;
1031 avi_cfg.db3_itc = HDMI_INFOFRAME_AVI_DB3ITC_NO;
1032 avi_cfg.db3_ec = HDMI_INFOFRAME_AVI_DB3EC_XVYUV601;
1033 avi_cfg.db3_q_range = HDMI_INFOFRAME_AVI_DB3Q_DEFAULT;
1034 avi_cfg.db3_nup_scaling = HDMI_INFOFRAME_AVI_DB3SC_NO;
1035 avi_cfg.db4_videocode = cfg->cm.code;
1036 avi_cfg.db5_pixel_repeat = HDMI_INFOFRAME_AVI_DB5PR_NO;
1037 avi_cfg.db6_7_line_eoftop = 0;
1038 avi_cfg.db8_9_line_sofbottom = 0;
1039 avi_cfg.db10_11_pixel_eofleft = 0;
1040 avi_cfg.db12_13_pixel_sofright = 0;
1041
1042 hdmi_core_aux_infoframe_avi_config(avi_cfg);
1043
1044 /* enable/repeat the infoframe */
1045 repeat_cfg.avi_infoframe = HDMI_PACKETENABLE;
1046 repeat_cfg.avi_infoframe_repeat = HDMI_PACKETREPEATON;
1047 /* wakeup */
1048 repeat_cfg.audio_pkt = HDMI_PACKETENABLE;
1049 repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON;
1050 hdmi_core_av_packet_config(repeat_cfg);
1051}
1052
1053static void update_hdmi_timings(struct hdmi_config *cfg,
1054 struct omap_video_timings *timings, int code)
1055{
1056 cfg->timings.timings.x_res = timings->x_res;
1057 cfg->timings.timings.y_res = timings->y_res;
1058 cfg->timings.timings.hbp = timings->hbp;
1059 cfg->timings.timings.hfp = timings->hfp;
1060 cfg->timings.timings.hsw = timings->hsw;
1061 cfg->timings.timings.vbp = timings->vbp;
1062 cfg->timings.timings.vfp = timings->vfp;
1063 cfg->timings.timings.vsw = timings->vsw;
1064 cfg->timings.timings.pixel_clock = timings->pixel_clock;
1065 cfg->timings.vsync_pol = cea_vesa_timings[code].vsync_pol;
1066 cfg->timings.hsync_pol = cea_vesa_timings[code].hsync_pol;
1067}
1068
6cb07b25
AT		 1069static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
1070 struct hdmi_pll_info *pi)
c3198a5e 1071{
6cb07b25 1072 unsigned long clkin, refclk;
c3198a5e
M		 1073 u32 mf;
1074
4fbafaf3 1075 clkin = clk_get_rate(hdmi.sys_clk) / 10000;
c3198a5e
M		 1076 /*
1077 * Input clock is predivided by N + 1
1078 * out put of which is reference clk
1079 */
6cb07b25
AT		 1080 pi->regn = dssdev->clocks.hdmi.regn;
1081 refclk = clkin / (pi->regn + 1);
c3198a5e
M		 1082
1083 /*
1084 * multiplier is pixel_clk/ref_clk
1085 * Multiplying by 100 to avoid fractional part removal
1086 */
6cb07b25
AT		 1087 pi->regm = (phy * 100 / (refclk)) / 100;
1088 pi->regm2 = dssdev->clocks.hdmi.regm2;
c3198a5e
M		 1089
1090 /*
1091 * fractional multiplier is remainder of the difference between
1092 * multiplier and actual phy(required pixel clock thus should be
1093 * multiplied by 2^18(262144) divided by the reference clock
1094 */
1095 mf = (phy - pi->regm * refclk) * 262144;
6cb07b25 1096 pi->regmf = mf / (refclk);
c3198a5e
M		 1097
1098 /*
1099 * Dcofreq should be set to 1 if required pixel clock
1100 * is greater than 1000MHz
1101 */
1102 pi->dcofreq = phy > 1000 * 100;
6cb07b25 1103 pi->regsd = ((pi->regm * clkin / 10) / ((pi->regn + 1) * 250) + 5) / 10;
c3198a5e
M		 1104
1105 DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
1106 DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
1107}
1108
c3198a5e
M		 1109static int hdmi_power_on(struct omap_dss_device *dssdev)
1110{
1111 int r, code = 0;
1112 struct hdmi_pll_info pll_data;
1113 struct omap_video_timings *p;
6cb07b25 1114 unsigned long phy;
c3198a5e 1115
4fbafaf3
TV		 1116 r = hdmi_runtime_get();
1117 if (r)
1118 return r;
c3198a5e
M		 1119
1120 dispc_enable_channel(OMAP_DSS_CHANNEL_DIGIT, 0);
1121
1122 p = &dssdev->panel.timings;
1123
1124 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n",
1125 dssdev->panel.timings.x_res,
1126 dssdev->panel.timings.y_res);
1127
1128 if (!hdmi.custom_set) {
1129 DSSDBG("Read EDID as no EDID is not set on poweron\n");
1130 hdmi_read_edid(p);
1131 }
1132 code = get_timings_index();
1133 dssdev->panel.timings = cea_vesa_timings[code].timings;
1134 update_hdmi_timings(&hdmi.cfg, p, code);
1135
c3198a5e
M		 1136 phy = p->pixel_clock;
1137
6cb07b25 1138 hdmi_compute_pll(dssdev, phy, &pll_data);
c3198a5e
M		 1139
1140 hdmi_wp_video_start(0);
1141
1142 /* config the PLL and PHY first */
1143 r = hdmi_pll_program(&pll_data);
1144 if (r) {
1145 DSSDBG("Failed to lock PLL\n");
1146 goto err;
1147 }
1148
1149 r = hdmi_phy_init();
1150 if (r) {
1151 DSSDBG("Failed to start PHY\n");
1152 goto err;
1153 }
1154
1155 hdmi.cfg.cm.mode = hdmi.mode;
1156 hdmi.cfg.cm.code = hdmi.code;
1157 hdmi_basic_configure(&hdmi.cfg);
1158
1159 /* Make selection of HDMI in DSS */
1160 dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
1161
1162 /* Select the dispc clock source as PRCM clock, to ensure that it is not
1163 * DSI PLL source as the clock selected by DSI PLL might not be
1164 * sufficient for the resolution selected / that can be changed
1165 * dynamically by user. This can be moved to single location , say
1166 * Boardfile.
1167 */
6cb07b25 1168 dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
c3198a5e
M		 1169
1170 /* bypass TV gamma table */
1171 dispc_enable_gamma_table(0);
1172
1173 /* tv size */
1174 dispc_set_digit_size(dssdev->panel.timings.x_res,
1175 dssdev->panel.timings.y_res);
1176
1177 dispc_enable_channel(OMAP_DSS_CHANNEL_DIGIT, 1);
1178
1179 hdmi_wp_video_start(1);
1180
1181 return 0;
1182err:
4fbafaf3 1183 hdmi_runtime_put();
c3198a5e
M		 1184 return -EIO;
1185}
1186
1187static void hdmi_power_off(struct omap_dss_device *dssdev)
1188{
1189 dispc_enable_channel(OMAP_DSS_CHANNEL_DIGIT, 0);
1190
1191 hdmi_wp_video_start(0);
1192 hdmi_phy_off();
1193 hdmi_set_pll_pwr(HDMI_PLLPWRCMD_ALLOFF);
4fbafaf3 1194 hdmi_runtime_put();
c3198a5e
M		 1195
1196 hdmi.edid_set = 0;
1197}
1198
1199int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
1200 struct omap_video_timings *timings)
1201{
1202 struct hdmi_cm cm;
1203
1204 cm = hdmi_get_code(timings);
1205 if (cm.code == -1) {
1206 DSSERR("Invalid timing entered\n");
1207 return -EINVAL;
1208 }
1209
1210 return 0;
1211
1212}
1213
1214void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev)
1215{
1216 struct hdmi_cm cm;
1217
1218 hdmi.custom_set = 1;
1219 cm = hdmi_get_code(&dssdev->panel.timings);
1220 hdmi.code = cm.code;
1221 hdmi.mode = cm.mode;
1222 omapdss_hdmi_display_enable(dssdev);
1223 hdmi.custom_set = 0;
1224}
1225
1226int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev)
1227{
1228 int r = 0;
1229
1230 DSSDBG("ENTER hdmi_display_enable\n");
1231
1232 mutex_lock(&hdmi.lock);
1233
05e1d606
TV		 1234 if (dssdev->manager == NULL) {
1235 DSSERR("failed to enable display: no manager\n");
1236 r = -ENODEV;
1237 goto err0;
1238 }
1239
c3198a5e
M		 1240 r = omap_dss_start_device(dssdev);
1241 if (r) {
1242 DSSERR("failed to start device\n");
1243 goto err0;
1244 }
1245
1246 if (dssdev->platform_enable) {
1247 r = dssdev->platform_enable(dssdev);
1248 if (r) {
1249 DSSERR("failed to enable GPIO's\n");
1250 goto err1;
1251 }
1252 }
1253
1254 r = hdmi_power_on(dssdev);
1255 if (r) {
1256 DSSERR("failed to power on device\n");
1257 goto err2;
1258 }
1259
1260 mutex_unlock(&hdmi.lock);
1261 return 0;
1262
1263err2:
1264 if (dssdev->platform_disable)
1265 dssdev->platform_disable(dssdev);
1266err1:
1267 omap_dss_stop_device(dssdev);
1268err0:
1269 mutex_unlock(&hdmi.lock);
1270 return r;
1271}
1272
1273void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev)
1274{
1275 DSSDBG("Enter hdmi_display_disable\n");
1276
1277 mutex_lock(&hdmi.lock);
1278
1279 hdmi_power_off(dssdev);
1280
1281 if (dssdev->platform_disable)
1282 dssdev->platform_disable(dssdev);
1283
1284 omap_dss_stop_device(dssdev);
1285
1286 mutex_unlock(&hdmi.lock);
1287}
1288
82335c4c
RN		 1289#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
1290 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
1291static void hdmi_wp_audio_config_format(
1292 struct hdmi_audio_format *aud_fmt)
1293{
1294 u32 r;
1295
1296 DSSDBG("Enter hdmi_wp_audio_config_format\n");
1297
1298 r = hdmi_read_reg(HDMI_WP_AUDIO_CFG);
1299 r = FLD_MOD(r, aud_fmt->stereo_channels, 26, 24);
1300 r = FLD_MOD(r, aud_fmt->active_chnnls_msk, 23, 16);
1301 r = FLD_MOD(r, aud_fmt->en_sig_blk_strt_end, 5, 5);
1302 r = FLD_MOD(r, aud_fmt->type, 4, 4);
1303 r = FLD_MOD(r, aud_fmt->justification, 3, 3);
1304 r = FLD_MOD(r, aud_fmt->sample_order, 2, 2);
1305 r = FLD_MOD(r, aud_fmt->samples_per_word, 1, 1);
1306 r = FLD_MOD(r, aud_fmt->sample_size, 0, 0);
1307 hdmi_write_reg(HDMI_WP_AUDIO_CFG, r);
1308}
1309
1310static void hdmi_wp_audio_config_dma(struct hdmi_audio_dma *aud_dma)
1311{
1312 u32 r;
1313
1314 DSSDBG("Enter hdmi_wp_audio_config_dma\n");
1315
1316 r = hdmi_read_reg(HDMI_WP_AUDIO_CFG2);
1317 r = FLD_MOD(r, aud_dma->transfer_size, 15, 8);
1318 r = FLD_MOD(r, aud_dma->block_size, 7, 0);
1319 hdmi_write_reg(HDMI_WP_AUDIO_CFG2, r);
1320
1321 r = hdmi_read_reg(HDMI_WP_AUDIO_CTRL);
1322 r = FLD_MOD(r, aud_dma->mode, 9, 9);
1323 r = FLD_MOD(r, aud_dma->fifo_threshold, 8, 0);
1324 hdmi_write_reg(HDMI_WP_AUDIO_CTRL, r);
1325}
1326
1327static void hdmi_core_audio_config(struct hdmi_core_audio_config *cfg)
1328{
1329 u32 r;
1330
1331 /* audio clock recovery parameters */
1332 r = hdmi_read_reg(HDMI_CORE_AV_ACR_CTRL);
1333 r = FLD_MOD(r, cfg->use_mclk, 2, 2);
1334 r = FLD_MOD(r, cfg->en_acr_pkt, 1, 1);
1335 r = FLD_MOD(r, cfg->cts_mode, 0, 0);
1336 hdmi_write_reg(HDMI_CORE_AV_ACR_CTRL, r);
1337
1338 REG_FLD_MOD(HDMI_CORE_AV_N_SVAL1, cfg->n, 7, 0);
1339 REG_FLD_MOD(HDMI_CORE_AV_N_SVAL2, cfg->n >> 8, 7, 0);
1340 REG_FLD_MOD(HDMI_CORE_AV_N_SVAL3, cfg->n >> 16, 7, 0);
1341
1342 if (cfg->cts_mode == HDMI_AUDIO_CTS_MODE_SW) {
1343 REG_FLD_MOD(HDMI_CORE_AV_CTS_SVAL1, cfg->cts, 7, 0);
1344 REG_FLD_MOD(HDMI_CORE_AV_CTS_SVAL2, cfg->cts >> 8, 7, 0);
1345 REG_FLD_MOD(HDMI_CORE_AV_CTS_SVAL3, cfg->cts >> 16, 7, 0);
1346 } else {
1347 /*
1348 * HDMI IP uses this configuration to divide the MCLK to
1349 * update CTS value.
1350 */
1351 REG_FLD_MOD(HDMI_CORE_AV_FREQ_SVAL, cfg->mclk_mode, 2, 0);
1352
1353 /* Configure clock for audio packets */
1354 REG_FLD_MOD(HDMI_CORE_AV_AUD_PAR_BUSCLK_1,
1355 cfg->aud_par_busclk, 7, 0);
1356 REG_FLD_MOD(HDMI_CORE_AV_AUD_PAR_BUSCLK_2,
1357 (cfg->aud_par_busclk >> 8), 7, 0);
1358 REG_FLD_MOD(HDMI_CORE_AV_AUD_PAR_BUSCLK_3,
1359 (cfg->aud_par_busclk >> 16), 7, 0);
1360 }
1361
1362 /* Override of SPDIF sample frequency with value in I2S_CHST4 */
1363 REG_FLD_MOD(HDMI_CORE_AV_SPDIF_CTRL, cfg->fs_override, 1, 1);
1364
1365 /* I2S parameters */
1366 REG_FLD_MOD(HDMI_CORE_AV_I2S_CHST4, cfg->freq_sample, 3, 0);
1367
1368 r = hdmi_read_reg(HDMI_CORE_AV_I2S_IN_CTRL);
1369 r = FLD_MOD(r, cfg->i2s_cfg.en_high_bitrate_aud, 7, 7);
1370 r = FLD_MOD(r, cfg->i2s_cfg.sck_edge_mode, 6, 6);
1371 r = FLD_MOD(r, cfg->i2s_cfg.cbit_order, 5, 5);
1372 r = FLD_MOD(r, cfg->i2s_cfg.vbit, 4, 4);
1373 r = FLD_MOD(r, cfg->i2s_cfg.ws_polarity, 3, 3);
1374 r = FLD_MOD(r, cfg->i2s_cfg.justification, 2, 2);
1375 r = FLD_MOD(r, cfg->i2s_cfg.direction, 1, 1);
1376 r = FLD_MOD(r, cfg->i2s_cfg.shift, 0, 0);
1377 hdmi_write_reg(HDMI_CORE_AV_I2S_IN_CTRL, r);
1378
1379 r = hdmi_read_reg(HDMI_CORE_AV_I2S_CHST5);
1380 r = FLD_MOD(r, cfg->freq_sample, 7, 4);
1381 r = FLD_MOD(r, cfg->i2s_cfg.word_length, 3, 1);
1382 r = FLD_MOD(r, cfg->i2s_cfg.word_max_length, 0, 0);
1383 hdmi_write_reg(HDMI_CORE_AV_I2S_CHST5, r);
1384
1385 REG_FLD_MOD(HDMI_CORE_AV_I2S_IN_LEN, cfg->i2s_cfg.in_length_bits, 3, 0);
1386
1387 /* Audio channels and mode parameters */
1388 REG_FLD_MOD(HDMI_CORE_AV_HDMI_CTRL, cfg->layout, 2, 1);
1389 r = hdmi_read_reg(HDMI_CORE_AV_AUD_MODE);
1390 r = FLD_MOD(r, cfg->i2s_cfg.active_sds, 7, 4);
1391 r = FLD_MOD(r, cfg->en_dsd_audio, 3, 3);
1392 r = FLD_MOD(r, cfg->en_parallel_aud_input, 2, 2);
1393 r = FLD_MOD(r, cfg->en_spdif, 1, 1);
1394 hdmi_write_reg(HDMI_CORE_AV_AUD_MODE, r);
1395}
1396
1397static void hdmi_core_audio_infoframe_config(
1398 struct hdmi_core_infoframe_audio *info_aud)
1399{
1400 u8 val;
1401 u8 sum = 0, checksum = 0;
1402
1403 /*
1404 * Set audio info frame type, version and length as
1405 * described in HDMI 1.4a Section 8.2.2 specification.
1406 * Checksum calculation is defined in Section 5.3.5.
1407 */
1408 hdmi_write_reg(HDMI_CORE_AV_AUDIO_TYPE, 0x84);
1409 hdmi_write_reg(HDMI_CORE_AV_AUDIO_VERS, 0x01);
1410 hdmi_write_reg(HDMI_CORE_AV_AUDIO_LEN, 0x0a);
1411 sum += 0x84 + 0x001 + 0x00a;
1412
1413 val = (info_aud->db1_coding_type << 4)
1414 | (info_aud->db1_channel_count - 1);
1415 hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(0), val);
1416 sum += val;
1417
1418 val = (info_aud->db2_sample_freq << 2) | info_aud->db2_sample_size;
1419 hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(1), val);
1420 sum += val;
1421
1422 hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(2), 0x00);
1423
1424 val = info_aud->db4_channel_alloc;
1425 hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(3), val);
1426 sum += val;
1427
1428 val = (info_aud->db5_downmix_inh << 7) | (info_aud->db5_lsv << 3);
1429 hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(4), val);
1430 sum += val;
1431
1432 hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(5), 0x00);
1433 hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(6), 0x00);
1434 hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(7), 0x00);
1435 hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(8), 0x00);
1436 hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(9), 0x00);
1437
1438 checksum = 0x100 - sum;
1439 hdmi_write_reg(HDMI_CORE_AV_AUDIO_CHSUM, checksum);
1440
1441 /*
1442 * TODO: Add MPEG and SPD enable and repeat cfg when EDID parsing
1443 * is available.
1444 */
1445}
1446
1447static int hdmi_config_audio_acr(u32 sample_freq, u32 *n, u32 *cts)
1448{
1449 u32 r;
1450 u32 deep_color = 0;
1451 u32 pclk = hdmi.cfg.timings.timings.pixel_clock;
1452
1453 if (n == NULL || cts == NULL)
1454 return -EINVAL;
1455 /*
1456 * Obtain current deep color configuration. This needed
1457 * to calculate the TMDS clock based on the pixel clock.
1458 */
1459 r = REG_GET(HDMI_WP_VIDEO_CFG, 1, 0);
1460 switch (r) {
1461 case 1: /* No deep color selected */
1462 deep_color = 100;
1463 break;
1464 case 2: /* 10-bit deep color selected */
1465 deep_color = 125;
1466 break;
1467 case 3: /* 12-bit deep color selected */
1468 deep_color = 150;
1469 break;
1470 default:
1471 return -EINVAL;
1472 }
1473
1474 switch (sample_freq) {
1475 case 32000:
1476 if ((deep_color == 125) && ((pclk == 54054)
1477 || (pclk == 74250)))
1478 *n = 8192;
1479 else
1480 *n = 4096;
1481 break;
1482 case 44100:
1483 *n = 6272;
1484 break;
1485 case 48000:
1486 if ((deep_color == 125) && ((pclk == 54054)
1487 || (pclk == 74250)))
1488 *n = 8192;
1489 else
1490 *n = 6144;
1491 break;
1492 default:
1493 *n = 0;
1494 return -EINVAL;
1495 }
1496
1497 /* Calculate CTS. See HDMI 1.3a or 1.4a specifications */
1498 *cts = pclk * (*n / 128) * deep_color / (sample_freq / 10);
1499
1500 return 0;
1501}
ad44cc32
RN		 1502
1503static int hdmi_audio_hw_params(struct snd_pcm_substream *substream,
1504 struct snd_pcm_hw_params *params,
1505 struct snd_soc_dai *dai)
1506{
1507 struct hdmi_audio_format audio_format;
1508 struct hdmi_audio_dma audio_dma;
1509 struct hdmi_core_audio_config core_cfg;
1510 struct hdmi_core_infoframe_audio aud_if_cfg;
1511 int err, n, cts;
1512 enum hdmi_core_audio_sample_freq sample_freq;
1513
1514 switch (params_format(params)) {
1515 case SNDRV_PCM_FORMAT_S16_LE:
1516 core_cfg.i2s_cfg.word_max_length =
1517 HDMI_AUDIO_I2S_MAX_WORD_20BITS;
1518 core_cfg.i2s_cfg.word_length = HDMI_AUDIO_I2S_CHST_WORD_16_BITS;
1519 core_cfg.i2s_cfg.in_length_bits =
1520 HDMI_AUDIO_I2S_INPUT_LENGTH_16;
1521 core_cfg.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_LEFT;
1522 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES;
1523 audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS;
1524 audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT;
1525 audio_dma.transfer_size = 0x10;
1526 break;
1527 case SNDRV_PCM_FORMAT_S24_LE:
1528 core_cfg.i2s_cfg.word_max_length =
1529 HDMI_AUDIO_I2S_MAX_WORD_24BITS;
1530 core_cfg.i2s_cfg.word_length = HDMI_AUDIO_I2S_CHST_WORD_24_BITS;
1531 core_cfg.i2s_cfg.in_length_bits =
1532 HDMI_AUDIO_I2S_INPUT_LENGTH_24;
1533 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_ONESAMPLE;
1534 audio_format.sample_size = HDMI_AUDIO_SAMPLE_24BITS;
1535 audio_format.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
1536 core_cfg.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
1537 audio_dma.transfer_size = 0x20;
1538 break;
1539 default:
1540 return -EINVAL;
1541 }
1542
1543 switch (params_rate(params)) {
1544 case 32000:
1545 sample_freq = HDMI_AUDIO_FS_32000;
1546 break;
1547 case 44100:
1548 sample_freq = HDMI_AUDIO_FS_44100;
1549 break;
1550 case 48000:
1551 sample_freq = HDMI_AUDIO_FS_48000;
1552 break;
1553 default:
1554 return -EINVAL;
1555 }
1556
1557 err = hdmi_config_audio_acr(params_rate(params), &n, &cts);
1558 if (err < 0)
1559 return err;
1560
1561 /* Audio wrapper config */
1562 audio_format.stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL;
1563 audio_format.active_chnnls_msk = 0x03;
1564 audio_format.type = HDMI_AUDIO_TYPE_LPCM;
1565 audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
1566 /* Disable start/stop signals of IEC 60958 blocks */
1567 audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF;
1568
1569 audio_dma.block_size = 0xC0;
1570 audio_dma.mode = HDMI_AUDIO_TRANSF_DMA;
1571 audio_dma.fifo_threshold = 0x20; /* in number of samples */
1572
1573 hdmi_wp_audio_config_dma(&audio_dma);
1574 hdmi_wp_audio_config_format(&audio_format);
1575
1576 /*
1577 * I2S config
1578 */
1579 core_cfg.i2s_cfg.en_high_bitrate_aud = false;
1580 /* Only used with high bitrate audio */
1581 core_cfg.i2s_cfg.cbit_order = false;
1582 /* Serial data and word select should change on sck rising edge */
1583 core_cfg.i2s_cfg.sck_edge_mode = HDMI_AUDIO_I2S_SCK_EDGE_RISING;
1584 core_cfg.i2s_cfg.vbit = HDMI_AUDIO_I2S_VBIT_FOR_PCM;
1585 /* Set I2S word select polarity */
1586 core_cfg.i2s_cfg.ws_polarity = HDMI_AUDIO_I2S_WS_POLARITY_LOW_IS_LEFT;
1587 core_cfg.i2s_cfg.direction = HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST;
1588 /* Set serial data to word select shift. See Phillips spec. */
1589 core_cfg.i2s_cfg.shift = HDMI_AUDIO_I2S_FIRST_BIT_SHIFT;
1590 /* Enable one of the four available serial data channels */
1591 core_cfg.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN;
1592
1593 /* Core audio config */
1594 core_cfg.freq_sample = sample_freq;
1595 core_cfg.n = n;
1596 core_cfg.cts = cts;
1597 if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) {
1598 core_cfg.aud_par_busclk = 0;
1599 core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_SW;
1600 core_cfg.use_mclk = false;
1601 } else {
1602 core_cfg.aud_par_busclk = (((128 * 31) - 1) << 8);
1603 core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_HW;
1604 core_cfg.use_mclk = true;
1605 core_cfg.mclk_mode = HDMI_AUDIO_MCLK_128FS;
1606 }
1607 core_cfg.layout = HDMI_AUDIO_LAYOUT_2CH;
1608 core_cfg.en_spdif = false;
1609 /* Use sample frequency from channel status word */
1610 core_cfg.fs_override = true;
1611 /* Enable ACR packets */
1612 core_cfg.en_acr_pkt = true;
1613 /* Disable direct streaming digital audio */
1614 core_cfg.en_dsd_audio = false;
1615 /* Use parallel audio interface */
1616 core_cfg.en_parallel_aud_input = true;
1617
1618 hdmi_core_audio_config(&core_cfg);
1619
1620 /*
1621 * Configure packet
1622 * info frame audio see doc CEA861-D page 74
1623 */
1624 aud_if_cfg.db1_coding_type = HDMI_INFOFRAME_AUDIO_DB1CT_FROM_STREAM;
1625 aud_if_cfg.db1_channel_count = 2;
1626 aud_if_cfg.db2_sample_freq = HDMI_INFOFRAME_AUDIO_DB2SF_FROM_STREAM;
1627 aud_if_cfg.db2_sample_size = HDMI_INFOFRAME_AUDIO_DB2SS_FROM_STREAM;
1628 aud_if_cfg.db4_channel_alloc = 0x00;
1629 aud_if_cfg.db5_downmix_inh = false;
1630 aud_if_cfg.db5_lsv = 0;
1631
1632 hdmi_core_audio_infoframe_config(&aud_if_cfg);
1633 return 0;
1634}
1635
1636static int hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd,
1637 struct snd_soc_dai *dai)
1638{
1639 int err = 0;
1640 switch (cmd) {
1641 case SNDRV_PCM_TRIGGER_START:
1642 case SNDRV_PCM_TRIGGER_RESUME:
1643 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1644 REG_FLD_MOD(HDMI_CORE_AV_AUD_MODE, 1, 0, 0);
1645 REG_FLD_MOD(HDMI_WP_AUDIO_CTRL, 1, 31, 31);
1646 REG_FLD_MOD(HDMI_WP_AUDIO_CTRL, 1, 30, 30);
1647 break;
1648
1649 case SNDRV_PCM_TRIGGER_STOP:
1650 case SNDRV_PCM_TRIGGER_SUSPEND:
1651 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1652 REG_FLD_MOD(HDMI_CORE_AV_AUD_MODE, 0, 0, 0);
1653 REG_FLD_MOD(HDMI_WP_AUDIO_CTRL, 0, 30, 30);
1654 REG_FLD_MOD(HDMI_WP_AUDIO_CTRL, 0, 31, 31);
1655 break;
1656 default:
1657 err = -EINVAL;
1658 }
1659 return err;
1660}
1661
1662static int hdmi_audio_startup(struct snd_pcm_substream *substream,
1663 struct snd_soc_dai *dai)
1664{
1665 if (!hdmi.mode) {
1666 pr_err("Current video settings do not support audio.\n");
1667 return -EIO;
1668 }
1669 return 0;
1670}
1671
1672static struct snd_soc_codec_driver hdmi_audio_codec_drv = {
1673};
1674
1675static struct snd_soc_dai_ops hdmi_audio_codec_ops = {
1676 .hw_params = hdmi_audio_hw_params,
1677 .trigger = hdmi_audio_trigger,
1678 .startup = hdmi_audio_startup,
1679};
1680
1681static struct snd_soc_dai_driver hdmi_codec_dai_drv = {
1682 .name = "hdmi-audio-codec",
1683 .playback = {
1684 .channels_min = 2,
1685 .channels_max = 2,
1686 .rates = SNDRV_PCM_RATE_32000 |
1687 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1688 .formats = SNDRV_PCM_FMTBIT_S16_LE |
1689 SNDRV_PCM_FMTBIT_S24_LE,
1690 },
1691 .ops = &hdmi_audio_codec_ops,
1692};
82335c4c
RN		 1693#endif
1694
4fbafaf3
TV		 1695static int hdmi_get_clocks(struct platform_device *pdev)
1696{
1697 struct clk *clk;
1698
1699 clk = clk_get(&pdev->dev, "sys_clk");
1700 if (IS_ERR(clk)) {
1701 DSSERR("can't get sys_clk\n");
1702 return PTR_ERR(clk);
1703 }
1704
1705 hdmi.sys_clk = clk;
1706
df5d3ed2 1707 clk = clk_get(&pdev->dev, "dss_48mhz_clk");
4fbafaf3 1708 if (IS_ERR(clk)) {
df5d3ed2 1709 DSSERR("can't get hdmi_clk\n");
4fbafaf3
TV		 1710 clk_put(hdmi.sys_clk);
1711 return PTR_ERR(clk);
1712 }
1713
1714 hdmi.hdmi_clk = clk;
1715
1716 return 0;
1717}
1718
1719static void hdmi_put_clocks(void)
1720{
1721 if (hdmi.sys_clk)
1722 clk_put(hdmi.sys_clk);
1723 if (hdmi.hdmi_clk)
1724 clk_put(hdmi.hdmi_clk);
1725}
1726
c3198a5e
M		 1727/* HDMI HW IP initialisation */
1728static int omapdss_hdmihw_probe(struct platform_device *pdev)
1729{
1730 struct resource *hdmi_mem;
4fbafaf3 1731 int r;
c3198a5e
M		 1732
1733 hdmi.pdata = pdev->dev.platform_data;
1734 hdmi.pdev = pdev;
1735
1736 mutex_init(&hdmi.lock);
1737
1738 hdmi_mem = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0);
1739 if (!hdmi_mem) {
1740 DSSERR("can't get IORESOURCE_MEM HDMI\n");
1741 return -EINVAL;
1742 }
1743
1744 /* Base address taken from platform */
1745 hdmi.base_wp = ioremap(hdmi_mem->start, resource_size(hdmi_mem));
1746 if (!hdmi.base_wp) {
1747 DSSERR("can't ioremap WP\n");
1748 return -ENOMEM;
1749 }
1750
4fbafaf3
TV		 1751 r = hdmi_get_clocks(pdev);
1752 if (r) {
1753 iounmap(hdmi.base_wp);
1754 return r;
1755 }
1756
1757 pm_runtime_enable(&pdev->dev);
1758
c3198a5e
M		 1759 hdmi_panel_init();
1760
ad44cc32
RN		 1761#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
1762 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
1763
1764 /* Register ASoC codec DAI */
4fbafaf3 1765 r = snd_soc_register_codec(&pdev->dev, &hdmi_audio_codec_drv,
ad44cc32 1766 &hdmi_codec_dai_drv, 1);
4fbafaf3 1767 if (r) {
ad44cc32 1768 DSSERR("can't register ASoC HDMI audio codec\n");
4fbafaf3 1769 return r;
ad44cc32
RN		 1770 }
1771#endif
c3198a5e
M		 1772 return 0;
1773}
1774
1775static int omapdss_hdmihw_remove(struct platform_device *pdev)
1776{
1777 hdmi_panel_exit();
1778
ad44cc32
RN		 1779#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
1780 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
1781 snd_soc_unregister_codec(&pdev->dev);
1782#endif
1783
4fbafaf3
TV		 1784 pm_runtime_disable(&pdev->dev);
1785
1786 hdmi_put_clocks();
1787
c3198a5e
M		 1788 iounmap(hdmi.base_wp);
1789
1790 return 0;
1791}
1792
4fbafaf3
TV		 1793static int hdmi_runtime_suspend(struct device *dev)
1794{
1795 clk_disable(hdmi.hdmi_clk);
1796 clk_disable(hdmi.sys_clk);
1797
1798 dispc_runtime_put();
1799 dss_runtime_put();
1800
1801 return 0;
1802}
1803
1804static int hdmi_runtime_resume(struct device *dev)
1805{
1806 int r;
1807
1808 r = dss_runtime_get();
1809 if (r < 0)
1810 goto err_get_dss;
1811
1812 r = dispc_runtime_get();
1813 if (r < 0)
1814 goto err_get_dispc;
1815
1816
1817 clk_enable(hdmi.sys_clk);
1818 clk_enable(hdmi.hdmi_clk);
1819
1820 return 0;
1821
1822err_get_dispc:
1823 dss_runtime_put();
1824err_get_dss:
1825 return r;
1826}
1827
1828static const struct dev_pm_ops hdmi_pm_ops = {
1829 .runtime_suspend = hdmi_runtime_suspend,
1830 .runtime_resume = hdmi_runtime_resume,
1831};
1832
c3198a5e
M		 1833static struct platform_driver omapdss_hdmihw_driver = {
1834 .probe = omapdss_hdmihw_probe,
1835 .remove = omapdss_hdmihw_remove,
1836 .driver = {
1837 .name = "omapdss_hdmi",
1838 .owner = THIS_MODULE,
4fbafaf3 1839 .pm = &hdmi_pm_ops,
c3198a5e
M		 1840 },
1841};
1842
1843int hdmi_init_platform_driver(void)
1844{
1845 return platform_driver_register(&omapdss_hdmihw_driver);
1846}
1847
1848void hdmi_uninit_platform_driver(void)
1849{
1850 return platform_driver_unregister(&omapdss_hdmihw_driver);
1851}
Linux kernel - Deliverables
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