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OMAP4: DSS2: HDMI: Rename the functions in HDMI IP library
[deliverable/linux.git] / drivers / video / omap2 / dss / hdmi.c
CommitLineData
c3198a5e
M		 1/*
2 * hdmi.c
3 *
4 * HDMI interface DSS driver setting for TI's OMAP4 family of processor.
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
6 * Authors: Yong Zhi
7 * Mythri pk <mythripk@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#define DSS_SUBSYS_NAME "HDMI"
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/err.h>
27#include <linux/io.h>
28#include <linux/interrupt.h>
29#include <linux/mutex.h>
30#include <linux/delay.h>
31#include <linux/string.h>
24e6289c 32#include <linux/platform_device.h>
4fbafaf3
TV		 33#include <linux/pm_runtime.h>
34#include <linux/clk.h>
a0b38cc4 35#include <video/omapdss.h>
ad44cc32
RN		 36#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
37 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
38#include <sound/soc.h>
39#include <sound/pcm_params.h>
7334167b 40#include "ti_hdmi_4xxx_ip.h"
ad44cc32 41#endif
c3198a5e 42
94c52987 43#include "ti_hdmi.h"
c3198a5e 44#include "dss.h"
ad44cc32 45#include "dss_features.h"
c3198a5e 46
95a8aeb6
M		 47#define HDMI_WP 0x0
48#define HDMI_CORE_SYS 0x400
49#define HDMI_CORE_AV 0x900
50#define HDMI_PLLCTRL 0x200
51#define HDMI_PHY 0x300
52
7c1f1eca
M		 53/* HDMI EDID Length move this */
54#define HDMI_EDID_MAX_LENGTH 256
55#define EDID_TIMING_DESCRIPTOR_SIZE 0x12
56#define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36
57#define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80
58#define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4
59#define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4
60
61#define OMAP_HDMI_TIMINGS_NB 34
62
c3198a5e
M		 63static struct {
64 struct mutex lock;
65 struct omap_display_platform_data *pdata;
66 struct platform_device *pdev;
95a8aeb6 67 struct hdmi_ip_data ip_data;
c3198a5e
M		 68 int code;
69 int mode;
70 u8 edid[HDMI_EDID_MAX_LENGTH];
71 u8 edid_set;
72 bool custom_set;
4fbafaf3
TV		 73
74 struct clk *sys_clk;
c3198a5e
M		 75} hdmi;
76
77/*
78 * Logic for the below structure :
79 * user enters the CEA or VESA timings by specifying the HDMI/DVI code.
80 * There is a correspondence between CEA/VESA timing and code, please
81 * refer to section 6.3 in HDMI 1.3 specification for timing code.
82 *
83 * In the below structure, cea_vesa_timings corresponds to all OMAP4
84 * supported CEA and VESA timing values.code_cea corresponds to the CEA
85 * code, It is used to get the timing from cea_vesa_timing array.Similarly
86 * with code_vesa. Code_index is used for back mapping, that is once EDID
87 * is read from the TV, EDID is parsed to find the timing values and then
88 * map it to corresponding CEA or VESA index.
89 */
90
91static const struct hdmi_timings cea_vesa_timings[OMAP_HDMI_TIMINGS_NB] = {
92 { {640, 480, 25200, 96, 16, 48, 2, 10, 33} , 0 , 0},
93 { {1280, 720, 74250, 40, 440, 220, 5, 5, 20}, 1, 1},
94 { {1280, 720, 74250, 40, 110, 220, 5, 5, 20}, 1, 1},
95 { {720, 480, 27027, 62, 16, 60, 6, 9, 30}, 0, 0},
96 { {2880, 576, 108000, 256, 48, 272, 5, 5, 39}, 0, 0},
97 { {1440, 240, 27027, 124, 38, 114, 3, 4, 15}, 0, 0},
98 { {1440, 288, 27000, 126, 24, 138, 3, 2, 19}, 0, 0},
99 { {1920, 540, 74250, 44, 528, 148, 5, 2, 15}, 1, 1},
100 { {1920, 540, 74250, 44, 88, 148, 5, 2, 15}, 1, 1},
101 { {1920, 1080, 148500, 44, 88, 148, 5, 4, 36}, 1, 1},
102 { {720, 576, 27000, 64, 12, 68, 5, 5, 39}, 0, 0},
103 { {1440, 576, 54000, 128, 24, 136, 5, 5, 39}, 0, 0},
104 { {1920, 1080, 148500, 44, 528, 148, 5, 4, 36}, 1, 1},
105 { {2880, 480, 108108, 248, 64, 240, 6, 9, 30}, 0, 0},
106 { {1920, 1080, 74250, 44, 638, 148, 5, 4, 36}, 1, 1},
107 /* VESA From Here */
108 { {640, 480, 25175, 96, 16, 48, 2 , 11, 31}, 0, 0},
109 { {800, 600, 40000, 128, 40, 88, 4 , 1, 23}, 1, 1},
110 { {848, 480, 33750, 112, 16, 112, 8 , 6, 23}, 1, 1},
111 { {1280, 768, 79500, 128, 64, 192, 7 , 3, 20}, 1, 0},
112 { {1280, 800, 83500, 128, 72, 200, 6 , 3, 22}, 1, 0},
113 { {1360, 768, 85500, 112, 64, 256, 6 , 3, 18}, 1, 1},
114 { {1280, 960, 108000, 112, 96, 312, 3 , 1, 36}, 1, 1},
115 { {1280, 1024, 108000, 112, 48, 248, 3 , 1, 38}, 1, 1},
116 { {1024, 768, 65000, 136, 24, 160, 6, 3, 29}, 0, 0},
117 { {1400, 1050, 121750, 144, 88, 232, 4, 3, 32}, 1, 0},
118 { {1440, 900, 106500, 152, 80, 232, 6, 3, 25}, 1, 0},
119 { {1680, 1050, 146250, 176 , 104, 280, 6, 3, 30}, 1, 0},
120 { {1366, 768, 85500, 143, 70, 213, 3, 3, 24}, 1, 1},
121 { {1920, 1080, 148500, 44, 148, 80, 5, 4, 36}, 1, 1},
122 { {1280, 768, 68250, 32, 48, 80, 7, 3, 12}, 0, 1},
123 { {1400, 1050, 101000, 32, 48, 80, 4, 3, 23}, 0, 1},
124 { {1680, 1050, 119000, 32, 48, 80, 6, 3, 21}, 0, 1},
125 { {1280, 800, 79500, 32, 48, 80, 6, 3, 14}, 0, 1},
126 { {1280, 720, 74250, 40, 110, 220, 5, 5, 20}, 1, 1}
127};
128
129/*
130 * This is a static mapping array which maps the timing values
131 * with corresponding CEA / VESA code
132 */
133static const int code_index[OMAP_HDMI_TIMINGS_NB] = {
134 1, 19, 4, 2, 37, 6, 21, 20, 5, 16, 17, 29, 31, 35, 32,
135 /* <--15 CEA 17--> vesa*/
136 4, 9, 0xE, 0x17, 0x1C, 0x27, 0x20, 0x23, 0x10, 0x2A,
137 0X2F, 0x3A, 0X51, 0X52, 0x16, 0x29, 0x39, 0x1B
138};
139
140/*
141 * This is reverse static mapping which maps the CEA / VESA code
142 * to the corresponding timing values
143 */
144static const int code_cea[39] = {
145 -1, 0, 3, 3, 2, 8, 5, 5, -1, -1,
146 -1, -1, -1, -1, -1, -1, 9, 10, 10, 1,
147 7, 6, 6, -1, -1, -1, -1, -1, -1, 11,
148 11, 12, 14, -1, -1, 13, 13, 4, 4
149};
150
151static const int code_vesa[85] = {
152 -1, -1, -1, -1, 15, -1, -1, -1, -1, 16,
153 -1, -1, -1, -1, 17, -1, 23, -1, -1, -1,
154 -1, -1, 29, 18, -1, -1, -1, 32, 19, -1,
155 -1, -1, 21, -1, -1, 22, -1, -1, -1, 20,
156 -1, 30, 24, -1, -1, -1, -1, 25, -1, -1,
157 -1, -1, -1, -1, -1, -1, -1, 31, 26, -1,
158 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
159 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
160 -1, 27, 28, -1, 33};
161
162static const u8 edid_header[8] = {0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0};
163
4fbafaf3
TV		 164static int hdmi_runtime_get(void)
165{
166 int r;
167
168 DSSDBG("hdmi_runtime_get\n");
169
170 r = pm_runtime_get_sync(&hdmi.pdev->dev);
171 WARN_ON(r < 0);
172 return r < 0 ? r : 0;
173}
174
175static void hdmi_runtime_put(void)
176{
177 int r;
178
179 DSSDBG("hdmi_runtime_put\n");
180
181 r = pm_runtime_put(&hdmi.pdev->dev);
182 WARN_ON(r < 0);
183}
184
c3198a5e
M		 185int hdmi_init_display(struct omap_dss_device *dssdev)
186{
187 DSSDBG("init_display\n");
188
189 return 0;
190}
191
38863b7e
M		 192static void copy_hdmi_to_dss_timings(
193 const struct hdmi_video_timings *hdmi_timings,
194 struct omap_video_timings *timings)
195{
196 timings->x_res = hdmi_timings->x_res;
197 timings->y_res = hdmi_timings->y_res;
198 timings->pixel_clock = hdmi_timings->pixel_clock;
199 timings->hbp = hdmi_timings->hbp;
200 timings->hfp = hdmi_timings->hfp;
201 timings->hsw = hdmi_timings->hsw;
202 timings->vbp = hdmi_timings->vbp;
203 timings->vfp = hdmi_timings->vfp;
204 timings->vsw = hdmi_timings->vsw;
205}
206
c3198a5e
M		 207static int get_timings_index(void)
208{
209 int code;
210
211 if (hdmi.mode == 0)
212 code = code_vesa[hdmi.code];
213 else
214 code = code_cea[hdmi.code];
215
216 if (code == -1) {
217 /* HDMI code 4 corresponds to 640 * 480 VGA */
218 hdmi.code = 4;
219 /* DVI mode 1 corresponds to HDMI 0 to DVI */
220 hdmi.mode = HDMI_DVI;
221
222 code = code_vesa[hdmi.code];
223 }
224 return code;
225}
226
227static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing)
228{
229 int i = 0, code = -1, temp_vsync = 0, temp_hsync = 0;
230 int timing_vsync = 0, timing_hsync = 0;
38863b7e 231 struct hdmi_video_timings temp;
c3198a5e
M		 232 struct hdmi_cm cm = {-1};
233 DSSDBG("hdmi_get_code\n");
234
235 for (i = 0; i < OMAP_HDMI_TIMINGS_NB; i++) {
236 temp = cea_vesa_timings[i].timings;
237 if ((temp.pixel_clock == timing->pixel_clock) &&
238 (temp.x_res == timing->x_res) &&
239 (temp.y_res == timing->y_res)) {
240
241 temp_hsync = temp.hfp + temp.hsw + temp.hbp;
242 timing_hsync = timing->hfp + timing->hsw + timing->hbp;
243 temp_vsync = temp.vfp + temp.vsw + temp.vbp;
244 timing_vsync = timing->vfp + timing->vsw + timing->vbp;
245
246 DSSDBG("temp_hsync = %d , temp_vsync = %d"
247 "timing_hsync = %d, timing_vsync = %d\n",
248 temp_hsync, temp_hsync,
249 timing_hsync, timing_vsync);
250
251 if ((temp_hsync == timing_hsync) &&
252 (temp_vsync == timing_vsync)) {
253 code = i;
254 cm.code = code_index[i];
255 if (code < 14)
256 cm.mode = HDMI_HDMI;
257 else
258 cm.mode = HDMI_DVI;
259 DSSDBG("Hdmi_code = %d mode = %d\n",
260 cm.code, cm.mode);
261 break;
262 }
263 }
264 }
265
266 return cm;
267}
268
269static void get_horz_vert_timing_info(int current_descriptor_addrs, u8 *edid ,
270 struct omap_video_timings *timings)
271{
272 /* X and Y resolution */
273 timings->x_res = (((edid[current_descriptor_addrs + 4] & 0xF0) << 4) |
274 edid[current_descriptor_addrs + 2]);
275 timings->y_res = (((edid[current_descriptor_addrs + 7] & 0xF0) << 4) |
276 edid[current_descriptor_addrs + 5]);
277
278 timings->pixel_clock = ((edid[current_descriptor_addrs + 1] << 8) |
279 edid[current_descriptor_addrs]);
280
281 timings->pixel_clock = 10 * timings->pixel_clock;
282
283 /* HORIZONTAL FRONT PORCH */
284 timings->hfp = edid[current_descriptor_addrs + 8] |
285 ((edid[current_descriptor_addrs + 11] & 0xc0) << 2);
286 /* HORIZONTAL SYNC WIDTH */
287 timings->hsw = edid[current_descriptor_addrs + 9] |
288 ((edid[current_descriptor_addrs + 11] & 0x30) << 4);
289 /* HORIZONTAL BACK PORCH */
290 timings->hbp = (((edid[current_descriptor_addrs + 4] & 0x0F) << 8) |
291 edid[current_descriptor_addrs + 3]) -
292 (timings->hfp + timings->hsw);
293 /* VERTICAL FRONT PORCH */
294 timings->vfp = ((edid[current_descriptor_addrs + 10] & 0xF0) >> 4) |
295 ((edid[current_descriptor_addrs + 11] & 0x0f) << 2);
296 /* VERTICAL SYNC WIDTH */
297 timings->vsw = (edid[current_descriptor_addrs + 10] & 0x0F) |
298 ((edid[current_descriptor_addrs + 11] & 0x03) << 4);
299 /* VERTICAL BACK PORCH */
300 timings->vbp = (((edid[current_descriptor_addrs + 7] & 0x0F) << 8) |
301 edid[current_descriptor_addrs + 6]) -
302 (timings->vfp + timings->vsw);
303
304}
305
306/* Description : This function gets the resolution information from EDID */
307static void get_edid_timing_data(u8 *edid)
308{
309 u8 count;
310 u16 current_descriptor_addrs;
311 struct hdmi_cm cm;
312 struct omap_video_timings edid_timings;
313
25985edc 314 /* search block 0, there are 4 DTDs arranged in priority order */
c3198a5e
M		 315 for (count = 0; count < EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR; count++) {
316 current_descriptor_addrs =
317 EDID_DESCRIPTOR_BLOCK0_ADDRESS +
318 count * EDID_TIMING_DESCRIPTOR_SIZE;
319 get_horz_vert_timing_info(current_descriptor_addrs,
320 edid, &edid_timings);
321 cm = hdmi_get_code(&edid_timings);
322 DSSDBG("Block0[%d] value matches code = %d , mode = %d\n",
323 count, cm.code, cm.mode);
324 if (cm.code == -1) {
325 continue;
326 } else {
327 hdmi.code = cm.code;
328 hdmi.mode = cm.mode;
329 DSSDBG("code = %d , mode = %d\n",
330 hdmi.code, hdmi.mode);
331 return;
332 }
333 }
334 if (edid[0x7e] != 0x00) {
335 for (count = 0; count < EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR;
336 count++) {
337 current_descriptor_addrs =
338 EDID_DESCRIPTOR_BLOCK1_ADDRESS +
339 count * EDID_TIMING_DESCRIPTOR_SIZE;
340 get_horz_vert_timing_info(current_descriptor_addrs,
341 edid, &edid_timings);
342 cm = hdmi_get_code(&edid_timings);
343 DSSDBG("Block1[%d] value matches code = %d, mode = %d",
344 count, cm.code, cm.mode);
345 if (cm.code == -1) {
346 continue;
347 } else {
348 hdmi.code = cm.code;
349 hdmi.mode = cm.mode;
350 DSSDBG("code = %d , mode = %d\n",
351 hdmi.code, hdmi.mode);
352 return;
353 }
354 }
355 }
356
357 DSSINFO("no valid timing found , falling back to VGA\n");
358 hdmi.code = 4; /* setting default value of 640 480 VGA */
359 hdmi.mode = HDMI_DVI;
360}
361
362static void hdmi_read_edid(struct omap_video_timings *dp)
363{
364 int ret = 0, code;
365
366 memset(hdmi.edid, 0, HDMI_EDID_MAX_LENGTH);
367
368 if (!hdmi.edid_set)
176b578b 369 ret = ti_hdmi_4xxx_read_edid(&hdmi.ip_data, hdmi.edid,
95a8aeb6 370 HDMI_EDID_MAX_LENGTH);
c3198a5e
M		 371 if (!ret) {
372 if (!memcmp(hdmi.edid, edid_header, sizeof(edid_header))) {
373 /* search for timings of default resolution */
374 get_edid_timing_data(hdmi.edid);
375 hdmi.edid_set = true;
376 }
377 } else {
378 DSSWARN("failed to read E-EDID\n");
379 }
380
381 if (!hdmi.edid_set) {
382 DSSINFO("fallback to VGA\n");
383 hdmi.code = 4; /* setting default value of 640 480 VGA */
384 hdmi.mode = HDMI_DVI;
385 }
386
387 code = get_timings_index();
388
38863b7e
M		 389 copy_hdmi_to_dss_timings(&cea_vesa_timings[code].timings, dp);
390
c3198a5e
M		 391}
392
c3198a5e
M		 393static void update_hdmi_timings(struct hdmi_config *cfg,
394 struct omap_video_timings *timings, int code)
395{
396 cfg->timings.timings.x_res = timings->x_res;
397 cfg->timings.timings.y_res = timings->y_res;
398 cfg->timings.timings.hbp = timings->hbp;
399 cfg->timings.timings.hfp = timings->hfp;
400 cfg->timings.timings.hsw = timings->hsw;
401 cfg->timings.timings.vbp = timings->vbp;
402 cfg->timings.timings.vfp = timings->vfp;
403 cfg->timings.timings.vsw = timings->vsw;
404 cfg->timings.timings.pixel_clock = timings->pixel_clock;
405 cfg->timings.vsync_pol = cea_vesa_timings[code].vsync_pol;
406 cfg->timings.hsync_pol = cea_vesa_timings[code].hsync_pol;
407}
408
6cb07b25
AT		 409static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
410 struct hdmi_pll_info *pi)
c3198a5e 411{
6cb07b25 412 unsigned long clkin, refclk;
c3198a5e
M		 413 u32 mf;
414
4fbafaf3 415 clkin = clk_get_rate(hdmi.sys_clk) / 10000;
c3198a5e
M		 416 /*
417 * Input clock is predivided by N + 1
418 * out put of which is reference clk
419 */
6cb07b25
AT		 420 pi->regn = dssdev->clocks.hdmi.regn;
421 refclk = clkin / (pi->regn + 1);
c3198a5e
M		 422
423 /*
424 * multiplier is pixel_clk/ref_clk
425 * Multiplying by 100 to avoid fractional part removal
426 */
6cb07b25
AT		 427 pi->regm = (phy * 100 / (refclk)) / 100;
428 pi->regm2 = dssdev->clocks.hdmi.regm2;
c3198a5e
M		 429
430 /*
431 * fractional multiplier is remainder of the difference between
432 * multiplier and actual phy(required pixel clock thus should be
433 * multiplied by 2^18(262144) divided by the reference clock
434 */
435 mf = (phy - pi->regm * refclk) * 262144;
6cb07b25 436 pi->regmf = mf / (refclk);
c3198a5e
M		 437
438 /*
439 * Dcofreq should be set to 1 if required pixel clock
440 * is greater than 1000MHz
441 */
442 pi->dcofreq = phy > 1000 * 100;
6cb07b25 443 pi->regsd = ((pi->regm * clkin / 10) / ((pi->regn + 1) * 250) + 5) / 10;
c3198a5e 444
7b27da54
M		 445 /* Set the reference clock to sysclk reference */
446 pi->refsel = HDMI_REFSEL_SYSCLK;
447
c3198a5e
M		 448 DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
449 DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
450}
451
c3198a5e
M		 452static int hdmi_power_on(struct omap_dss_device *dssdev)
453{
454 int r, code = 0;
c3198a5e 455 struct omap_video_timings *p;
6cb07b25 456 unsigned long phy;
c3198a5e 457
4fbafaf3
TV		 458 r = hdmi_runtime_get();
459 if (r)
460 return r;
c3198a5e 461
26d9dd0d 462 dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, 0);
c3198a5e
M		 463
464 p = &dssdev->panel.timings;
465
466 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n",
467 dssdev->panel.timings.x_res,
468 dssdev->panel.timings.y_res);
469
470 if (!hdmi.custom_set) {
471 DSSDBG("Read EDID as no EDID is not set on poweron\n");
472 hdmi_read_edid(p);
473 }
474 code = get_timings_index();
38863b7e
M		 475 copy_hdmi_to_dss_timings(&cea_vesa_timings[code].timings,
476 &dssdev->panel.timings);
7b27da54 477 update_hdmi_timings(&hdmi.ip_data.cfg, p, code);
c3198a5e 478
c3198a5e
M		 479 phy = p->pixel_clock;
480
7b27da54 481 hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data);
c3198a5e 482
176b578b 483 ti_hdmi_4xxx_wp_video_start(&hdmi.ip_data, 0);
c3198a5e 484
95a8aeb6 485 /* config the PLL and PHY hdmi_set_pll_pwrfirst */
176b578b 486 r = ti_hdmi_4xxx_pll_enable(&hdmi.ip_data);
c3198a5e
M		 487 if (r) {
488 DSSDBG("Failed to lock PLL\n");
489 goto err;
490 }
491
176b578b 492 r = ti_hdmi_4xxx_phy_enable(&hdmi.ip_data);
c3198a5e
M		 493 if (r) {
494 DSSDBG("Failed to start PHY\n");
495 goto err;
496 }
497
7b27da54
M		 498 hdmi.ip_data.cfg.cm.mode = hdmi.mode;
499 hdmi.ip_data.cfg.cm.code = hdmi.code;
176b578b 500 ti_hdmi_4xxx_basic_configure(&hdmi.ip_data);
c3198a5e
M		 501
502 /* Make selection of HDMI in DSS */
503 dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
504
505 /* Select the dispc clock source as PRCM clock, to ensure that it is not
506 * DSI PLL source as the clock selected by DSI PLL might not be
507 * sufficient for the resolution selected / that can be changed
508 * dynamically by user. This can be moved to single location , say
509 * Boardfile.
510 */
6cb07b25 511 dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
c3198a5e
M		 512
513 /* bypass TV gamma table */
514 dispc_enable_gamma_table(0);
515
516 /* tv size */
517 dispc_set_digit_size(dssdev->panel.timings.x_res,
518 dssdev->panel.timings.y_res);
519
26d9dd0d 520 dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, 1);
c3198a5e 521
176b578b 522 ti_hdmi_4xxx_wp_video_start(&hdmi.ip_data, 1);
c3198a5e
M		 523
524 return 0;
525err:
4fbafaf3 526 hdmi_runtime_put();
c3198a5e
M		 527 return -EIO;
528}
529
530static void hdmi_power_off(struct omap_dss_device *dssdev)
531{
26d9dd0d 532 dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, 0);
c3198a5e 533
176b578b
M		 534 ti_hdmi_4xxx_wp_video_start(&hdmi.ip_data, 0);
535 ti_hdmi_4xxx_phy_disable(&hdmi.ip_data);
536 ti_hdmi_4xxx_pll_disable(&hdmi.ip_data);
4fbafaf3 537 hdmi_runtime_put();
c3198a5e
M		 538
539 hdmi.edid_set = 0;
540}
541
542int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
543 struct omap_video_timings *timings)
544{
545 struct hdmi_cm cm;
546
547 cm = hdmi_get_code(timings);
548 if (cm.code == -1) {
549 DSSERR("Invalid timing entered\n");
550 return -EINVAL;
551 }
552
553 return 0;
554
555}
556
557void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev)
558{
559 struct hdmi_cm cm;
560
561 hdmi.custom_set = 1;
562 cm = hdmi_get_code(&dssdev->panel.timings);
563 hdmi.code = cm.code;
564 hdmi.mode = cm.mode;
565 omapdss_hdmi_display_enable(dssdev);
566 hdmi.custom_set = 0;
567}
568
569int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev)
570{
571 int r = 0;
572
573 DSSDBG("ENTER hdmi_display_enable\n");
574
575 mutex_lock(&hdmi.lock);
576
05e1d606
TV		 577 if (dssdev->manager == NULL) {
578 DSSERR("failed to enable display: no manager\n");
579 r = -ENODEV;
580 goto err0;
581 }
582
c3198a5e
M		 583 r = omap_dss_start_device(dssdev);
584 if (r) {
585 DSSERR("failed to start device\n");
586 goto err0;
587 }
588
589 if (dssdev->platform_enable) {
590 r = dssdev->platform_enable(dssdev);
591 if (r) {
592 DSSERR("failed to enable GPIO's\n");
593 goto err1;
594 }
595 }
596
597 r = hdmi_power_on(dssdev);
598 if (r) {
599 DSSERR("failed to power on device\n");
600 goto err2;
601 }
602
603 mutex_unlock(&hdmi.lock);
604 return 0;
605
606err2:
607 if (dssdev->platform_disable)
608 dssdev->platform_disable(dssdev);
609err1:
610 omap_dss_stop_device(dssdev);
611err0:
612 mutex_unlock(&hdmi.lock);
613 return r;
614}
615
616void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev)
617{
618 DSSDBG("Enter hdmi_display_disable\n");
619
620 mutex_lock(&hdmi.lock);
621
622 hdmi_power_off(dssdev);
623
624 if (dssdev->platform_disable)
625 dssdev->platform_disable(dssdev);
626
627 omap_dss_stop_device(dssdev);
628
629 mutex_unlock(&hdmi.lock);
630}
631
82335c4c
RN		 632#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
633 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
ad44cc32 634
95a8aeb6
M		 635static int hdmi_audio_hw_params(struct hdmi_ip_data *ip_data,
636 struct snd_pcm_substream *substream,
ad44cc32
RN		 637 struct snd_pcm_hw_params *params,
638 struct snd_soc_dai *dai)
639{
640 struct hdmi_audio_format audio_format;
641 struct hdmi_audio_dma audio_dma;
642 struct hdmi_core_audio_config core_cfg;
643 struct hdmi_core_infoframe_audio aud_if_cfg;
644 int err, n, cts;
645 enum hdmi_core_audio_sample_freq sample_freq;
646
647 switch (params_format(params)) {
648 case SNDRV_PCM_FORMAT_S16_LE:
649 core_cfg.i2s_cfg.word_max_length =
650 HDMI_AUDIO_I2S_MAX_WORD_20BITS;
651 core_cfg.i2s_cfg.word_length = HDMI_AUDIO_I2S_CHST_WORD_16_BITS;
652 core_cfg.i2s_cfg.in_length_bits =
653 HDMI_AUDIO_I2S_INPUT_LENGTH_16;
654 core_cfg.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_LEFT;
655 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES;
656 audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS;
657 audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT;
658 audio_dma.transfer_size = 0x10;
659 break;
660 case SNDRV_PCM_FORMAT_S24_LE:
661 core_cfg.i2s_cfg.word_max_length =
662 HDMI_AUDIO_I2S_MAX_WORD_24BITS;
663 core_cfg.i2s_cfg.word_length = HDMI_AUDIO_I2S_CHST_WORD_24_BITS;
664 core_cfg.i2s_cfg.in_length_bits =
665 HDMI_AUDIO_I2S_INPUT_LENGTH_24;
666 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_ONESAMPLE;
667 audio_format.sample_size = HDMI_AUDIO_SAMPLE_24BITS;
668 audio_format.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
669 core_cfg.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
670 audio_dma.transfer_size = 0x20;
671 break;
672 default:
673 return -EINVAL;
674 }
675
676 switch (params_rate(params)) {
677 case 32000:
678 sample_freq = HDMI_AUDIO_FS_32000;
679 break;
680 case 44100:
681 sample_freq = HDMI_AUDIO_FS_44100;
682 break;
683 case 48000:
684 sample_freq = HDMI_AUDIO_FS_48000;
685 break;
686 default:
687 return -EINVAL;
688 }
689
95a8aeb6 690 err = hdmi_config_audio_acr(ip_data, params_rate(params), &n, &cts);
ad44cc32
RN		 691 if (err < 0)
692 return err;
693
694 /* Audio wrapper config */
695 audio_format.stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL;
696 audio_format.active_chnnls_msk = 0x03;
697 audio_format.type = HDMI_AUDIO_TYPE_LPCM;
698 audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
699 /* Disable start/stop signals of IEC 60958 blocks */
700 audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF;
701
702 audio_dma.block_size = 0xC0;
703 audio_dma.mode = HDMI_AUDIO_TRANSF_DMA;
704 audio_dma.fifo_threshold = 0x20; /* in number of samples */
705
95a8aeb6
M		 706 hdmi_wp_audio_config_dma(ip_data, &audio_dma);
707 hdmi_wp_audio_config_format(ip_data, &audio_format);
ad44cc32
RN		 708
709 /*
710 * I2S config
711 */
712 core_cfg.i2s_cfg.en_high_bitrate_aud = false;
713 /* Only used with high bitrate audio */
714 core_cfg.i2s_cfg.cbit_order = false;
715 /* Serial data and word select should change on sck rising edge */
716 core_cfg.i2s_cfg.sck_edge_mode = HDMI_AUDIO_I2S_SCK_EDGE_RISING;
717 core_cfg.i2s_cfg.vbit = HDMI_AUDIO_I2S_VBIT_FOR_PCM;
718 /* Set I2S word select polarity */
719 core_cfg.i2s_cfg.ws_polarity = HDMI_AUDIO_I2S_WS_POLARITY_LOW_IS_LEFT;
720 core_cfg.i2s_cfg.direction = HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST;
721 /* Set serial data to word select shift. See Phillips spec. */
722 core_cfg.i2s_cfg.shift = HDMI_AUDIO_I2S_FIRST_BIT_SHIFT;
723 /* Enable one of the four available serial data channels */
724 core_cfg.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN;
725
726 /* Core audio config */
727 core_cfg.freq_sample = sample_freq;
728 core_cfg.n = n;
729 core_cfg.cts = cts;
730 if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) {
731 core_cfg.aud_par_busclk = 0;
732 core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_SW;
733 core_cfg.use_mclk = false;
734 } else {
735 core_cfg.aud_par_busclk = (((128 * 31) - 1) << 8);
736 core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_HW;
737 core_cfg.use_mclk = true;
738 core_cfg.mclk_mode = HDMI_AUDIO_MCLK_128FS;
739 }
740 core_cfg.layout = HDMI_AUDIO_LAYOUT_2CH;
741 core_cfg.en_spdif = false;
742 /* Use sample frequency from channel status word */
743 core_cfg.fs_override = true;
744 /* Enable ACR packets */
745 core_cfg.en_acr_pkt = true;
746 /* Disable direct streaming digital audio */
747 core_cfg.en_dsd_audio = false;
748 /* Use parallel audio interface */
749 core_cfg.en_parallel_aud_input = true;
750
95a8aeb6 751 hdmi_core_audio_config(ip_data, &core_cfg);
ad44cc32
RN		 752
753 /*
754 * Configure packet
755 * info frame audio see doc CEA861-D page 74
756 */
757 aud_if_cfg.db1_coding_type = HDMI_INFOFRAME_AUDIO_DB1CT_FROM_STREAM;
758 aud_if_cfg.db1_channel_count = 2;
759 aud_if_cfg.db2_sample_freq = HDMI_INFOFRAME_AUDIO_DB2SF_FROM_STREAM;
760 aud_if_cfg.db2_sample_size = HDMI_INFOFRAME_AUDIO_DB2SS_FROM_STREAM;
761 aud_if_cfg.db4_channel_alloc = 0x00;
762 aud_if_cfg.db5_downmix_inh = false;
763 aud_if_cfg.db5_lsv = 0;
764
95a8aeb6 765 hdmi_core_audio_infoframe_config(ip_data, &aud_if_cfg);
ad44cc32
RN		 766 return 0;
767}
768
ad44cc32
RN		 769static int hdmi_audio_startup(struct snd_pcm_substream *substream,
770 struct snd_soc_dai *dai)
771{
772 if (!hdmi.mode) {
773 pr_err("Current video settings do not support audio.\n");
774 return -EIO;
775 }
776 return 0;
777}
778
779static struct snd_soc_codec_driver hdmi_audio_codec_drv = {
780};
781
782static struct snd_soc_dai_ops hdmi_audio_codec_ops = {
783 .hw_params = hdmi_audio_hw_params,
784 .trigger = hdmi_audio_trigger,
785 .startup = hdmi_audio_startup,
786};
787
788static struct snd_soc_dai_driver hdmi_codec_dai_drv = {
789 .name = "hdmi-audio-codec",
790 .playback = {
791 .channels_min = 2,
792 .channels_max = 2,
793 .rates = SNDRV_PCM_RATE_32000 |
794 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
795 .formats = SNDRV_PCM_FMTBIT_S16_LE |
796 SNDRV_PCM_FMTBIT_S24_LE,
797 },
798 .ops = &hdmi_audio_codec_ops,
799};
82335c4c
RN		 800#endif
801
4fbafaf3
TV		 802static int hdmi_get_clocks(struct platform_device *pdev)
803{
804 struct clk *clk;
805
806 clk = clk_get(&pdev->dev, "sys_clk");
807 if (IS_ERR(clk)) {
808 DSSERR("can't get sys_clk\n");
809 return PTR_ERR(clk);
810 }
811
812 hdmi.sys_clk = clk;
813
4fbafaf3
TV		 814 return 0;
815}
816
817static void hdmi_put_clocks(void)
818{
819 if (hdmi.sys_clk)
820 clk_put(hdmi.sys_clk);
4fbafaf3
TV		 821}
822
c3198a5e
M		 823/* HDMI HW IP initialisation */
824static int omapdss_hdmihw_probe(struct platform_device *pdev)
825{
826 struct resource *hdmi_mem;
4fbafaf3 827 int r;
c3198a5e
M		 828
829 hdmi.pdata = pdev->dev.platform_data;
830 hdmi.pdev = pdev;
831
832 mutex_init(&hdmi.lock);
833
834 hdmi_mem = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0);
835 if (!hdmi_mem) {
836 DSSERR("can't get IORESOURCE_MEM HDMI\n");
837 return -EINVAL;
838 }
839
840 /* Base address taken from platform */
95a8aeb6
M		 841 hdmi.ip_data.base_wp = ioremap(hdmi_mem->start,
842 resource_size(hdmi_mem));
843 if (!hdmi.ip_data.base_wp) {
c3198a5e
M		 844 DSSERR("can't ioremap WP\n");
845 return -ENOMEM;
846 }
847
4fbafaf3
TV		 848 r = hdmi_get_clocks(pdev);
849 if (r) {
95a8aeb6 850 iounmap(hdmi.ip_data.base_wp);
4fbafaf3
TV		 851 return r;
852 }
853
854 pm_runtime_enable(&pdev->dev);
855
95a8aeb6
M		 856 hdmi.ip_data.core_sys_offset = HDMI_CORE_SYS;
857 hdmi.ip_data.core_av_offset = HDMI_CORE_AV;
858 hdmi.ip_data.pll_offset = HDMI_PLLCTRL;
859 hdmi.ip_data.phy_offset = HDMI_PHY;
860
c3198a5e
M		 861 hdmi_panel_init();
862
ad44cc32
RN		 863#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
864 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
865
866 /* Register ASoC codec DAI */
4fbafaf3 867 r = snd_soc_register_codec(&pdev->dev, &hdmi_audio_codec_drv,
ad44cc32 868 &hdmi_codec_dai_drv, 1);
4fbafaf3 869 if (r) {
ad44cc32 870 DSSERR("can't register ASoC HDMI audio codec\n");
4fbafaf3 871 return r;
ad44cc32
RN		 872 }
873#endif
c3198a5e
M		 874 return 0;
875}
876
877static int omapdss_hdmihw_remove(struct platform_device *pdev)
878{
879 hdmi_panel_exit();
880
ad44cc32
RN		 881#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
882 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
883 snd_soc_unregister_codec(&pdev->dev);
884#endif
885
4fbafaf3
TV		 886 pm_runtime_disable(&pdev->dev);
887
888 hdmi_put_clocks();
889
95a8aeb6 890 iounmap(hdmi.ip_data.base_wp);
c3198a5e
M		 891
892 return 0;
893}
894
4fbafaf3
TV		 895static int hdmi_runtime_suspend(struct device *dev)
896{
4fbafaf3
TV		 897 clk_disable(hdmi.sys_clk);
898
899 dispc_runtime_put();
900 dss_runtime_put();
901
902 return 0;
903}
904
905static int hdmi_runtime_resume(struct device *dev)
906{
907 int r;
908
909 r = dss_runtime_get();
910 if (r < 0)
911 goto err_get_dss;
912
913 r = dispc_runtime_get();
914 if (r < 0)
915 goto err_get_dispc;
916
917
918 clk_enable(hdmi.sys_clk);
4fbafaf3
TV		 919
920 return 0;
921
922err_get_dispc:
923 dss_runtime_put();
924err_get_dss:
925 return r;
926}
927
928static const struct dev_pm_ops hdmi_pm_ops = {
929 .runtime_suspend = hdmi_runtime_suspend,
930 .runtime_resume = hdmi_runtime_resume,
931};
932
c3198a5e
M		 933static struct platform_driver omapdss_hdmihw_driver = {
934 .probe = omapdss_hdmihw_probe,
935 .remove = omapdss_hdmihw_remove,
936 .driver = {
937 .name = "omapdss_hdmi",
938 .owner = THIS_MODULE,
4fbafaf3 939 .pm = &hdmi_pm_ops,
c3198a5e
M		 940 },
941};
942
943int hdmi_init_platform_driver(void)
944{
945 return platform_driver_register(&omapdss_hdmihw_driver);
946}
947
948void hdmi_uninit_platform_driver(void)
949{
950 return platform_driver_unregister(&omapdss_hdmihw_driver);
951}
Linux kernel - Deliverables
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