Commit | Line | Data |
---|---|---|
c3198a5e M |
1 | /* |
2 | * hdmi.c | |
3 | * | |
4 | * HDMI interface DSS driver setting for TI's OMAP4 family of processor. | |
5 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ | |
6 | * Authors: Yong Zhi | |
7 | * Mythri pk <mythripk@ti.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License version 2 as published by | |
11 | * the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along with | |
19 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #define DSS_SUBSYS_NAME "HDMI" | |
23 | ||
24 | #include <linux/kernel.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/err.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/mutex.h> | |
30 | #include <linux/delay.h> | |
31 | #include <linux/string.h> | |
24e6289c | 32 | #include <linux/platform_device.h> |
4fbafaf3 TV |
33 | #include <linux/pm_runtime.h> |
34 | #include <linux/clk.h> | |
a0b38cc4 | 35 | #include <video/omapdss.h> |
c3198a5e | 36 | |
94c52987 | 37 | #include "ti_hdmi.h" |
c3198a5e | 38 | #include "dss.h" |
ad44cc32 | 39 | #include "dss_features.h" |
c3198a5e | 40 | |
95a8aeb6 M |
41 | #define HDMI_WP 0x0 |
42 | #define HDMI_CORE_SYS 0x400 | |
43 | #define HDMI_CORE_AV 0x900 | |
44 | #define HDMI_PLLCTRL 0x200 | |
45 | #define HDMI_PHY 0x300 | |
46 | ||
7c1f1eca M |
47 | /* HDMI EDID Length move this */ |
48 | #define HDMI_EDID_MAX_LENGTH 256 | |
49 | #define EDID_TIMING_DESCRIPTOR_SIZE 0x12 | |
50 | #define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36 | |
51 | #define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80 | |
52 | #define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4 | |
53 | #define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4 | |
54 | ||
b44e4582 | 55 | #define HDMI_DEFAULT_REGN 16 |
8d88767a TV |
56 | #define HDMI_DEFAULT_REGM2 1 |
57 | ||
c3198a5e M |
58 | static struct { |
59 | struct mutex lock; | |
c3198a5e | 60 | struct platform_device *pdev; |
95a8aeb6 | 61 | struct hdmi_ip_data ip_data; |
4fbafaf3 TV |
62 | |
63 | struct clk *sys_clk; | |
c3198a5e M |
64 | } hdmi; |
65 | ||
66 | /* | |
67 | * Logic for the below structure : | |
68 | * user enters the CEA or VESA timings by specifying the HDMI/DVI code. | |
69 | * There is a correspondence between CEA/VESA timing and code, please | |
70 | * refer to section 6.3 in HDMI 1.3 specification for timing code. | |
71 | * | |
72 | * In the below structure, cea_vesa_timings corresponds to all OMAP4 | |
73 | * supported CEA and VESA timing values.code_cea corresponds to the CEA | |
74 | * code, It is used to get the timing from cea_vesa_timing array.Similarly | |
75 | * with code_vesa. Code_index is used for back mapping, that is once EDID | |
76 | * is read from the TV, EDID is parsed to find the timing values and then | |
77 | * map it to corresponding CEA or VESA index. | |
78 | */ | |
79 | ||
46095b2d | 80 | static const struct hdmi_config cea_timings[] = { |
a05ce78f M |
81 | { {640, 480, 25200, 96, 16, 48, 2, 10, 33, 0, 0, 0}, {1, HDMI_HDMI} }, |
82 | { {720, 480, 27027, 62, 16, 60, 6, 9, 30, 0, 0, 0}, {2, HDMI_HDMI} }, | |
83 | { {1280, 720, 74250, 40, 110, 220, 5, 5, 20, 1, 1, 0}, {4, HDMI_HDMI} }, | |
84 | { {1920, 540, 74250, 44, 88, 148, 5, 2, 15, 1, 1, 1}, {5, HDMI_HDMI} }, | |
85 | { {1440, 240, 27027, 124, 38, 114, 3, 4, 15, 0, 0, 1}, {6, HDMI_HDMI} }, | |
86 | { {1920, 1080, 148500, 44, 88, 148, 5, 4, 36, 1, 1, 0}, {16, HDMI_HDMI} }, | |
87 | { {720, 576, 27000, 64, 12, 68, 5, 5, 39, 0, 0, 0}, {17, HDMI_HDMI} }, | |
88 | { {1280, 720, 74250, 40, 440, 220, 5, 5, 20, 1, 1, 0}, {19, HDMI_HDMI} }, | |
89 | { {1920, 540, 74250, 44, 528, 148, 5, 2, 15, 1, 1, 1}, {20, HDMI_HDMI} }, | |
90 | { {1440, 288, 27000, 126, 24, 138, 3, 2, 19, 0, 0, 1}, {21, HDMI_HDMI} }, | |
91 | { {1440, 576, 54000, 128, 24, 136, 5, 5, 39, 0, 0, 0}, {29, HDMI_HDMI} }, | |
92 | { {1920, 1080, 148500, 44, 528, 148, 5, 4, 36, 1, 1, 0}, {31, HDMI_HDMI} }, | |
93 | { {1920, 1080, 74250, 44, 638, 148, 5, 4, 36, 1, 1, 0}, {32, HDMI_HDMI} }, | |
94 | { {2880, 480, 108108, 248, 64, 240, 6, 9, 30, 0, 0, 0}, {35, HDMI_HDMI} }, | |
95 | { {2880, 576, 108000, 256, 48, 272, 5, 5, 39, 0, 0, 0}, {37, HDMI_HDMI} }, | |
46095b2d M |
96 | }; |
97 | static const struct hdmi_config vesa_timings[] = { | |
a05ce78f M |
98 | /* VESA From Here */ |
99 | { {640, 480, 25175, 96, 16, 48, 2 , 11, 31, 0, 0, 0}, {4, HDMI_DVI} }, | |
100 | { {800, 600, 40000, 128, 40, 88, 4 , 1, 23, 1, 1, 0}, {9, HDMI_DVI} }, | |
101 | { {848, 480, 33750, 112, 16, 112, 8 , 6, 23, 1, 1, 0}, {0xE, HDMI_DVI} }, | |
102 | { {1280, 768, 79500, 128, 64, 192, 7 , 3, 20, 1, 0, 0}, {0x17, HDMI_DVI} }, | |
103 | { {1280, 800, 83500, 128, 72, 200, 6 , 3, 22, 1, 0, 0}, {0x1C, HDMI_DVI} }, | |
104 | { {1360, 768, 85500, 112, 64, 256, 6 , 3, 18, 1, 1, 0}, {0x27, HDMI_DVI} }, | |
105 | { {1280, 960, 108000, 112, 96, 312, 3 , 1, 36, 1, 1, 0}, {0x20, HDMI_DVI} }, | |
106 | { {1280, 1024, 108000, 112, 48, 248, 3 , 1, 38, 1, 1, 0}, {0x23, HDMI_DVI} }, | |
107 | { {1024, 768, 65000, 136, 24, 160, 6, 3, 29, 0, 0, 0}, {0x10, HDMI_DVI} }, | |
108 | { {1400, 1050, 121750, 144, 88, 232, 4, 3, 32, 1, 0, 0}, {0x2A, HDMI_DVI} }, | |
109 | { {1440, 900, 106500, 152, 80, 232, 6, 3, 25, 1, 0, 0}, {0x2F, HDMI_DVI} }, | |
110 | { {1680, 1050, 146250, 176 , 104, 280, 6, 3, 30, 1, 0, 0}, {0x3A, HDMI_DVI} }, | |
111 | { {1366, 768, 85500, 143, 70, 213, 3, 3, 24, 1, 1, 0}, {0x51, HDMI_DVI} }, | |
112 | { {1920, 1080, 148500, 44, 148, 80, 5, 4, 36, 1, 1, 0}, {0x52, HDMI_DVI} }, | |
113 | { {1280, 768, 68250, 32, 48, 80, 7, 3, 12, 0, 1, 0}, {0x16, HDMI_DVI} }, | |
114 | { {1400, 1050, 101000, 32, 48, 80, 4, 3, 23, 0, 1, 0}, {0x29, HDMI_DVI} }, | |
115 | { {1680, 1050, 119000, 32, 48, 80, 6, 3, 21, 0, 1, 0}, {0x39, HDMI_DVI} }, | |
116 | { {1280, 800, 79500, 32, 48, 80, 6, 3, 14, 0, 1, 0}, {0x1B, HDMI_DVI} }, | |
117 | { {1280, 720, 74250, 40, 110, 220, 5, 5, 20, 1, 1, 0}, {0x55, HDMI_DVI} } | |
c3198a5e M |
118 | }; |
119 | ||
4fbafaf3 TV |
120 | static int hdmi_runtime_get(void) |
121 | { | |
122 | int r; | |
123 | ||
124 | DSSDBG("hdmi_runtime_get\n"); | |
125 | ||
126 | r = pm_runtime_get_sync(&hdmi.pdev->dev); | |
127 | WARN_ON(r < 0); | |
a247ce78 | 128 | if (r < 0) |
852f0838 | 129 | return r; |
a247ce78 AT |
130 | |
131 | return 0; | |
4fbafaf3 TV |
132 | } |
133 | ||
134 | static void hdmi_runtime_put(void) | |
135 | { | |
136 | int r; | |
137 | ||
138 | DSSDBG("hdmi_runtime_put\n"); | |
139 | ||
0eaf9f52 | 140 | r = pm_runtime_put_sync(&hdmi.pdev->dev); |
4fbafaf3 TV |
141 | WARN_ON(r < 0); |
142 | } | |
143 | ||
9d8232a7 | 144 | static int __init hdmi_init_display(struct omap_dss_device *dssdev) |
c3198a5e M |
145 | { |
146 | DSSDBG("init_display\n"); | |
147 | ||
60634a28 | 148 | dss_init_hdmi_ip_ops(&hdmi.ip_data); |
c3198a5e M |
149 | return 0; |
150 | } | |
151 | ||
46095b2d M |
152 | static const struct hdmi_config *hdmi_find_timing( |
153 | const struct hdmi_config *timings_arr, | |
154 | int len) | |
c3198a5e | 155 | { |
46095b2d | 156 | int i; |
c3198a5e | 157 | |
46095b2d | 158 | for (i = 0; i < len; i++) { |
9e4ed603 | 159 | if (timings_arr[i].cm.code == hdmi.ip_data.cfg.cm.code) |
46095b2d M |
160 | return &timings_arr[i]; |
161 | } | |
162 | return NULL; | |
163 | } | |
c3198a5e | 164 | |
46095b2d M |
165 | static const struct hdmi_config *hdmi_get_timings(void) |
166 | { | |
167 | const struct hdmi_config *arr; | |
168 | int len; | |
169 | ||
9e4ed603 | 170 | if (hdmi.ip_data.cfg.cm.mode == HDMI_DVI) { |
46095b2d M |
171 | arr = vesa_timings; |
172 | len = ARRAY_SIZE(vesa_timings); | |
173 | } else { | |
174 | arr = cea_timings; | |
175 | len = ARRAY_SIZE(cea_timings); | |
176 | } | |
177 | ||
178 | return hdmi_find_timing(arr, len); | |
179 | } | |
180 | ||
181 | static bool hdmi_timings_compare(struct omap_video_timings *timing1, | |
182 | const struct hdmi_video_timings *timing2) | |
183 | { | |
184 | int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync; | |
185 | ||
186 | if ((timing2->pixel_clock == timing1->pixel_clock) && | |
187 | (timing2->x_res == timing1->x_res) && | |
188 | (timing2->y_res == timing1->y_res)) { | |
c3198a5e | 189 | |
46095b2d M |
190 | timing2_hsync = timing2->hfp + timing2->hsw + timing2->hbp; |
191 | timing1_hsync = timing1->hfp + timing1->hsw + timing1->hbp; | |
192 | timing2_vsync = timing2->vfp + timing2->vsw + timing2->vbp; | |
193 | timing1_vsync = timing2->vfp + timing2->vsw + timing2->vbp; | |
194 | ||
195 | DSSDBG("timing1_hsync = %d timing1_vsync = %d"\ | |
196 | "timing2_hsync = %d timing2_vsync = %d\n", | |
197 | timing1_hsync, timing1_vsync, | |
198 | timing2_hsync, timing2_vsync); | |
199 | ||
200 | if ((timing1_hsync == timing2_hsync) && | |
201 | (timing1_vsync == timing2_vsync)) { | |
202 | return true; | |
203 | } | |
c3198a5e | 204 | } |
46095b2d | 205 | return false; |
c3198a5e M |
206 | } |
207 | ||
208 | static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing) | |
209 | { | |
46095b2d | 210 | int i; |
c3198a5e M |
211 | struct hdmi_cm cm = {-1}; |
212 | DSSDBG("hdmi_get_code\n"); | |
213 | ||
46095b2d M |
214 | for (i = 0; i < ARRAY_SIZE(cea_timings); i++) { |
215 | if (hdmi_timings_compare(timing, &cea_timings[i].timings)) { | |
216 | cm = cea_timings[i].cm; | |
217 | goto end; | |
218 | } | |
219 | } | |
220 | for (i = 0; i < ARRAY_SIZE(vesa_timings); i++) { | |
221 | if (hdmi_timings_compare(timing, &vesa_timings[i].timings)) { | |
222 | cm = vesa_timings[i].cm; | |
223 | goto end; | |
c3198a5e M |
224 | } |
225 | } | |
226 | ||
46095b2d | 227 | end: return cm; |
c3198a5e | 228 | |
c3198a5e M |
229 | } |
230 | ||
c3dc6a7a AT |
231 | unsigned long hdmi_get_pixel_clock(void) |
232 | { | |
233 | /* HDMI Pixel Clock in Mhz */ | |
a05ce78f | 234 | return hdmi.ip_data.cfg.timings.pixel_clock * 1000; |
c3dc6a7a AT |
235 | } |
236 | ||
6cb07b25 AT |
237 | static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy, |
238 | struct hdmi_pll_info *pi) | |
c3198a5e | 239 | { |
6cb07b25 | 240 | unsigned long clkin, refclk; |
c3198a5e M |
241 | u32 mf; |
242 | ||
4fbafaf3 | 243 | clkin = clk_get_rate(hdmi.sys_clk) / 10000; |
c3198a5e M |
244 | /* |
245 | * Input clock is predivided by N + 1 | |
246 | * out put of which is reference clk | |
247 | */ | |
8d88767a TV |
248 | if (dssdev->clocks.hdmi.regn == 0) |
249 | pi->regn = HDMI_DEFAULT_REGN; | |
250 | else | |
251 | pi->regn = dssdev->clocks.hdmi.regn; | |
252 | ||
b44e4582 | 253 | refclk = clkin / pi->regn; |
c3198a5e | 254 | |
8d88767a TV |
255 | if (dssdev->clocks.hdmi.regm2 == 0) |
256 | pi->regm2 = HDMI_DEFAULT_REGM2; | |
257 | else | |
258 | pi->regm2 = dssdev->clocks.hdmi.regm2; | |
c3198a5e | 259 | |
dd2116a3 M |
260 | /* |
261 | * multiplier is pixel_clk/ref_clk | |
262 | * Multiplying by 100 to avoid fractional part removal | |
263 | */ | |
264 | pi->regm = phy * pi->regm2 / refclk; | |
265 | ||
c3198a5e M |
266 | /* |
267 | * fractional multiplier is remainder of the difference between | |
268 | * multiplier and actual phy(required pixel clock thus should be | |
269 | * multiplied by 2^18(262144) divided by the reference clock | |
270 | */ | |
dd2116a3 M |
271 | mf = (phy - pi->regm / pi->regm2 * refclk) * 262144; |
272 | pi->regmf = pi->regm2 * mf / refclk; | |
c3198a5e M |
273 | |
274 | /* | |
275 | * Dcofreq should be set to 1 if required pixel clock | |
276 | * is greater than 1000MHz | |
277 | */ | |
278 | pi->dcofreq = phy > 1000 * 100; | |
b44e4582 | 279 | pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10; |
c3198a5e | 280 | |
7b27da54 M |
281 | /* Set the reference clock to sysclk reference */ |
282 | pi->refsel = HDMI_REFSEL_SYSCLK; | |
283 | ||
c3198a5e M |
284 | DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf); |
285 | DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd); | |
286 | } | |
287 | ||
c3198a5e M |
288 | static int hdmi_power_on(struct omap_dss_device *dssdev) |
289 | { | |
46095b2d M |
290 | int r; |
291 | const struct hdmi_config *timing; | |
c3198a5e | 292 | struct omap_video_timings *p; |
6cb07b25 | 293 | unsigned long phy; |
c3198a5e | 294 | |
4fbafaf3 TV |
295 | r = hdmi_runtime_get(); |
296 | if (r) | |
297 | return r; | |
c3198a5e | 298 | |
7797c6da | 299 | dss_mgr_disable(dssdev->manager); |
c3198a5e M |
300 | |
301 | p = &dssdev->panel.timings; | |
302 | ||
303 | DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", | |
304 | dssdev->panel.timings.x_res, | |
305 | dssdev->panel.timings.y_res); | |
306 | ||
46095b2d M |
307 | timing = hdmi_get_timings(); |
308 | if (timing == NULL) { | |
309 | /* HDMI code 4 corresponds to 640 * 480 VGA */ | |
9e4ed603 | 310 | hdmi.ip_data.cfg.cm.code = 4; |
46095b2d | 311 | /* DVI mode 1 corresponds to HDMI 0 to DVI */ |
9e4ed603 | 312 | hdmi.ip_data.cfg.cm.mode = HDMI_DVI; |
46095b2d M |
313 | hdmi.ip_data.cfg = vesa_timings[0]; |
314 | } else { | |
315 | hdmi.ip_data.cfg = *timing; | |
316 | } | |
c3198a5e M |
317 | phy = p->pixel_clock; |
318 | ||
7b27da54 | 319 | hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data); |
c3198a5e | 320 | |
c0456be3 | 321 | hdmi.ip_data.ops->video_disable(&hdmi.ip_data); |
c3198a5e | 322 | |
95a8aeb6 | 323 | /* config the PLL and PHY hdmi_set_pll_pwrfirst */ |
60634a28 | 324 | r = hdmi.ip_data.ops->pll_enable(&hdmi.ip_data); |
c3198a5e M |
325 | if (r) { |
326 | DSSDBG("Failed to lock PLL\n"); | |
327 | goto err; | |
328 | } | |
329 | ||
60634a28 | 330 | r = hdmi.ip_data.ops->phy_enable(&hdmi.ip_data); |
c3198a5e M |
331 | if (r) { |
332 | DSSDBG("Failed to start PHY\n"); | |
333 | goto err; | |
334 | } | |
335 | ||
60634a28 | 336 | hdmi.ip_data.ops->video_configure(&hdmi.ip_data); |
c3198a5e M |
337 | |
338 | /* Make selection of HDMI in DSS */ | |
339 | dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK); | |
340 | ||
341 | /* Select the dispc clock source as PRCM clock, to ensure that it is not | |
342 | * DSI PLL source as the clock selected by DSI PLL might not be | |
343 | * sufficient for the resolution selected / that can be changed | |
344 | * dynamically by user. This can be moved to single location , say | |
345 | * Boardfile. | |
346 | */ | |
6cb07b25 | 347 | dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src); |
c3198a5e M |
348 | |
349 | /* bypass TV gamma table */ | |
350 | dispc_enable_gamma_table(0); | |
351 | ||
352 | /* tv size */ | |
41721163 | 353 | dss_mgr_set_timings(dssdev->manager, &dssdev->panel.timings); |
c3198a5e | 354 | |
c0456be3 RN |
355 | r = hdmi.ip_data.ops->video_enable(&hdmi.ip_data); |
356 | if (r) | |
357 | goto err_vid_enable; | |
c3198a5e | 358 | |
33ca237f TV |
359 | r = dss_mgr_enable(dssdev->manager); |
360 | if (r) | |
361 | goto err_mgr_enable; | |
3870c909 | 362 | |
c3198a5e | 363 | return 0; |
33ca237f TV |
364 | |
365 | err_mgr_enable: | |
c0456be3 RN |
366 | hdmi.ip_data.ops->video_disable(&hdmi.ip_data); |
367 | err_vid_enable: | |
33ca237f TV |
368 | hdmi.ip_data.ops->phy_disable(&hdmi.ip_data); |
369 | hdmi.ip_data.ops->pll_disable(&hdmi.ip_data); | |
c3198a5e | 370 | err: |
4fbafaf3 | 371 | hdmi_runtime_put(); |
c3198a5e M |
372 | return -EIO; |
373 | } | |
374 | ||
375 | static void hdmi_power_off(struct omap_dss_device *dssdev) | |
376 | { | |
7797c6da | 377 | dss_mgr_disable(dssdev->manager); |
c3198a5e | 378 | |
c0456be3 | 379 | hdmi.ip_data.ops->video_disable(&hdmi.ip_data); |
60634a28 M |
380 | hdmi.ip_data.ops->phy_disable(&hdmi.ip_data); |
381 | hdmi.ip_data.ops->pll_disable(&hdmi.ip_data); | |
4fbafaf3 | 382 | hdmi_runtime_put(); |
c3198a5e M |
383 | } |
384 | ||
385 | int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev, | |
386 | struct omap_video_timings *timings) | |
387 | { | |
388 | struct hdmi_cm cm; | |
389 | ||
390 | cm = hdmi_get_code(timings); | |
391 | if (cm.code == -1) { | |
c3198a5e M |
392 | return -EINVAL; |
393 | } | |
394 | ||
395 | return 0; | |
396 | ||
397 | } | |
398 | ||
399 | void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev) | |
400 | { | |
401 | struct hdmi_cm cm; | |
402 | ||
c3198a5e | 403 | cm = hdmi_get_code(&dssdev->panel.timings); |
9e4ed603 M |
404 | hdmi.ip_data.cfg.cm.code = cm.code; |
405 | hdmi.ip_data.cfg.cm.mode = cm.mode; | |
fa70dc5f TV |
406 | |
407 | if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) { | |
408 | int r; | |
409 | ||
410 | hdmi_power_off(dssdev); | |
411 | ||
412 | r = hdmi_power_on(dssdev); | |
413 | if (r) | |
414 | DSSERR("failed to power on device\n"); | |
fcc36619 AT |
415 | } else { |
416 | dss_mgr_set_timings(dssdev->manager, &dssdev->panel.timings); | |
fa70dc5f | 417 | } |
c3198a5e M |
418 | } |
419 | ||
e40402cf | 420 | static void hdmi_dump_regs(struct seq_file *s) |
162874d5 M |
421 | { |
422 | mutex_lock(&hdmi.lock); | |
423 | ||
424 | if (hdmi_runtime_get()) | |
425 | return; | |
426 | ||
427 | hdmi.ip_data.ops->dump_wrapper(&hdmi.ip_data, s); | |
428 | hdmi.ip_data.ops->dump_pll(&hdmi.ip_data, s); | |
429 | hdmi.ip_data.ops->dump_phy(&hdmi.ip_data, s); | |
430 | hdmi.ip_data.ops->dump_core(&hdmi.ip_data, s); | |
431 | ||
432 | hdmi_runtime_put(); | |
433 | mutex_unlock(&hdmi.lock); | |
434 | } | |
435 | ||
47024565 TV |
436 | int omapdss_hdmi_read_edid(u8 *buf, int len) |
437 | { | |
438 | int r; | |
439 | ||
440 | mutex_lock(&hdmi.lock); | |
441 | ||
442 | r = hdmi_runtime_get(); | |
443 | BUG_ON(r); | |
444 | ||
445 | r = hdmi.ip_data.ops->read_edid(&hdmi.ip_data, buf, len); | |
446 | ||
447 | hdmi_runtime_put(); | |
448 | mutex_unlock(&hdmi.lock); | |
449 | ||
450 | return r; | |
451 | } | |
452 | ||
759593ff TV |
453 | bool omapdss_hdmi_detect(void) |
454 | { | |
455 | int r; | |
456 | ||
457 | mutex_lock(&hdmi.lock); | |
458 | ||
459 | r = hdmi_runtime_get(); | |
460 | BUG_ON(r); | |
461 | ||
462 | r = hdmi.ip_data.ops->detect(&hdmi.ip_data); | |
463 | ||
464 | hdmi_runtime_put(); | |
465 | mutex_unlock(&hdmi.lock); | |
466 | ||
467 | return r == 1; | |
468 | } | |
469 | ||
c3198a5e M |
470 | int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev) |
471 | { | |
c49d005b | 472 | struct omap_dss_hdmi_data *priv = dssdev->data; |
c3198a5e M |
473 | int r = 0; |
474 | ||
475 | DSSDBG("ENTER hdmi_display_enable\n"); | |
476 | ||
477 | mutex_lock(&hdmi.lock); | |
478 | ||
05e1d606 TV |
479 | if (dssdev->manager == NULL) { |
480 | DSSERR("failed to enable display: no manager\n"); | |
481 | r = -ENODEV; | |
482 | goto err0; | |
483 | } | |
484 | ||
c49d005b TV |
485 | hdmi.ip_data.hpd_gpio = priv->hpd_gpio; |
486 | ||
c3198a5e M |
487 | r = omap_dss_start_device(dssdev); |
488 | if (r) { | |
489 | DSSERR("failed to start device\n"); | |
490 | goto err0; | |
491 | } | |
492 | ||
493 | if (dssdev->platform_enable) { | |
494 | r = dssdev->platform_enable(dssdev); | |
495 | if (r) { | |
496 | DSSERR("failed to enable GPIO's\n"); | |
497 | goto err1; | |
498 | } | |
499 | } | |
500 | ||
501 | r = hdmi_power_on(dssdev); | |
502 | if (r) { | |
503 | DSSERR("failed to power on device\n"); | |
504 | goto err2; | |
505 | } | |
506 | ||
507 | mutex_unlock(&hdmi.lock); | |
508 | return 0; | |
509 | ||
510 | err2: | |
511 | if (dssdev->platform_disable) | |
512 | dssdev->platform_disable(dssdev); | |
513 | err1: | |
514 | omap_dss_stop_device(dssdev); | |
515 | err0: | |
516 | mutex_unlock(&hdmi.lock); | |
517 | return r; | |
518 | } | |
519 | ||
520 | void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev) | |
521 | { | |
522 | DSSDBG("Enter hdmi_display_disable\n"); | |
523 | ||
524 | mutex_lock(&hdmi.lock); | |
525 | ||
526 | hdmi_power_off(dssdev); | |
527 | ||
528 | if (dssdev->platform_disable) | |
529 | dssdev->platform_disable(dssdev); | |
530 | ||
531 | omap_dss_stop_device(dssdev); | |
532 | ||
533 | mutex_unlock(&hdmi.lock); | |
534 | } | |
535 | ||
4fbafaf3 TV |
536 | static int hdmi_get_clocks(struct platform_device *pdev) |
537 | { | |
538 | struct clk *clk; | |
539 | ||
540 | clk = clk_get(&pdev->dev, "sys_clk"); | |
541 | if (IS_ERR(clk)) { | |
542 | DSSERR("can't get sys_clk\n"); | |
543 | return PTR_ERR(clk); | |
544 | } | |
545 | ||
546 | hdmi.sys_clk = clk; | |
547 | ||
4fbafaf3 TV |
548 | return 0; |
549 | } | |
550 | ||
551 | static void hdmi_put_clocks(void) | |
552 | { | |
553 | if (hdmi.sys_clk) | |
554 | clk_put(hdmi.sys_clk); | |
4fbafaf3 TV |
555 | } |
556 | ||
35547626 RN |
557 | #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) |
558 | int hdmi_compute_acr(u32 sample_freq, u32 *n, u32 *cts) | |
559 | { | |
560 | u32 deep_color; | |
25a65359 | 561 | bool deep_color_correct = false; |
35547626 RN |
562 | u32 pclk = hdmi.ip_data.cfg.timings.pixel_clock; |
563 | ||
564 | if (n == NULL || cts == NULL) | |
565 | return -EINVAL; | |
566 | ||
567 | /* TODO: When implemented, query deep color mode here. */ | |
568 | deep_color = 100; | |
569 | ||
25a65359 RN |
570 | /* |
571 | * When using deep color, the default N value (as in the HDMI | |
572 | * specification) yields to an non-integer CTS. Hence, we | |
573 | * modify it while keeping the restrictions described in | |
574 | * section 7.2.1 of the HDMI 1.4a specification. | |
575 | */ | |
35547626 RN |
576 | switch (sample_freq) { |
577 | case 32000: | |
25a65359 RN |
578 | case 48000: |
579 | case 96000: | |
580 | case 192000: | |
581 | if (deep_color == 125) | |
582 | if (pclk == 27027 || pclk == 74250) | |
583 | deep_color_correct = true; | |
584 | if (deep_color == 150) | |
585 | if (pclk == 27027) | |
586 | deep_color_correct = true; | |
35547626 RN |
587 | break; |
588 | case 44100: | |
25a65359 RN |
589 | case 88200: |
590 | case 176400: | |
591 | if (deep_color == 125) | |
592 | if (pclk == 27027) | |
593 | deep_color_correct = true; | |
35547626 RN |
594 | break; |
595 | default: | |
35547626 RN |
596 | return -EINVAL; |
597 | } | |
598 | ||
25a65359 RN |
599 | if (deep_color_correct) { |
600 | switch (sample_freq) { | |
601 | case 32000: | |
602 | *n = 8192; | |
603 | break; | |
604 | case 44100: | |
605 | *n = 12544; | |
606 | break; | |
607 | case 48000: | |
608 | *n = 8192; | |
609 | break; | |
610 | case 88200: | |
611 | *n = 25088; | |
612 | break; | |
613 | case 96000: | |
614 | *n = 16384; | |
615 | break; | |
616 | case 176400: | |
617 | *n = 50176; | |
618 | break; | |
619 | case 192000: | |
620 | *n = 32768; | |
621 | break; | |
622 | default: | |
623 | return -EINVAL; | |
624 | } | |
625 | } else { | |
626 | switch (sample_freq) { | |
627 | case 32000: | |
628 | *n = 4096; | |
629 | break; | |
630 | case 44100: | |
631 | *n = 6272; | |
632 | break; | |
633 | case 48000: | |
634 | *n = 6144; | |
635 | break; | |
636 | case 88200: | |
637 | *n = 12544; | |
638 | break; | |
639 | case 96000: | |
640 | *n = 12288; | |
641 | break; | |
642 | case 176400: | |
643 | *n = 25088; | |
644 | break; | |
645 | case 192000: | |
646 | *n = 24576; | |
647 | break; | |
648 | default: | |
649 | return -EINVAL; | |
650 | } | |
651 | } | |
35547626 RN |
652 | /* Calculate CTS. See HDMI 1.3a or 1.4a specifications */ |
653 | *cts = pclk * (*n / 128) * deep_color / (sample_freq / 10); | |
654 | ||
655 | return 0; | |
656 | } | |
f3a97491 RN |
657 | |
658 | int hdmi_audio_enable(void) | |
659 | { | |
660 | DSSDBG("audio_enable\n"); | |
661 | ||
662 | return hdmi.ip_data.ops->audio_enable(&hdmi.ip_data); | |
663 | } | |
664 | ||
665 | void hdmi_audio_disable(void) | |
666 | { | |
667 | DSSDBG("audio_disable\n"); | |
668 | ||
669 | hdmi.ip_data.ops->audio_disable(&hdmi.ip_data); | |
670 | } | |
671 | ||
672 | int hdmi_audio_start(void) | |
673 | { | |
674 | DSSDBG("audio_start\n"); | |
675 | ||
676 | return hdmi.ip_data.ops->audio_start(&hdmi.ip_data); | |
677 | } | |
678 | ||
679 | void hdmi_audio_stop(void) | |
680 | { | |
681 | DSSDBG("audio_stop\n"); | |
682 | ||
683 | hdmi.ip_data.ops->audio_stop(&hdmi.ip_data); | |
684 | } | |
685 | ||
686 | bool hdmi_mode_has_audio(void) | |
687 | { | |
688 | if (hdmi.ip_data.cfg.cm.mode == HDMI_HDMI) | |
689 | return true; | |
690 | else | |
691 | return false; | |
692 | } | |
693 | ||
694 | int hdmi_audio_config(struct omap_dss_audio *audio) | |
695 | { | |
696 | return hdmi.ip_data.ops->audio_config(&hdmi.ip_data, audio); | |
697 | } | |
698 | ||
35547626 RN |
699 | #endif |
700 | ||
38f3daf6 TV |
701 | static void __init hdmi_probe_pdata(struct platform_device *pdev) |
702 | { | |
703 | struct omap_dss_board_info *pdata = pdev->dev.platform_data; | |
704 | int r, i; | |
705 | ||
706 | for (i = 0; i < pdata->num_devices; ++i) { | |
707 | struct omap_dss_device *dssdev = pdata->devices[i]; | |
708 | ||
709 | if (dssdev->type != OMAP_DISPLAY_TYPE_HDMI) | |
710 | continue; | |
711 | ||
712 | r = hdmi_init_display(dssdev); | |
713 | if (r) { | |
714 | DSSERR("device %s init failed: %d\n", dssdev->name, r); | |
715 | continue; | |
716 | } | |
717 | ||
718 | r = omap_dss_register_device(dssdev, &pdev->dev, i); | |
719 | if (r) | |
720 | DSSERR("device %s register failed: %d\n", | |
721 | dssdev->name, r); | |
722 | } | |
723 | } | |
724 | ||
c3198a5e | 725 | /* HDMI HW IP initialisation */ |
6e7e8f06 | 726 | static int __init omapdss_hdmihw_probe(struct platform_device *pdev) |
c3198a5e M |
727 | { |
728 | struct resource *hdmi_mem; | |
38f3daf6 | 729 | int r; |
c3198a5e | 730 | |
c3198a5e M |
731 | hdmi.pdev = pdev; |
732 | ||
733 | mutex_init(&hdmi.lock); | |
734 | ||
735 | hdmi_mem = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0); | |
736 | if (!hdmi_mem) { | |
737 | DSSERR("can't get IORESOURCE_MEM HDMI\n"); | |
738 | return -EINVAL; | |
739 | } | |
740 | ||
741 | /* Base address taken from platform */ | |
95a8aeb6 M |
742 | hdmi.ip_data.base_wp = ioremap(hdmi_mem->start, |
743 | resource_size(hdmi_mem)); | |
744 | if (!hdmi.ip_data.base_wp) { | |
c3198a5e M |
745 | DSSERR("can't ioremap WP\n"); |
746 | return -ENOMEM; | |
747 | } | |
748 | ||
4fbafaf3 TV |
749 | r = hdmi_get_clocks(pdev); |
750 | if (r) { | |
95a8aeb6 | 751 | iounmap(hdmi.ip_data.base_wp); |
4fbafaf3 TV |
752 | return r; |
753 | } | |
754 | ||
755 | pm_runtime_enable(&pdev->dev); | |
756 | ||
95a8aeb6 M |
757 | hdmi.ip_data.core_sys_offset = HDMI_CORE_SYS; |
758 | hdmi.ip_data.core_av_offset = HDMI_CORE_AV; | |
759 | hdmi.ip_data.pll_offset = HDMI_PLLCTRL; | |
760 | hdmi.ip_data.phy_offset = HDMI_PHY; | |
761 | ||
c3198a5e M |
762 | hdmi_panel_init(); |
763 | ||
e40402cf TV |
764 | dss_debugfs_create_file("hdmi", hdmi_dump_regs); |
765 | ||
38f3daf6 | 766 | hdmi_probe_pdata(pdev); |
35deca3d | 767 | |
c3198a5e M |
768 | return 0; |
769 | } | |
770 | ||
6e7e8f06 | 771 | static int __exit omapdss_hdmihw_remove(struct platform_device *pdev) |
c3198a5e | 772 | { |
35deca3d TV |
773 | omap_dss_unregister_child_devices(&pdev->dev); |
774 | ||
c3198a5e M |
775 | hdmi_panel_exit(); |
776 | ||
4fbafaf3 TV |
777 | pm_runtime_disable(&pdev->dev); |
778 | ||
779 | hdmi_put_clocks(); | |
780 | ||
95a8aeb6 | 781 | iounmap(hdmi.ip_data.base_wp); |
c3198a5e M |
782 | |
783 | return 0; | |
784 | } | |
785 | ||
4fbafaf3 TV |
786 | static int hdmi_runtime_suspend(struct device *dev) |
787 | { | |
f11766d1 | 788 | clk_disable_unprepare(hdmi.sys_clk); |
4fbafaf3 TV |
789 | |
790 | dispc_runtime_put(); | |
4fbafaf3 TV |
791 | |
792 | return 0; | |
793 | } | |
794 | ||
795 | static int hdmi_runtime_resume(struct device *dev) | |
796 | { | |
797 | int r; | |
798 | ||
4fbafaf3 TV |
799 | r = dispc_runtime_get(); |
800 | if (r < 0) | |
852f0838 | 801 | return r; |
4fbafaf3 | 802 | |
f11766d1 | 803 | clk_prepare_enable(hdmi.sys_clk); |
4fbafaf3 TV |
804 | |
805 | return 0; | |
4fbafaf3 TV |
806 | } |
807 | ||
808 | static const struct dev_pm_ops hdmi_pm_ops = { | |
809 | .runtime_suspend = hdmi_runtime_suspend, | |
810 | .runtime_resume = hdmi_runtime_resume, | |
811 | }; | |
812 | ||
c3198a5e | 813 | static struct platform_driver omapdss_hdmihw_driver = { |
6e7e8f06 | 814 | .remove = __exit_p(omapdss_hdmihw_remove), |
c3198a5e M |
815 | .driver = { |
816 | .name = "omapdss_hdmi", | |
817 | .owner = THIS_MODULE, | |
4fbafaf3 | 818 | .pm = &hdmi_pm_ops, |
c3198a5e M |
819 | }, |
820 | }; | |
821 | ||
6e7e8f06 | 822 | int __init hdmi_init_platform_driver(void) |
c3198a5e | 823 | { |
61055d4b | 824 | return platform_driver_probe(&omapdss_hdmihw_driver, omapdss_hdmihw_probe); |
c3198a5e M |
825 | } |
826 | ||
6e7e8f06 | 827 | void __exit hdmi_uninit_platform_driver(void) |
c3198a5e | 828 | { |
04c742c3 | 829 | platform_driver_unregister(&omapdss_hdmihw_driver); |
c3198a5e | 830 | } |