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OMAPDSS: nec-nl8048 panel: Use dev_pm_ops
[deliverable/linux.git] / drivers / video / omap2 / dss / hdmi.c
CommitLineData
c3198a5e
M		 1/*
2 * hdmi.c
3 *
4 * HDMI interface DSS driver setting for TI's OMAP4 family of processor.
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
6 * Authors: Yong Zhi
7 * Mythri pk <mythripk@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#define DSS_SUBSYS_NAME "HDMI"
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/err.h>
27#include <linux/io.h>
28#include <linux/interrupt.h>
29#include <linux/mutex.h>
30#include <linux/delay.h>
31#include <linux/string.h>
24e6289c 32#include <linux/platform_device.h>
4fbafaf3
TV		 33#include <linux/pm_runtime.h>
34#include <linux/clk.h>
cca35017 35#include <linux/gpio.h>
17486943 36#include <linux/regulator/consumer.h>
a0b38cc4 37#include <video/omapdss.h>
c3198a5e 38
94c52987 39#include "ti_hdmi.h"
c3198a5e 40#include "dss.h"
ad44cc32 41#include "dss_features.h"
c3198a5e 42
95a8aeb6
M		 43#define HDMI_WP 0x0
44#define HDMI_CORE_SYS 0x400
45#define HDMI_CORE_AV 0x900
46#define HDMI_PLLCTRL 0x200
47#define HDMI_PHY 0x300
48
7c1f1eca
M		 49/* HDMI EDID Length move this */
50#define HDMI_EDID_MAX_LENGTH 256
51#define EDID_TIMING_DESCRIPTOR_SIZE 0x12
52#define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36
53#define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80
54#define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4
55#define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4
56
b44e4582 57#define HDMI_DEFAULT_REGN 16
8d88767a
TV		 58#define HDMI_DEFAULT_REGM2 1
59
c3198a5e
M		 60static struct {
61 struct mutex lock;
c3198a5e 62 struct platform_device *pdev;
66a06b0c 63
95a8aeb6 64 struct hdmi_ip_data ip_data;
4fbafaf3
TV		 65
66 struct clk *sys_clk;
17486943 67 struct regulator *vdda_hdmi_dac_reg;
cca35017
TV		 68
69 int ct_cp_hpd_gpio;
70 int ls_oe_gpio;
71 int hpd_gpio;
81b87f51
AT		 72
73 struct omap_dss_output output;
c3198a5e
M		 74} hdmi;
75
76/*
77 * Logic for the below structure :
78 * user enters the CEA or VESA timings by specifying the HDMI/DVI code.
79 * There is a correspondence between CEA/VESA timing and code, please
80 * refer to section 6.3 in HDMI 1.3 specification for timing code.
81 *
82 * In the below structure, cea_vesa_timings corresponds to all OMAP4
83 * supported CEA and VESA timing values.code_cea corresponds to the CEA
84 * code, It is used to get the timing from cea_vesa_timing array.Similarly
85 * with code_vesa. Code_index is used for back mapping, that is once EDID
86 * is read from the TV, EDID is parsed to find the timing values and then
87 * map it to corresponding CEA or VESA index.
88 */
89
46095b2d 90static const struct hdmi_config cea_timings[] = {
cc937e5e
AT		 91 {
92 { 640, 480, 25200, 96, 16, 48, 2, 10, 33,
93 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
94 false, },
95 { 1, HDMI_HDMI },
96 },
97 {
98 { 720, 480, 27027, 62, 16, 60, 6, 9, 30,
99 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
100 false, },
101 { 2, HDMI_HDMI },
102 },
103 {
104 { 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
105 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
106 false, },
107 { 4, HDMI_HDMI },
108 },
109 {
110 { 1920, 540, 74250, 44, 88, 148, 5, 2, 15,
111 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
112 true, },
113 { 5, HDMI_HDMI },
114 },
115 {
116 { 1440, 240, 27027, 124, 38, 114, 3, 4, 15,
117 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
118 true, },
119 { 6, HDMI_HDMI },
120 },
121 {
122 { 1920, 1080, 148500, 44, 88, 148, 5, 4, 36,
123 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
124 false, },
125 { 16, HDMI_HDMI },
126 },
127 {
128 { 720, 576, 27000, 64, 12, 68, 5, 5, 39,
129 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
130 false, },
131 { 17, HDMI_HDMI },
132 },
133 {
134 { 1280, 720, 74250, 40, 440, 220, 5, 5, 20,
135 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
136 false, },
137 { 19, HDMI_HDMI },
138 },
139 {
140 { 1920, 540, 74250, 44, 528, 148, 5, 2, 15,
141 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
142 true, },
143 { 20, HDMI_HDMI },
144 },
145 {
146 { 1440, 288, 27000, 126, 24, 138, 3, 2, 19,
147 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
148 true, },
149 { 21, HDMI_HDMI },
150 },
151 {
152 { 1440, 576, 54000, 128, 24, 136, 5, 5, 39,
153 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
154 false, },
155 { 29, HDMI_HDMI },
156 },
157 {
158 { 1920, 1080, 148500, 44, 528, 148, 5, 4, 36,
159 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
160 false, },
161 { 31, HDMI_HDMI },
162 },
163 {
164 { 1920, 1080, 74250, 44, 638, 148, 5, 4, 36,
165 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
166 false, },
167 { 32, HDMI_HDMI },
168 },
169 {
170 { 2880, 480, 108108, 248, 64, 240, 6, 9, 30,
171 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
172 false, },
173 { 35, HDMI_HDMI },
174 },
175 {
176 { 2880, 576, 108000, 256, 48, 272, 5, 5, 39,
177 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
178 false, },
179 { 37, HDMI_HDMI },
180 },
46095b2d 181};
cc937e5e 182
46095b2d 183static const struct hdmi_config vesa_timings[] = {
a05ce78f 184/* VESA From Here */
cc937e5e
AT		 185 {
186 { 640, 480, 25175, 96, 16, 48, 2, 11, 31,
187 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
188 false, },
189 { 4, HDMI_DVI },
190 },
191 {
192 { 800, 600, 40000, 128, 40, 88, 4, 1, 23,
193 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
194 false, },
195 { 9, HDMI_DVI },
196 },
197 {
198 { 848, 480, 33750, 112, 16, 112, 8, 6, 23,
199 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
200 false, },
201 { 0xE, HDMI_DVI },
202 },
203 {
204 { 1280, 768, 79500, 128, 64, 192, 7, 3, 20,
205 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
206 false, },
207 { 0x17, HDMI_DVI },
208 },
209 {
210 { 1280, 800, 83500, 128, 72, 200, 6, 3, 22,
211 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
212 false, },
213 { 0x1C, HDMI_DVI },
214 },
215 {
216 { 1360, 768, 85500, 112, 64, 256, 6, 3, 18,
217 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
218 false, },
219 { 0x27, HDMI_DVI },
220 },
221 {
222 { 1280, 960, 108000, 112, 96, 312, 3, 1, 36,
223 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
224 false, },
225 { 0x20, HDMI_DVI },
226 },
227 {
228 { 1280, 1024, 108000, 112, 48, 248, 3, 1, 38,
229 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
230 false, },
231 { 0x23, HDMI_DVI },
232 },
233 {
234 { 1024, 768, 65000, 136, 24, 160, 6, 3, 29,
235 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
236 false, },
237 { 0x10, HDMI_DVI },
238 },
239 {
240 { 1400, 1050, 121750, 144, 88, 232, 4, 3, 32,
241 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
242 false, },
243 { 0x2A, HDMI_DVI },
244 },
245 {
246 { 1440, 900, 106500, 152, 80, 232, 6, 3, 25,
247 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
248 false, },
249 { 0x2F, HDMI_DVI },
250 },
251 {
252 { 1680, 1050, 146250, 176 , 104, 280, 6, 3, 30,
253 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
254 false, },
255 { 0x3A, HDMI_DVI },
256 },
257 {
258 { 1366, 768, 85500, 143, 70, 213, 3, 3, 24,
259 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
260 false, },
261 { 0x51, HDMI_DVI },
262 },
263 {
264 { 1920, 1080, 148500, 44, 148, 80, 5, 4, 36,
265 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
266 false, },
267 { 0x52, HDMI_DVI },
268 },
269 {
270 { 1280, 768, 68250, 32, 48, 80, 7, 3, 12,
271 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
272 false, },
273 { 0x16, HDMI_DVI },
274 },
275 {
276 { 1400, 1050, 101000, 32, 48, 80, 4, 3, 23,
277 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
278 false, },
279 { 0x29, HDMI_DVI },
280 },
281 {
282 { 1680, 1050, 119000, 32, 48, 80, 6, 3, 21,
283 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
284 false, },
285 { 0x39, HDMI_DVI },
286 },
287 {
288 { 1280, 800, 79500, 32, 48, 80, 6, 3, 14,
289 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
290 false, },
291 { 0x1B, HDMI_DVI },
292 },
293 {
294 { 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
295 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
296 false, },
297 { 0x55, HDMI_DVI },
298 },
7a7ce2c7
TV		 299 {
300 { 1920, 1200, 154000, 32, 48, 80, 6, 3, 26,
301 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
302 false, },
303 { 0x44, HDMI_DVI },
304 },
c3198a5e
M		 305};
306
4fbafaf3
TV		 307static int hdmi_runtime_get(void)
308{
309 int r;
310
311 DSSDBG("hdmi_runtime_get\n");
312
313 r = pm_runtime_get_sync(&hdmi.pdev->dev);
314 WARN_ON(r < 0);
a247ce78 315 if (r < 0)
852f0838 316 return r;
a247ce78
AT		 317
318 return 0;
4fbafaf3
TV		 319}
320
321static void hdmi_runtime_put(void)
322{
323 int r;
324
325 DSSDBG("hdmi_runtime_put\n");
326
0eaf9f52 327 r = pm_runtime_put_sync(&hdmi.pdev->dev);
5be3aebd 328 WARN_ON(r < 0 && r != -ENOSYS);
4fbafaf3
TV		 329}
330
9d8232a7 331static int __init hdmi_init_display(struct omap_dss_device *dssdev)
c3198a5e 332{
cca35017
TV		 333 int r;
334
335 struct gpio gpios[] = {
336 { hdmi.ct_cp_hpd_gpio, GPIOF_OUT_INIT_LOW, "hdmi_ct_cp_hpd" },
337 { hdmi.ls_oe_gpio, GPIOF_OUT_INIT_LOW, "hdmi_ls_oe" },
338 { hdmi.hpd_gpio, GPIOF_DIR_IN, "hdmi_hpd" },
339 };
340
c3198a5e
M		 341 DSSDBG("init_display\n");
342
b2c7d54f 343 dss_init_hdmi_ip_ops(&hdmi.ip_data, omapdss_get_version());
cca35017 344
17486943
TV		 345 if (hdmi.vdda_hdmi_dac_reg == NULL) {
346 struct regulator *reg;
347
348 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda_hdmi_dac");
349
76eed4bc
TV		 350 /* DT HACK: try VDAC to make omapdss work for o4 sdp/panda */
351 if (IS_ERR(reg))
352 reg = devm_regulator_get(&hdmi.pdev->dev, "VDAC");
353
17486943
TV		 354 if (IS_ERR(reg)) {
355 DSSERR("can't get VDDA_HDMI_DAC regulator\n");
356 return PTR_ERR(reg);
357 }
358
359 hdmi.vdda_hdmi_dac_reg = reg;
360 }
361
cca35017
TV		 362 r = gpio_request_array(gpios, ARRAY_SIZE(gpios));
363 if (r)
364 return r;
365
c3198a5e
M		 366 return 0;
367}
368
37584765 369static void hdmi_uninit_display(struct omap_dss_device *dssdev)
cca35017
TV		 370{
371 DSSDBG("uninit_display\n");
372
373 gpio_free(hdmi.ct_cp_hpd_gpio);
374 gpio_free(hdmi.ls_oe_gpio);
375 gpio_free(hdmi.hpd_gpio);
376}
377
46095b2d
M		 378static const struct hdmi_config *hdmi_find_timing(
379 const struct hdmi_config *timings_arr,
380 int len)
c3198a5e 381{
46095b2d 382 int i;
c3198a5e 383
46095b2d 384 for (i = 0; i < len; i++) {
9e4ed603 385 if (timings_arr[i].cm.code == hdmi.ip_data.cfg.cm.code)
46095b2d
M		 386 return &timings_arr[i];
387 }
388 return NULL;
389}
c3198a5e 390
46095b2d
M		 391static const struct hdmi_config *hdmi_get_timings(void)
392{
393 const struct hdmi_config *arr;
394 int len;
395
9e4ed603 396 if (hdmi.ip_data.cfg.cm.mode == HDMI_DVI) {
46095b2d
M		 397 arr = vesa_timings;
398 len = ARRAY_SIZE(vesa_timings);
399 } else {
400 arr = cea_timings;
401 len = ARRAY_SIZE(cea_timings);
402 }
403
404 return hdmi_find_timing(arr, len);
405}
406
407static bool hdmi_timings_compare(struct omap_video_timings *timing1,
cc937e5e 408 const struct omap_video_timings *timing2)
46095b2d
M		 409{
410 int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync;
411
f236b892
TV		 412 if ((DIV_ROUND_CLOSEST(timing2->pixel_clock, 1000) ==
413 DIV_ROUND_CLOSEST(timing1->pixel_clock, 1000)) &&
46095b2d
M		 414 (timing2->x_res == timing1->x_res) &&
415 (timing2->y_res == timing1->y_res)) {
c3198a5e 416
46095b2d
M		 417 timing2_hsync = timing2->hfp + timing2->hsw + timing2->hbp;
418 timing1_hsync = timing1->hfp + timing1->hsw + timing1->hbp;
419 timing2_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
420 timing1_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
421
422 DSSDBG("timing1_hsync = %d timing1_vsync = %d"\
423 "timing2_hsync = %d timing2_vsync = %d\n",
424 timing1_hsync, timing1_vsync,
425 timing2_hsync, timing2_vsync);
426
427 if ((timing1_hsync == timing2_hsync) &&
428 (timing1_vsync == timing2_vsync)) {
429 return true;
430 }
c3198a5e 431 }
46095b2d 432 return false;
c3198a5e
M		 433}
434
435static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing)
436{
46095b2d 437 int i;
c3198a5e
M		 438 struct hdmi_cm cm = {-1};
439 DSSDBG("hdmi_get_code\n");
440
46095b2d
M		 441 for (i = 0; i < ARRAY_SIZE(cea_timings); i++) {
442 if (hdmi_timings_compare(timing, &cea_timings[i].timings)) {
443 cm = cea_timings[i].cm;
444 goto end;
445 }
446 }
447 for (i = 0; i < ARRAY_SIZE(vesa_timings); i++) {
448 if (hdmi_timings_compare(timing, &vesa_timings[i].timings)) {
449 cm = vesa_timings[i].cm;
450 goto end;
c3198a5e
M		 451 }
452 }
453
46095b2d 454end: return cm;
c3198a5e 455
c3198a5e
M		 456}
457
c3dc6a7a
AT		 458unsigned long hdmi_get_pixel_clock(void)
459{
460 /* HDMI Pixel Clock in Mhz */
a05ce78f 461 return hdmi.ip_data.cfg.timings.pixel_clock * 1000;
c3dc6a7a
AT		 462}
463
6cb07b25
AT		 464static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
465 struct hdmi_pll_info *pi)
c3198a5e 466{
6cb07b25 467 unsigned long clkin, refclk;
c3198a5e
M		 468 u32 mf;
469
4fbafaf3 470 clkin = clk_get_rate(hdmi.sys_clk) / 10000;
c3198a5e
M		 471 /*
472 * Input clock is predivided by N + 1
473 * out put of which is reference clk
474 */
8d88767a
TV		 475 if (dssdev->clocks.hdmi.regn == 0)
476 pi->regn = HDMI_DEFAULT_REGN;
477 else
478 pi->regn = dssdev->clocks.hdmi.regn;
479
b44e4582 480 refclk = clkin / pi->regn;
c3198a5e 481
8d88767a
TV		 482 if (dssdev->clocks.hdmi.regm2 == 0)
483 pi->regm2 = HDMI_DEFAULT_REGM2;
484 else
485 pi->regm2 = dssdev->clocks.hdmi.regm2;
c3198a5e 486
dd2116a3
M		 487 /*
488 * multiplier is pixel_clk/ref_clk
489 * Multiplying by 100 to avoid fractional part removal
490 */
491 pi->regm = phy * pi->regm2 / refclk;
492
c3198a5e
M		 493 /*
494 * fractional multiplier is remainder of the difference between
495 * multiplier and actual phy(required pixel clock thus should be
496 * multiplied by 2^18(262144) divided by the reference clock
497 */
dd2116a3
M		 498 mf = (phy - pi->regm / pi->regm2 * refclk) * 262144;
499 pi->regmf = pi->regm2 * mf / refclk;
c3198a5e
M		 500
501 /*
502 * Dcofreq should be set to 1 if required pixel clock
503 * is greater than 1000MHz
504 */
505 pi->dcofreq = phy > 1000 * 100;
b44e4582 506 pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10;
c3198a5e 507
7b27da54
M		 508 /* Set the reference clock to sysclk reference */
509 pi->refsel = HDMI_REFSEL_SYSCLK;
510
c3198a5e
M		 511 DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
512 DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
513}
514
bb426fc9 515static int hdmi_power_on_core(struct omap_dss_device *dssdev)
c3198a5e 516{
46095b2d 517 int r;
c3198a5e 518
cca35017
TV		 519 gpio_set_value(hdmi.ct_cp_hpd_gpio, 1);
520 gpio_set_value(hdmi.ls_oe_gpio, 1);
521
a84b2065
TV		 522 /* wait 300us after CT_CP_HPD for the 5V power output to reach 90% */
523 udelay(300);
524
17486943
TV		 525 r = regulator_enable(hdmi.vdda_hdmi_dac_reg);
526 if (r)
527 goto err_vdac_enable;
528
4fbafaf3
TV		 529 r = hdmi_runtime_get();
530 if (r)
cca35017 531 goto err_runtime_get;
c3198a5e 532
bb426fc9
TV		 533 /* Make selection of HDMI in DSS */
534 dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
535
bb426fc9
TV		 536 return 0;
537
538err_runtime_get:
539 regulator_disable(hdmi.vdda_hdmi_dac_reg);
540err_vdac_enable:
541 gpio_set_value(hdmi.ct_cp_hpd_gpio, 0);
542 gpio_set_value(hdmi.ls_oe_gpio, 0);
543 return r;
544}
545
546static void hdmi_power_off_core(struct omap_dss_device *dssdev)
547{
548 hdmi_runtime_put();
549 regulator_disable(hdmi.vdda_hdmi_dac_reg);
550 gpio_set_value(hdmi.ct_cp_hpd_gpio, 0);
551 gpio_set_value(hdmi.ls_oe_gpio, 0);
552}
553
554static int hdmi_power_on_full(struct omap_dss_device *dssdev)
555{
556 int r;
557 struct omap_video_timings *p;
558 struct omap_overlay_manager *mgr = dssdev->output->manager;
559 unsigned long phy;
560
561 r = hdmi_power_on_core(dssdev);
562 if (r)
563 return r;
564
cea87b92 565 dss_mgr_disable(mgr);
c3198a5e 566
7849398f 567 p = &hdmi.ip_data.cfg.timings;
c3198a5e 568
7849398f 569 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
c3198a5e 570
c3198a5e
M		 571 phy = p->pixel_clock;
572
7b27da54 573 hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data);
c3198a5e 574
c0456be3 575 hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
c3198a5e 576
95a8aeb6 577 /* config the PLL and PHY hdmi_set_pll_pwrfirst */
60634a28 578 r = hdmi.ip_data.ops->pll_enable(&hdmi.ip_data);
c3198a5e
M		 579 if (r) {
580 DSSDBG("Failed to lock PLL\n");
cca35017 581 goto err_pll_enable;
c3198a5e
M		 582 }
583
60634a28 584 r = hdmi.ip_data.ops->phy_enable(&hdmi.ip_data);
c3198a5e
M		 585 if (r) {
586 DSSDBG("Failed to start PHY\n");
d3b4aa51 587 goto err_phy_enable;
c3198a5e
M		 588 }
589
60634a28 590 hdmi.ip_data.ops->video_configure(&hdmi.ip_data);
c3198a5e 591
c3198a5e
M		 592 /* bypass TV gamma table */
593 dispc_enable_gamma_table(0);
594
595 /* tv size */
cea87b92 596 dss_mgr_set_timings(mgr, p);
c3198a5e 597
c0456be3
RN		 598 r = hdmi.ip_data.ops->video_enable(&hdmi.ip_data);
599 if (r)
600 goto err_vid_enable;
c3198a5e 601
cea87b92 602 r = dss_mgr_enable(mgr);
33ca237f
TV		 603 if (r)
604 goto err_mgr_enable;
3870c909 605
c3198a5e 606 return 0;
33ca237f
TV		 607
608err_mgr_enable:
c0456be3
RN		 609 hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
610err_vid_enable:
33ca237f 611 hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
d3b4aa51 612err_phy_enable:
33ca237f 613 hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
cca35017 614err_pll_enable:
bb426fc9 615 hdmi_power_off_core(dssdev);
c3198a5e
M		 616 return -EIO;
617}
618
bb426fc9 619static void hdmi_power_off_full(struct omap_dss_device *dssdev)
c3198a5e 620{
cea87b92
AT		 621 struct omap_overlay_manager *mgr = dssdev->output->manager;
622
623 dss_mgr_disable(mgr);
c3198a5e 624
c0456be3 625 hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
60634a28
M		 626 hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
627 hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
17486943 628
bb426fc9 629 hdmi_power_off_core(dssdev);
c3198a5e
M		 630}
631
632int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
633 struct omap_video_timings *timings)
634{
635 struct hdmi_cm cm;
636
637 cm = hdmi_get_code(timings);
638 if (cm.code == -1) {
c3198a5e
M		 639 return -EINVAL;
640 }
641
642 return 0;
643
644}
645
7849398f
AT		 646void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev,
647 struct omap_video_timings *timings)
c3198a5e
M		 648{
649 struct hdmi_cm cm;
7849398f 650 const struct hdmi_config *t;
c3198a5e 651
ed1aa900
AT		 652 mutex_lock(&hdmi.lock);
653
7849398f
AT		 654 cm = hdmi_get_code(timings);
655 hdmi.ip_data.cfg.cm = cm;
656
657 t = hdmi_get_timings();
658 if (t != NULL)
659 hdmi.ip_data.cfg = *t;
fa70dc5f 660
ed1aa900 661 mutex_unlock(&hdmi.lock);
c3198a5e
M		 662}
663
e40402cf 664static void hdmi_dump_regs(struct seq_file *s)
162874d5
M		 665{
666 mutex_lock(&hdmi.lock);
667
f8fb7d7b
WY		 668 if (hdmi_runtime_get()) {
669 mutex_unlock(&hdmi.lock);
162874d5 670 return;
f8fb7d7b 671 }
162874d5
M		 672
673 hdmi.ip_data.ops->dump_wrapper(&hdmi.ip_data, s);
674 hdmi.ip_data.ops->dump_pll(&hdmi.ip_data, s);
675 hdmi.ip_data.ops->dump_phy(&hdmi.ip_data, s);
676 hdmi.ip_data.ops->dump_core(&hdmi.ip_data, s);
677
678 hdmi_runtime_put();
679 mutex_unlock(&hdmi.lock);
680}
681
47024565
TV		 682int omapdss_hdmi_read_edid(u8 *buf, int len)
683{
684 int r;
685
686 mutex_lock(&hdmi.lock);
687
688 r = hdmi_runtime_get();
689 BUG_ON(r);
690
691 r = hdmi.ip_data.ops->read_edid(&hdmi.ip_data, buf, len);
692
693 hdmi_runtime_put();
694 mutex_unlock(&hdmi.lock);
695
696 return r;
697}
698
759593ff
TV		 699bool omapdss_hdmi_detect(void)
700{
701 int r;
702
703 mutex_lock(&hdmi.lock);
704
705 r = hdmi_runtime_get();
706 BUG_ON(r);
707
708 r = hdmi.ip_data.ops->detect(&hdmi.ip_data);
709
710 hdmi_runtime_put();
711 mutex_unlock(&hdmi.lock);
712
713 return r == 1;
714}
715
c3198a5e
M		 716int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev)
717{
cea87b92 718 struct omap_dss_output *out = dssdev->output;
c3198a5e
M		 719 int r = 0;
720
721 DSSDBG("ENTER hdmi_display_enable\n");
722
723 mutex_lock(&hdmi.lock);
724
cea87b92
AT		 725 if (out == NULL || out->manager == NULL) {
726 DSSERR("failed to enable display: no output/manager\n");
05e1d606
TV		 727 r = -ENODEV;
728 goto err0;
729 }
730
cca35017 731 hdmi.ip_data.hpd_gpio = hdmi.hpd_gpio;
c49d005b 732
c3198a5e
M		 733 r = omap_dss_start_device(dssdev);
734 if (r) {
735 DSSERR("failed to start device\n");
736 goto err0;
737 }
738
bb426fc9 739 r = hdmi_power_on_full(dssdev);
c3198a5e
M		 740 if (r) {
741 DSSERR("failed to power on device\n");
cca35017 742 goto err1;
c3198a5e
M		 743 }
744
745 mutex_unlock(&hdmi.lock);
746 return 0;
747
c3198a5e
M		 748err1:
749 omap_dss_stop_device(dssdev);
750err0:
751 mutex_unlock(&hdmi.lock);
752 return r;
753}
754
755void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev)
756{
757 DSSDBG("Enter hdmi_display_disable\n");
758
759 mutex_lock(&hdmi.lock);
760
bb426fc9 761 hdmi_power_off_full(dssdev);
c3198a5e 762
c3198a5e
M		 763 omap_dss_stop_device(dssdev);
764
765 mutex_unlock(&hdmi.lock);
766}
767
4489823c
TV		 768int omapdss_hdmi_core_enable(struct omap_dss_device *dssdev)
769{
770 int r = 0;
771
772 DSSDBG("ENTER omapdss_hdmi_core_enable\n");
773
774 mutex_lock(&hdmi.lock);
775
776 hdmi.ip_data.hpd_gpio = hdmi.hpd_gpio;
777
778 r = hdmi_power_on_core(dssdev);
779 if (r) {
780 DSSERR("failed to power on device\n");
781 goto err0;
782 }
783
784 mutex_unlock(&hdmi.lock);
785 return 0;
786
787err0:
788 mutex_unlock(&hdmi.lock);
789 return r;
790}
791
792void omapdss_hdmi_core_disable(struct omap_dss_device *dssdev)
793{
794 DSSDBG("Enter omapdss_hdmi_core_disable\n");
795
796 mutex_lock(&hdmi.lock);
797
798 hdmi_power_off_core(dssdev);
799
800 mutex_unlock(&hdmi.lock);
801}
802
4fbafaf3
TV		 803static int hdmi_get_clocks(struct platform_device *pdev)
804{
805 struct clk *clk;
806
807 clk = clk_get(&pdev->dev, "sys_clk");
808 if (IS_ERR(clk)) {
809 DSSERR("can't get sys_clk\n");
810 return PTR_ERR(clk);
811 }
812
813 hdmi.sys_clk = clk;
814
4fbafaf3
TV		 815 return 0;
816}
817
818static void hdmi_put_clocks(void)
819{
820 if (hdmi.sys_clk)
821 clk_put(hdmi.sys_clk);
4fbafaf3
TV		 822}
823
35547626
RN		 824#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
825int hdmi_compute_acr(u32 sample_freq, u32 *n, u32 *cts)
826{
827 u32 deep_color;
25a65359 828 bool deep_color_correct = false;
35547626
RN		 829 u32 pclk = hdmi.ip_data.cfg.timings.pixel_clock;
830
831 if (n == NULL || cts == NULL)
832 return -EINVAL;
833
834 /* TODO: When implemented, query deep color mode here. */
835 deep_color = 100;
836
25a65359
RN		 837 /*
838 * When using deep color, the default N value (as in the HDMI
839 * specification) yields to an non-integer CTS. Hence, we
840 * modify it while keeping the restrictions described in
841 * section 7.2.1 of the HDMI 1.4a specification.
842 */
35547626
RN		 843 switch (sample_freq) {
844 case 32000:
25a65359
RN		 845 case 48000:
846 case 96000:
847 case 192000:
848 if (deep_color == 125)
849 if (pclk == 27027 || pclk == 74250)
850 deep_color_correct = true;
851 if (deep_color == 150)
852 if (pclk == 27027)
853 deep_color_correct = true;
35547626
RN		 854 break;
855 case 44100:
25a65359
RN		 856 case 88200:
857 case 176400:
858 if (deep_color == 125)
859 if (pclk == 27027)
860 deep_color_correct = true;
35547626
RN		 861 break;
862 default:
35547626
RN		 863 return -EINVAL;
864 }
865
25a65359
RN		 866 if (deep_color_correct) {
867 switch (sample_freq) {
868 case 32000:
869 *n = 8192;
870 break;
871 case 44100:
872 *n = 12544;
873 break;
874 case 48000:
875 *n = 8192;
876 break;
877 case 88200:
878 *n = 25088;
879 break;
880 case 96000:
881 *n = 16384;
882 break;
883 case 176400:
884 *n = 50176;
885 break;
886 case 192000:
887 *n = 32768;
888 break;
889 default:
890 return -EINVAL;
891 }
892 } else {
893 switch (sample_freq) {
894 case 32000:
895 *n = 4096;
896 break;
897 case 44100:
898 *n = 6272;
899 break;
900 case 48000:
901 *n = 6144;
902 break;
903 case 88200:
904 *n = 12544;
905 break;
906 case 96000:
907 *n = 12288;
908 break;
909 case 176400:
910 *n = 25088;
911 break;
912 case 192000:
913 *n = 24576;
914 break;
915 default:
916 return -EINVAL;
917 }
918 }
35547626
RN		 919 /* Calculate CTS. See HDMI 1.3a or 1.4a specifications */
920 *cts = pclk * (*n / 128) * deep_color / (sample_freq / 10);
921
922 return 0;
923}
f3a97491
RN		 924
925int hdmi_audio_enable(void)
926{
927 DSSDBG("audio_enable\n");
928
929 return hdmi.ip_data.ops->audio_enable(&hdmi.ip_data);
930}
931
932void hdmi_audio_disable(void)
933{
934 DSSDBG("audio_disable\n");
935
936 hdmi.ip_data.ops->audio_disable(&hdmi.ip_data);
937}
938
939int hdmi_audio_start(void)
940{
941 DSSDBG("audio_start\n");
942
943 return hdmi.ip_data.ops->audio_start(&hdmi.ip_data);
944}
945
946void hdmi_audio_stop(void)
947{
948 DSSDBG("audio_stop\n");
949
950 hdmi.ip_data.ops->audio_stop(&hdmi.ip_data);
951}
952
953bool hdmi_mode_has_audio(void)
954{
955 if (hdmi.ip_data.cfg.cm.mode == HDMI_HDMI)
956 return true;
957 else
958 return false;
959}
960
961int hdmi_audio_config(struct omap_dss_audio *audio)
962{
963 return hdmi.ip_data.ops->audio_config(&hdmi.ip_data, audio);
964}
965
35547626
RN		 966#endif
967
1521653c 968static struct omap_dss_device * __init hdmi_find_dssdev(struct platform_device *pdev)
38f3daf6
TV		 969{
970 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
2bbcce5e 971 const char *def_disp_name = omapdss_get_default_display_name();
1521653c
TV		 972 struct omap_dss_device *def_dssdev;
973 int i;
974
975 def_dssdev = NULL;
38f3daf6
TV		 976
977 for (i = 0; i < pdata->num_devices; ++i) {
978 struct omap_dss_device *dssdev = pdata->devices[i];
979
980 if (dssdev->type != OMAP_DISPLAY_TYPE_HDMI)
981 continue;
982
1521653c
TV		 983 if (def_dssdev == NULL)
984 def_dssdev = dssdev;
cca35017 985
1521653c
TV		 986 if (def_disp_name != NULL &&
987 strcmp(dssdev->name, def_disp_name) == 0) {
988 def_dssdev = dssdev;
989 break;
38f3daf6 990 }
1521653c
TV		 991 }
992
993 return def_dssdev;
994}
995
996static void __init hdmi_probe_pdata(struct platform_device *pdev)
997{
5274484b 998 struct omap_dss_device *plat_dssdev;
1521653c
TV		 999 struct omap_dss_device *dssdev;
1000 struct omap_dss_hdmi_data *priv;
1001 int r;
38f3daf6 1002
5274484b 1003 plat_dssdev = hdmi_find_dssdev(pdev);
1521653c 1004
5274484b
TV		 1005 if (!plat_dssdev)
1006 return;
1007
1008 dssdev = dss_alloc_and_init_device(&pdev->dev);
1521653c
TV		 1009 if (!dssdev)
1010 return;
1011
5274484b
TV		 1012 dss_copy_device_pdata(dssdev, plat_dssdev);
1013
1521653c
TV		 1014 priv = dssdev->data;
1015
1016 hdmi.ct_cp_hpd_gpio = priv->ct_cp_hpd_gpio;
1017 hdmi.ls_oe_gpio = priv->ls_oe_gpio;
1018 hdmi.hpd_gpio = priv->hpd_gpio;
1019
bcb226a9
TV		 1020 dssdev->channel = OMAP_DSS_CHANNEL_DIGIT;
1021
1521653c
TV		 1022 r = hdmi_init_display(dssdev);
1023 if (r) {
1024 DSSERR("device %s init failed: %d\n", dssdev->name, r);
5274484b 1025 dss_put_device(dssdev);
1521653c
TV		 1026 return;
1027 }
1028
486c0e17
TV		 1029 r = omapdss_output_set_device(&hdmi.output, dssdev);
1030 if (r) {
1031 DSSERR("failed to connect output to new device: %s\n",
1032 dssdev->name);
1033 dss_put_device(dssdev);
1034 return;
1035 }
1036
5274484b 1037 r = dss_add_device(dssdev);
1521653c
TV		 1038 if (r) {
1039 DSSERR("device %s register failed: %d\n", dssdev->name, r);
486c0e17 1040 omapdss_output_unset_device(&hdmi.output);
d18bc455 1041 hdmi_uninit_display(dssdev);
5274484b 1042 dss_put_device(dssdev);
1521653c 1043 return;
38f3daf6
TV		 1044 }
1045}
1046
81b87f51
AT		 1047static void __init hdmi_init_output(struct platform_device *pdev)
1048{
1049 struct omap_dss_output *out = &hdmi.output;
1050
1051 out->pdev = pdev;
1052 out->id = OMAP_DSS_OUTPUT_HDMI;
1053 out->type = OMAP_DISPLAY_TYPE_HDMI;
1054
1055 dss_register_output(out);
1056}
1057
1058static void __exit hdmi_uninit_output(struct platform_device *pdev)
1059{
1060 struct omap_dss_output *out = &hdmi.output;
1061
1062 dss_unregister_output(out);
1063}
1064
c3198a5e 1065/* HDMI HW IP initialisation */
6e7e8f06 1066static int __init omapdss_hdmihw_probe(struct platform_device *pdev)
c3198a5e 1067{
af23cb35 1068 struct resource *res;
38f3daf6 1069 int r;
c3198a5e 1070
c3198a5e
M		 1071 hdmi.pdev = pdev;
1072
1073 mutex_init(&hdmi.lock);
66a06b0c 1074 mutex_init(&hdmi.ip_data.lock);
c3198a5e 1075
af23cb35
RN		 1076 res = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0);
1077 if (!res) {
c3198a5e
M		 1078 DSSERR("can't get IORESOURCE_MEM HDMI\n");
1079 return -EINVAL;
1080 }
1081
1082 /* Base address taken from platform */
bc3bad16
TR		 1083 hdmi.ip_data.base_wp = devm_ioremap_resource(&pdev->dev, res);
1084 if (IS_ERR(hdmi.ip_data.base_wp))
1085 return PTR_ERR(hdmi.ip_data.base_wp);
c3198a5e 1086
4fbafaf3
TV		 1087 r = hdmi_get_clocks(pdev);
1088 if (r) {
47e443bc 1089 DSSERR("can't get clocks\n");
4fbafaf3
TV		 1090 return r;
1091 }
1092
1093 pm_runtime_enable(&pdev->dev);
1094
95a8aeb6
M		 1095 hdmi.ip_data.core_sys_offset = HDMI_CORE_SYS;
1096 hdmi.ip_data.core_av_offset = HDMI_CORE_AV;
1097 hdmi.ip_data.pll_offset = HDMI_PLLCTRL;
1098 hdmi.ip_data.phy_offset = HDMI_PHY;
7849398f 1099
66a06b0c
RN		 1100 r = hdmi_panel_init();
1101 if (r) {
1102 DSSERR("can't init panel\n");
1103 goto err_panel_init;
1104 }
c3198a5e 1105
e40402cf
TV		 1106 dss_debugfs_create_file("hdmi", hdmi_dump_regs);
1107
81b87f51
AT		 1108 hdmi_init_output(pdev);
1109
38f3daf6 1110 hdmi_probe_pdata(pdev);
35deca3d 1111
c3198a5e 1112 return 0;
66a06b0c
RN		 1113
1114err_panel_init:
1115 hdmi_put_clocks();
1116 return r;
c3198a5e
M		 1117}
1118
cca35017
TV		 1119static int __exit hdmi_remove_child(struct device *dev, void *data)
1120{
1121 struct omap_dss_device *dssdev = to_dss_device(dev);
1122 hdmi_uninit_display(dssdev);
1123 return 0;
1124}
1125
6e7e8f06 1126static int __exit omapdss_hdmihw_remove(struct platform_device *pdev)
c3198a5e 1127{
cca35017
TV		 1128 device_for_each_child(&pdev->dev, NULL, hdmi_remove_child);
1129
5274484b 1130 dss_unregister_child_devices(&pdev->dev);
35deca3d 1131
c3198a5e
M		 1132 hdmi_panel_exit();
1133
81b87f51
AT		 1134 hdmi_uninit_output(pdev);
1135
4fbafaf3
TV		 1136 pm_runtime_disable(&pdev->dev);
1137
1138 hdmi_put_clocks();
1139
c3198a5e
M		 1140 return 0;
1141}
1142
4fbafaf3
TV		 1143static int hdmi_runtime_suspend(struct device *dev)
1144{
f11766d1 1145 clk_disable_unprepare(hdmi.sys_clk);
4fbafaf3
TV		 1146
1147 dispc_runtime_put();
4fbafaf3
TV		 1148
1149 return 0;
1150}
1151
1152static int hdmi_runtime_resume(struct device *dev)
1153{
1154 int r;
1155
4fbafaf3
TV		 1156 r = dispc_runtime_get();
1157 if (r < 0)
852f0838 1158 return r;
4fbafaf3 1159
f11766d1 1160 clk_prepare_enable(hdmi.sys_clk);
4fbafaf3
TV		 1161
1162 return 0;
4fbafaf3
TV		 1163}
1164
1165static const struct dev_pm_ops hdmi_pm_ops = {
1166 .runtime_suspend = hdmi_runtime_suspend,
1167 .runtime_resume = hdmi_runtime_resume,
1168};
1169
c3198a5e 1170static struct platform_driver omapdss_hdmihw_driver = {
6e7e8f06 1171 .remove = __exit_p(omapdss_hdmihw_remove),
c3198a5e
M		 1172 .driver = {
1173 .name = "omapdss_hdmi",
1174 .owner = THIS_MODULE,
4fbafaf3 1175 .pm = &hdmi_pm_ops,
c3198a5e
M		 1176 },
1177};
1178
6e7e8f06 1179int __init hdmi_init_platform_driver(void)
c3198a5e 1180{
61055d4b 1181 return platform_driver_probe(&omapdss_hdmihw_driver, omapdss_hdmihw_probe);
c3198a5e
M		 1182}
1183
6e7e8f06 1184void __exit hdmi_uninit_platform_driver(void)
c3198a5e 1185{
04c742c3 1186 platform_driver_unregister(&omapdss_hdmihw_driver);
c3198a5e 1187}
Linux kernel - Deliverables
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