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OMAPDSS: HDMI: change the timing match logic
[deliverable/linux.git] / drivers / video / omap2 / dss / hdmi.c
CommitLineData
c3198a5e
M		 1/*
2 * hdmi.c
3 *
4 * HDMI interface DSS driver setting for TI's OMAP4 family of processor.
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
6 * Authors: Yong Zhi
7 * Mythri pk <mythripk@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#define DSS_SUBSYS_NAME "HDMI"
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/err.h>
27#include <linux/io.h>
28#include <linux/interrupt.h>
29#include <linux/mutex.h>
30#include <linux/delay.h>
31#include <linux/string.h>
24e6289c 32#include <linux/platform_device.h>
4fbafaf3
TV		 33#include <linux/pm_runtime.h>
34#include <linux/clk.h>
a0b38cc4 35#include <video/omapdss.h>
ad44cc32
RN		 36#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
37 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
38#include <sound/soc.h>
39#include <sound/pcm_params.h>
7334167b 40#include "ti_hdmi_4xxx_ip.h"
ad44cc32 41#endif
c3198a5e 42
94c52987 43#include "ti_hdmi.h"
c3198a5e 44#include "dss.h"
ad44cc32 45#include "dss_features.h"
c3198a5e 46
95a8aeb6
M		 47#define HDMI_WP 0x0
48#define HDMI_CORE_SYS 0x400
49#define HDMI_CORE_AV 0x900
50#define HDMI_PLLCTRL 0x200
51#define HDMI_PHY 0x300
52
7c1f1eca
M		 53/* HDMI EDID Length move this */
54#define HDMI_EDID_MAX_LENGTH 256
55#define EDID_TIMING_DESCRIPTOR_SIZE 0x12
56#define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36
57#define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80
58#define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4
59#define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4
60
b44e4582 61#define HDMI_DEFAULT_REGN 16
8d88767a
TV		 62#define HDMI_DEFAULT_REGM2 1
63
c3198a5e
M		 64static struct {
65 struct mutex lock;
66 struct omap_display_platform_data *pdata;
67 struct platform_device *pdev;
95a8aeb6 68 struct hdmi_ip_data ip_data;
c3198a5e
M		 69 int code;
70 int mode;
4fbafaf3
TV		 71
72 struct clk *sys_clk;
c3198a5e
M		 73} hdmi;
74
75/*
76 * Logic for the below structure :
77 * user enters the CEA or VESA timings by specifying the HDMI/DVI code.
78 * There is a correspondence between CEA/VESA timing and code, please
79 * refer to section 6.3 in HDMI 1.3 specification for timing code.
80 *
81 * In the below structure, cea_vesa_timings corresponds to all OMAP4
82 * supported CEA and VESA timing values.code_cea corresponds to the CEA
83 * code, It is used to get the timing from cea_vesa_timing array.Similarly
84 * with code_vesa. Code_index is used for back mapping, that is once EDID
85 * is read from the TV, EDID is parsed to find the timing values and then
86 * map it to corresponding CEA or VESA index.
87 */
88
46095b2d 89static const struct hdmi_config cea_timings[] = {
a05ce78f
M		 90{ {640, 480, 25200, 96, 16, 48, 2, 10, 33, 0, 0, 0}, {1, HDMI_HDMI} },
91{ {720, 480, 27027, 62, 16, 60, 6, 9, 30, 0, 0, 0}, {2, HDMI_HDMI} },
92{ {1280, 720, 74250, 40, 110, 220, 5, 5, 20, 1, 1, 0}, {4, HDMI_HDMI} },
93{ {1920, 540, 74250, 44, 88, 148, 5, 2, 15, 1, 1, 1}, {5, HDMI_HDMI} },
94{ {1440, 240, 27027, 124, 38, 114, 3, 4, 15, 0, 0, 1}, {6, HDMI_HDMI} },
95{ {1920, 1080, 148500, 44, 88, 148, 5, 4, 36, 1, 1, 0}, {16, HDMI_HDMI} },
96{ {720, 576, 27000, 64, 12, 68, 5, 5, 39, 0, 0, 0}, {17, HDMI_HDMI} },
97{ {1280, 720, 74250, 40, 440, 220, 5, 5, 20, 1, 1, 0}, {19, HDMI_HDMI} },
98{ {1920, 540, 74250, 44, 528, 148, 5, 2, 15, 1, 1, 1}, {20, HDMI_HDMI} },
99{ {1440, 288, 27000, 126, 24, 138, 3, 2, 19, 0, 0, 1}, {21, HDMI_HDMI} },
100{ {1440, 576, 54000, 128, 24, 136, 5, 5, 39, 0, 0, 0}, {29, HDMI_HDMI} },
101{ {1920, 1080, 148500, 44, 528, 148, 5, 4, 36, 1, 1, 0}, {31, HDMI_HDMI} },
102{ {1920, 1080, 74250, 44, 638, 148, 5, 4, 36, 1, 1, 0}, {32, HDMI_HDMI} },
103{ {2880, 480, 108108, 248, 64, 240, 6, 9, 30, 0, 0, 0}, {35, HDMI_HDMI} },
104{ {2880, 576, 108000, 256, 48, 272, 5, 5, 39, 0, 0, 0}, {37, HDMI_HDMI} },
46095b2d
M		 105};
106static const struct hdmi_config vesa_timings[] = {
a05ce78f
M		 107/* VESA From Here */
108{ {640, 480, 25175, 96, 16, 48, 2 , 11, 31, 0, 0, 0}, {4, HDMI_DVI} },
109{ {800, 600, 40000, 128, 40, 88, 4 , 1, 23, 1, 1, 0}, {9, HDMI_DVI} },
110{ {848, 480, 33750, 112, 16, 112, 8 , 6, 23, 1, 1, 0}, {0xE, HDMI_DVI} },
111{ {1280, 768, 79500, 128, 64, 192, 7 , 3, 20, 1, 0, 0}, {0x17, HDMI_DVI} },
112{ {1280, 800, 83500, 128, 72, 200, 6 , 3, 22, 1, 0, 0}, {0x1C, HDMI_DVI} },
113{ {1360, 768, 85500, 112, 64, 256, 6 , 3, 18, 1, 1, 0}, {0x27, HDMI_DVI} },
114{ {1280, 960, 108000, 112, 96, 312, 3 , 1, 36, 1, 1, 0}, {0x20, HDMI_DVI} },
115{ {1280, 1024, 108000, 112, 48, 248, 3 , 1, 38, 1, 1, 0}, {0x23, HDMI_DVI} },
116{ {1024, 768, 65000, 136, 24, 160, 6, 3, 29, 0, 0, 0}, {0x10, HDMI_DVI} },
117{ {1400, 1050, 121750, 144, 88, 232, 4, 3, 32, 1, 0, 0}, {0x2A, HDMI_DVI} },
118{ {1440, 900, 106500, 152, 80, 232, 6, 3, 25, 1, 0, 0}, {0x2F, HDMI_DVI} },
119{ {1680, 1050, 146250, 176 , 104, 280, 6, 3, 30, 1, 0, 0}, {0x3A, HDMI_DVI} },
120{ {1366, 768, 85500, 143, 70, 213, 3, 3, 24, 1, 1, 0}, {0x51, HDMI_DVI} },
121{ {1920, 1080, 148500, 44, 148, 80, 5, 4, 36, 1, 1, 0}, {0x52, HDMI_DVI} },
122{ {1280, 768, 68250, 32, 48, 80, 7, 3, 12, 0, 1, 0}, {0x16, HDMI_DVI} },
123{ {1400, 1050, 101000, 32, 48, 80, 4, 3, 23, 0, 1, 0}, {0x29, HDMI_DVI} },
124{ {1680, 1050, 119000, 32, 48, 80, 6, 3, 21, 0, 1, 0}, {0x39, HDMI_DVI} },
125{ {1280, 800, 79500, 32, 48, 80, 6, 3, 14, 0, 1, 0}, {0x1B, HDMI_DVI} },
126{ {1280, 720, 74250, 40, 110, 220, 5, 5, 20, 1, 1, 0}, {0x55, HDMI_DVI} }
c3198a5e
M		 127};
128
4fbafaf3
TV		 129static int hdmi_runtime_get(void)
130{
131 int r;
132
133 DSSDBG("hdmi_runtime_get\n");
134
135 r = pm_runtime_get_sync(&hdmi.pdev->dev);
136 WARN_ON(r < 0);
137 return r < 0 ? r : 0;
138}
139
140static void hdmi_runtime_put(void)
141{
142 int r;
143
144 DSSDBG("hdmi_runtime_put\n");
145
146 r = pm_runtime_put(&hdmi.pdev->dev);
147 WARN_ON(r < 0);
148}
149
c3198a5e
M		 150int hdmi_init_display(struct omap_dss_device *dssdev)
151{
152 DSSDBG("init_display\n");
153
60634a28 154 dss_init_hdmi_ip_ops(&hdmi.ip_data);
c3198a5e
M		 155 return 0;
156}
157
46095b2d
M		 158static const struct hdmi_config *hdmi_find_timing(
159 const struct hdmi_config *timings_arr,
160 int len)
c3198a5e 161{
46095b2d 162 int i;
c3198a5e 163
46095b2d
M		 164 for (i = 0; i < len; i++) {
165 if (timings_arr[i].cm.code == hdmi.code)
166 return &timings_arr[i];
167 }
168 return NULL;
169}
c3198a5e 170
46095b2d
M		 171static const struct hdmi_config *hdmi_get_timings(void)
172{
173 const struct hdmi_config *arr;
174 int len;
175
176 if (hdmi.mode == HDMI_DVI) {
177 arr = vesa_timings;
178 len = ARRAY_SIZE(vesa_timings);
179 } else {
180 arr = cea_timings;
181 len = ARRAY_SIZE(cea_timings);
182 }
183
184 return hdmi_find_timing(arr, len);
185}
186
187static bool hdmi_timings_compare(struct omap_video_timings *timing1,
188 const struct hdmi_video_timings *timing2)
189{
190 int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync;
191
192 if ((timing2->pixel_clock == timing1->pixel_clock) &&
193 (timing2->x_res == timing1->x_res) &&
194 (timing2->y_res == timing1->y_res)) {
c3198a5e 195
46095b2d
M		 196 timing2_hsync = timing2->hfp + timing2->hsw + timing2->hbp;
197 timing1_hsync = timing1->hfp + timing1->hsw + timing1->hbp;
198 timing2_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
199 timing1_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
200
201 DSSDBG("timing1_hsync = %d timing1_vsync = %d"\
202 "timing2_hsync = %d timing2_vsync = %d\n",
203 timing1_hsync, timing1_vsync,
204 timing2_hsync, timing2_vsync);
205
206 if ((timing1_hsync == timing2_hsync) &&
207 (timing1_vsync == timing2_vsync)) {
208 return true;
209 }
c3198a5e 210 }
46095b2d 211 return false;
c3198a5e
M		 212}
213
214static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing)
215{
46095b2d 216 int i;
c3198a5e
M		 217 struct hdmi_cm cm = {-1};
218 DSSDBG("hdmi_get_code\n");
219
46095b2d
M		 220 for (i = 0; i < ARRAY_SIZE(cea_timings); i++) {
221 if (hdmi_timings_compare(timing, &cea_timings[i].timings)) {
222 cm = cea_timings[i].cm;
223 goto end;
224 }
225 }
226 for (i = 0; i < ARRAY_SIZE(vesa_timings); i++) {
227 if (hdmi_timings_compare(timing, &vesa_timings[i].timings)) {
228 cm = vesa_timings[i].cm;
229 goto end;
c3198a5e
M		 230 }
231 }
232
46095b2d 233end: return cm;
c3198a5e 234
c3198a5e
M		 235}
236
c3dc6a7a
AT		 237unsigned long hdmi_get_pixel_clock(void)
238{
239 /* HDMI Pixel Clock in Mhz */
a05ce78f 240 return hdmi.ip_data.cfg.timings.pixel_clock * 1000;
c3dc6a7a
AT		 241}
242
6cb07b25
AT		 243static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
244 struct hdmi_pll_info *pi)
c3198a5e 245{
6cb07b25 246 unsigned long clkin, refclk;
c3198a5e
M		 247 u32 mf;
248
4fbafaf3 249 clkin = clk_get_rate(hdmi.sys_clk) / 10000;
c3198a5e
M		 250 /*
251 * Input clock is predivided by N + 1
252 * out put of which is reference clk
253 */
8d88767a
TV		 254 if (dssdev->clocks.hdmi.regn == 0)
255 pi->regn = HDMI_DEFAULT_REGN;
256 else
257 pi->regn = dssdev->clocks.hdmi.regn;
258
b44e4582 259 refclk = clkin / pi->regn;
c3198a5e
M		 260
261 /*
262 * multiplier is pixel_clk/ref_clk
263 * Multiplying by 100 to avoid fractional part removal
264 */
6cb07b25 265 pi->regm = (phy * 100 / (refclk)) / 100;
8d88767a
TV		 266
267 if (dssdev->clocks.hdmi.regm2 == 0)
268 pi->regm2 = HDMI_DEFAULT_REGM2;
269 else
270 pi->regm2 = dssdev->clocks.hdmi.regm2;
c3198a5e
M		 271
272 /*
273 * fractional multiplier is remainder of the difference between
274 * multiplier and actual phy(required pixel clock thus should be
275 * multiplied by 2^18(262144) divided by the reference clock
276 */
277 mf = (phy - pi->regm * refclk) * 262144;
6cb07b25 278 pi->regmf = mf / (refclk);
c3198a5e
M		 279
280 /*
281 * Dcofreq should be set to 1 if required pixel clock
282 * is greater than 1000MHz
283 */
284 pi->dcofreq = phy > 1000 * 100;
b44e4582 285 pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10;
c3198a5e 286
7b27da54
M		 287 /* Set the reference clock to sysclk reference */
288 pi->refsel = HDMI_REFSEL_SYSCLK;
289
c3198a5e
M		 290 DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
291 DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
292}
293
c3198a5e
M		 294static int hdmi_power_on(struct omap_dss_device *dssdev)
295{
46095b2d
M		 296 int r;
297 const struct hdmi_config *timing;
c3198a5e 298 struct omap_video_timings *p;
6cb07b25 299 unsigned long phy;
c3198a5e 300
4fbafaf3
TV		 301 r = hdmi_runtime_get();
302 if (r)
303 return r;
c3198a5e 304
7797c6da 305 dss_mgr_disable(dssdev->manager);
c3198a5e
M		 306
307 p = &dssdev->panel.timings;
308
309 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n",
310 dssdev->panel.timings.x_res,
311 dssdev->panel.timings.y_res);
312
46095b2d
M		 313 timing = hdmi_get_timings();
314 if (timing == NULL) {
315 /* HDMI code 4 corresponds to 640 * 480 VGA */
316 hdmi.code = 4;
317 /* DVI mode 1 corresponds to HDMI 0 to DVI */
318 hdmi.mode = HDMI_DVI;
319 hdmi.ip_data.cfg = vesa_timings[0];
320 } else {
321 hdmi.ip_data.cfg = *timing;
322 }
c3198a5e
M		 323 phy = p->pixel_clock;
324
7b27da54 325 hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data);
c3198a5e 326
60634a28 327 hdmi.ip_data.ops->video_enable(&hdmi.ip_data, 0);
c3198a5e 328
95a8aeb6 329 /* config the PLL and PHY hdmi_set_pll_pwrfirst */
60634a28 330 r = hdmi.ip_data.ops->pll_enable(&hdmi.ip_data);
c3198a5e
M		 331 if (r) {
332 DSSDBG("Failed to lock PLL\n");
333 goto err;
334 }
335
60634a28 336 r = hdmi.ip_data.ops->phy_enable(&hdmi.ip_data);
c3198a5e
M		 337 if (r) {
338 DSSDBG("Failed to start PHY\n");
339 goto err;
340 }
341
7b27da54
M		 342 hdmi.ip_data.cfg.cm.mode = hdmi.mode;
343 hdmi.ip_data.cfg.cm.code = hdmi.code;
60634a28 344 hdmi.ip_data.ops->video_configure(&hdmi.ip_data);
c3198a5e
M		 345
346 /* Make selection of HDMI in DSS */
347 dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
348
349 /* Select the dispc clock source as PRCM clock, to ensure that it is not
350 * DSI PLL source as the clock selected by DSI PLL might not be
351 * sufficient for the resolution selected / that can be changed
352 * dynamically by user. This can be moved to single location , say
353 * Boardfile.
354 */
6cb07b25 355 dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
c3198a5e
M		 356
357 /* bypass TV gamma table */
358 dispc_enable_gamma_table(0);
359
360 /* tv size */
361 dispc_set_digit_size(dssdev->panel.timings.x_res,
362 dssdev->panel.timings.y_res);
363
60634a28 364 hdmi.ip_data.ops->video_enable(&hdmi.ip_data, 1);
c3198a5e 365
33ca237f
TV		 366 r = dss_mgr_enable(dssdev->manager);
367 if (r)
368 goto err_mgr_enable;
3870c909 369
c3198a5e 370 return 0;
33ca237f
TV		 371
372err_mgr_enable:
373 hdmi.ip_data.ops->video_enable(&hdmi.ip_data, 0);
374 hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
375 hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
c3198a5e 376err:
4fbafaf3 377 hdmi_runtime_put();
c3198a5e
M		 378 return -EIO;
379}
380
381static void hdmi_power_off(struct omap_dss_device *dssdev)
382{
7797c6da 383 dss_mgr_disable(dssdev->manager);
c3198a5e 384
60634a28
M		 385 hdmi.ip_data.ops->video_enable(&hdmi.ip_data, 0);
386 hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
387 hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
4fbafaf3 388 hdmi_runtime_put();
c3198a5e
M		 389}
390
391int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
392 struct omap_video_timings *timings)
393{
394 struct hdmi_cm cm;
395
396 cm = hdmi_get_code(timings);
397 if (cm.code == -1) {
c3198a5e
M		 398 return -EINVAL;
399 }
400
401 return 0;
402
403}
404
405void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev)
406{
407 struct hdmi_cm cm;
408
c3198a5e
M		 409 cm = hdmi_get_code(&dssdev->panel.timings);
410 hdmi.code = cm.code;
411 hdmi.mode = cm.mode;
fa70dc5f
TV		 412
413 if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
414 int r;
415
416 hdmi_power_off(dssdev);
417
418 r = hdmi_power_on(dssdev);
419 if (r)
420 DSSERR("failed to power on device\n");
421 }
c3198a5e
M		 422}
423
162874d5
M		 424void hdmi_dump_regs(struct seq_file *s)
425{
426 mutex_lock(&hdmi.lock);
427
428 if (hdmi_runtime_get())
429 return;
430
431 hdmi.ip_data.ops->dump_wrapper(&hdmi.ip_data, s);
432 hdmi.ip_data.ops->dump_pll(&hdmi.ip_data, s);
433 hdmi.ip_data.ops->dump_phy(&hdmi.ip_data, s);
434 hdmi.ip_data.ops->dump_core(&hdmi.ip_data, s);
435
436 hdmi_runtime_put();
437 mutex_unlock(&hdmi.lock);
438}
439
47024565
TV		 440int omapdss_hdmi_read_edid(u8 *buf, int len)
441{
442 int r;
443
444 mutex_lock(&hdmi.lock);
445
446 r = hdmi_runtime_get();
447 BUG_ON(r);
448
449 r = hdmi.ip_data.ops->read_edid(&hdmi.ip_data, buf, len);
450
451 hdmi_runtime_put();
452 mutex_unlock(&hdmi.lock);
453
454 return r;
455}
456
759593ff
TV		 457bool omapdss_hdmi_detect(void)
458{
459 int r;
460
461 mutex_lock(&hdmi.lock);
462
463 r = hdmi_runtime_get();
464 BUG_ON(r);
465
466 r = hdmi.ip_data.ops->detect(&hdmi.ip_data);
467
468 hdmi_runtime_put();
469 mutex_unlock(&hdmi.lock);
470
471 return r == 1;
472}
473
c3198a5e
M		 474int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev)
475{
476 int r = 0;
477
478 DSSDBG("ENTER hdmi_display_enable\n");
479
480 mutex_lock(&hdmi.lock);
481
05e1d606
TV		 482 if (dssdev->manager == NULL) {
483 DSSERR("failed to enable display: no manager\n");
484 r = -ENODEV;
485 goto err0;
486 }
487
c3198a5e
M		 488 r = omap_dss_start_device(dssdev);
489 if (r) {
490 DSSERR("failed to start device\n");
491 goto err0;
492 }
493
494 if (dssdev->platform_enable) {
495 r = dssdev->platform_enable(dssdev);
496 if (r) {
497 DSSERR("failed to enable GPIO's\n");
498 goto err1;
499 }
500 }
501
502 r = hdmi_power_on(dssdev);
503 if (r) {
504 DSSERR("failed to power on device\n");
505 goto err2;
506 }
507
508 mutex_unlock(&hdmi.lock);
509 return 0;
510
511err2:
512 if (dssdev->platform_disable)
513 dssdev->platform_disable(dssdev);
514err1:
515 omap_dss_stop_device(dssdev);
516err0:
517 mutex_unlock(&hdmi.lock);
518 return r;
519}
520
521void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev)
522{
523 DSSDBG("Enter hdmi_display_disable\n");
524
525 mutex_lock(&hdmi.lock);
526
527 hdmi_power_off(dssdev);
528
529 if (dssdev->platform_disable)
530 dssdev->platform_disable(dssdev);
531
532 omap_dss_stop_device(dssdev);
533
534 mutex_unlock(&hdmi.lock);
535}
536
82335c4c
RN		 537#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
538 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
ad44cc32 539
edefcdad
RN		 540static int hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd,
541 struct snd_soc_dai *dai)
542{
543 struct snd_soc_pcm_runtime *rtd = substream->private_data;
544 struct snd_soc_codec *codec = rtd->codec;
545 struct platform_device *pdev = to_platform_device(codec->dev);
546 struct hdmi_ip_data *ip_data = snd_soc_codec_get_drvdata(codec);
547 int err = 0;
548
549 if (!(ip_data->ops) && !(ip_data->ops->audio_enable)) {
550 dev_err(&pdev->dev, "Cannot enable/disable audio\n");
551 return -ENODEV;
552 }
553
554 switch (cmd) {
555 case SNDRV_PCM_TRIGGER_START:
556 case SNDRV_PCM_TRIGGER_RESUME:
557 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
558 ip_data->ops->audio_enable(ip_data, true);
559 break;
560 case SNDRV_PCM_TRIGGER_STOP:
561 case SNDRV_PCM_TRIGGER_SUSPEND:
562 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
563 ip_data->ops->audio_enable(ip_data, false);
564 break;
565 default:
566 err = -EINVAL;
567 }
568 return err;
569}
570
284cb318 571static int hdmi_audio_hw_params(struct snd_pcm_substream *substream,
ad44cc32
RN		 572 struct snd_pcm_hw_params *params,
573 struct snd_soc_dai *dai)
574{
284cb318
RN		 575 struct snd_soc_pcm_runtime *rtd = substream->private_data;
576 struct snd_soc_codec *codec = rtd->codec;
577 struct hdmi_ip_data *ip_data = snd_soc_codec_get_drvdata(codec);
ad44cc32
RN		 578 struct hdmi_audio_format audio_format;
579 struct hdmi_audio_dma audio_dma;
580 struct hdmi_core_audio_config core_cfg;
581 struct hdmi_core_infoframe_audio aud_if_cfg;
582 int err, n, cts;
583 enum hdmi_core_audio_sample_freq sample_freq;
584
585 switch (params_format(params)) {
586 case SNDRV_PCM_FORMAT_S16_LE:
587 core_cfg.i2s_cfg.word_max_length =
588 HDMI_AUDIO_I2S_MAX_WORD_20BITS;
589 core_cfg.i2s_cfg.word_length = HDMI_AUDIO_I2S_CHST_WORD_16_BITS;
590 core_cfg.i2s_cfg.in_length_bits =
591 HDMI_AUDIO_I2S_INPUT_LENGTH_16;
592 core_cfg.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_LEFT;
593 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES;
594 audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS;
595 audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT;
596 audio_dma.transfer_size = 0x10;
597 break;
598 case SNDRV_PCM_FORMAT_S24_LE:
599 core_cfg.i2s_cfg.word_max_length =
600 HDMI_AUDIO_I2S_MAX_WORD_24BITS;
601 core_cfg.i2s_cfg.word_length = HDMI_AUDIO_I2S_CHST_WORD_24_BITS;
602 core_cfg.i2s_cfg.in_length_bits =
603 HDMI_AUDIO_I2S_INPUT_LENGTH_24;
604 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_ONESAMPLE;
605 audio_format.sample_size = HDMI_AUDIO_SAMPLE_24BITS;
606 audio_format.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
607 core_cfg.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
608 audio_dma.transfer_size = 0x20;
609 break;
610 default:
611 return -EINVAL;
612 }
613
614 switch (params_rate(params)) {
615 case 32000:
616 sample_freq = HDMI_AUDIO_FS_32000;
617 break;
618 case 44100:
619 sample_freq = HDMI_AUDIO_FS_44100;
620 break;
621 case 48000:
622 sample_freq = HDMI_AUDIO_FS_48000;
623 break;
624 default:
625 return -EINVAL;
626 }
627
95a8aeb6 628 err = hdmi_config_audio_acr(ip_data, params_rate(params), &n, &cts);
ad44cc32
RN		 629 if (err < 0)
630 return err;
631
632 /* Audio wrapper config */
633 audio_format.stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL;
634 audio_format.active_chnnls_msk = 0x03;
635 audio_format.type = HDMI_AUDIO_TYPE_LPCM;
636 audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
637 /* Disable start/stop signals of IEC 60958 blocks */
638 audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF;
639
640 audio_dma.block_size = 0xC0;
641 audio_dma.mode = HDMI_AUDIO_TRANSF_DMA;
642 audio_dma.fifo_threshold = 0x20; /* in number of samples */
643
95a8aeb6
M		 644 hdmi_wp_audio_config_dma(ip_data, &audio_dma);
645 hdmi_wp_audio_config_format(ip_data, &audio_format);
ad44cc32
RN		 646
647 /*
648 * I2S config
649 */
650 core_cfg.i2s_cfg.en_high_bitrate_aud = false;
651 /* Only used with high bitrate audio */
652 core_cfg.i2s_cfg.cbit_order = false;
653 /* Serial data and word select should change on sck rising edge */
654 core_cfg.i2s_cfg.sck_edge_mode = HDMI_AUDIO_I2S_SCK_EDGE_RISING;
655 core_cfg.i2s_cfg.vbit = HDMI_AUDIO_I2S_VBIT_FOR_PCM;
656 /* Set I2S word select polarity */
657 core_cfg.i2s_cfg.ws_polarity = HDMI_AUDIO_I2S_WS_POLARITY_LOW_IS_LEFT;
658 core_cfg.i2s_cfg.direction = HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST;
659 /* Set serial data to word select shift. See Phillips spec. */
660 core_cfg.i2s_cfg.shift = HDMI_AUDIO_I2S_FIRST_BIT_SHIFT;
661 /* Enable one of the four available serial data channels */
662 core_cfg.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN;
663
664 /* Core audio config */
665 core_cfg.freq_sample = sample_freq;
666 core_cfg.n = n;
667 core_cfg.cts = cts;
668 if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) {
669 core_cfg.aud_par_busclk = 0;
670 core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_SW;
671 core_cfg.use_mclk = false;
672 } else {
673 core_cfg.aud_par_busclk = (((128 * 31) - 1) << 8);
674 core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_HW;
675 core_cfg.use_mclk = true;
676 core_cfg.mclk_mode = HDMI_AUDIO_MCLK_128FS;
677 }
678 core_cfg.layout = HDMI_AUDIO_LAYOUT_2CH;
679 core_cfg.en_spdif = false;
680 /* Use sample frequency from channel status word */
681 core_cfg.fs_override = true;
682 /* Enable ACR packets */
683 core_cfg.en_acr_pkt = true;
684 /* Disable direct streaming digital audio */
685 core_cfg.en_dsd_audio = false;
686 /* Use parallel audio interface */
687 core_cfg.en_parallel_aud_input = true;
688
95a8aeb6 689 hdmi_core_audio_config(ip_data, &core_cfg);
ad44cc32
RN		 690
691 /*
692 * Configure packet
693 * info frame audio see doc CEA861-D page 74
694 */
695 aud_if_cfg.db1_coding_type = HDMI_INFOFRAME_AUDIO_DB1CT_FROM_STREAM;
696 aud_if_cfg.db1_channel_count = 2;
697 aud_if_cfg.db2_sample_freq = HDMI_INFOFRAME_AUDIO_DB2SF_FROM_STREAM;
698 aud_if_cfg.db2_sample_size = HDMI_INFOFRAME_AUDIO_DB2SS_FROM_STREAM;
699 aud_if_cfg.db4_channel_alloc = 0x00;
700 aud_if_cfg.db5_downmix_inh = false;
701 aud_if_cfg.db5_lsv = 0;
702
95a8aeb6 703 hdmi_core_audio_infoframe_config(ip_data, &aud_if_cfg);
ad44cc32
RN		 704 return 0;
705}
706
ad44cc32
RN		 707static int hdmi_audio_startup(struct snd_pcm_substream *substream,
708 struct snd_soc_dai *dai)
709{
710 if (!hdmi.mode) {
711 pr_err("Current video settings do not support audio.\n");
712 return -EIO;
713 }
714 return 0;
715}
716
b17ce117
RN		 717static int hdmi_audio_codec_probe(struct snd_soc_codec *codec)
718{
719 struct hdmi_ip_data *priv = &hdmi.ip_data;
720
721 snd_soc_codec_set_drvdata(codec, priv);
722 return 0;
723}
724
ad44cc32 725static struct snd_soc_codec_driver hdmi_audio_codec_drv = {
b17ce117 726 .probe = hdmi_audio_codec_probe,
ad44cc32
RN		 727};
728
729static struct snd_soc_dai_ops hdmi_audio_codec_ops = {
730 .hw_params = hdmi_audio_hw_params,
731 .trigger = hdmi_audio_trigger,
732 .startup = hdmi_audio_startup,
733};
734
735static struct snd_soc_dai_driver hdmi_codec_dai_drv = {
736 .name = "hdmi-audio-codec",
737 .playback = {
738 .channels_min = 2,
739 .channels_max = 2,
740 .rates = SNDRV_PCM_RATE_32000 |
741 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
742 .formats = SNDRV_PCM_FMTBIT_S16_LE |
743 SNDRV_PCM_FMTBIT_S24_LE,
744 },
745 .ops = &hdmi_audio_codec_ops,
746};
82335c4c
RN		 747#endif
748
4fbafaf3
TV		 749static int hdmi_get_clocks(struct platform_device *pdev)
750{
751 struct clk *clk;
752
753 clk = clk_get(&pdev->dev, "sys_clk");
754 if (IS_ERR(clk)) {
755 DSSERR("can't get sys_clk\n");
756 return PTR_ERR(clk);
757 }
758
759 hdmi.sys_clk = clk;
760
4fbafaf3
TV		 761 return 0;
762}
763
764static void hdmi_put_clocks(void)
765{
766 if (hdmi.sys_clk)
767 clk_put(hdmi.sys_clk);
4fbafaf3
TV		 768}
769
c3198a5e
M		 770/* HDMI HW IP initialisation */
771static int omapdss_hdmihw_probe(struct platform_device *pdev)
772{
773 struct resource *hdmi_mem;
4fbafaf3 774 int r;
c3198a5e
M		 775
776 hdmi.pdata = pdev->dev.platform_data;
777 hdmi.pdev = pdev;
778
779 mutex_init(&hdmi.lock);
780
781 hdmi_mem = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0);
782 if (!hdmi_mem) {
783 DSSERR("can't get IORESOURCE_MEM HDMI\n");
784 return -EINVAL;
785 }
786
787 /* Base address taken from platform */
95a8aeb6
M		 788 hdmi.ip_data.base_wp = ioremap(hdmi_mem->start,
789 resource_size(hdmi_mem));
790 if (!hdmi.ip_data.base_wp) {
c3198a5e
M		 791 DSSERR("can't ioremap WP\n");
792 return -ENOMEM;
793 }
794
4fbafaf3
TV		 795 r = hdmi_get_clocks(pdev);
796 if (r) {
95a8aeb6 797 iounmap(hdmi.ip_data.base_wp);
4fbafaf3
TV		 798 return r;
799 }
800
801 pm_runtime_enable(&pdev->dev);
802
95a8aeb6
M		 803 hdmi.ip_data.core_sys_offset = HDMI_CORE_SYS;
804 hdmi.ip_data.core_av_offset = HDMI_CORE_AV;
805 hdmi.ip_data.pll_offset = HDMI_PLLCTRL;
806 hdmi.ip_data.phy_offset = HDMI_PHY;
807
c3198a5e
M		 808 hdmi_panel_init();
809
ad44cc32
RN		 810#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
811 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
812
813 /* Register ASoC codec DAI */
4fbafaf3 814 r = snd_soc_register_codec(&pdev->dev, &hdmi_audio_codec_drv,
ad44cc32 815 &hdmi_codec_dai_drv, 1);
4fbafaf3 816 if (r) {
ad44cc32 817 DSSERR("can't register ASoC HDMI audio codec\n");
4fbafaf3 818 return r;
ad44cc32
RN		 819 }
820#endif
c3198a5e
M		 821 return 0;
822}
823
824static int omapdss_hdmihw_remove(struct platform_device *pdev)
825{
826 hdmi_panel_exit();
827
ad44cc32
RN		 828#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
829 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
830 snd_soc_unregister_codec(&pdev->dev);
831#endif
832
4fbafaf3
TV		 833 pm_runtime_disable(&pdev->dev);
834
835 hdmi_put_clocks();
836
95a8aeb6 837 iounmap(hdmi.ip_data.base_wp);
c3198a5e
M		 838
839 return 0;
840}
841
4fbafaf3
TV		 842static int hdmi_runtime_suspend(struct device *dev)
843{
4fbafaf3
TV		 844 clk_disable(hdmi.sys_clk);
845
846 dispc_runtime_put();
847 dss_runtime_put();
848
849 return 0;
850}
851
852static int hdmi_runtime_resume(struct device *dev)
853{
854 int r;
855
856 r = dss_runtime_get();
857 if (r < 0)
858 goto err_get_dss;
859
860 r = dispc_runtime_get();
861 if (r < 0)
862 goto err_get_dispc;
863
864
865 clk_enable(hdmi.sys_clk);
4fbafaf3
TV		 866
867 return 0;
868
869err_get_dispc:
870 dss_runtime_put();
871err_get_dss:
872 return r;
873}
874
875static const struct dev_pm_ops hdmi_pm_ops = {
876 .runtime_suspend = hdmi_runtime_suspend,
877 .runtime_resume = hdmi_runtime_resume,
878};
879
c3198a5e
M		 880static struct platform_driver omapdss_hdmihw_driver = {
881 .probe = omapdss_hdmihw_probe,
882 .remove = omapdss_hdmihw_remove,
883 .driver = {
884 .name = "omapdss_hdmi",
885 .owner = THIS_MODULE,
4fbafaf3 886 .pm = &hdmi_pm_ops,
c3198a5e
M		 887 },
888};
889
890int hdmi_init_platform_driver(void)
891{
892 return platform_driver_register(&omapdss_hdmihw_driver);
893}
894
895void hdmi_uninit_platform_driver(void)
896{
897 return platform_driver_unregister(&omapdss_hdmihw_driver);
898}
Linux kernel - Deliverables
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