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OMAPDSS: gracefully disable overlay at error
[deliverable/linux.git] / drivers / video / omap2 / dss / hdmi.c
CommitLineData
c3198a5e
M		 1/*
2 * hdmi.c
3 *
4 * HDMI interface DSS driver setting for TI's OMAP4 family of processor.
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
6 * Authors: Yong Zhi
7 * Mythri pk <mythripk@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#define DSS_SUBSYS_NAME "HDMI"
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/err.h>
27#include <linux/io.h>
28#include <linux/interrupt.h>
29#include <linux/mutex.h>
30#include <linux/delay.h>
31#include <linux/string.h>
24e6289c 32#include <linux/platform_device.h>
4fbafaf3
TV		 33#include <linux/pm_runtime.h>
34#include <linux/clk.h>
cca35017 35#include <linux/gpio.h>
17486943 36#include <linux/regulator/consumer.h>
a0b38cc4 37#include <video/omapdss.h>
c3198a5e 38
94c52987 39#include "ti_hdmi.h"
c3198a5e 40#include "dss.h"
ad44cc32 41#include "dss_features.h"
c3198a5e 42
95a8aeb6
M		 43#define HDMI_WP 0x0
44#define HDMI_CORE_SYS 0x400
45#define HDMI_CORE_AV 0x900
46#define HDMI_PLLCTRL 0x200
47#define HDMI_PHY 0x300
48
7c1f1eca
M		 49/* HDMI EDID Length move this */
50#define HDMI_EDID_MAX_LENGTH 256
51#define EDID_TIMING_DESCRIPTOR_SIZE 0x12
52#define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36
53#define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80
54#define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4
55#define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4
56
b44e4582 57#define HDMI_DEFAULT_REGN 16
8d88767a
TV		 58#define HDMI_DEFAULT_REGM2 1
59
c3198a5e
M		 60static struct {
61 struct mutex lock;
c3198a5e 62 struct platform_device *pdev;
66a06b0c 63
95a8aeb6 64 struct hdmi_ip_data ip_data;
4fbafaf3
TV		 65
66 struct clk *sys_clk;
17486943 67 struct regulator *vdda_hdmi_dac_reg;
cca35017
TV		 68
69 int ct_cp_hpd_gpio;
70 int ls_oe_gpio;
71 int hpd_gpio;
81b87f51 72
1f68d9c4 73 struct omap_dss_device output;
c3198a5e
M		 74} hdmi;
75
76/*
77 * Logic for the below structure :
78 * user enters the CEA or VESA timings by specifying the HDMI/DVI code.
79 * There is a correspondence between CEA/VESA timing and code, please
80 * refer to section 6.3 in HDMI 1.3 specification for timing code.
81 *
82 * In the below structure, cea_vesa_timings corresponds to all OMAP4
83 * supported CEA and VESA timing values.code_cea corresponds to the CEA
84 * code, It is used to get the timing from cea_vesa_timing array.Similarly
85 * with code_vesa. Code_index is used for back mapping, that is once EDID
86 * is read from the TV, EDID is parsed to find the timing values and then
87 * map it to corresponding CEA or VESA index.
88 */
89
46095b2d 90static const struct hdmi_config cea_timings[] = {
cc937e5e
AT		 91 {
92 { 640, 480, 25200, 96, 16, 48, 2, 10, 33,
93 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
94 false, },
95 { 1, HDMI_HDMI },
96 },
97 {
98 { 720, 480, 27027, 62, 16, 60, 6, 9, 30,
99 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
100 false, },
101 { 2, HDMI_HDMI },
102 },
103 {
104 { 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
105 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
106 false, },
107 { 4, HDMI_HDMI },
108 },
109 {
110 { 1920, 540, 74250, 44, 88, 148, 5, 2, 15,
111 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
112 true, },
113 { 5, HDMI_HDMI },
114 },
115 {
116 { 1440, 240, 27027, 124, 38, 114, 3, 4, 15,
117 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
118 true, },
119 { 6, HDMI_HDMI },
120 },
121 {
122 { 1920, 1080, 148500, 44, 88, 148, 5, 4, 36,
123 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
124 false, },
125 { 16, HDMI_HDMI },
126 },
127 {
128 { 720, 576, 27000, 64, 12, 68, 5, 5, 39,
129 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
130 false, },
131 { 17, HDMI_HDMI },
132 },
133 {
134 { 1280, 720, 74250, 40, 440, 220, 5, 5, 20,
135 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
136 false, },
137 { 19, HDMI_HDMI },
138 },
139 {
140 { 1920, 540, 74250, 44, 528, 148, 5, 2, 15,
141 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
142 true, },
143 { 20, HDMI_HDMI },
144 },
145 {
146 { 1440, 288, 27000, 126, 24, 138, 3, 2, 19,
147 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
148 true, },
149 { 21, HDMI_HDMI },
150 },
151 {
152 { 1440, 576, 54000, 128, 24, 136, 5, 5, 39,
153 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
154 false, },
155 { 29, HDMI_HDMI },
156 },
157 {
158 { 1920, 1080, 148500, 44, 528, 148, 5, 4, 36,
159 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
160 false, },
161 { 31, HDMI_HDMI },
162 },
163 {
164 { 1920, 1080, 74250, 44, 638, 148, 5, 4, 36,
165 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
166 false, },
167 { 32, HDMI_HDMI },
168 },
169 {
170 { 2880, 480, 108108, 248, 64, 240, 6, 9, 30,
171 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
172 false, },
173 { 35, HDMI_HDMI },
174 },
175 {
176 { 2880, 576, 108000, 256, 48, 272, 5, 5, 39,
177 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
178 false, },
179 { 37, HDMI_HDMI },
180 },
46095b2d 181};
cc937e5e 182
46095b2d 183static const struct hdmi_config vesa_timings[] = {
a05ce78f 184/* VESA From Here */
cc937e5e
AT		 185 {
186 { 640, 480, 25175, 96, 16, 48, 2, 11, 31,
187 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
188 false, },
189 { 4, HDMI_DVI },
190 },
191 {
192 { 800, 600, 40000, 128, 40, 88, 4, 1, 23,
193 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
194 false, },
195 { 9, HDMI_DVI },
196 },
197 {
198 { 848, 480, 33750, 112, 16, 112, 8, 6, 23,
199 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
200 false, },
201 { 0xE, HDMI_DVI },
202 },
203 {
204 { 1280, 768, 79500, 128, 64, 192, 7, 3, 20,
205 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
206 false, },
207 { 0x17, HDMI_DVI },
208 },
209 {
210 { 1280, 800, 83500, 128, 72, 200, 6, 3, 22,
211 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
212 false, },
213 { 0x1C, HDMI_DVI },
214 },
215 {
216 { 1360, 768, 85500, 112, 64, 256, 6, 3, 18,
217 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
218 false, },
219 { 0x27, HDMI_DVI },
220 },
221 {
222 { 1280, 960, 108000, 112, 96, 312, 3, 1, 36,
223 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
224 false, },
225 { 0x20, HDMI_DVI },
226 },
227 {
228 { 1280, 1024, 108000, 112, 48, 248, 3, 1, 38,
229 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
230 false, },
231 { 0x23, HDMI_DVI },
232 },
233 {
234 { 1024, 768, 65000, 136, 24, 160, 6, 3, 29,
235 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
236 false, },
237 { 0x10, HDMI_DVI },
238 },
239 {
240 { 1400, 1050, 121750, 144, 88, 232, 4, 3, 32,
241 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
242 false, },
243 { 0x2A, HDMI_DVI },
244 },
245 {
246 { 1440, 900, 106500, 152, 80, 232, 6, 3, 25,
247 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
248 false, },
249 { 0x2F, HDMI_DVI },
250 },
251 {
252 { 1680, 1050, 146250, 176 , 104, 280, 6, 3, 30,
253 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
254 false, },
255 { 0x3A, HDMI_DVI },
256 },
257 {
258 { 1366, 768, 85500, 143, 70, 213, 3, 3, 24,
259 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
260 false, },
261 { 0x51, HDMI_DVI },
262 },
263 {
264 { 1920, 1080, 148500, 44, 148, 80, 5, 4, 36,
265 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
266 false, },
267 { 0x52, HDMI_DVI },
268 },
269 {
270 { 1280, 768, 68250, 32, 48, 80, 7, 3, 12,
271 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
272 false, },
273 { 0x16, HDMI_DVI },
274 },
275 {
276 { 1400, 1050, 101000, 32, 48, 80, 4, 3, 23,
277 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
278 false, },
279 { 0x29, HDMI_DVI },
280 },
281 {
282 { 1680, 1050, 119000, 32, 48, 80, 6, 3, 21,
283 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
284 false, },
285 { 0x39, HDMI_DVI },
286 },
287 {
288 { 1280, 800, 79500, 32, 48, 80, 6, 3, 14,
289 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
290 false, },
291 { 0x1B, HDMI_DVI },
292 },
293 {
294 { 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
295 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
296 false, },
297 { 0x55, HDMI_DVI },
298 },
7a7ce2c7
TV		 299 {
300 { 1920, 1200, 154000, 32, 48, 80, 6, 3, 26,
301 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
302 false, },
303 { 0x44, HDMI_DVI },
304 },
c3198a5e
M		 305};
306
4fbafaf3
TV		 307static int hdmi_runtime_get(void)
308{
309 int r;
310
311 DSSDBG("hdmi_runtime_get\n");
312
313 r = pm_runtime_get_sync(&hdmi.pdev->dev);
314 WARN_ON(r < 0);
a247ce78 315 if (r < 0)
852f0838 316 return r;
a247ce78
AT		 317
318 return 0;
4fbafaf3
TV		 319}
320
321static void hdmi_runtime_put(void)
322{
323 int r;
324
325 DSSDBG("hdmi_runtime_put\n");
326
0eaf9f52 327 r = pm_runtime_put_sync(&hdmi.pdev->dev);
5be3aebd 328 WARN_ON(r < 0 && r != -ENOSYS);
4fbafaf3
TV		 329}
330
e25001d8
TV		 331static int hdmi_init_regulator(void)
332{
333 struct regulator *reg;
334
335 if (hdmi.vdda_hdmi_dac_reg != NULL)
336 return 0;
337
338 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda_hdmi_dac");
339
340 /* DT HACK: try VDAC to make omapdss work for o4 sdp/panda */
341 if (IS_ERR(reg))
342 reg = devm_regulator_get(&hdmi.pdev->dev, "VDAC");
343
344 if (IS_ERR(reg)) {
345 DSSERR("can't get VDDA_HDMI_DAC regulator\n");
346 return PTR_ERR(reg);
347 }
348
349 hdmi.vdda_hdmi_dac_reg = reg;
350
351 return 0;
352}
353
17ae4e8c 354static int hdmi_init_display(struct omap_dss_device *dssdev)
c3198a5e 355{
cca35017
TV		 356 int r;
357
358 struct gpio gpios[] = {
359 { hdmi.ct_cp_hpd_gpio, GPIOF_OUT_INIT_LOW, "hdmi_ct_cp_hpd" },
360 { hdmi.ls_oe_gpio, GPIOF_OUT_INIT_LOW, "hdmi_ls_oe" },
361 { hdmi.hpd_gpio, GPIOF_DIR_IN, "hdmi_hpd" },
362 };
363
c3198a5e
M		 364 DSSDBG("init_display\n");
365
b2c7d54f 366 dss_init_hdmi_ip_ops(&hdmi.ip_data, omapdss_get_version());
cca35017 367
e25001d8
TV		 368 r = hdmi_init_regulator();
369 if (r)
370 return r;
17486943 371
cca35017
TV		 372 r = gpio_request_array(gpios, ARRAY_SIZE(gpios));
373 if (r)
374 return r;
375
c3198a5e
M		 376 return 0;
377}
378
37584765 379static void hdmi_uninit_display(struct omap_dss_device *dssdev)
cca35017
TV		 380{
381 DSSDBG("uninit_display\n");
382
383 gpio_free(hdmi.ct_cp_hpd_gpio);
384 gpio_free(hdmi.ls_oe_gpio);
385 gpio_free(hdmi.hpd_gpio);
386}
387
46095b2d
M		 388static const struct hdmi_config *hdmi_find_timing(
389 const struct hdmi_config *timings_arr,
390 int len)
c3198a5e 391{
46095b2d 392 int i;
c3198a5e 393
46095b2d 394 for (i = 0; i < len; i++) {
9e4ed603 395 if (timings_arr[i].cm.code == hdmi.ip_data.cfg.cm.code)
46095b2d
M		 396 return &timings_arr[i];
397 }
398 return NULL;
399}
c3198a5e 400
46095b2d
M		 401static const struct hdmi_config *hdmi_get_timings(void)
402{
403 const struct hdmi_config *arr;
404 int len;
405
9e4ed603 406 if (hdmi.ip_data.cfg.cm.mode == HDMI_DVI) {
46095b2d
M		 407 arr = vesa_timings;
408 len = ARRAY_SIZE(vesa_timings);
409 } else {
410 arr = cea_timings;
411 len = ARRAY_SIZE(cea_timings);
412 }
413
414 return hdmi_find_timing(arr, len);
415}
416
417static bool hdmi_timings_compare(struct omap_video_timings *timing1,
cc937e5e 418 const struct omap_video_timings *timing2)
46095b2d
M		 419{
420 int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync;
421
f236b892
TV		 422 if ((DIV_ROUND_CLOSEST(timing2->pixel_clock, 1000) ==
423 DIV_ROUND_CLOSEST(timing1->pixel_clock, 1000)) &&
46095b2d
M		 424 (timing2->x_res == timing1->x_res) &&
425 (timing2->y_res == timing1->y_res)) {
c3198a5e 426
46095b2d
M		 427 timing2_hsync = timing2->hfp + timing2->hsw + timing2->hbp;
428 timing1_hsync = timing1->hfp + timing1->hsw + timing1->hbp;
429 timing2_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
430 timing1_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
431
432 DSSDBG("timing1_hsync = %d timing1_vsync = %d"\
433 "timing2_hsync = %d timing2_vsync = %d\n",
434 timing1_hsync, timing1_vsync,
435 timing2_hsync, timing2_vsync);
436
437 if ((timing1_hsync == timing2_hsync) &&
438 (timing1_vsync == timing2_vsync)) {
439 return true;
440 }
c3198a5e 441 }
46095b2d 442 return false;
c3198a5e
M		 443}
444
445static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing)
446{
46095b2d 447 int i;
c3198a5e
M		 448 struct hdmi_cm cm = {-1};
449 DSSDBG("hdmi_get_code\n");
450
46095b2d
M		 451 for (i = 0; i < ARRAY_SIZE(cea_timings); i++) {
452 if (hdmi_timings_compare(timing, &cea_timings[i].timings)) {
453 cm = cea_timings[i].cm;
454 goto end;
455 }
456 }
457 for (i = 0; i < ARRAY_SIZE(vesa_timings); i++) {
458 if (hdmi_timings_compare(timing, &vesa_timings[i].timings)) {
459 cm = vesa_timings[i].cm;
460 goto end;
c3198a5e
M		 461 }
462 }
463
46095b2d 464end: return cm;
c3198a5e 465
c3198a5e
M		 466}
467
6cb07b25
AT		 468static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
469 struct hdmi_pll_info *pi)
c3198a5e 470{
6cb07b25 471 unsigned long clkin, refclk;
c3198a5e
M		 472 u32 mf;
473
4fbafaf3 474 clkin = clk_get_rate(hdmi.sys_clk) / 10000;
c3198a5e
M		 475 /*
476 * Input clock is predivided by N + 1
477 * out put of which is reference clk
478 */
4fdfdf06
TV		 479
480 pi->regn = HDMI_DEFAULT_REGN;
8d88767a 481
b44e4582 482 refclk = clkin / pi->regn;
c3198a5e 483
4fdfdf06 484 pi->regm2 = HDMI_DEFAULT_REGM2;
c3198a5e 485
dd2116a3
M		 486 /*
487 * multiplier is pixel_clk/ref_clk
488 * Multiplying by 100 to avoid fractional part removal
489 */
490 pi->regm = phy * pi->regm2 / refclk;
491
c3198a5e
M		 492 /*
493 * fractional multiplier is remainder of the difference between
494 * multiplier and actual phy(required pixel clock thus should be
495 * multiplied by 2^18(262144) divided by the reference clock
496 */
dd2116a3
M		 497 mf = (phy - pi->regm / pi->regm2 * refclk) * 262144;
498 pi->regmf = pi->regm2 * mf / refclk;
c3198a5e
M		 499
500 /*
501 * Dcofreq should be set to 1 if required pixel clock
502 * is greater than 1000MHz
503 */
504 pi->dcofreq = phy > 1000 * 100;
b44e4582 505 pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10;
c3198a5e 506
7b27da54
M		 507 /* Set the reference clock to sysclk reference */
508 pi->refsel = HDMI_REFSEL_SYSCLK;
509
c3198a5e
M		 510 DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
511 DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
512}
513
bb426fc9 514static int hdmi_power_on_core(struct omap_dss_device *dssdev)
c3198a5e 515{
46095b2d 516 int r;
c3198a5e 517
cca35017
TV		 518 gpio_set_value(hdmi.ct_cp_hpd_gpio, 1);
519 gpio_set_value(hdmi.ls_oe_gpio, 1);
520
a84b2065
TV		 521 /* wait 300us after CT_CP_HPD for the 5V power output to reach 90% */
522 udelay(300);
523
17486943
TV		 524 r = regulator_enable(hdmi.vdda_hdmi_dac_reg);
525 if (r)
526 goto err_vdac_enable;
527
4fbafaf3
TV		 528 r = hdmi_runtime_get();
529 if (r)
cca35017 530 goto err_runtime_get;
c3198a5e 531
bb426fc9
TV		 532 /* Make selection of HDMI in DSS */
533 dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
534
bb426fc9
TV		 535 return 0;
536
537err_runtime_get:
538 regulator_disable(hdmi.vdda_hdmi_dac_reg);
539err_vdac_enable:
540 gpio_set_value(hdmi.ct_cp_hpd_gpio, 0);
541 gpio_set_value(hdmi.ls_oe_gpio, 0);
542 return r;
543}
544
545static void hdmi_power_off_core(struct omap_dss_device *dssdev)
546{
547 hdmi_runtime_put();
548 regulator_disable(hdmi.vdda_hdmi_dac_reg);
549 gpio_set_value(hdmi.ct_cp_hpd_gpio, 0);
550 gpio_set_value(hdmi.ls_oe_gpio, 0);
551}
552
553static int hdmi_power_on_full(struct omap_dss_device *dssdev)
554{
555 int r;
556 struct omap_video_timings *p;
7ae9a71e 557 struct omap_overlay_manager *mgr = hdmi.output.manager;
bb426fc9
TV		 558 unsigned long phy;
559
560 r = hdmi_power_on_core(dssdev);
561 if (r)
562 return r;
563
cea87b92 564 dss_mgr_disable(mgr);
c3198a5e 565
7849398f 566 p = &hdmi.ip_data.cfg.timings;
c3198a5e 567
7849398f 568 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
c3198a5e 569
c3198a5e
M		 570 phy = p->pixel_clock;
571
7b27da54 572 hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data);
c3198a5e 573
c0456be3 574 hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
c3198a5e 575
95a8aeb6 576 /* config the PLL and PHY hdmi_set_pll_pwrfirst */
60634a28 577 r = hdmi.ip_data.ops->pll_enable(&hdmi.ip_data);
c3198a5e
M		 578 if (r) {
579 DSSDBG("Failed to lock PLL\n");
cca35017 580 goto err_pll_enable;
c3198a5e
M		 581 }
582
60634a28 583 r = hdmi.ip_data.ops->phy_enable(&hdmi.ip_data);
c3198a5e
M		 584 if (r) {
585 DSSDBG("Failed to start PHY\n");
d3b4aa51 586 goto err_phy_enable;
c3198a5e
M		 587 }
588
60634a28 589 hdmi.ip_data.ops->video_configure(&hdmi.ip_data);
c3198a5e 590
c3198a5e
M		 591 /* bypass TV gamma table */
592 dispc_enable_gamma_table(0);
593
594 /* tv size */
cea87b92 595 dss_mgr_set_timings(mgr, p);
c3198a5e 596
c0456be3
RN		 597 r = hdmi.ip_data.ops->video_enable(&hdmi.ip_data);
598 if (r)
599 goto err_vid_enable;
c3198a5e 600
cea87b92 601 r = dss_mgr_enable(mgr);
33ca237f
TV		 602 if (r)
603 goto err_mgr_enable;
3870c909 604
c3198a5e 605 return 0;
33ca237f
TV		 606
607err_mgr_enable:
c0456be3
RN		 608 hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
609err_vid_enable:
33ca237f 610 hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
d3b4aa51 611err_phy_enable:
33ca237f 612 hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
cca35017 613err_pll_enable:
bb426fc9 614 hdmi_power_off_core(dssdev);
c3198a5e
M		 615 return -EIO;
616}
617
bb426fc9 618static void hdmi_power_off_full(struct omap_dss_device *dssdev)
c3198a5e 619{
7ae9a71e 620 struct omap_overlay_manager *mgr = hdmi.output.manager;
cea87b92
AT		 621
622 dss_mgr_disable(mgr);
c3198a5e 623
c0456be3 624 hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
60634a28
M		 625 hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
626 hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
17486943 627
bb426fc9 628 hdmi_power_off_core(dssdev);
c3198a5e
M		 629}
630
631int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
632 struct omap_video_timings *timings)
633{
634 struct hdmi_cm cm;
635
636 cm = hdmi_get_code(timings);
637 if (cm.code == -1) {
c3198a5e
M		 638 return -EINVAL;
639 }
640
641 return 0;
642
643}
644
7849398f
AT		 645void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev,
646 struct omap_video_timings *timings)
c3198a5e
M		 647{
648 struct hdmi_cm cm;
7849398f 649 const struct hdmi_config *t;
c3198a5e 650
ed1aa900
AT		 651 mutex_lock(&hdmi.lock);
652
7849398f
AT		 653 cm = hdmi_get_code(timings);
654 hdmi.ip_data.cfg.cm = cm;
655
656 t = hdmi_get_timings();
657 if (t != NULL)
658 hdmi.ip_data.cfg = *t;
fa70dc5f 659
5391e87d
TV		 660 dispc_set_tv_pclk(t->timings.pixel_clock * 1000);
661
ed1aa900 662 mutex_unlock(&hdmi.lock);
c3198a5e
M		 663}
664
e40402cf 665static void hdmi_dump_regs(struct seq_file *s)
162874d5
M		 666{
667 mutex_lock(&hdmi.lock);
668
f8fb7d7b
WY		 669 if (hdmi_runtime_get()) {
670 mutex_unlock(&hdmi.lock);
162874d5 671 return;
f8fb7d7b 672 }
162874d5
M		 673
674 hdmi.ip_data.ops->dump_wrapper(&hdmi.ip_data, s);
675 hdmi.ip_data.ops->dump_pll(&hdmi.ip_data, s);
676 hdmi.ip_data.ops->dump_phy(&hdmi.ip_data, s);
677 hdmi.ip_data.ops->dump_core(&hdmi.ip_data, s);
678
679 hdmi_runtime_put();
680 mutex_unlock(&hdmi.lock);
681}
682
47024565
TV		 683int omapdss_hdmi_read_edid(u8 *buf, int len)
684{
685 int r;
686
687 mutex_lock(&hdmi.lock);
688
689 r = hdmi_runtime_get();
690 BUG_ON(r);
691
692 r = hdmi.ip_data.ops->read_edid(&hdmi.ip_data, buf, len);
693
694 hdmi_runtime_put();
695 mutex_unlock(&hdmi.lock);
696
697 return r;
698}
699
759593ff
TV		 700bool omapdss_hdmi_detect(void)
701{
702 int r;
703
704 mutex_lock(&hdmi.lock);
705
706 r = hdmi_runtime_get();
707 BUG_ON(r);
708
29356be1 709 r = gpio_get_value(hdmi.hpd_gpio);
759593ff
TV		 710
711 hdmi_runtime_put();
712 mutex_unlock(&hdmi.lock);
713
714 return r == 1;
715}
716
c3198a5e
M		 717int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev)
718{
1f68d9c4 719 struct omap_dss_device *out = &hdmi.output;
c3198a5e
M		 720 int r = 0;
721
722 DSSDBG("ENTER hdmi_display_enable\n");
723
724 mutex_lock(&hdmi.lock);
725
cea87b92
AT		 726 if (out == NULL || out->manager == NULL) {
727 DSSERR("failed to enable display: no output/manager\n");
05e1d606
TV		 728 r = -ENODEV;
729 goto err0;
730 }
731
bb426fc9 732 r = hdmi_power_on_full(dssdev);
c3198a5e
M		 733 if (r) {
734 DSSERR("failed to power on device\n");
d3923933 735 goto err0;
c3198a5e
M		 736 }
737
738 mutex_unlock(&hdmi.lock);
739 return 0;
740
c3198a5e
M		 741err0:
742 mutex_unlock(&hdmi.lock);
743 return r;
744}
745
746void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev)
747{
748 DSSDBG("Enter hdmi_display_disable\n");
749
750 mutex_lock(&hdmi.lock);
751
bb426fc9 752 hdmi_power_off_full(dssdev);
c3198a5e 753
c3198a5e
M		 754 mutex_unlock(&hdmi.lock);
755}
756
4489823c
TV		 757int omapdss_hdmi_core_enable(struct omap_dss_device *dssdev)
758{
759 int r = 0;
760
761 DSSDBG("ENTER omapdss_hdmi_core_enable\n");
762
763 mutex_lock(&hdmi.lock);
764
4489823c
TV		 765 r = hdmi_power_on_core(dssdev);
766 if (r) {
767 DSSERR("failed to power on device\n");
768 goto err0;
769 }
770
771 mutex_unlock(&hdmi.lock);
772 return 0;
773
774err0:
775 mutex_unlock(&hdmi.lock);
776 return r;
777}
778
779void omapdss_hdmi_core_disable(struct omap_dss_device *dssdev)
780{
781 DSSDBG("Enter omapdss_hdmi_core_disable\n");
782
783 mutex_lock(&hdmi.lock);
784
785 hdmi_power_off_core(dssdev);
786
787 mutex_unlock(&hdmi.lock);
788}
789
4fbafaf3
TV		 790static int hdmi_get_clocks(struct platform_device *pdev)
791{
792 struct clk *clk;
793
b2c9c8ee 794 clk = devm_clk_get(&pdev->dev, "sys_clk");
4fbafaf3
TV		 795 if (IS_ERR(clk)) {
796 DSSERR("can't get sys_clk\n");
797 return PTR_ERR(clk);
798 }
799
800 hdmi.sys_clk = clk;
801
4fbafaf3
TV		 802 return 0;
803}
804
35547626
RN		 805#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
806int hdmi_compute_acr(u32 sample_freq, u32 *n, u32 *cts)
807{
808 u32 deep_color;
25a65359 809 bool deep_color_correct = false;
35547626
RN		 810 u32 pclk = hdmi.ip_data.cfg.timings.pixel_clock;
811
812 if (n == NULL || cts == NULL)
813 return -EINVAL;
814
815 /* TODO: When implemented, query deep color mode here. */
816 deep_color = 100;
817
25a65359
RN		 818 /*
819 * When using deep color, the default N value (as in the HDMI
820 * specification) yields to an non-integer CTS. Hence, we
821 * modify it while keeping the restrictions described in
822 * section 7.2.1 of the HDMI 1.4a specification.
823 */
35547626
RN		 824 switch (sample_freq) {
825 case 32000:
25a65359
RN		 826 case 48000:
827 case 96000:
828 case 192000:
829 if (deep_color == 125)
830 if (pclk == 27027 || pclk == 74250)
831 deep_color_correct = true;
832 if (deep_color == 150)
833 if (pclk == 27027)
834 deep_color_correct = true;
35547626
RN		 835 break;
836 case 44100:
25a65359
RN		 837 case 88200:
838 case 176400:
839 if (deep_color == 125)
840 if (pclk == 27027)
841 deep_color_correct = true;
35547626
RN		 842 break;
843 default:
35547626
RN		 844 return -EINVAL;
845 }
846
25a65359
RN		 847 if (deep_color_correct) {
848 switch (sample_freq) {
849 case 32000:
850 *n = 8192;
851 break;
852 case 44100:
853 *n = 12544;
854 break;
855 case 48000:
856 *n = 8192;
857 break;
858 case 88200:
859 *n = 25088;
860 break;
861 case 96000:
862 *n = 16384;
863 break;
864 case 176400:
865 *n = 50176;
866 break;
867 case 192000:
868 *n = 32768;
869 break;
870 default:
871 return -EINVAL;
872 }
873 } else {
874 switch (sample_freq) {
875 case 32000:
876 *n = 4096;
877 break;
878 case 44100:
879 *n = 6272;
880 break;
881 case 48000:
882 *n = 6144;
883 break;
884 case 88200:
885 *n = 12544;
886 break;
887 case 96000:
888 *n = 12288;
889 break;
890 case 176400:
891 *n = 25088;
892 break;
893 case 192000:
894 *n = 24576;
895 break;
896 default:
897 return -EINVAL;
898 }
899 }
35547626
RN		 900 /* Calculate CTS. See HDMI 1.3a or 1.4a specifications */
901 *cts = pclk * (*n / 128) * deep_color / (sample_freq / 10);
902
903 return 0;
904}
f3a97491
RN		 905
906int hdmi_audio_enable(void)
907{
908 DSSDBG("audio_enable\n");
909
910 return hdmi.ip_data.ops->audio_enable(&hdmi.ip_data);
911}
912
913void hdmi_audio_disable(void)
914{
915 DSSDBG("audio_disable\n");
916
917 hdmi.ip_data.ops->audio_disable(&hdmi.ip_data);
918}
919
920int hdmi_audio_start(void)
921{
922 DSSDBG("audio_start\n");
923
924 return hdmi.ip_data.ops->audio_start(&hdmi.ip_data);
925}
926
927void hdmi_audio_stop(void)
928{
929 DSSDBG("audio_stop\n");
930
931 hdmi.ip_data.ops->audio_stop(&hdmi.ip_data);
932}
933
934bool hdmi_mode_has_audio(void)
935{
936 if (hdmi.ip_data.cfg.cm.mode == HDMI_HDMI)
937 return true;
938 else
939 return false;
940}
941
942int hdmi_audio_config(struct omap_dss_audio *audio)
943{
944 return hdmi.ip_data.ops->audio_config(&hdmi.ip_data, audio);
945}
946
35547626
RN		 947#endif
948
17ae4e8c 949static struct omap_dss_device *hdmi_find_dssdev(struct platform_device *pdev)
38f3daf6
TV		 950{
951 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
2bbcce5e 952 const char *def_disp_name = omapdss_get_default_display_name();
1521653c
TV		 953 struct omap_dss_device *def_dssdev;
954 int i;
955
956 def_dssdev = NULL;
38f3daf6
TV		 957
958 for (i = 0; i < pdata->num_devices; ++i) {
959 struct omap_dss_device *dssdev = pdata->devices[i];
960
961 if (dssdev->type != OMAP_DISPLAY_TYPE_HDMI)
962 continue;
963
1521653c
TV		 964 if (def_dssdev == NULL)
965 def_dssdev = dssdev;
cca35017 966
1521653c
TV		 967 if (def_disp_name != NULL &&
968 strcmp(dssdev->name, def_disp_name) == 0) {
969 def_dssdev = dssdev;
970 break;
38f3daf6 971 }
1521653c
TV		 972 }
973
974 return def_dssdev;
975}
976
c0980297 977static int hdmi_probe_pdata(struct platform_device *pdev)
1521653c 978{
5274484b 979 struct omap_dss_device *plat_dssdev;
1521653c
TV		 980 struct omap_dss_device *dssdev;
981 struct omap_dss_hdmi_data *priv;
982 int r;
38f3daf6 983
5274484b 984 plat_dssdev = hdmi_find_dssdev(pdev);
1521653c 985
5274484b 986 if (!plat_dssdev)
c0980297 987 return 0;
5274484b
TV		 988
989 dssdev = dss_alloc_and_init_device(&pdev->dev);
1521653c 990 if (!dssdev)
c0980297 991 return -ENOMEM;
1521653c 992
5274484b
TV		 993 dss_copy_device_pdata(dssdev, plat_dssdev);
994
1521653c
TV		 995 priv = dssdev->data;
996
997 hdmi.ct_cp_hpd_gpio = priv->ct_cp_hpd_gpio;
998 hdmi.ls_oe_gpio = priv->ls_oe_gpio;
999 hdmi.hpd_gpio = priv->hpd_gpio;
1000
1001 r = hdmi_init_display(dssdev);
1002 if (r) {
1003 DSSERR("device %s init failed: %d\n", dssdev->name, r);
5274484b 1004 dss_put_device(dssdev);
c0980297 1005 return r;
1521653c
TV		 1006 }
1007
486c0e17
TV		 1008 r = omapdss_output_set_device(&hdmi.output, dssdev);
1009 if (r) {
1010 DSSERR("failed to connect output to new device: %s\n",
1011 dssdev->name);
1012 dss_put_device(dssdev);
c0980297 1013 return r;
486c0e17
TV		 1014 }
1015
5274484b 1016 r = dss_add_device(dssdev);
1521653c
TV		 1017 if (r) {
1018 DSSERR("device %s register failed: %d\n", dssdev->name, r);
486c0e17 1019 omapdss_output_unset_device(&hdmi.output);
d18bc455 1020 hdmi_uninit_display(dssdev);
5274484b 1021 dss_put_device(dssdev);
c0980297 1022 return r;
38f3daf6 1023 }
c0980297
TV		 1024
1025 return 0;
38f3daf6
TV		 1026}
1027
17ae4e8c 1028static void hdmi_init_output(struct platform_device *pdev)
81b87f51 1029{
1f68d9c4 1030 struct omap_dss_device *out = &hdmi.output;
81b87f51 1031
1f68d9c4 1032 out->dev = &pdev->dev;
81b87f51 1033 out->id = OMAP_DSS_OUTPUT_HDMI;
1f68d9c4 1034 out->output_type = OMAP_DISPLAY_TYPE_HDMI;
7286a08f 1035 out->name = "hdmi.0";
2eea5ae6 1036 out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
b7328e14 1037 out->owner = THIS_MODULE;
81b87f51
AT		 1038
1039 dss_register_output(out);
1040}
1041
1042static void __exit hdmi_uninit_output(struct platform_device *pdev)
1043{
1f68d9c4 1044 struct omap_dss_device *out = &hdmi.output;
81b87f51
AT		 1045
1046 dss_unregister_output(out);
1047}
1048
c3198a5e 1049/* HDMI HW IP initialisation */
17ae4e8c 1050static int omapdss_hdmihw_probe(struct platform_device *pdev)
c3198a5e 1051{
af23cb35 1052 struct resource *res;
38f3daf6 1053 int r;
c3198a5e 1054
c3198a5e
M		 1055 hdmi.pdev = pdev;
1056
1057 mutex_init(&hdmi.lock);
66a06b0c 1058 mutex_init(&hdmi.ip_data.lock);
c3198a5e 1059
af23cb35 1060 res = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0);
c3198a5e
M		 1061
1062 /* Base address taken from platform */
bc3bad16
TR		 1063 hdmi.ip_data.base_wp = devm_ioremap_resource(&pdev->dev, res);
1064 if (IS_ERR(hdmi.ip_data.base_wp))
1065 return PTR_ERR(hdmi.ip_data.base_wp);
c3198a5e 1066
ddb1d5ca
TV		 1067 hdmi.ip_data.irq = platform_get_irq(pdev, 0);
1068 if (hdmi.ip_data.irq < 0) {
1069 DSSERR("platform_get_irq failed\n");
1070 return -ENODEV;
1071 }
1072
4fbafaf3
TV		 1073 r = hdmi_get_clocks(pdev);
1074 if (r) {
47e443bc 1075 DSSERR("can't get clocks\n");
4fbafaf3
TV		 1076 return r;
1077 }
1078
1079 pm_runtime_enable(&pdev->dev);
1080
95a8aeb6
M		 1081 hdmi.ip_data.core_sys_offset = HDMI_CORE_SYS;
1082 hdmi.ip_data.core_av_offset = HDMI_CORE_AV;
1083 hdmi.ip_data.pll_offset = HDMI_PLLCTRL;
1084 hdmi.ip_data.phy_offset = HDMI_PHY;
7849398f 1085
002d368d
TV		 1086 hdmi_init_output(pdev);
1087
66a06b0c
RN		 1088 r = hdmi_panel_init();
1089 if (r) {
1090 DSSERR("can't init panel\n");
b2c9c8ee 1091 return r;
66a06b0c 1092 }
c3198a5e 1093
e40402cf
TV		 1094 dss_debugfs_create_file("hdmi", hdmi_dump_regs);
1095
c6ca5b22
TV		 1096 if (pdev->dev.platform_data) {
1097 r = hdmi_probe_pdata(pdev);
1098 if (r)
1099 goto err_probe;
c0980297 1100 }
35deca3d 1101
c3198a5e 1102 return 0;
c6ca5b22
TV		 1103
1104err_probe:
1105 hdmi_panel_exit();
1106 hdmi_uninit_output(pdev);
1107 pm_runtime_disable(&pdev->dev);
1108 return r;
c3198a5e
M		 1109}
1110
cca35017
TV		 1111static int __exit hdmi_remove_child(struct device *dev, void *data)
1112{
1113 struct omap_dss_device *dssdev = to_dss_device(dev);
1114 hdmi_uninit_display(dssdev);
1115 return 0;
1116}
1117
6e7e8f06 1118static int __exit omapdss_hdmihw_remove(struct platform_device *pdev)
c3198a5e 1119{
cca35017
TV		 1120 device_for_each_child(&pdev->dev, NULL, hdmi_remove_child);
1121
5274484b 1122 dss_unregister_child_devices(&pdev->dev);
35deca3d 1123
c3198a5e
M		 1124 hdmi_panel_exit();
1125
81b87f51
AT		 1126 hdmi_uninit_output(pdev);
1127
4fbafaf3
TV		 1128 pm_runtime_disable(&pdev->dev);
1129
c3198a5e
M		 1130 return 0;
1131}
1132
4fbafaf3
TV		 1133static int hdmi_runtime_suspend(struct device *dev)
1134{
f11766d1 1135 clk_disable_unprepare(hdmi.sys_clk);
4fbafaf3
TV		 1136
1137 dispc_runtime_put();
4fbafaf3
TV		 1138
1139 return 0;
1140}
1141
1142static int hdmi_runtime_resume(struct device *dev)
1143{
1144 int r;
1145
4fbafaf3
TV		 1146 r = dispc_runtime_get();
1147 if (r < 0)
852f0838 1148 return r;
4fbafaf3 1149
f11766d1 1150 clk_prepare_enable(hdmi.sys_clk);
4fbafaf3
TV		 1151
1152 return 0;
4fbafaf3
TV		 1153}
1154
1155static const struct dev_pm_ops hdmi_pm_ops = {
1156 .runtime_suspend = hdmi_runtime_suspend,
1157 .runtime_resume = hdmi_runtime_resume,
1158};
1159
c3198a5e 1160static struct platform_driver omapdss_hdmihw_driver = {
17ae4e8c 1161 .probe = omapdss_hdmihw_probe,
6e7e8f06 1162 .remove = __exit_p(omapdss_hdmihw_remove),
c3198a5e
M		 1163 .driver = {
1164 .name = "omapdss_hdmi",
1165 .owner = THIS_MODULE,
4fbafaf3 1166 .pm = &hdmi_pm_ops,
c3198a5e
M		 1167 },
1168};
1169
6e7e8f06 1170int __init hdmi_init_platform_driver(void)
c3198a5e 1171{
17ae4e8c 1172 return platform_driver_register(&omapdss_hdmihw_driver);
c3198a5e
M		 1173}
1174
6e7e8f06 1175void __exit hdmi_uninit_platform_driver(void)
c3198a5e 1176{
04c742c3 1177 platform_driver_unregister(&omapdss_hdmihw_driver);
c3198a5e 1178}
Linux kernel - Deliverables
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