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OMAPDSS: HDMI: Handle panel init error at probe
[deliverable/linux.git] / drivers / video / omap2 / dss / hdmi.c
CommitLineData
c3198a5e
M		 1/*
2 * hdmi.c
3 *
4 * HDMI interface DSS driver setting for TI's OMAP4 family of processor.
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
6 * Authors: Yong Zhi
7 * Mythri pk <mythripk@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#define DSS_SUBSYS_NAME "HDMI"
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/err.h>
27#include <linux/io.h>
28#include <linux/interrupt.h>
29#include <linux/mutex.h>
30#include <linux/delay.h>
31#include <linux/string.h>
24e6289c 32#include <linux/platform_device.h>
4fbafaf3
TV		 33#include <linux/pm_runtime.h>
34#include <linux/clk.h>
cca35017 35#include <linux/gpio.h>
17486943 36#include <linux/regulator/consumer.h>
a0b38cc4 37#include <video/omapdss.h>
c3198a5e 38
94c52987 39#include "ti_hdmi.h"
c3198a5e 40#include "dss.h"
ad44cc32 41#include "dss_features.h"
c3198a5e 42
95a8aeb6
M		 43#define HDMI_WP 0x0
44#define HDMI_CORE_SYS 0x400
45#define HDMI_CORE_AV 0x900
46#define HDMI_PLLCTRL 0x200
47#define HDMI_PHY 0x300
48
7c1f1eca
M		 49/* HDMI EDID Length move this */
50#define HDMI_EDID_MAX_LENGTH 256
51#define EDID_TIMING_DESCRIPTOR_SIZE 0x12
52#define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36
53#define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80
54#define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4
55#define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4
56
b44e4582 57#define HDMI_DEFAULT_REGN 16
8d88767a
TV		 58#define HDMI_DEFAULT_REGM2 1
59
c3198a5e
M		 60static struct {
61 struct mutex lock;
c3198a5e 62 struct platform_device *pdev;
66a06b0c 63
95a8aeb6 64 struct hdmi_ip_data ip_data;
4fbafaf3
TV		 65
66 struct clk *sys_clk;
17486943 67 struct regulator *vdda_hdmi_dac_reg;
cca35017
TV		 68
69 int ct_cp_hpd_gpio;
70 int ls_oe_gpio;
71 int hpd_gpio;
81b87f51
AT		 72
73 struct omap_dss_output output;
c3198a5e
M		 74} hdmi;
75
76/*
77 * Logic for the below structure :
78 * user enters the CEA or VESA timings by specifying the HDMI/DVI code.
79 * There is a correspondence between CEA/VESA timing and code, please
80 * refer to section 6.3 in HDMI 1.3 specification for timing code.
81 *
82 * In the below structure, cea_vesa_timings corresponds to all OMAP4
83 * supported CEA and VESA timing values.code_cea corresponds to the CEA
84 * code, It is used to get the timing from cea_vesa_timing array.Similarly
85 * with code_vesa. Code_index is used for back mapping, that is once EDID
86 * is read from the TV, EDID is parsed to find the timing values and then
87 * map it to corresponding CEA or VESA index.
88 */
89
46095b2d 90static const struct hdmi_config cea_timings[] = {
cc937e5e
AT		 91 {
92 { 640, 480, 25200, 96, 16, 48, 2, 10, 33,
93 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
94 false, },
95 { 1, HDMI_HDMI },
96 },
97 {
98 { 720, 480, 27027, 62, 16, 60, 6, 9, 30,
99 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
100 false, },
101 { 2, HDMI_HDMI },
102 },
103 {
104 { 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
105 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
106 false, },
107 { 4, HDMI_HDMI },
108 },
109 {
110 { 1920, 540, 74250, 44, 88, 148, 5, 2, 15,
111 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
112 true, },
113 { 5, HDMI_HDMI },
114 },
115 {
116 { 1440, 240, 27027, 124, 38, 114, 3, 4, 15,
117 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
118 true, },
119 { 6, HDMI_HDMI },
120 },
121 {
122 { 1920, 1080, 148500, 44, 88, 148, 5, 4, 36,
123 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
124 false, },
125 { 16, HDMI_HDMI },
126 },
127 {
128 { 720, 576, 27000, 64, 12, 68, 5, 5, 39,
129 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
130 false, },
131 { 17, HDMI_HDMI },
132 },
133 {
134 { 1280, 720, 74250, 40, 440, 220, 5, 5, 20,
135 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
136 false, },
137 { 19, HDMI_HDMI },
138 },
139 {
140 { 1920, 540, 74250, 44, 528, 148, 5, 2, 15,
141 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
142 true, },
143 { 20, HDMI_HDMI },
144 },
145 {
146 { 1440, 288, 27000, 126, 24, 138, 3, 2, 19,
147 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
148 true, },
149 { 21, HDMI_HDMI },
150 },
151 {
152 { 1440, 576, 54000, 128, 24, 136, 5, 5, 39,
153 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
154 false, },
155 { 29, HDMI_HDMI },
156 },
157 {
158 { 1920, 1080, 148500, 44, 528, 148, 5, 4, 36,
159 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
160 false, },
161 { 31, HDMI_HDMI },
162 },
163 {
164 { 1920, 1080, 74250, 44, 638, 148, 5, 4, 36,
165 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
166 false, },
167 { 32, HDMI_HDMI },
168 },
169 {
170 { 2880, 480, 108108, 248, 64, 240, 6, 9, 30,
171 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
172 false, },
173 { 35, HDMI_HDMI },
174 },
175 {
176 { 2880, 576, 108000, 256, 48, 272, 5, 5, 39,
177 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
178 false, },
179 { 37, HDMI_HDMI },
180 },
46095b2d 181};
cc937e5e 182
46095b2d 183static const struct hdmi_config vesa_timings[] = {
a05ce78f 184/* VESA From Here */
cc937e5e
AT		 185 {
186 { 640, 480, 25175, 96, 16, 48, 2, 11, 31,
187 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
188 false, },
189 { 4, HDMI_DVI },
190 },
191 {
192 { 800, 600, 40000, 128, 40, 88, 4, 1, 23,
193 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
194 false, },
195 { 9, HDMI_DVI },
196 },
197 {
198 { 848, 480, 33750, 112, 16, 112, 8, 6, 23,
199 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
200 false, },
201 { 0xE, HDMI_DVI },
202 },
203 {
204 { 1280, 768, 79500, 128, 64, 192, 7, 3, 20,
205 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
206 false, },
207 { 0x17, HDMI_DVI },
208 },
209 {
210 { 1280, 800, 83500, 128, 72, 200, 6, 3, 22,
211 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
212 false, },
213 { 0x1C, HDMI_DVI },
214 },
215 {
216 { 1360, 768, 85500, 112, 64, 256, 6, 3, 18,
217 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
218 false, },
219 { 0x27, HDMI_DVI },
220 },
221 {
222 { 1280, 960, 108000, 112, 96, 312, 3, 1, 36,
223 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
224 false, },
225 { 0x20, HDMI_DVI },
226 },
227 {
228 { 1280, 1024, 108000, 112, 48, 248, 3, 1, 38,
229 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
230 false, },
231 { 0x23, HDMI_DVI },
232 },
233 {
234 { 1024, 768, 65000, 136, 24, 160, 6, 3, 29,
235 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
236 false, },
237 { 0x10, HDMI_DVI },
238 },
239 {
240 { 1400, 1050, 121750, 144, 88, 232, 4, 3, 32,
241 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
242 false, },
243 { 0x2A, HDMI_DVI },
244 },
245 {
246 { 1440, 900, 106500, 152, 80, 232, 6, 3, 25,
247 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
248 false, },
249 { 0x2F, HDMI_DVI },
250 },
251 {
252 { 1680, 1050, 146250, 176 , 104, 280, 6, 3, 30,
253 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
254 false, },
255 { 0x3A, HDMI_DVI },
256 },
257 {
258 { 1366, 768, 85500, 143, 70, 213, 3, 3, 24,
259 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
260 false, },
261 { 0x51, HDMI_DVI },
262 },
263 {
264 { 1920, 1080, 148500, 44, 148, 80, 5, 4, 36,
265 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
266 false, },
267 { 0x52, HDMI_DVI },
268 },
269 {
270 { 1280, 768, 68250, 32, 48, 80, 7, 3, 12,
271 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
272 false, },
273 { 0x16, HDMI_DVI },
274 },
275 {
276 { 1400, 1050, 101000, 32, 48, 80, 4, 3, 23,
277 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
278 false, },
279 { 0x29, HDMI_DVI },
280 },
281 {
282 { 1680, 1050, 119000, 32, 48, 80, 6, 3, 21,
283 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
284 false, },
285 { 0x39, HDMI_DVI },
286 },
287 {
288 { 1280, 800, 79500, 32, 48, 80, 6, 3, 14,
289 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
290 false, },
291 { 0x1B, HDMI_DVI },
292 },
293 {
294 { 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
295 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
296 false, },
297 { 0x55, HDMI_DVI },
298 },
7a7ce2c7
TV		 299 {
300 { 1920, 1200, 154000, 32, 48, 80, 6, 3, 26,
301 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
302 false, },
303 { 0x44, HDMI_DVI },
304 },
c3198a5e
M		 305};
306
4fbafaf3
TV		 307static int hdmi_runtime_get(void)
308{
309 int r;
310
311 DSSDBG("hdmi_runtime_get\n");
312
313 r = pm_runtime_get_sync(&hdmi.pdev->dev);
314 WARN_ON(r < 0);
a247ce78 315 if (r < 0)
852f0838 316 return r;
a247ce78
AT		 317
318 return 0;
4fbafaf3
TV		 319}
320
321static void hdmi_runtime_put(void)
322{
323 int r;
324
325 DSSDBG("hdmi_runtime_put\n");
326
0eaf9f52 327 r = pm_runtime_put_sync(&hdmi.pdev->dev);
5be3aebd 328 WARN_ON(r < 0 && r != -ENOSYS);
4fbafaf3
TV		 329}
330
9d8232a7 331static int __init hdmi_init_display(struct omap_dss_device *dssdev)
c3198a5e 332{
cca35017
TV		 333 int r;
334
335 struct gpio gpios[] = {
336 { hdmi.ct_cp_hpd_gpio, GPIOF_OUT_INIT_LOW, "hdmi_ct_cp_hpd" },
337 { hdmi.ls_oe_gpio, GPIOF_OUT_INIT_LOW, "hdmi_ls_oe" },
338 { hdmi.hpd_gpio, GPIOF_DIR_IN, "hdmi_hpd" },
339 };
340
c3198a5e
M		 341 DSSDBG("init_display\n");
342
b2c7d54f 343 dss_init_hdmi_ip_ops(&hdmi.ip_data, omapdss_get_version());
cca35017 344
17486943
TV		 345 if (hdmi.vdda_hdmi_dac_reg == NULL) {
346 struct regulator *reg;
347
348 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda_hdmi_dac");
349
350 if (IS_ERR(reg)) {
351 DSSERR("can't get VDDA_HDMI_DAC regulator\n");
352 return PTR_ERR(reg);
353 }
354
355 hdmi.vdda_hdmi_dac_reg = reg;
356 }
357
cca35017
TV		 358 r = gpio_request_array(gpios, ARRAY_SIZE(gpios));
359 if (r)
360 return r;
361
c3198a5e
M		 362 return 0;
363}
364
cca35017
TV		 365static void __exit hdmi_uninit_display(struct omap_dss_device *dssdev)
366{
367 DSSDBG("uninit_display\n");
368
369 gpio_free(hdmi.ct_cp_hpd_gpio);
370 gpio_free(hdmi.ls_oe_gpio);
371 gpio_free(hdmi.hpd_gpio);
372}
373
46095b2d
M		 374static const struct hdmi_config *hdmi_find_timing(
375 const struct hdmi_config *timings_arr,
376 int len)
c3198a5e 377{
46095b2d 378 int i;
c3198a5e 379
46095b2d 380 for (i = 0; i < len; i++) {
9e4ed603 381 if (timings_arr[i].cm.code == hdmi.ip_data.cfg.cm.code)
46095b2d
M		 382 return &timings_arr[i];
383 }
384 return NULL;
385}
c3198a5e 386
46095b2d
M		 387static const struct hdmi_config *hdmi_get_timings(void)
388{
389 const struct hdmi_config *arr;
390 int len;
391
9e4ed603 392 if (hdmi.ip_data.cfg.cm.mode == HDMI_DVI) {
46095b2d
M		 393 arr = vesa_timings;
394 len = ARRAY_SIZE(vesa_timings);
395 } else {
396 arr = cea_timings;
397 len = ARRAY_SIZE(cea_timings);
398 }
399
400 return hdmi_find_timing(arr, len);
401}
402
403static bool hdmi_timings_compare(struct omap_video_timings *timing1,
cc937e5e 404 const struct omap_video_timings *timing2)
46095b2d
M		 405{
406 int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync;
407
f236b892
TV		 408 if ((DIV_ROUND_CLOSEST(timing2->pixel_clock, 1000) ==
409 DIV_ROUND_CLOSEST(timing1->pixel_clock, 1000)) &&
46095b2d
M		 410 (timing2->x_res == timing1->x_res) &&
411 (timing2->y_res == timing1->y_res)) {
c3198a5e 412
46095b2d
M		 413 timing2_hsync = timing2->hfp + timing2->hsw + timing2->hbp;
414 timing1_hsync = timing1->hfp + timing1->hsw + timing1->hbp;
415 timing2_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
416 timing1_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
417
418 DSSDBG("timing1_hsync = %d timing1_vsync = %d"\
419 "timing2_hsync = %d timing2_vsync = %d\n",
420 timing1_hsync, timing1_vsync,
421 timing2_hsync, timing2_vsync);
422
423 if ((timing1_hsync == timing2_hsync) &&
424 (timing1_vsync == timing2_vsync)) {
425 return true;
426 }
c3198a5e 427 }
46095b2d 428 return false;
c3198a5e
M		 429}
430
431static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing)
432{
46095b2d 433 int i;
c3198a5e
M		 434 struct hdmi_cm cm = {-1};
435 DSSDBG("hdmi_get_code\n");
436
46095b2d
M		 437 for (i = 0; i < ARRAY_SIZE(cea_timings); i++) {
438 if (hdmi_timings_compare(timing, &cea_timings[i].timings)) {
439 cm = cea_timings[i].cm;
440 goto end;
441 }
442 }
443 for (i = 0; i < ARRAY_SIZE(vesa_timings); i++) {
444 if (hdmi_timings_compare(timing, &vesa_timings[i].timings)) {
445 cm = vesa_timings[i].cm;
446 goto end;
c3198a5e
M		 447 }
448 }
449
46095b2d 450end: return cm;
c3198a5e 451
c3198a5e
M		 452}
453
c3dc6a7a
AT		 454unsigned long hdmi_get_pixel_clock(void)
455{
456 /* HDMI Pixel Clock in Mhz */
a05ce78f 457 return hdmi.ip_data.cfg.timings.pixel_clock * 1000;
c3dc6a7a
AT		 458}
459
6cb07b25
AT		 460static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
461 struct hdmi_pll_info *pi)
c3198a5e 462{
6cb07b25 463 unsigned long clkin, refclk;
c3198a5e
M		 464 u32 mf;
465
4fbafaf3 466 clkin = clk_get_rate(hdmi.sys_clk) / 10000;
c3198a5e
M		 467 /*
468 * Input clock is predivided by N + 1
469 * out put of which is reference clk
470 */
8d88767a
TV		 471 if (dssdev->clocks.hdmi.regn == 0)
472 pi->regn = HDMI_DEFAULT_REGN;
473 else
474 pi->regn = dssdev->clocks.hdmi.regn;
475
b44e4582 476 refclk = clkin / pi->regn;
c3198a5e 477
8d88767a
TV		 478 if (dssdev->clocks.hdmi.regm2 == 0)
479 pi->regm2 = HDMI_DEFAULT_REGM2;
480 else
481 pi->regm2 = dssdev->clocks.hdmi.regm2;
c3198a5e 482
dd2116a3
M		 483 /*
484 * multiplier is pixel_clk/ref_clk
485 * Multiplying by 100 to avoid fractional part removal
486 */
487 pi->regm = phy * pi->regm2 / refclk;
488
c3198a5e
M		 489 /*
490 * fractional multiplier is remainder of the difference between
491 * multiplier and actual phy(required pixel clock thus should be
492 * multiplied by 2^18(262144) divided by the reference clock
493 */
dd2116a3
M		 494 mf = (phy - pi->regm / pi->regm2 * refclk) * 262144;
495 pi->regmf = pi->regm2 * mf / refclk;
c3198a5e
M		 496
497 /*
498 * Dcofreq should be set to 1 if required pixel clock
499 * is greater than 1000MHz
500 */
501 pi->dcofreq = phy > 1000 * 100;
b44e4582 502 pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10;
c3198a5e 503
7b27da54
M		 504 /* Set the reference clock to sysclk reference */
505 pi->refsel = HDMI_REFSEL_SYSCLK;
506
c3198a5e
M		 507 DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
508 DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
509}
510
bb426fc9 511static int hdmi_power_on_core(struct omap_dss_device *dssdev)
c3198a5e 512{
46095b2d 513 int r;
c3198a5e 514
cca35017
TV		 515 gpio_set_value(hdmi.ct_cp_hpd_gpio, 1);
516 gpio_set_value(hdmi.ls_oe_gpio, 1);
517
a84b2065
TV		 518 /* wait 300us after CT_CP_HPD for the 5V power output to reach 90% */
519 udelay(300);
520
17486943
TV		 521 r = regulator_enable(hdmi.vdda_hdmi_dac_reg);
522 if (r)
523 goto err_vdac_enable;
524
4fbafaf3
TV		 525 r = hdmi_runtime_get();
526 if (r)
cca35017 527 goto err_runtime_get;
c3198a5e 528
bb426fc9
TV		 529 /* Make selection of HDMI in DSS */
530 dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
531
bb426fc9
TV		 532 return 0;
533
534err_runtime_get:
535 regulator_disable(hdmi.vdda_hdmi_dac_reg);
536err_vdac_enable:
537 gpio_set_value(hdmi.ct_cp_hpd_gpio, 0);
538 gpio_set_value(hdmi.ls_oe_gpio, 0);
539 return r;
540}
541
542static void hdmi_power_off_core(struct omap_dss_device *dssdev)
543{
544 hdmi_runtime_put();
545 regulator_disable(hdmi.vdda_hdmi_dac_reg);
546 gpio_set_value(hdmi.ct_cp_hpd_gpio, 0);
547 gpio_set_value(hdmi.ls_oe_gpio, 0);
548}
549
550static int hdmi_power_on_full(struct omap_dss_device *dssdev)
551{
552 int r;
553 struct omap_video_timings *p;
554 struct omap_overlay_manager *mgr = dssdev->output->manager;
555 unsigned long phy;
556
557 r = hdmi_power_on_core(dssdev);
558 if (r)
559 return r;
560
cea87b92 561 dss_mgr_disable(mgr);
c3198a5e 562
7849398f 563 p = &hdmi.ip_data.cfg.timings;
c3198a5e 564
7849398f 565 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
c3198a5e 566
c3198a5e
M		 567 phy = p->pixel_clock;
568
7b27da54 569 hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data);
c3198a5e 570
c0456be3 571 hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
c3198a5e 572
95a8aeb6 573 /* config the PLL and PHY hdmi_set_pll_pwrfirst */
60634a28 574 r = hdmi.ip_data.ops->pll_enable(&hdmi.ip_data);
c3198a5e
M		 575 if (r) {
576 DSSDBG("Failed to lock PLL\n");
cca35017 577 goto err_pll_enable;
c3198a5e
M		 578 }
579
60634a28 580 r = hdmi.ip_data.ops->phy_enable(&hdmi.ip_data);
c3198a5e
M		 581 if (r) {
582 DSSDBG("Failed to start PHY\n");
d3b4aa51 583 goto err_phy_enable;
c3198a5e
M		 584 }
585
60634a28 586 hdmi.ip_data.ops->video_configure(&hdmi.ip_data);
c3198a5e 587
c3198a5e
M		 588 /* bypass TV gamma table */
589 dispc_enable_gamma_table(0);
590
591 /* tv size */
cea87b92 592 dss_mgr_set_timings(mgr, p);
c3198a5e 593
c0456be3
RN		 594 r = hdmi.ip_data.ops->video_enable(&hdmi.ip_data);
595 if (r)
596 goto err_vid_enable;
c3198a5e 597
cea87b92 598 r = dss_mgr_enable(mgr);
33ca237f
TV		 599 if (r)
600 goto err_mgr_enable;
3870c909 601
c3198a5e 602 return 0;
33ca237f
TV		 603
604err_mgr_enable:
c0456be3
RN		 605 hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
606err_vid_enable:
33ca237f 607 hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
d3b4aa51 608err_phy_enable:
33ca237f 609 hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
cca35017 610err_pll_enable:
bb426fc9 611 hdmi_power_off_core(dssdev);
c3198a5e
M		 612 return -EIO;
613}
614
bb426fc9 615static void hdmi_power_off_full(struct omap_dss_device *dssdev)
c3198a5e 616{
cea87b92
AT		 617 struct omap_overlay_manager *mgr = dssdev->output->manager;
618
619 dss_mgr_disable(mgr);
c3198a5e 620
c0456be3 621 hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
60634a28
M		 622 hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
623 hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
17486943 624
bb426fc9 625 hdmi_power_off_core(dssdev);
c3198a5e
M		 626}
627
628int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
629 struct omap_video_timings *timings)
630{
631 struct hdmi_cm cm;
632
633 cm = hdmi_get_code(timings);
634 if (cm.code == -1) {
c3198a5e
M		 635 return -EINVAL;
636 }
637
638 return 0;
639
640}
641
7849398f
AT		 642void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev,
643 struct omap_video_timings *timings)
c3198a5e
M		 644{
645 struct hdmi_cm cm;
7849398f 646 const struct hdmi_config *t;
c3198a5e 647
ed1aa900
AT		 648 mutex_lock(&hdmi.lock);
649
7849398f
AT		 650 cm = hdmi_get_code(timings);
651 hdmi.ip_data.cfg.cm = cm;
652
653 t = hdmi_get_timings();
654 if (t != NULL)
655 hdmi.ip_data.cfg = *t;
fa70dc5f 656
ed1aa900 657 mutex_unlock(&hdmi.lock);
c3198a5e
M		 658}
659
e40402cf 660static void hdmi_dump_regs(struct seq_file *s)
162874d5
M		 661{
662 mutex_lock(&hdmi.lock);
663
f8fb7d7b
WY		 664 if (hdmi_runtime_get()) {
665 mutex_unlock(&hdmi.lock);
162874d5 666 return;
f8fb7d7b 667 }
162874d5
M		 668
669 hdmi.ip_data.ops->dump_wrapper(&hdmi.ip_data, s);
670 hdmi.ip_data.ops->dump_pll(&hdmi.ip_data, s);
671 hdmi.ip_data.ops->dump_phy(&hdmi.ip_data, s);
672 hdmi.ip_data.ops->dump_core(&hdmi.ip_data, s);
673
674 hdmi_runtime_put();
675 mutex_unlock(&hdmi.lock);
676}
677
47024565
TV		 678int omapdss_hdmi_read_edid(u8 *buf, int len)
679{
680 int r;
681
682 mutex_lock(&hdmi.lock);
683
684 r = hdmi_runtime_get();
685 BUG_ON(r);
686
687 r = hdmi.ip_data.ops->read_edid(&hdmi.ip_data, buf, len);
688
689 hdmi_runtime_put();
690 mutex_unlock(&hdmi.lock);
691
692 return r;
693}
694
759593ff
TV		 695bool omapdss_hdmi_detect(void)
696{
697 int r;
698
699 mutex_lock(&hdmi.lock);
700
701 r = hdmi_runtime_get();
702 BUG_ON(r);
703
704 r = hdmi.ip_data.ops->detect(&hdmi.ip_data);
705
706 hdmi_runtime_put();
707 mutex_unlock(&hdmi.lock);
708
709 return r == 1;
710}
711
c3198a5e
M		 712int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev)
713{
cea87b92 714 struct omap_dss_output *out = dssdev->output;
c3198a5e
M		 715 int r = 0;
716
717 DSSDBG("ENTER hdmi_display_enable\n");
718
719 mutex_lock(&hdmi.lock);
720
cea87b92
AT		 721 if (out == NULL || out->manager == NULL) {
722 DSSERR("failed to enable display: no output/manager\n");
05e1d606
TV		 723 r = -ENODEV;
724 goto err0;
725 }
726
cca35017 727 hdmi.ip_data.hpd_gpio = hdmi.hpd_gpio;
c49d005b 728
c3198a5e
M		 729 r = omap_dss_start_device(dssdev);
730 if (r) {
731 DSSERR("failed to start device\n");
732 goto err0;
733 }
734
bb426fc9 735 r = hdmi_power_on_full(dssdev);
c3198a5e
M		 736 if (r) {
737 DSSERR("failed to power on device\n");
cca35017 738 goto err1;
c3198a5e
M		 739 }
740
741 mutex_unlock(&hdmi.lock);
742 return 0;
743
c3198a5e
M		 744err1:
745 omap_dss_stop_device(dssdev);
746err0:
747 mutex_unlock(&hdmi.lock);
748 return r;
749}
750
751void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev)
752{
753 DSSDBG("Enter hdmi_display_disable\n");
754
755 mutex_lock(&hdmi.lock);
756
bb426fc9 757 hdmi_power_off_full(dssdev);
c3198a5e 758
c3198a5e
M		 759 omap_dss_stop_device(dssdev);
760
761 mutex_unlock(&hdmi.lock);
762}
763
4489823c
TV		 764int omapdss_hdmi_core_enable(struct omap_dss_device *dssdev)
765{
766 int r = 0;
767
768 DSSDBG("ENTER omapdss_hdmi_core_enable\n");
769
770 mutex_lock(&hdmi.lock);
771
772 hdmi.ip_data.hpd_gpio = hdmi.hpd_gpio;
773
774 r = hdmi_power_on_core(dssdev);
775 if (r) {
776 DSSERR("failed to power on device\n");
777 goto err0;
778 }
779
780 mutex_unlock(&hdmi.lock);
781 return 0;
782
783err0:
784 mutex_unlock(&hdmi.lock);
785 return r;
786}
787
788void omapdss_hdmi_core_disable(struct omap_dss_device *dssdev)
789{
790 DSSDBG("Enter omapdss_hdmi_core_disable\n");
791
792 mutex_lock(&hdmi.lock);
793
794 hdmi_power_off_core(dssdev);
795
796 mutex_unlock(&hdmi.lock);
797}
798
4fbafaf3
TV		 799static int hdmi_get_clocks(struct platform_device *pdev)
800{
801 struct clk *clk;
802
803 clk = clk_get(&pdev->dev, "sys_clk");
804 if (IS_ERR(clk)) {
805 DSSERR("can't get sys_clk\n");
806 return PTR_ERR(clk);
807 }
808
809 hdmi.sys_clk = clk;
810
4fbafaf3
TV		 811 return 0;
812}
813
814static void hdmi_put_clocks(void)
815{
816 if (hdmi.sys_clk)
817 clk_put(hdmi.sys_clk);
4fbafaf3
TV		 818}
819
35547626
RN		 820#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
821int hdmi_compute_acr(u32 sample_freq, u32 *n, u32 *cts)
822{
823 u32 deep_color;
25a65359 824 bool deep_color_correct = false;
35547626
RN		 825 u32 pclk = hdmi.ip_data.cfg.timings.pixel_clock;
826
827 if (n == NULL || cts == NULL)
828 return -EINVAL;
829
830 /* TODO: When implemented, query deep color mode here. */
831 deep_color = 100;
832
25a65359
RN		 833 /*
834 * When using deep color, the default N value (as in the HDMI
835 * specification) yields to an non-integer CTS. Hence, we
836 * modify it while keeping the restrictions described in
837 * section 7.2.1 of the HDMI 1.4a specification.
838 */
35547626
RN		 839 switch (sample_freq) {
840 case 32000:
25a65359
RN		 841 case 48000:
842 case 96000:
843 case 192000:
844 if (deep_color == 125)
845 if (pclk == 27027 || pclk == 74250)
846 deep_color_correct = true;
847 if (deep_color == 150)
848 if (pclk == 27027)
849 deep_color_correct = true;
35547626
RN		 850 break;
851 case 44100:
25a65359
RN		 852 case 88200:
853 case 176400:
854 if (deep_color == 125)
855 if (pclk == 27027)
856 deep_color_correct = true;
35547626
RN		 857 break;
858 default:
35547626
RN		 859 return -EINVAL;
860 }
861
25a65359
RN		 862 if (deep_color_correct) {
863 switch (sample_freq) {
864 case 32000:
865 *n = 8192;
866 break;
867 case 44100:
868 *n = 12544;
869 break;
870 case 48000:
871 *n = 8192;
872 break;
873 case 88200:
874 *n = 25088;
875 break;
876 case 96000:
877 *n = 16384;
878 break;
879 case 176400:
880 *n = 50176;
881 break;
882 case 192000:
883 *n = 32768;
884 break;
885 default:
886 return -EINVAL;
887 }
888 } else {
889 switch (sample_freq) {
890 case 32000:
891 *n = 4096;
892 break;
893 case 44100:
894 *n = 6272;
895 break;
896 case 48000:
897 *n = 6144;
898 break;
899 case 88200:
900 *n = 12544;
901 break;
902 case 96000:
903 *n = 12288;
904 break;
905 case 176400:
906 *n = 25088;
907 break;
908 case 192000:
909 *n = 24576;
910 break;
911 default:
912 return -EINVAL;
913 }
914 }
35547626
RN		 915 /* Calculate CTS. See HDMI 1.3a or 1.4a specifications */
916 *cts = pclk * (*n / 128) * deep_color / (sample_freq / 10);
917
918 return 0;
919}
f3a97491
RN		 920
921int hdmi_audio_enable(void)
922{
923 DSSDBG("audio_enable\n");
924
925 return hdmi.ip_data.ops->audio_enable(&hdmi.ip_data);
926}
927
928void hdmi_audio_disable(void)
929{
930 DSSDBG("audio_disable\n");
931
932 hdmi.ip_data.ops->audio_disable(&hdmi.ip_data);
933}
934
935int hdmi_audio_start(void)
936{
937 DSSDBG("audio_start\n");
938
939 return hdmi.ip_data.ops->audio_start(&hdmi.ip_data);
940}
941
942void hdmi_audio_stop(void)
943{
944 DSSDBG("audio_stop\n");
945
946 hdmi.ip_data.ops->audio_stop(&hdmi.ip_data);
947}
948
949bool hdmi_mode_has_audio(void)
950{
951 if (hdmi.ip_data.cfg.cm.mode == HDMI_HDMI)
952 return true;
953 else
954 return false;
955}
956
957int hdmi_audio_config(struct omap_dss_audio *audio)
958{
959 return hdmi.ip_data.ops->audio_config(&hdmi.ip_data, audio);
960}
961
35547626
RN		 962#endif
963
1521653c 964static struct omap_dss_device * __init hdmi_find_dssdev(struct platform_device *pdev)
38f3daf6
TV		 965{
966 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
2bbcce5e 967 const char *def_disp_name = omapdss_get_default_display_name();
1521653c
TV		 968 struct omap_dss_device *def_dssdev;
969 int i;
970
971 def_dssdev = NULL;
38f3daf6
TV		 972
973 for (i = 0; i < pdata->num_devices; ++i) {
974 struct omap_dss_device *dssdev = pdata->devices[i];
975
976 if (dssdev->type != OMAP_DISPLAY_TYPE_HDMI)
977 continue;
978
1521653c
TV		 979 if (def_dssdev == NULL)
980 def_dssdev = dssdev;
cca35017 981
1521653c
TV		 982 if (def_disp_name != NULL &&
983 strcmp(dssdev->name, def_disp_name) == 0) {
984 def_dssdev = dssdev;
985 break;
38f3daf6 986 }
1521653c
TV		 987 }
988
989 return def_dssdev;
990}
991
992static void __init hdmi_probe_pdata(struct platform_device *pdev)
993{
5274484b 994 struct omap_dss_device *plat_dssdev;
1521653c
TV		 995 struct omap_dss_device *dssdev;
996 struct omap_dss_hdmi_data *priv;
997 int r;
38f3daf6 998
5274484b 999 plat_dssdev = hdmi_find_dssdev(pdev);
1521653c 1000
5274484b
TV		 1001 if (!plat_dssdev)
1002 return;
1003
1004 dssdev = dss_alloc_and_init_device(&pdev->dev);
1521653c
TV		 1005 if (!dssdev)
1006 return;
1007
5274484b
TV		 1008 dss_copy_device_pdata(dssdev, plat_dssdev);
1009
1521653c
TV		 1010 priv = dssdev->data;
1011
1012 hdmi.ct_cp_hpd_gpio = priv->ct_cp_hpd_gpio;
1013 hdmi.ls_oe_gpio = priv->ls_oe_gpio;
1014 hdmi.hpd_gpio = priv->hpd_gpio;
1015
bcb226a9
TV		 1016 dssdev->channel = OMAP_DSS_CHANNEL_DIGIT;
1017
1521653c
TV		 1018 r = hdmi_init_display(dssdev);
1019 if (r) {
1020 DSSERR("device %s init failed: %d\n", dssdev->name, r);
5274484b 1021 dss_put_device(dssdev);
1521653c
TV		 1022 return;
1023 }
1024
5274484b 1025 r = dss_add_device(dssdev);
1521653c
TV		 1026 if (r) {
1027 DSSERR("device %s register failed: %d\n", dssdev->name, r);
5274484b 1028 dss_put_device(dssdev);
1521653c 1029 return;
38f3daf6
TV		 1030 }
1031}
1032
81b87f51
AT		 1033static void __init hdmi_init_output(struct platform_device *pdev)
1034{
1035 struct omap_dss_output *out = &hdmi.output;
1036
1037 out->pdev = pdev;
1038 out->id = OMAP_DSS_OUTPUT_HDMI;
1039 out->type = OMAP_DISPLAY_TYPE_HDMI;
1040
1041 dss_register_output(out);
1042}
1043
1044static void __exit hdmi_uninit_output(struct platform_device *pdev)
1045{
1046 struct omap_dss_output *out = &hdmi.output;
1047
1048 dss_unregister_output(out);
1049}
1050
c3198a5e 1051/* HDMI HW IP initialisation */
6e7e8f06 1052static int __init omapdss_hdmihw_probe(struct platform_device *pdev)
c3198a5e 1053{
af23cb35 1054 struct resource *res;
38f3daf6 1055 int r;
c3198a5e 1056
c3198a5e
M		 1057 hdmi.pdev = pdev;
1058
1059 mutex_init(&hdmi.lock);
66a06b0c 1060 mutex_init(&hdmi.ip_data.lock);
c3198a5e 1061
af23cb35
RN		 1062 res = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0);
1063 if (!res) {
c3198a5e
M		 1064 DSSERR("can't get IORESOURCE_MEM HDMI\n");
1065 return -EINVAL;
1066 }
1067
1068 /* Base address taken from platform */
47e443bc 1069 hdmi.ip_data.base_wp = devm_request_and_ioremap(&pdev->dev, res);
95a8aeb6 1070 if (!hdmi.ip_data.base_wp) {
c3198a5e
M		 1071 DSSERR("can't ioremap WP\n");
1072 return -ENOMEM;
1073 }
1074
4fbafaf3
TV		 1075 r = hdmi_get_clocks(pdev);
1076 if (r) {
47e443bc 1077 DSSERR("can't get clocks\n");
4fbafaf3
TV		 1078 return r;
1079 }
1080
1081 pm_runtime_enable(&pdev->dev);
1082
95a8aeb6
M		 1083 hdmi.ip_data.core_sys_offset = HDMI_CORE_SYS;
1084 hdmi.ip_data.core_av_offset = HDMI_CORE_AV;
1085 hdmi.ip_data.pll_offset = HDMI_PLLCTRL;
1086 hdmi.ip_data.phy_offset = HDMI_PHY;
7849398f 1087
66a06b0c
RN		 1088 r = hdmi_panel_init();
1089 if (r) {
1090 DSSERR("can't init panel\n");
1091 goto err_panel_init;
1092 }
c3198a5e 1093
e40402cf
TV		 1094 dss_debugfs_create_file("hdmi", hdmi_dump_regs);
1095
81b87f51
AT		 1096 hdmi_init_output(pdev);
1097
38f3daf6 1098 hdmi_probe_pdata(pdev);
35deca3d 1099
c3198a5e 1100 return 0;
66a06b0c
RN		 1101
1102err_panel_init:
1103 hdmi_put_clocks();
1104 return r;
c3198a5e
M		 1105}
1106
cca35017
TV		 1107static int __exit hdmi_remove_child(struct device *dev, void *data)
1108{
1109 struct omap_dss_device *dssdev = to_dss_device(dev);
1110 hdmi_uninit_display(dssdev);
1111 return 0;
1112}
1113
6e7e8f06 1114static int __exit omapdss_hdmihw_remove(struct platform_device *pdev)
c3198a5e 1115{
cca35017
TV		 1116 device_for_each_child(&pdev->dev, NULL, hdmi_remove_child);
1117
5274484b 1118 dss_unregister_child_devices(&pdev->dev);
35deca3d 1119
c3198a5e
M		 1120 hdmi_panel_exit();
1121
81b87f51
AT		 1122 hdmi_uninit_output(pdev);
1123
4fbafaf3
TV		 1124 pm_runtime_disable(&pdev->dev);
1125
1126 hdmi_put_clocks();
1127
c3198a5e
M		 1128 return 0;
1129}
1130
4fbafaf3
TV		 1131static int hdmi_runtime_suspend(struct device *dev)
1132{
f11766d1 1133 clk_disable_unprepare(hdmi.sys_clk);
4fbafaf3
TV		 1134
1135 dispc_runtime_put();
4fbafaf3
TV		 1136
1137 return 0;
1138}
1139
1140static int hdmi_runtime_resume(struct device *dev)
1141{
1142 int r;
1143
4fbafaf3
TV		 1144 r = dispc_runtime_get();
1145 if (r < 0)
852f0838 1146 return r;
4fbafaf3 1147
f11766d1 1148 clk_prepare_enable(hdmi.sys_clk);
4fbafaf3
TV		 1149
1150 return 0;
4fbafaf3
TV		 1151}
1152
1153static const struct dev_pm_ops hdmi_pm_ops = {
1154 .runtime_suspend = hdmi_runtime_suspend,
1155 .runtime_resume = hdmi_runtime_resume,
1156};
1157
c3198a5e 1158static struct platform_driver omapdss_hdmihw_driver = {
6e7e8f06 1159 .remove = __exit_p(omapdss_hdmihw_remove),
c3198a5e
M		 1160 .driver = {
1161 .name = "omapdss_hdmi",
1162 .owner = THIS_MODULE,
4fbafaf3 1163 .pm = &hdmi_pm_ops,
c3198a5e
M		 1164 },
1165};
1166
6e7e8f06 1167int __init hdmi_init_platform_driver(void)
c3198a5e 1168{
61055d4b 1169 return platform_driver_probe(&omapdss_hdmihw_driver, omapdss_hdmihw_probe);
c3198a5e
M		 1170}
1171
6e7e8f06 1172void __exit hdmi_uninit_platform_driver(void)
c3198a5e 1173{
04c742c3 1174 platform_driver_unregister(&omapdss_hdmihw_driver);
c3198a5e 1175}
Linux kernel - Deliverables
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