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OMAPDSS: Add dss_get_default_display_name()
[deliverable/linux.git] / drivers / video / omap2 / dss / hdmi.c
CommitLineData
c3198a5e
M		 1/*
2 * hdmi.c
3 *
4 * HDMI interface DSS driver setting for TI's OMAP4 family of processor.
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
6 * Authors: Yong Zhi
7 * Mythri pk <mythripk@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#define DSS_SUBSYS_NAME "HDMI"
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/err.h>
27#include <linux/io.h>
28#include <linux/interrupt.h>
29#include <linux/mutex.h>
30#include <linux/delay.h>
31#include <linux/string.h>
24e6289c 32#include <linux/platform_device.h>
4fbafaf3
TV		 33#include <linux/pm_runtime.h>
34#include <linux/clk.h>
cca35017 35#include <linux/gpio.h>
17486943 36#include <linux/regulator/consumer.h>
a0b38cc4 37#include <video/omapdss.h>
c3198a5e 38
94c52987 39#include "ti_hdmi.h"
c3198a5e 40#include "dss.h"
ad44cc32 41#include "dss_features.h"
c3198a5e 42
95a8aeb6
M		 43#define HDMI_WP 0x0
44#define HDMI_CORE_SYS 0x400
45#define HDMI_CORE_AV 0x900
46#define HDMI_PLLCTRL 0x200
47#define HDMI_PHY 0x300
48
7c1f1eca
M		 49/* HDMI EDID Length move this */
50#define HDMI_EDID_MAX_LENGTH 256
51#define EDID_TIMING_DESCRIPTOR_SIZE 0x12
52#define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36
53#define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80
54#define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4
55#define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4
56
b44e4582 57#define HDMI_DEFAULT_REGN 16
8d88767a
TV		 58#define HDMI_DEFAULT_REGM2 1
59
c3198a5e
M		 60static struct {
61 struct mutex lock;
c3198a5e 62 struct platform_device *pdev;
95a8aeb6 63 struct hdmi_ip_data ip_data;
4fbafaf3
TV		 64
65 struct clk *sys_clk;
17486943 66 struct regulator *vdda_hdmi_dac_reg;
cca35017
TV		 67
68 int ct_cp_hpd_gpio;
69 int ls_oe_gpio;
70 int hpd_gpio;
c3198a5e
M		 71} hdmi;
72
73/*
74 * Logic for the below structure :
75 * user enters the CEA or VESA timings by specifying the HDMI/DVI code.
76 * There is a correspondence between CEA/VESA timing and code, please
77 * refer to section 6.3 in HDMI 1.3 specification for timing code.
78 *
79 * In the below structure, cea_vesa_timings corresponds to all OMAP4
80 * supported CEA and VESA timing values.code_cea corresponds to the CEA
81 * code, It is used to get the timing from cea_vesa_timing array.Similarly
82 * with code_vesa. Code_index is used for back mapping, that is once EDID
83 * is read from the TV, EDID is parsed to find the timing values and then
84 * map it to corresponding CEA or VESA index.
85 */
86
46095b2d 87static const struct hdmi_config cea_timings[] = {
cc937e5e
AT		 88 {
89 { 640, 480, 25200, 96, 16, 48, 2, 10, 33,
90 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
91 false, },
92 { 1, HDMI_HDMI },
93 },
94 {
95 { 720, 480, 27027, 62, 16, 60, 6, 9, 30,
96 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
97 false, },
98 { 2, HDMI_HDMI },
99 },
100 {
101 { 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
102 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
103 false, },
104 { 4, HDMI_HDMI },
105 },
106 {
107 { 1920, 540, 74250, 44, 88, 148, 5, 2, 15,
108 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
109 true, },
110 { 5, HDMI_HDMI },
111 },
112 {
113 { 1440, 240, 27027, 124, 38, 114, 3, 4, 15,
114 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
115 true, },
116 { 6, HDMI_HDMI },
117 },
118 {
119 { 1920, 1080, 148500, 44, 88, 148, 5, 4, 36,
120 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
121 false, },
122 { 16, HDMI_HDMI },
123 },
124 {
125 { 720, 576, 27000, 64, 12, 68, 5, 5, 39,
126 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
127 false, },
128 { 17, HDMI_HDMI },
129 },
130 {
131 { 1280, 720, 74250, 40, 440, 220, 5, 5, 20,
132 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
133 false, },
134 { 19, HDMI_HDMI },
135 },
136 {
137 { 1920, 540, 74250, 44, 528, 148, 5, 2, 15,
138 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
139 true, },
140 { 20, HDMI_HDMI },
141 },
142 {
143 { 1440, 288, 27000, 126, 24, 138, 3, 2, 19,
144 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
145 true, },
146 { 21, HDMI_HDMI },
147 },
148 {
149 { 1440, 576, 54000, 128, 24, 136, 5, 5, 39,
150 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
151 false, },
152 { 29, HDMI_HDMI },
153 },
154 {
155 { 1920, 1080, 148500, 44, 528, 148, 5, 4, 36,
156 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
157 false, },
158 { 31, HDMI_HDMI },
159 },
160 {
161 { 1920, 1080, 74250, 44, 638, 148, 5, 4, 36,
162 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
163 false, },
164 { 32, HDMI_HDMI },
165 },
166 {
167 { 2880, 480, 108108, 248, 64, 240, 6, 9, 30,
168 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
169 false, },
170 { 35, HDMI_HDMI },
171 },
172 {
173 { 2880, 576, 108000, 256, 48, 272, 5, 5, 39,
174 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
175 false, },
176 { 37, HDMI_HDMI },
177 },
46095b2d 178};
cc937e5e 179
46095b2d 180static const struct hdmi_config vesa_timings[] = {
a05ce78f 181/* VESA From Here */
cc937e5e
AT		 182 {
183 { 640, 480, 25175, 96, 16, 48, 2, 11, 31,
184 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
185 false, },
186 { 4, HDMI_DVI },
187 },
188 {
189 { 800, 600, 40000, 128, 40, 88, 4, 1, 23,
190 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
191 false, },
192 { 9, HDMI_DVI },
193 },
194 {
195 { 848, 480, 33750, 112, 16, 112, 8, 6, 23,
196 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
197 false, },
198 { 0xE, HDMI_DVI },
199 },
200 {
201 { 1280, 768, 79500, 128, 64, 192, 7, 3, 20,
202 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
203 false, },
204 { 0x17, HDMI_DVI },
205 },
206 {
207 { 1280, 800, 83500, 128, 72, 200, 6, 3, 22,
208 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
209 false, },
210 { 0x1C, HDMI_DVI },
211 },
212 {
213 { 1360, 768, 85500, 112, 64, 256, 6, 3, 18,
214 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
215 false, },
216 { 0x27, HDMI_DVI },
217 },
218 {
219 { 1280, 960, 108000, 112, 96, 312, 3, 1, 36,
220 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
221 false, },
222 { 0x20, HDMI_DVI },
223 },
224 {
225 { 1280, 1024, 108000, 112, 48, 248, 3, 1, 38,
226 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
227 false, },
228 { 0x23, HDMI_DVI },
229 },
230 {
231 { 1024, 768, 65000, 136, 24, 160, 6, 3, 29,
232 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
233 false, },
234 { 0x10, HDMI_DVI },
235 },
236 {
237 { 1400, 1050, 121750, 144, 88, 232, 4, 3, 32,
238 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
239 false, },
240 { 0x2A, HDMI_DVI },
241 },
242 {
243 { 1440, 900, 106500, 152, 80, 232, 6, 3, 25,
244 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
245 false, },
246 { 0x2F, HDMI_DVI },
247 },
248 {
249 { 1680, 1050, 146250, 176 , 104, 280, 6, 3, 30,
250 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
251 false, },
252 { 0x3A, HDMI_DVI },
253 },
254 {
255 { 1366, 768, 85500, 143, 70, 213, 3, 3, 24,
256 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
257 false, },
258 { 0x51, HDMI_DVI },
259 },
260 {
261 { 1920, 1080, 148500, 44, 148, 80, 5, 4, 36,
262 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
263 false, },
264 { 0x52, HDMI_DVI },
265 },
266 {
267 { 1280, 768, 68250, 32, 48, 80, 7, 3, 12,
268 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
269 false, },
270 { 0x16, HDMI_DVI },
271 },
272 {
273 { 1400, 1050, 101000, 32, 48, 80, 4, 3, 23,
274 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
275 false, },
276 { 0x29, HDMI_DVI },
277 },
278 {
279 { 1680, 1050, 119000, 32, 48, 80, 6, 3, 21,
280 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
281 false, },
282 { 0x39, HDMI_DVI },
283 },
284 {
285 { 1280, 800, 79500, 32, 48, 80, 6, 3, 14,
286 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
287 false, },
288 { 0x1B, HDMI_DVI },
289 },
290 {
291 { 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
292 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
293 false, },
294 { 0x55, HDMI_DVI },
295 },
c3198a5e
M		 296};
297
4fbafaf3
TV		 298static int hdmi_runtime_get(void)
299{
300 int r;
301
302 DSSDBG("hdmi_runtime_get\n");
303
304 r = pm_runtime_get_sync(&hdmi.pdev->dev);
305 WARN_ON(r < 0);
a247ce78 306 if (r < 0)
852f0838 307 return r;
a247ce78
AT		 308
309 return 0;
4fbafaf3
TV		 310}
311
312static void hdmi_runtime_put(void)
313{
314 int r;
315
316 DSSDBG("hdmi_runtime_put\n");
317
0eaf9f52 318 r = pm_runtime_put_sync(&hdmi.pdev->dev);
5be3aebd 319 WARN_ON(r < 0 && r != -ENOSYS);
4fbafaf3
TV		 320}
321
9d8232a7 322static int __init hdmi_init_display(struct omap_dss_device *dssdev)
c3198a5e 323{
cca35017
TV		 324 int r;
325
326 struct gpio gpios[] = {
327 { hdmi.ct_cp_hpd_gpio, GPIOF_OUT_INIT_LOW, "hdmi_ct_cp_hpd" },
328 { hdmi.ls_oe_gpio, GPIOF_OUT_INIT_LOW, "hdmi_ls_oe" },
329 { hdmi.hpd_gpio, GPIOF_DIR_IN, "hdmi_hpd" },
330 };
331
c3198a5e
M		 332 DSSDBG("init_display\n");
333
60634a28 334 dss_init_hdmi_ip_ops(&hdmi.ip_data);
cca35017 335
17486943
TV		 336 if (hdmi.vdda_hdmi_dac_reg == NULL) {
337 struct regulator *reg;
338
339 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda_hdmi_dac");
340
341 if (IS_ERR(reg)) {
342 DSSERR("can't get VDDA_HDMI_DAC regulator\n");
343 return PTR_ERR(reg);
344 }
345
346 hdmi.vdda_hdmi_dac_reg = reg;
347 }
348
cca35017
TV		 349 r = gpio_request_array(gpios, ARRAY_SIZE(gpios));
350 if (r)
351 return r;
352
c3198a5e
M		 353 return 0;
354}
355
cca35017
TV		 356static void __exit hdmi_uninit_display(struct omap_dss_device *dssdev)
357{
358 DSSDBG("uninit_display\n");
359
360 gpio_free(hdmi.ct_cp_hpd_gpio);
361 gpio_free(hdmi.ls_oe_gpio);
362 gpio_free(hdmi.hpd_gpio);
363}
364
46095b2d
M		 365static const struct hdmi_config *hdmi_find_timing(
366 const struct hdmi_config *timings_arr,
367 int len)
c3198a5e 368{
46095b2d 369 int i;
c3198a5e 370
46095b2d 371 for (i = 0; i < len; i++) {
9e4ed603 372 if (timings_arr[i].cm.code == hdmi.ip_data.cfg.cm.code)
46095b2d
M		 373 return &timings_arr[i];
374 }
375 return NULL;
376}
c3198a5e 377
46095b2d
M		 378static const struct hdmi_config *hdmi_get_timings(void)
379{
380 const struct hdmi_config *arr;
381 int len;
382
9e4ed603 383 if (hdmi.ip_data.cfg.cm.mode == HDMI_DVI) {
46095b2d
M		 384 arr = vesa_timings;
385 len = ARRAY_SIZE(vesa_timings);
386 } else {
387 arr = cea_timings;
388 len = ARRAY_SIZE(cea_timings);
389 }
390
391 return hdmi_find_timing(arr, len);
392}
393
394static bool hdmi_timings_compare(struct omap_video_timings *timing1,
cc937e5e 395 const struct omap_video_timings *timing2)
46095b2d
M		 396{
397 int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync;
398
399 if ((timing2->pixel_clock == timing1->pixel_clock) &&
400 (timing2->x_res == timing1->x_res) &&
401 (timing2->y_res == timing1->y_res)) {
c3198a5e 402
46095b2d
M		 403 timing2_hsync = timing2->hfp + timing2->hsw + timing2->hbp;
404 timing1_hsync = timing1->hfp + timing1->hsw + timing1->hbp;
405 timing2_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
406 timing1_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
407
408 DSSDBG("timing1_hsync = %d timing1_vsync = %d"\
409 "timing2_hsync = %d timing2_vsync = %d\n",
410 timing1_hsync, timing1_vsync,
411 timing2_hsync, timing2_vsync);
412
413 if ((timing1_hsync == timing2_hsync) &&
414 (timing1_vsync == timing2_vsync)) {
415 return true;
416 }
c3198a5e 417 }
46095b2d 418 return false;
c3198a5e
M		 419}
420
421static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing)
422{
46095b2d 423 int i;
c3198a5e
M		 424 struct hdmi_cm cm = {-1};
425 DSSDBG("hdmi_get_code\n");
426
46095b2d
M		 427 for (i = 0; i < ARRAY_SIZE(cea_timings); i++) {
428 if (hdmi_timings_compare(timing, &cea_timings[i].timings)) {
429 cm = cea_timings[i].cm;
430 goto end;
431 }
432 }
433 for (i = 0; i < ARRAY_SIZE(vesa_timings); i++) {
434 if (hdmi_timings_compare(timing, &vesa_timings[i].timings)) {
435 cm = vesa_timings[i].cm;
436 goto end;
c3198a5e
M		 437 }
438 }
439
46095b2d 440end: return cm;
c3198a5e 441
c3198a5e
M		 442}
443
c3dc6a7a
AT		 444unsigned long hdmi_get_pixel_clock(void)
445{
446 /* HDMI Pixel Clock in Mhz */
a05ce78f 447 return hdmi.ip_data.cfg.timings.pixel_clock * 1000;
c3dc6a7a
AT		 448}
449
6cb07b25
AT		 450static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
451 struct hdmi_pll_info *pi)
c3198a5e 452{
6cb07b25 453 unsigned long clkin, refclk;
c3198a5e
M		 454 u32 mf;
455
4fbafaf3 456 clkin = clk_get_rate(hdmi.sys_clk) / 10000;
c3198a5e
M		 457 /*
458 * Input clock is predivided by N + 1
459 * out put of which is reference clk
460 */
8d88767a
TV		 461 if (dssdev->clocks.hdmi.regn == 0)
462 pi->regn = HDMI_DEFAULT_REGN;
463 else
464 pi->regn = dssdev->clocks.hdmi.regn;
465
b44e4582 466 refclk = clkin / pi->regn;
c3198a5e 467
8d88767a
TV		 468 if (dssdev->clocks.hdmi.regm2 == 0)
469 pi->regm2 = HDMI_DEFAULT_REGM2;
470 else
471 pi->regm2 = dssdev->clocks.hdmi.regm2;
c3198a5e 472
dd2116a3
M		 473 /*
474 * multiplier is pixel_clk/ref_clk
475 * Multiplying by 100 to avoid fractional part removal
476 */
477 pi->regm = phy * pi->regm2 / refclk;
478
c3198a5e
M		 479 /*
480 * fractional multiplier is remainder of the difference between
481 * multiplier and actual phy(required pixel clock thus should be
482 * multiplied by 2^18(262144) divided by the reference clock
483 */
dd2116a3
M		 484 mf = (phy - pi->regm / pi->regm2 * refclk) * 262144;
485 pi->regmf = pi->regm2 * mf / refclk;
c3198a5e
M		 486
487 /*
488 * Dcofreq should be set to 1 if required pixel clock
489 * is greater than 1000MHz
490 */
491 pi->dcofreq = phy > 1000 * 100;
b44e4582 492 pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10;
c3198a5e 493
7b27da54
M		 494 /* Set the reference clock to sysclk reference */
495 pi->refsel = HDMI_REFSEL_SYSCLK;
496
c3198a5e
M		 497 DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
498 DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
499}
500
c3198a5e
M		 501static int hdmi_power_on(struct omap_dss_device *dssdev)
502{
46095b2d 503 int r;
c3198a5e 504 struct omap_video_timings *p;
6cb07b25 505 unsigned long phy;
c3198a5e 506
cca35017
TV		 507 gpio_set_value(hdmi.ct_cp_hpd_gpio, 1);
508 gpio_set_value(hdmi.ls_oe_gpio, 1);
509
a84b2065
TV		 510 /* wait 300us after CT_CP_HPD for the 5V power output to reach 90% */
511 udelay(300);
512
17486943
TV		 513 r = regulator_enable(hdmi.vdda_hdmi_dac_reg);
514 if (r)
515 goto err_vdac_enable;
516
4fbafaf3
TV		 517 r = hdmi_runtime_get();
518 if (r)
cca35017 519 goto err_runtime_get;
c3198a5e 520
7797c6da 521 dss_mgr_disable(dssdev->manager);
c3198a5e 522
7849398f 523 p = &hdmi.ip_data.cfg.timings;
c3198a5e 524
7849398f 525 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
c3198a5e 526
c3198a5e
M		 527 phy = p->pixel_clock;
528
7b27da54 529 hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data);
c3198a5e 530
c0456be3 531 hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
c3198a5e 532
95a8aeb6 533 /* config the PLL and PHY hdmi_set_pll_pwrfirst */
60634a28 534 r = hdmi.ip_data.ops->pll_enable(&hdmi.ip_data);
c3198a5e
M		 535 if (r) {
536 DSSDBG("Failed to lock PLL\n");
cca35017 537 goto err_pll_enable;
c3198a5e
M		 538 }
539
60634a28 540 r = hdmi.ip_data.ops->phy_enable(&hdmi.ip_data);
c3198a5e
M		 541 if (r) {
542 DSSDBG("Failed to start PHY\n");
d3b4aa51 543 goto err_phy_enable;
c3198a5e
M		 544 }
545
60634a28 546 hdmi.ip_data.ops->video_configure(&hdmi.ip_data);
c3198a5e
M		 547
548 /* Make selection of HDMI in DSS */
549 dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
550
551 /* Select the dispc clock source as PRCM clock, to ensure that it is not
552 * DSI PLL source as the clock selected by DSI PLL might not be
553 * sufficient for the resolution selected / that can be changed
554 * dynamically by user. This can be moved to single location , say
555 * Boardfile.
556 */
6cb07b25 557 dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
c3198a5e
M		 558
559 /* bypass TV gamma table */
560 dispc_enable_gamma_table(0);
561
562 /* tv size */
7849398f 563 dss_mgr_set_timings(dssdev->manager, p);
c3198a5e 564
c0456be3
RN		 565 r = hdmi.ip_data.ops->video_enable(&hdmi.ip_data);
566 if (r)
567 goto err_vid_enable;
c3198a5e 568
33ca237f
TV		 569 r = dss_mgr_enable(dssdev->manager);
570 if (r)
571 goto err_mgr_enable;
3870c909 572
c3198a5e 573 return 0;
33ca237f
TV		 574
575err_mgr_enable:
c0456be3
RN		 576 hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
577err_vid_enable:
33ca237f 578 hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
d3b4aa51 579err_phy_enable:
33ca237f 580 hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
cca35017 581err_pll_enable:
4fbafaf3 582 hdmi_runtime_put();
cca35017 583err_runtime_get:
17486943
TV		 584 regulator_disable(hdmi.vdda_hdmi_dac_reg);
585err_vdac_enable:
cca35017
TV		 586 gpio_set_value(hdmi.ct_cp_hpd_gpio, 0);
587 gpio_set_value(hdmi.ls_oe_gpio, 0);
c3198a5e
M		 588 return -EIO;
589}
590
591static void hdmi_power_off(struct omap_dss_device *dssdev)
592{
7797c6da 593 dss_mgr_disable(dssdev->manager);
c3198a5e 594
c0456be3 595 hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
60634a28
M		 596 hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
597 hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
4fbafaf3 598 hdmi_runtime_put();
cca35017 599
17486943
TV		 600 regulator_disable(hdmi.vdda_hdmi_dac_reg);
601
cca35017
TV		 602 gpio_set_value(hdmi.ct_cp_hpd_gpio, 0);
603 gpio_set_value(hdmi.ls_oe_gpio, 0);
c3198a5e
M		 604}
605
606int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
607 struct omap_video_timings *timings)
608{
609 struct hdmi_cm cm;
610
611 cm = hdmi_get_code(timings);
612 if (cm.code == -1) {
c3198a5e
M		 613 return -EINVAL;
614 }
615
616 return 0;
617
618}
619
7849398f
AT		 620void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev,
621 struct omap_video_timings *timings)
c3198a5e
M		 622{
623 struct hdmi_cm cm;
7849398f 624 const struct hdmi_config *t;
c3198a5e 625
ed1aa900
AT		 626 mutex_lock(&hdmi.lock);
627
7849398f
AT		 628 cm = hdmi_get_code(timings);
629 hdmi.ip_data.cfg.cm = cm;
630
631 t = hdmi_get_timings();
632 if (t != NULL)
633 hdmi.ip_data.cfg = *t;
fa70dc5f 634
ed1aa900 635 mutex_unlock(&hdmi.lock);
c3198a5e
M		 636}
637
e40402cf 638static void hdmi_dump_regs(struct seq_file *s)
162874d5
M		 639{
640 mutex_lock(&hdmi.lock);
641
642 if (hdmi_runtime_get())
643 return;
644
645 hdmi.ip_data.ops->dump_wrapper(&hdmi.ip_data, s);
646 hdmi.ip_data.ops->dump_pll(&hdmi.ip_data, s);
647 hdmi.ip_data.ops->dump_phy(&hdmi.ip_data, s);
648 hdmi.ip_data.ops->dump_core(&hdmi.ip_data, s);
649
650 hdmi_runtime_put();
651 mutex_unlock(&hdmi.lock);
652}
653
47024565
TV		 654int omapdss_hdmi_read_edid(u8 *buf, int len)
655{
656 int r;
657
658 mutex_lock(&hdmi.lock);
659
660 r = hdmi_runtime_get();
661 BUG_ON(r);
662
663 r = hdmi.ip_data.ops->read_edid(&hdmi.ip_data, buf, len);
664
665 hdmi_runtime_put();
666 mutex_unlock(&hdmi.lock);
667
668 return r;
669}
670
759593ff
TV		 671bool omapdss_hdmi_detect(void)
672{
673 int r;
674
675 mutex_lock(&hdmi.lock);
676
677 r = hdmi_runtime_get();
678 BUG_ON(r);
679
680 r = hdmi.ip_data.ops->detect(&hdmi.ip_data);
681
682 hdmi_runtime_put();
683 mutex_unlock(&hdmi.lock);
684
685 return r == 1;
686}
687
c3198a5e
M		 688int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev)
689{
690 int r = 0;
691
692 DSSDBG("ENTER hdmi_display_enable\n");
693
694 mutex_lock(&hdmi.lock);
695
05e1d606
TV		 696 if (dssdev->manager == NULL) {
697 DSSERR("failed to enable display: no manager\n");
698 r = -ENODEV;
699 goto err0;
700 }
701
cca35017 702 hdmi.ip_data.hpd_gpio = hdmi.hpd_gpio;
c49d005b 703
c3198a5e
M		 704 r = omap_dss_start_device(dssdev);
705 if (r) {
706 DSSERR("failed to start device\n");
707 goto err0;
708 }
709
c3198a5e
M		 710 r = hdmi_power_on(dssdev);
711 if (r) {
712 DSSERR("failed to power on device\n");
cca35017 713 goto err1;
c3198a5e
M		 714 }
715
716 mutex_unlock(&hdmi.lock);
717 return 0;
718
c3198a5e
M		 719err1:
720 omap_dss_stop_device(dssdev);
721err0:
722 mutex_unlock(&hdmi.lock);
723 return r;
724}
725
726void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev)
727{
728 DSSDBG("Enter hdmi_display_disable\n");
729
730 mutex_lock(&hdmi.lock);
731
732 hdmi_power_off(dssdev);
733
c3198a5e
M		 734 omap_dss_stop_device(dssdev);
735
736 mutex_unlock(&hdmi.lock);
737}
738
4fbafaf3
TV		 739static int hdmi_get_clocks(struct platform_device *pdev)
740{
741 struct clk *clk;
742
743 clk = clk_get(&pdev->dev, "sys_clk");
744 if (IS_ERR(clk)) {
745 DSSERR("can't get sys_clk\n");
746 return PTR_ERR(clk);
747 }
748
749 hdmi.sys_clk = clk;
750
4fbafaf3
TV		 751 return 0;
752}
753
754static void hdmi_put_clocks(void)
755{
756 if (hdmi.sys_clk)
757 clk_put(hdmi.sys_clk);
4fbafaf3
TV		 758}
759
35547626
RN		 760#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
761int hdmi_compute_acr(u32 sample_freq, u32 *n, u32 *cts)
762{
763 u32 deep_color;
25a65359 764 bool deep_color_correct = false;
35547626
RN		 765 u32 pclk = hdmi.ip_data.cfg.timings.pixel_clock;
766
767 if (n == NULL || cts == NULL)
768 return -EINVAL;
769
770 /* TODO: When implemented, query deep color mode here. */
771 deep_color = 100;
772
25a65359
RN		 773 /*
774 * When using deep color, the default N value (as in the HDMI
775 * specification) yields to an non-integer CTS. Hence, we
776 * modify it while keeping the restrictions described in
777 * section 7.2.1 of the HDMI 1.4a specification.
778 */
35547626
RN		 779 switch (sample_freq) {
780 case 32000:
25a65359
RN		 781 case 48000:
782 case 96000:
783 case 192000:
784 if (deep_color == 125)
785 if (pclk == 27027 || pclk == 74250)
786 deep_color_correct = true;
787 if (deep_color == 150)
788 if (pclk == 27027)
789 deep_color_correct = true;
35547626
RN		 790 break;
791 case 44100:
25a65359
RN		 792 case 88200:
793 case 176400:
794 if (deep_color == 125)
795 if (pclk == 27027)
796 deep_color_correct = true;
35547626
RN		 797 break;
798 default:
35547626
RN		 799 return -EINVAL;
800 }
801
25a65359
RN		 802 if (deep_color_correct) {
803 switch (sample_freq) {
804 case 32000:
805 *n = 8192;
806 break;
807 case 44100:
808 *n = 12544;
809 break;
810 case 48000:
811 *n = 8192;
812 break;
813 case 88200:
814 *n = 25088;
815 break;
816 case 96000:
817 *n = 16384;
818 break;
819 case 176400:
820 *n = 50176;
821 break;
822 case 192000:
823 *n = 32768;
824 break;
825 default:
826 return -EINVAL;
827 }
828 } else {
829 switch (sample_freq) {
830 case 32000:
831 *n = 4096;
832 break;
833 case 44100:
834 *n = 6272;
835 break;
836 case 48000:
837 *n = 6144;
838 break;
839 case 88200:
840 *n = 12544;
841 break;
842 case 96000:
843 *n = 12288;
844 break;
845 case 176400:
846 *n = 25088;
847 break;
848 case 192000:
849 *n = 24576;
850 break;
851 default:
852 return -EINVAL;
853 }
854 }
35547626
RN		 855 /* Calculate CTS. See HDMI 1.3a or 1.4a specifications */
856 *cts = pclk * (*n / 128) * deep_color / (sample_freq / 10);
857
858 return 0;
859}
f3a97491
RN		 860
861int hdmi_audio_enable(void)
862{
863 DSSDBG("audio_enable\n");
864
865 return hdmi.ip_data.ops->audio_enable(&hdmi.ip_data);
866}
867
868void hdmi_audio_disable(void)
869{
870 DSSDBG("audio_disable\n");
871
872 hdmi.ip_data.ops->audio_disable(&hdmi.ip_data);
873}
874
875int hdmi_audio_start(void)
876{
877 DSSDBG("audio_start\n");
878
879 return hdmi.ip_data.ops->audio_start(&hdmi.ip_data);
880}
881
882void hdmi_audio_stop(void)
883{
884 DSSDBG("audio_stop\n");
885
886 hdmi.ip_data.ops->audio_stop(&hdmi.ip_data);
887}
888
889bool hdmi_mode_has_audio(void)
890{
891 if (hdmi.ip_data.cfg.cm.mode == HDMI_HDMI)
892 return true;
893 else
894 return false;
895}
896
897int hdmi_audio_config(struct omap_dss_audio *audio)
898{
899 return hdmi.ip_data.ops->audio_config(&hdmi.ip_data, audio);
900}
901
35547626
RN		 902#endif
903
38f3daf6
TV		 904static void __init hdmi_probe_pdata(struct platform_device *pdev)
905{
906 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
907 int r, i;
908
909 for (i = 0; i < pdata->num_devices; ++i) {
910 struct omap_dss_device *dssdev = pdata->devices[i];
cca35017 911 struct omap_dss_hdmi_data *priv = dssdev->data;
38f3daf6
TV		 912
913 if (dssdev->type != OMAP_DISPLAY_TYPE_HDMI)
914 continue;
915
cca35017
TV		 916 hdmi.ct_cp_hpd_gpio = priv->ct_cp_hpd_gpio;
917 hdmi.ls_oe_gpio = priv->ls_oe_gpio;
918 hdmi.hpd_gpio = priv->hpd_gpio;
919
38f3daf6
TV		 920 r = hdmi_init_display(dssdev);
921 if (r) {
922 DSSERR("device %s init failed: %d\n", dssdev->name, r);
923 continue;
924 }
925
8768a52f 926 r = omap_dss_register_device(dssdev, &pdev->dev);
38f3daf6
TV		 927 if (r)
928 DSSERR("device %s register failed: %d\n",
929 dssdev->name, r);
930 }
931}
932
c3198a5e 933/* HDMI HW IP initialisation */
6e7e8f06 934static int __init omapdss_hdmihw_probe(struct platform_device *pdev)
c3198a5e
M		 935{
936 struct resource *hdmi_mem;
38f3daf6 937 int r;
c3198a5e 938
c3198a5e
M		 939 hdmi.pdev = pdev;
940
941 mutex_init(&hdmi.lock);
942
943 hdmi_mem = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0);
944 if (!hdmi_mem) {
945 DSSERR("can't get IORESOURCE_MEM HDMI\n");
946 return -EINVAL;
947 }
948
949 /* Base address taken from platform */
95a8aeb6
M		 950 hdmi.ip_data.base_wp = ioremap(hdmi_mem->start,
951 resource_size(hdmi_mem));
952 if (!hdmi.ip_data.base_wp) {
c3198a5e
M		 953 DSSERR("can't ioremap WP\n");
954 return -ENOMEM;
955 }
956
4fbafaf3
TV		 957 r = hdmi_get_clocks(pdev);
958 if (r) {
95a8aeb6 959 iounmap(hdmi.ip_data.base_wp);
4fbafaf3
TV		 960 return r;
961 }
962
963 pm_runtime_enable(&pdev->dev);
964
95a8aeb6
M		 965 hdmi.ip_data.core_sys_offset = HDMI_CORE_SYS;
966 hdmi.ip_data.core_av_offset = HDMI_CORE_AV;
967 hdmi.ip_data.pll_offset = HDMI_PLLCTRL;
968 hdmi.ip_data.phy_offset = HDMI_PHY;
7849398f 969
3a5383a2 970 mutex_init(&hdmi.ip_data.lock);
95a8aeb6 971
c3198a5e
M		 972 hdmi_panel_init();
973
e40402cf
TV		 974 dss_debugfs_create_file("hdmi", hdmi_dump_regs);
975
38f3daf6 976 hdmi_probe_pdata(pdev);
35deca3d 977
c3198a5e
M		 978 return 0;
979}
980
cca35017
TV		 981static int __exit hdmi_remove_child(struct device *dev, void *data)
982{
983 struct omap_dss_device *dssdev = to_dss_device(dev);
984 hdmi_uninit_display(dssdev);
985 return 0;
986}
987
6e7e8f06 988static int __exit omapdss_hdmihw_remove(struct platform_device *pdev)
c3198a5e 989{
cca35017
TV		 990 device_for_each_child(&pdev->dev, NULL, hdmi_remove_child);
991
35deca3d
TV		 992 omap_dss_unregister_child_devices(&pdev->dev);
993
c3198a5e
M		 994 hdmi_panel_exit();
995
4fbafaf3
TV		 996 pm_runtime_disable(&pdev->dev);
997
998 hdmi_put_clocks();
999
95a8aeb6 1000 iounmap(hdmi.ip_data.base_wp);
c3198a5e
M		 1001
1002 return 0;
1003}
1004
4fbafaf3
TV		 1005static int hdmi_runtime_suspend(struct device *dev)
1006{
f11766d1 1007 clk_disable_unprepare(hdmi.sys_clk);
4fbafaf3
TV		 1008
1009 dispc_runtime_put();
4fbafaf3
TV		 1010
1011 return 0;
1012}
1013
1014static int hdmi_runtime_resume(struct device *dev)
1015{
1016 int r;
1017
4fbafaf3
TV		 1018 r = dispc_runtime_get();
1019 if (r < 0)
852f0838 1020 return r;
4fbafaf3 1021
f11766d1 1022 clk_prepare_enable(hdmi.sys_clk);
4fbafaf3
TV		 1023
1024 return 0;
4fbafaf3
TV		 1025}
1026
1027static const struct dev_pm_ops hdmi_pm_ops = {
1028 .runtime_suspend = hdmi_runtime_suspend,
1029 .runtime_resume = hdmi_runtime_resume,
1030};
1031
c3198a5e 1032static struct platform_driver omapdss_hdmihw_driver = {
6e7e8f06 1033 .remove = __exit_p(omapdss_hdmihw_remove),
c3198a5e
M		 1034 .driver = {
1035 .name = "omapdss_hdmi",
1036 .owner = THIS_MODULE,
4fbafaf3 1037 .pm = &hdmi_pm_ops,
c3198a5e
M		 1038 },
1039};
1040
6e7e8f06 1041int __init hdmi_init_platform_driver(void)
c3198a5e 1042{
61055d4b 1043 return platform_driver_probe(&omapdss_hdmihw_driver, omapdss_hdmihw_probe);
c3198a5e
M		 1044}
1045
6e7e8f06 1046void __exit hdmi_uninit_platform_driver(void)
c3198a5e 1047{
04c742c3 1048 platform_driver_unregister(&omapdss_hdmihw_driver);
c3198a5e 1049}
Linux kernel - Deliverables
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