Commit | Line | Data |
---|---|---|
c3198a5e M |
1 | /* |
2 | * hdmi.c | |
3 | * | |
4 | * HDMI interface DSS driver setting for TI's OMAP4 family of processor. | |
5 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ | |
6 | * Authors: Yong Zhi | |
7 | * Mythri pk <mythripk@ti.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License version 2 as published by | |
11 | * the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along with | |
19 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #define DSS_SUBSYS_NAME "HDMI" | |
23 | ||
24 | #include <linux/kernel.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/err.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/mutex.h> | |
30 | #include <linux/delay.h> | |
31 | #include <linux/string.h> | |
24e6289c | 32 | #include <linux/platform_device.h> |
4fbafaf3 TV |
33 | #include <linux/pm_runtime.h> |
34 | #include <linux/clk.h> | |
cca35017 | 35 | #include <linux/gpio.h> |
17486943 | 36 | #include <linux/regulator/consumer.h> |
a0b38cc4 | 37 | #include <video/omapdss.h> |
c3198a5e | 38 | |
94c52987 | 39 | #include "ti_hdmi.h" |
c3198a5e | 40 | #include "dss.h" |
ad44cc32 | 41 | #include "dss_features.h" |
c3198a5e | 42 | |
95a8aeb6 M |
43 | #define HDMI_WP 0x0 |
44 | #define HDMI_CORE_SYS 0x400 | |
45 | #define HDMI_CORE_AV 0x900 | |
46 | #define HDMI_PLLCTRL 0x200 | |
47 | #define HDMI_PHY 0x300 | |
48 | ||
7c1f1eca M |
49 | /* HDMI EDID Length move this */ |
50 | #define HDMI_EDID_MAX_LENGTH 256 | |
51 | #define EDID_TIMING_DESCRIPTOR_SIZE 0x12 | |
52 | #define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36 | |
53 | #define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80 | |
54 | #define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4 | |
55 | #define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4 | |
56 | ||
b44e4582 | 57 | #define HDMI_DEFAULT_REGN 16 |
8d88767a TV |
58 | #define HDMI_DEFAULT_REGM2 1 |
59 | ||
c3198a5e M |
60 | static struct { |
61 | struct mutex lock; | |
c3198a5e | 62 | struct platform_device *pdev; |
66a06b0c | 63 | |
95a8aeb6 | 64 | struct hdmi_ip_data ip_data; |
4fbafaf3 TV |
65 | |
66 | struct clk *sys_clk; | |
17486943 | 67 | struct regulator *vdda_hdmi_dac_reg; |
cca35017 | 68 | |
0b450c31 TV |
69 | bool core_enabled; |
70 | ||
1f68d9c4 | 71 | struct omap_dss_device output; |
c3198a5e M |
72 | } hdmi; |
73 | ||
74 | /* | |
75 | * Logic for the below structure : | |
76 | * user enters the CEA or VESA timings by specifying the HDMI/DVI code. | |
77 | * There is a correspondence between CEA/VESA timing and code, please | |
78 | * refer to section 6.3 in HDMI 1.3 specification for timing code. | |
79 | * | |
80 | * In the below structure, cea_vesa_timings corresponds to all OMAP4 | |
81 | * supported CEA and VESA timing values.code_cea corresponds to the CEA | |
82 | * code, It is used to get the timing from cea_vesa_timing array.Similarly | |
83 | * with code_vesa. Code_index is used for back mapping, that is once EDID | |
84 | * is read from the TV, EDID is parsed to find the timing values and then | |
85 | * map it to corresponding CEA or VESA index. | |
86 | */ | |
87 | ||
46095b2d | 88 | static const struct hdmi_config cea_timings[] = { |
cc937e5e AT |
89 | { |
90 | { 640, 480, 25200, 96, 16, 48, 2, 10, 33, | |
91 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
92 | false, }, | |
93 | { 1, HDMI_HDMI }, | |
94 | }, | |
95 | { | |
96 | { 720, 480, 27027, 62, 16, 60, 6, 9, 30, | |
97 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
98 | false, }, | |
99 | { 2, HDMI_HDMI }, | |
100 | }, | |
101 | { | |
102 | { 1280, 720, 74250, 40, 110, 220, 5, 5, 20, | |
103 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
104 | false, }, | |
105 | { 4, HDMI_HDMI }, | |
106 | }, | |
107 | { | |
108 | { 1920, 540, 74250, 44, 88, 148, 5, 2, 15, | |
109 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
110 | true, }, | |
111 | { 5, HDMI_HDMI }, | |
112 | }, | |
113 | { | |
114 | { 1440, 240, 27027, 124, 38, 114, 3, 4, 15, | |
115 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
116 | true, }, | |
117 | { 6, HDMI_HDMI }, | |
118 | }, | |
119 | { | |
120 | { 1920, 1080, 148500, 44, 88, 148, 5, 4, 36, | |
121 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
122 | false, }, | |
123 | { 16, HDMI_HDMI }, | |
124 | }, | |
125 | { | |
126 | { 720, 576, 27000, 64, 12, 68, 5, 5, 39, | |
127 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
128 | false, }, | |
129 | { 17, HDMI_HDMI }, | |
130 | }, | |
131 | { | |
132 | { 1280, 720, 74250, 40, 440, 220, 5, 5, 20, | |
133 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
134 | false, }, | |
135 | { 19, HDMI_HDMI }, | |
136 | }, | |
137 | { | |
138 | { 1920, 540, 74250, 44, 528, 148, 5, 2, 15, | |
139 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
140 | true, }, | |
141 | { 20, HDMI_HDMI }, | |
142 | }, | |
143 | { | |
144 | { 1440, 288, 27000, 126, 24, 138, 3, 2, 19, | |
145 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
146 | true, }, | |
147 | { 21, HDMI_HDMI }, | |
148 | }, | |
149 | { | |
150 | { 1440, 576, 54000, 128, 24, 136, 5, 5, 39, | |
151 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
152 | false, }, | |
153 | { 29, HDMI_HDMI }, | |
154 | }, | |
155 | { | |
156 | { 1920, 1080, 148500, 44, 528, 148, 5, 4, 36, | |
157 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
158 | false, }, | |
159 | { 31, HDMI_HDMI }, | |
160 | }, | |
161 | { | |
162 | { 1920, 1080, 74250, 44, 638, 148, 5, 4, 36, | |
163 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
164 | false, }, | |
165 | { 32, HDMI_HDMI }, | |
166 | }, | |
167 | { | |
168 | { 2880, 480, 108108, 248, 64, 240, 6, 9, 30, | |
169 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
170 | false, }, | |
171 | { 35, HDMI_HDMI }, | |
172 | }, | |
173 | { | |
174 | { 2880, 576, 108000, 256, 48, 272, 5, 5, 39, | |
175 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
176 | false, }, | |
177 | { 37, HDMI_HDMI }, | |
178 | }, | |
46095b2d | 179 | }; |
cc937e5e | 180 | |
46095b2d | 181 | static const struct hdmi_config vesa_timings[] = { |
a05ce78f | 182 | /* VESA From Here */ |
cc937e5e AT |
183 | { |
184 | { 640, 480, 25175, 96, 16, 48, 2, 11, 31, | |
185 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
186 | false, }, | |
187 | { 4, HDMI_DVI }, | |
188 | }, | |
189 | { | |
190 | { 800, 600, 40000, 128, 40, 88, 4, 1, 23, | |
191 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
192 | false, }, | |
193 | { 9, HDMI_DVI }, | |
194 | }, | |
195 | { | |
196 | { 848, 480, 33750, 112, 16, 112, 8, 6, 23, | |
197 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
198 | false, }, | |
199 | { 0xE, HDMI_DVI }, | |
200 | }, | |
201 | { | |
202 | { 1280, 768, 79500, 128, 64, 192, 7, 3, 20, | |
203 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, | |
204 | false, }, | |
205 | { 0x17, HDMI_DVI }, | |
206 | }, | |
207 | { | |
208 | { 1280, 800, 83500, 128, 72, 200, 6, 3, 22, | |
209 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, | |
210 | false, }, | |
211 | { 0x1C, HDMI_DVI }, | |
212 | }, | |
213 | { | |
214 | { 1360, 768, 85500, 112, 64, 256, 6, 3, 18, | |
215 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
216 | false, }, | |
217 | { 0x27, HDMI_DVI }, | |
218 | }, | |
219 | { | |
220 | { 1280, 960, 108000, 112, 96, 312, 3, 1, 36, | |
221 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
222 | false, }, | |
223 | { 0x20, HDMI_DVI }, | |
224 | }, | |
225 | { | |
226 | { 1280, 1024, 108000, 112, 48, 248, 3, 1, 38, | |
227 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
228 | false, }, | |
229 | { 0x23, HDMI_DVI }, | |
230 | }, | |
231 | { | |
232 | { 1024, 768, 65000, 136, 24, 160, 6, 3, 29, | |
233 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
234 | false, }, | |
235 | { 0x10, HDMI_DVI }, | |
236 | }, | |
237 | { | |
238 | { 1400, 1050, 121750, 144, 88, 232, 4, 3, 32, | |
239 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, | |
240 | false, }, | |
241 | { 0x2A, HDMI_DVI }, | |
242 | }, | |
243 | { | |
244 | { 1440, 900, 106500, 152, 80, 232, 6, 3, 25, | |
245 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, | |
246 | false, }, | |
247 | { 0x2F, HDMI_DVI }, | |
248 | }, | |
249 | { | |
250 | { 1680, 1050, 146250, 176 , 104, 280, 6, 3, 30, | |
251 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, | |
252 | false, }, | |
253 | { 0x3A, HDMI_DVI }, | |
254 | }, | |
255 | { | |
256 | { 1366, 768, 85500, 143, 70, 213, 3, 3, 24, | |
257 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
258 | false, }, | |
259 | { 0x51, HDMI_DVI }, | |
260 | }, | |
261 | { | |
262 | { 1920, 1080, 148500, 44, 148, 80, 5, 4, 36, | |
263 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
264 | false, }, | |
265 | { 0x52, HDMI_DVI }, | |
266 | }, | |
267 | { | |
268 | { 1280, 768, 68250, 32, 48, 80, 7, 3, 12, | |
269 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, | |
270 | false, }, | |
271 | { 0x16, HDMI_DVI }, | |
272 | }, | |
273 | { | |
274 | { 1400, 1050, 101000, 32, 48, 80, 4, 3, 23, | |
275 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, | |
276 | false, }, | |
277 | { 0x29, HDMI_DVI }, | |
278 | }, | |
279 | { | |
280 | { 1680, 1050, 119000, 32, 48, 80, 6, 3, 21, | |
281 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, | |
282 | false, }, | |
283 | { 0x39, HDMI_DVI }, | |
284 | }, | |
285 | { | |
286 | { 1280, 800, 79500, 32, 48, 80, 6, 3, 14, | |
287 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, | |
288 | false, }, | |
289 | { 0x1B, HDMI_DVI }, | |
290 | }, | |
291 | { | |
292 | { 1280, 720, 74250, 40, 110, 220, 5, 5, 20, | |
293 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
294 | false, }, | |
295 | { 0x55, HDMI_DVI }, | |
296 | }, | |
7a7ce2c7 TV |
297 | { |
298 | { 1920, 1200, 154000, 32, 48, 80, 6, 3, 26, | |
299 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, | |
300 | false, }, | |
301 | { 0x44, HDMI_DVI }, | |
302 | }, | |
c3198a5e M |
303 | }; |
304 | ||
4fbafaf3 TV |
305 | static int hdmi_runtime_get(void) |
306 | { | |
307 | int r; | |
308 | ||
309 | DSSDBG("hdmi_runtime_get\n"); | |
310 | ||
311 | r = pm_runtime_get_sync(&hdmi.pdev->dev); | |
312 | WARN_ON(r < 0); | |
a247ce78 | 313 | if (r < 0) |
852f0838 | 314 | return r; |
a247ce78 AT |
315 | |
316 | return 0; | |
4fbafaf3 TV |
317 | } |
318 | ||
319 | static void hdmi_runtime_put(void) | |
320 | { | |
321 | int r; | |
322 | ||
323 | DSSDBG("hdmi_runtime_put\n"); | |
324 | ||
0eaf9f52 | 325 | r = pm_runtime_put_sync(&hdmi.pdev->dev); |
5be3aebd | 326 | WARN_ON(r < 0 && r != -ENOSYS); |
4fbafaf3 TV |
327 | } |
328 | ||
e25001d8 TV |
329 | static int hdmi_init_regulator(void) |
330 | { | |
331 | struct regulator *reg; | |
332 | ||
333 | if (hdmi.vdda_hdmi_dac_reg != NULL) | |
334 | return 0; | |
335 | ||
336 | reg = devm_regulator_get(&hdmi.pdev->dev, "vdda_hdmi_dac"); | |
337 | ||
338 | /* DT HACK: try VDAC to make omapdss work for o4 sdp/panda */ | |
339 | if (IS_ERR(reg)) | |
340 | reg = devm_regulator_get(&hdmi.pdev->dev, "VDAC"); | |
341 | ||
342 | if (IS_ERR(reg)) { | |
343 | DSSERR("can't get VDDA_HDMI_DAC regulator\n"); | |
344 | return PTR_ERR(reg); | |
345 | } | |
346 | ||
347 | hdmi.vdda_hdmi_dac_reg = reg; | |
348 | ||
349 | return 0; | |
350 | } | |
351 | ||
46095b2d M |
352 | static const struct hdmi_config *hdmi_find_timing( |
353 | const struct hdmi_config *timings_arr, | |
354 | int len) | |
c3198a5e | 355 | { |
46095b2d | 356 | int i; |
c3198a5e | 357 | |
46095b2d | 358 | for (i = 0; i < len; i++) { |
9e4ed603 | 359 | if (timings_arr[i].cm.code == hdmi.ip_data.cfg.cm.code) |
46095b2d M |
360 | return &timings_arr[i]; |
361 | } | |
362 | return NULL; | |
363 | } | |
c3198a5e | 364 | |
46095b2d M |
365 | static const struct hdmi_config *hdmi_get_timings(void) |
366 | { | |
367 | const struct hdmi_config *arr; | |
368 | int len; | |
369 | ||
9e4ed603 | 370 | if (hdmi.ip_data.cfg.cm.mode == HDMI_DVI) { |
46095b2d M |
371 | arr = vesa_timings; |
372 | len = ARRAY_SIZE(vesa_timings); | |
373 | } else { | |
374 | arr = cea_timings; | |
375 | len = ARRAY_SIZE(cea_timings); | |
376 | } | |
377 | ||
378 | return hdmi_find_timing(arr, len); | |
379 | } | |
380 | ||
381 | static bool hdmi_timings_compare(struct omap_video_timings *timing1, | |
cc937e5e | 382 | const struct omap_video_timings *timing2) |
46095b2d M |
383 | { |
384 | int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync; | |
385 | ||
f236b892 TV |
386 | if ((DIV_ROUND_CLOSEST(timing2->pixel_clock, 1000) == |
387 | DIV_ROUND_CLOSEST(timing1->pixel_clock, 1000)) && | |
46095b2d M |
388 | (timing2->x_res == timing1->x_res) && |
389 | (timing2->y_res == timing1->y_res)) { | |
c3198a5e | 390 | |
46095b2d M |
391 | timing2_hsync = timing2->hfp + timing2->hsw + timing2->hbp; |
392 | timing1_hsync = timing1->hfp + timing1->hsw + timing1->hbp; | |
393 | timing2_vsync = timing2->vfp + timing2->vsw + timing2->vbp; | |
394 | timing1_vsync = timing2->vfp + timing2->vsw + timing2->vbp; | |
395 | ||
396 | DSSDBG("timing1_hsync = %d timing1_vsync = %d"\ | |
397 | "timing2_hsync = %d timing2_vsync = %d\n", | |
398 | timing1_hsync, timing1_vsync, | |
399 | timing2_hsync, timing2_vsync); | |
400 | ||
401 | if ((timing1_hsync == timing2_hsync) && | |
402 | (timing1_vsync == timing2_vsync)) { | |
403 | return true; | |
404 | } | |
c3198a5e | 405 | } |
46095b2d | 406 | return false; |
c3198a5e M |
407 | } |
408 | ||
409 | static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing) | |
410 | { | |
46095b2d | 411 | int i; |
c3198a5e M |
412 | struct hdmi_cm cm = {-1}; |
413 | DSSDBG("hdmi_get_code\n"); | |
414 | ||
46095b2d M |
415 | for (i = 0; i < ARRAY_SIZE(cea_timings); i++) { |
416 | if (hdmi_timings_compare(timing, &cea_timings[i].timings)) { | |
417 | cm = cea_timings[i].cm; | |
418 | goto end; | |
419 | } | |
420 | } | |
421 | for (i = 0; i < ARRAY_SIZE(vesa_timings); i++) { | |
422 | if (hdmi_timings_compare(timing, &vesa_timings[i].timings)) { | |
423 | cm = vesa_timings[i].cm; | |
424 | goto end; | |
c3198a5e M |
425 | } |
426 | } | |
427 | ||
46095b2d | 428 | end: return cm; |
c3198a5e | 429 | |
c3198a5e M |
430 | } |
431 | ||
6cb07b25 AT |
432 | static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy, |
433 | struct hdmi_pll_info *pi) | |
c3198a5e | 434 | { |
6cb07b25 | 435 | unsigned long clkin, refclk; |
c3198a5e M |
436 | u32 mf; |
437 | ||
4fbafaf3 | 438 | clkin = clk_get_rate(hdmi.sys_clk) / 10000; |
c3198a5e M |
439 | /* |
440 | * Input clock is predivided by N + 1 | |
441 | * out put of which is reference clk | |
442 | */ | |
4fdfdf06 TV |
443 | |
444 | pi->regn = HDMI_DEFAULT_REGN; | |
8d88767a | 445 | |
b44e4582 | 446 | refclk = clkin / pi->regn; |
c3198a5e | 447 | |
4fdfdf06 | 448 | pi->regm2 = HDMI_DEFAULT_REGM2; |
c3198a5e | 449 | |
dd2116a3 M |
450 | /* |
451 | * multiplier is pixel_clk/ref_clk | |
452 | * Multiplying by 100 to avoid fractional part removal | |
453 | */ | |
454 | pi->regm = phy * pi->regm2 / refclk; | |
455 | ||
c3198a5e M |
456 | /* |
457 | * fractional multiplier is remainder of the difference between | |
458 | * multiplier and actual phy(required pixel clock thus should be | |
459 | * multiplied by 2^18(262144) divided by the reference clock | |
460 | */ | |
dd2116a3 M |
461 | mf = (phy - pi->regm / pi->regm2 * refclk) * 262144; |
462 | pi->regmf = pi->regm2 * mf / refclk; | |
c3198a5e M |
463 | |
464 | /* | |
465 | * Dcofreq should be set to 1 if required pixel clock | |
466 | * is greater than 1000MHz | |
467 | */ | |
468 | pi->dcofreq = phy > 1000 * 100; | |
b44e4582 | 469 | pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10; |
c3198a5e | 470 | |
7b27da54 M |
471 | /* Set the reference clock to sysclk reference */ |
472 | pi->refsel = HDMI_REFSEL_SYSCLK; | |
473 | ||
c3198a5e M |
474 | DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf); |
475 | DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd); | |
476 | } | |
477 | ||
bb426fc9 | 478 | static int hdmi_power_on_core(struct omap_dss_device *dssdev) |
c3198a5e | 479 | { |
46095b2d | 480 | int r; |
c3198a5e | 481 | |
17486943 TV |
482 | r = regulator_enable(hdmi.vdda_hdmi_dac_reg); |
483 | if (r) | |
164ebdd1 | 484 | return r; |
17486943 | 485 | |
4fbafaf3 TV |
486 | r = hdmi_runtime_get(); |
487 | if (r) | |
cca35017 | 488 | goto err_runtime_get; |
c3198a5e | 489 | |
bb426fc9 TV |
490 | /* Make selection of HDMI in DSS */ |
491 | dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK); | |
492 | ||
0b450c31 TV |
493 | hdmi.core_enabled = true; |
494 | ||
bb426fc9 TV |
495 | return 0; |
496 | ||
497 | err_runtime_get: | |
498 | regulator_disable(hdmi.vdda_hdmi_dac_reg); | |
164ebdd1 | 499 | |
bb426fc9 TV |
500 | return r; |
501 | } | |
502 | ||
503 | static void hdmi_power_off_core(struct omap_dss_device *dssdev) | |
504 | { | |
0b450c31 TV |
505 | hdmi.core_enabled = false; |
506 | ||
bb426fc9 TV |
507 | hdmi_runtime_put(); |
508 | regulator_disable(hdmi.vdda_hdmi_dac_reg); | |
bb426fc9 TV |
509 | } |
510 | ||
511 | static int hdmi_power_on_full(struct omap_dss_device *dssdev) | |
512 | { | |
513 | int r; | |
514 | struct omap_video_timings *p; | |
7ae9a71e | 515 | struct omap_overlay_manager *mgr = hdmi.output.manager; |
bb426fc9 TV |
516 | unsigned long phy; |
517 | ||
518 | r = hdmi_power_on_core(dssdev); | |
519 | if (r) | |
520 | return r; | |
521 | ||
cea87b92 | 522 | dss_mgr_disable(mgr); |
c3198a5e | 523 | |
7849398f | 524 | p = &hdmi.ip_data.cfg.timings; |
c3198a5e | 525 | |
7849398f | 526 | DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res); |
c3198a5e | 527 | |
c3198a5e M |
528 | phy = p->pixel_clock; |
529 | ||
7b27da54 | 530 | hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data); |
c3198a5e | 531 | |
c0456be3 | 532 | hdmi.ip_data.ops->video_disable(&hdmi.ip_data); |
c3198a5e | 533 | |
95a8aeb6 | 534 | /* config the PLL and PHY hdmi_set_pll_pwrfirst */ |
60634a28 | 535 | r = hdmi.ip_data.ops->pll_enable(&hdmi.ip_data); |
c3198a5e M |
536 | if (r) { |
537 | DSSDBG("Failed to lock PLL\n"); | |
cca35017 | 538 | goto err_pll_enable; |
c3198a5e M |
539 | } |
540 | ||
60634a28 | 541 | r = hdmi.ip_data.ops->phy_enable(&hdmi.ip_data); |
c3198a5e M |
542 | if (r) { |
543 | DSSDBG("Failed to start PHY\n"); | |
d3b4aa51 | 544 | goto err_phy_enable; |
c3198a5e M |
545 | } |
546 | ||
60634a28 | 547 | hdmi.ip_data.ops->video_configure(&hdmi.ip_data); |
c3198a5e | 548 | |
c3198a5e M |
549 | /* bypass TV gamma table */ |
550 | dispc_enable_gamma_table(0); | |
551 | ||
552 | /* tv size */ | |
cea87b92 | 553 | dss_mgr_set_timings(mgr, p); |
c3198a5e | 554 | |
c0456be3 RN |
555 | r = hdmi.ip_data.ops->video_enable(&hdmi.ip_data); |
556 | if (r) | |
557 | goto err_vid_enable; | |
c3198a5e | 558 | |
cea87b92 | 559 | r = dss_mgr_enable(mgr); |
33ca237f TV |
560 | if (r) |
561 | goto err_mgr_enable; | |
3870c909 | 562 | |
c3198a5e | 563 | return 0; |
33ca237f TV |
564 | |
565 | err_mgr_enable: | |
c0456be3 RN |
566 | hdmi.ip_data.ops->video_disable(&hdmi.ip_data); |
567 | err_vid_enable: | |
33ca237f | 568 | hdmi.ip_data.ops->phy_disable(&hdmi.ip_data); |
d3b4aa51 | 569 | err_phy_enable: |
33ca237f | 570 | hdmi.ip_data.ops->pll_disable(&hdmi.ip_data); |
cca35017 | 571 | err_pll_enable: |
bb426fc9 | 572 | hdmi_power_off_core(dssdev); |
c3198a5e M |
573 | return -EIO; |
574 | } | |
575 | ||
bb426fc9 | 576 | static void hdmi_power_off_full(struct omap_dss_device *dssdev) |
c3198a5e | 577 | { |
7ae9a71e | 578 | struct omap_overlay_manager *mgr = hdmi.output.manager; |
cea87b92 AT |
579 | |
580 | dss_mgr_disable(mgr); | |
c3198a5e | 581 | |
c0456be3 | 582 | hdmi.ip_data.ops->video_disable(&hdmi.ip_data); |
60634a28 M |
583 | hdmi.ip_data.ops->phy_disable(&hdmi.ip_data); |
584 | hdmi.ip_data.ops->pll_disable(&hdmi.ip_data); | |
17486943 | 585 | |
bb426fc9 | 586 | hdmi_power_off_core(dssdev); |
c3198a5e M |
587 | } |
588 | ||
164ebdd1 | 589 | static int hdmi_display_check_timing(struct omap_dss_device *dssdev, |
c3198a5e M |
590 | struct omap_video_timings *timings) |
591 | { | |
592 | struct hdmi_cm cm; | |
593 | ||
594 | cm = hdmi_get_code(timings); | |
595 | if (cm.code == -1) { | |
c3198a5e M |
596 | return -EINVAL; |
597 | } | |
598 | ||
599 | return 0; | |
600 | ||
601 | } | |
602 | ||
164ebdd1 | 603 | static void hdmi_display_set_timing(struct omap_dss_device *dssdev, |
7849398f | 604 | struct omap_video_timings *timings) |
c3198a5e M |
605 | { |
606 | struct hdmi_cm cm; | |
7849398f | 607 | const struct hdmi_config *t; |
c3198a5e | 608 | |
ed1aa900 AT |
609 | mutex_lock(&hdmi.lock); |
610 | ||
7849398f AT |
611 | cm = hdmi_get_code(timings); |
612 | hdmi.ip_data.cfg.cm = cm; | |
613 | ||
614 | t = hdmi_get_timings(); | |
615 | if (t != NULL) | |
616 | hdmi.ip_data.cfg = *t; | |
fa70dc5f | 617 | |
5391e87d TV |
618 | dispc_set_tv_pclk(t->timings.pixel_clock * 1000); |
619 | ||
ed1aa900 | 620 | mutex_unlock(&hdmi.lock); |
c3198a5e M |
621 | } |
622 | ||
164ebdd1 | 623 | static void hdmi_display_get_timings(struct omap_dss_device *dssdev, |
0b450c31 TV |
624 | struct omap_video_timings *timings) |
625 | { | |
626 | const struct hdmi_config *cfg; | |
627 | ||
628 | cfg = hdmi_get_timings(); | |
629 | if (cfg == NULL) | |
630 | cfg = &vesa_timings[0]; | |
631 | ||
632 | memcpy(timings, &cfg->timings, sizeof(cfg->timings)); | |
633 | } | |
634 | ||
e40402cf | 635 | static void hdmi_dump_regs(struct seq_file *s) |
162874d5 M |
636 | { |
637 | mutex_lock(&hdmi.lock); | |
638 | ||
f8fb7d7b WY |
639 | if (hdmi_runtime_get()) { |
640 | mutex_unlock(&hdmi.lock); | |
162874d5 | 641 | return; |
f8fb7d7b | 642 | } |
162874d5 M |
643 | |
644 | hdmi.ip_data.ops->dump_wrapper(&hdmi.ip_data, s); | |
645 | hdmi.ip_data.ops->dump_pll(&hdmi.ip_data, s); | |
646 | hdmi.ip_data.ops->dump_phy(&hdmi.ip_data, s); | |
647 | hdmi.ip_data.ops->dump_core(&hdmi.ip_data, s); | |
648 | ||
649 | hdmi_runtime_put(); | |
650 | mutex_unlock(&hdmi.lock); | |
651 | } | |
652 | ||
164ebdd1 | 653 | static int read_edid(u8 *buf, int len) |
47024565 TV |
654 | { |
655 | int r; | |
656 | ||
657 | mutex_lock(&hdmi.lock); | |
658 | ||
659 | r = hdmi_runtime_get(); | |
660 | BUG_ON(r); | |
661 | ||
662 | r = hdmi.ip_data.ops->read_edid(&hdmi.ip_data, buf, len); | |
663 | ||
664 | hdmi_runtime_put(); | |
665 | mutex_unlock(&hdmi.lock); | |
666 | ||
667 | return r; | |
668 | } | |
669 | ||
164ebdd1 | 670 | static int hdmi_display_enable(struct omap_dss_device *dssdev) |
c3198a5e | 671 | { |
1f68d9c4 | 672 | struct omap_dss_device *out = &hdmi.output; |
c3198a5e M |
673 | int r = 0; |
674 | ||
675 | DSSDBG("ENTER hdmi_display_enable\n"); | |
676 | ||
677 | mutex_lock(&hdmi.lock); | |
678 | ||
cea87b92 AT |
679 | if (out == NULL || out->manager == NULL) { |
680 | DSSERR("failed to enable display: no output/manager\n"); | |
05e1d606 TV |
681 | r = -ENODEV; |
682 | goto err0; | |
683 | } | |
684 | ||
bb426fc9 | 685 | r = hdmi_power_on_full(dssdev); |
c3198a5e M |
686 | if (r) { |
687 | DSSERR("failed to power on device\n"); | |
d3923933 | 688 | goto err0; |
c3198a5e M |
689 | } |
690 | ||
691 | mutex_unlock(&hdmi.lock); | |
692 | return 0; | |
693 | ||
c3198a5e M |
694 | err0: |
695 | mutex_unlock(&hdmi.lock); | |
696 | return r; | |
697 | } | |
698 | ||
164ebdd1 | 699 | static void hdmi_display_disable(struct omap_dss_device *dssdev) |
c3198a5e M |
700 | { |
701 | DSSDBG("Enter hdmi_display_disable\n"); | |
702 | ||
703 | mutex_lock(&hdmi.lock); | |
704 | ||
bb426fc9 | 705 | hdmi_power_off_full(dssdev); |
c3198a5e | 706 | |
c3198a5e M |
707 | mutex_unlock(&hdmi.lock); |
708 | } | |
709 | ||
164ebdd1 | 710 | static int hdmi_core_enable(struct omap_dss_device *dssdev) |
4489823c TV |
711 | { |
712 | int r = 0; | |
713 | ||
714 | DSSDBG("ENTER omapdss_hdmi_core_enable\n"); | |
715 | ||
716 | mutex_lock(&hdmi.lock); | |
717 | ||
4489823c TV |
718 | r = hdmi_power_on_core(dssdev); |
719 | if (r) { | |
720 | DSSERR("failed to power on device\n"); | |
721 | goto err0; | |
722 | } | |
723 | ||
724 | mutex_unlock(&hdmi.lock); | |
725 | return 0; | |
726 | ||
727 | err0: | |
728 | mutex_unlock(&hdmi.lock); | |
729 | return r; | |
730 | } | |
731 | ||
164ebdd1 | 732 | static void hdmi_core_disable(struct omap_dss_device *dssdev) |
4489823c TV |
733 | { |
734 | DSSDBG("Enter omapdss_hdmi_core_disable\n"); | |
735 | ||
736 | mutex_lock(&hdmi.lock); | |
737 | ||
738 | hdmi_power_off_core(dssdev); | |
739 | ||
740 | mutex_unlock(&hdmi.lock); | |
741 | } | |
742 | ||
4fbafaf3 TV |
743 | static int hdmi_get_clocks(struct platform_device *pdev) |
744 | { | |
745 | struct clk *clk; | |
746 | ||
b2c9c8ee | 747 | clk = devm_clk_get(&pdev->dev, "sys_clk"); |
4fbafaf3 TV |
748 | if (IS_ERR(clk)) { |
749 | DSSERR("can't get sys_clk\n"); | |
750 | return PTR_ERR(clk); | |
751 | } | |
752 | ||
753 | hdmi.sys_clk = clk; | |
754 | ||
4fbafaf3 TV |
755 | return 0; |
756 | } | |
757 | ||
35547626 RN |
758 | #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) |
759 | int hdmi_compute_acr(u32 sample_freq, u32 *n, u32 *cts) | |
760 | { | |
761 | u32 deep_color; | |
25a65359 | 762 | bool deep_color_correct = false; |
35547626 RN |
763 | u32 pclk = hdmi.ip_data.cfg.timings.pixel_clock; |
764 | ||
765 | if (n == NULL || cts == NULL) | |
766 | return -EINVAL; | |
767 | ||
768 | /* TODO: When implemented, query deep color mode here. */ | |
769 | deep_color = 100; | |
770 | ||
25a65359 RN |
771 | /* |
772 | * When using deep color, the default N value (as in the HDMI | |
773 | * specification) yields to an non-integer CTS. Hence, we | |
774 | * modify it while keeping the restrictions described in | |
775 | * section 7.2.1 of the HDMI 1.4a specification. | |
776 | */ | |
35547626 RN |
777 | switch (sample_freq) { |
778 | case 32000: | |
25a65359 RN |
779 | case 48000: |
780 | case 96000: | |
781 | case 192000: | |
782 | if (deep_color == 125) | |
783 | if (pclk == 27027 || pclk == 74250) | |
784 | deep_color_correct = true; | |
785 | if (deep_color == 150) | |
786 | if (pclk == 27027) | |
787 | deep_color_correct = true; | |
35547626 RN |
788 | break; |
789 | case 44100: | |
25a65359 RN |
790 | case 88200: |
791 | case 176400: | |
792 | if (deep_color == 125) | |
793 | if (pclk == 27027) | |
794 | deep_color_correct = true; | |
35547626 RN |
795 | break; |
796 | default: | |
35547626 RN |
797 | return -EINVAL; |
798 | } | |
799 | ||
25a65359 RN |
800 | if (deep_color_correct) { |
801 | switch (sample_freq) { | |
802 | case 32000: | |
803 | *n = 8192; | |
804 | break; | |
805 | case 44100: | |
806 | *n = 12544; | |
807 | break; | |
808 | case 48000: | |
809 | *n = 8192; | |
810 | break; | |
811 | case 88200: | |
812 | *n = 25088; | |
813 | break; | |
814 | case 96000: | |
815 | *n = 16384; | |
816 | break; | |
817 | case 176400: | |
818 | *n = 50176; | |
819 | break; | |
820 | case 192000: | |
821 | *n = 32768; | |
822 | break; | |
823 | default: | |
824 | return -EINVAL; | |
825 | } | |
826 | } else { | |
827 | switch (sample_freq) { | |
828 | case 32000: | |
829 | *n = 4096; | |
830 | break; | |
831 | case 44100: | |
832 | *n = 6272; | |
833 | break; | |
834 | case 48000: | |
835 | *n = 6144; | |
836 | break; | |
837 | case 88200: | |
838 | *n = 12544; | |
839 | break; | |
840 | case 96000: | |
841 | *n = 12288; | |
842 | break; | |
843 | case 176400: | |
844 | *n = 25088; | |
845 | break; | |
846 | case 192000: | |
847 | *n = 24576; | |
848 | break; | |
849 | default: | |
850 | return -EINVAL; | |
851 | } | |
852 | } | |
35547626 RN |
853 | /* Calculate CTS. See HDMI 1.3a or 1.4a specifications */ |
854 | *cts = pclk * (*n / 128) * deep_color / (sample_freq / 10); | |
855 | ||
856 | return 0; | |
857 | } | |
f3a97491 | 858 | |
164ebdd1 | 859 | static bool hdmi_mode_has_audio(void) |
f3a97491 RN |
860 | { |
861 | if (hdmi.ip_data.cfg.cm.mode == HDMI_HDMI) | |
862 | return true; | |
863 | else | |
864 | return false; | |
865 | } | |
866 | ||
35547626 RN |
867 | #endif |
868 | ||
0b450c31 TV |
869 | static int hdmi_connect(struct omap_dss_device *dssdev, |
870 | struct omap_dss_device *dst) | |
871 | { | |
872 | struct omap_overlay_manager *mgr; | |
873 | int r; | |
874 | ||
875 | dss_init_hdmi_ip_ops(&hdmi.ip_data, omapdss_get_version()); | |
876 | ||
877 | r = hdmi_init_regulator(); | |
878 | if (r) | |
879 | return r; | |
880 | ||
881 | mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel); | |
882 | if (!mgr) | |
883 | return -ENODEV; | |
884 | ||
885 | r = dss_mgr_connect(mgr, dssdev); | |
886 | if (r) | |
887 | return r; | |
888 | ||
889 | r = omapdss_output_set_device(dssdev, dst); | |
890 | if (r) { | |
891 | DSSERR("failed to connect output to new device: %s\n", | |
892 | dst->name); | |
893 | dss_mgr_disconnect(mgr, dssdev); | |
894 | return r; | |
895 | } | |
896 | ||
897 | return 0; | |
898 | } | |
899 | ||
900 | static void hdmi_disconnect(struct omap_dss_device *dssdev, | |
901 | struct omap_dss_device *dst) | |
902 | { | |
903 | WARN_ON(dst != dssdev->device); | |
904 | ||
905 | if (dst != dssdev->device) | |
906 | return; | |
907 | ||
908 | omapdss_output_unset_device(dssdev); | |
909 | ||
910 | if (dssdev->manager) | |
911 | dss_mgr_disconnect(dssdev->manager, dssdev); | |
912 | } | |
913 | ||
914 | static int hdmi_read_edid(struct omap_dss_device *dssdev, | |
915 | u8 *edid, int len) | |
916 | { | |
917 | bool need_enable; | |
918 | int r; | |
919 | ||
920 | need_enable = hdmi.core_enabled == false; | |
921 | ||
922 | if (need_enable) { | |
164ebdd1 | 923 | r = hdmi_core_enable(dssdev); |
0b450c31 TV |
924 | if (r) |
925 | return r; | |
926 | } | |
927 | ||
164ebdd1 | 928 | r = read_edid(edid, len); |
0b450c31 TV |
929 | |
930 | if (need_enable) | |
164ebdd1 | 931 | hdmi_core_disable(dssdev); |
0b450c31 TV |
932 | |
933 | return r; | |
934 | } | |
935 | ||
936 | #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) | |
164ebdd1 | 937 | static int hdmi_audio_enable(struct omap_dss_device *dssdev) |
0b450c31 TV |
938 | { |
939 | int r; | |
940 | ||
941 | mutex_lock(&hdmi.lock); | |
942 | ||
943 | if (!hdmi_mode_has_audio()) { | |
944 | r = -EPERM; | |
945 | goto err; | |
946 | } | |
947 | ||
164ebdd1 TV |
948 | |
949 | r = hdmi.ip_data.ops->audio_enable(&hdmi.ip_data); | |
0b450c31 TV |
950 | if (r) |
951 | goto err; | |
952 | ||
953 | mutex_unlock(&hdmi.lock); | |
954 | return 0; | |
955 | ||
956 | err: | |
957 | mutex_unlock(&hdmi.lock); | |
958 | return r; | |
959 | } | |
960 | ||
164ebdd1 | 961 | static void hdmi_audio_disable(struct omap_dss_device *dssdev) |
0b450c31 | 962 | { |
164ebdd1 | 963 | hdmi.ip_data.ops->audio_disable(&hdmi.ip_data); |
0b450c31 TV |
964 | } |
965 | ||
164ebdd1 | 966 | static int hdmi_audio_start(struct omap_dss_device *dssdev) |
0b450c31 | 967 | { |
164ebdd1 | 968 | return hdmi.ip_data.ops->audio_start(&hdmi.ip_data); |
0b450c31 TV |
969 | } |
970 | ||
164ebdd1 | 971 | static void hdmi_audio_stop(struct omap_dss_device *dssdev) |
0b450c31 | 972 | { |
164ebdd1 | 973 | hdmi.ip_data.ops->audio_stop(&hdmi.ip_data); |
0b450c31 TV |
974 | } |
975 | ||
164ebdd1 | 976 | static bool hdmi_audio_supported(struct omap_dss_device *dssdev) |
0b450c31 TV |
977 | { |
978 | bool r; | |
979 | ||
980 | mutex_lock(&hdmi.lock); | |
981 | ||
982 | r = hdmi_mode_has_audio(); | |
983 | ||
984 | mutex_unlock(&hdmi.lock); | |
985 | return r; | |
986 | } | |
987 | ||
164ebdd1 | 988 | static int hdmi_audio_config(struct omap_dss_device *dssdev, |
0b450c31 TV |
989 | struct omap_dss_audio *audio) |
990 | { | |
991 | int r; | |
992 | ||
993 | mutex_lock(&hdmi.lock); | |
994 | ||
995 | if (!hdmi_mode_has_audio()) { | |
996 | r = -EPERM; | |
997 | goto err; | |
998 | } | |
999 | ||
164ebdd1 | 1000 | r = hdmi.ip_data.ops->audio_config(&hdmi.ip_data, audio); |
0b450c31 TV |
1001 | if (r) |
1002 | goto err; | |
1003 | ||
1004 | mutex_unlock(&hdmi.lock); | |
1005 | return 0; | |
1006 | ||
1007 | err: | |
1008 | mutex_unlock(&hdmi.lock); | |
1009 | return r; | |
1010 | } | |
1011 | #else | |
164ebdd1 | 1012 | static int hdmi_audio_enable(struct omap_dss_device *dssdev) |
0b450c31 TV |
1013 | { |
1014 | return -EPERM; | |
1015 | } | |
1016 | ||
164ebdd1 | 1017 | static void hdmi_audio_disable(struct omap_dss_device *dssdev) |
0b450c31 TV |
1018 | { |
1019 | } | |
1020 | ||
164ebdd1 | 1021 | static int hdmi_audio_start(struct omap_dss_device *dssdev) |
0b450c31 TV |
1022 | { |
1023 | return -EPERM; | |
1024 | } | |
1025 | ||
164ebdd1 | 1026 | static void hdmi_audio_stop(struct omap_dss_device *dssdev) |
0b450c31 TV |
1027 | { |
1028 | } | |
1029 | ||
164ebdd1 | 1030 | static bool hdmi_audio_supported(struct omap_dss_device *dssdev) |
0b450c31 TV |
1031 | { |
1032 | return false; | |
1033 | } | |
1034 | ||
164ebdd1 | 1035 | static int hdmi_audio_config(struct omap_dss_device *dssdev, |
0b450c31 TV |
1036 | struct omap_dss_audio *audio) |
1037 | { | |
1038 | return -EPERM; | |
1039 | } | |
1040 | #endif | |
1041 | ||
1042 | static const struct omapdss_hdmi_ops hdmi_ops = { | |
1043 | .connect = hdmi_connect, | |
1044 | .disconnect = hdmi_disconnect, | |
1045 | ||
164ebdd1 TV |
1046 | .enable = hdmi_display_enable, |
1047 | .disable = hdmi_display_disable, | |
0b450c31 | 1048 | |
164ebdd1 TV |
1049 | .check_timings = hdmi_display_check_timing, |
1050 | .set_timings = hdmi_display_set_timing, | |
1051 | .get_timings = hdmi_display_get_timings, | |
0b450c31 TV |
1052 | |
1053 | .read_edid = hdmi_read_edid, | |
1054 | ||
164ebdd1 TV |
1055 | .audio_enable = hdmi_audio_enable, |
1056 | .audio_disable = hdmi_audio_disable, | |
1057 | .audio_start = hdmi_audio_start, | |
1058 | .audio_stop = hdmi_audio_stop, | |
1059 | .audio_supported = hdmi_audio_supported, | |
1060 | .audio_config = hdmi_audio_config, | |
0b450c31 TV |
1061 | }; |
1062 | ||
17ae4e8c | 1063 | static void hdmi_init_output(struct platform_device *pdev) |
81b87f51 | 1064 | { |
1f68d9c4 | 1065 | struct omap_dss_device *out = &hdmi.output; |
81b87f51 | 1066 | |
1f68d9c4 | 1067 | out->dev = &pdev->dev; |
81b87f51 | 1068 | out->id = OMAP_DSS_OUTPUT_HDMI; |
1f68d9c4 | 1069 | out->output_type = OMAP_DISPLAY_TYPE_HDMI; |
7286a08f | 1070 | out->name = "hdmi.0"; |
2eea5ae6 | 1071 | out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT; |
0b450c31 | 1072 | out->ops.hdmi = &hdmi_ops; |
b7328e14 | 1073 | out->owner = THIS_MODULE; |
81b87f51 | 1074 | |
5d47dbc8 | 1075 | omapdss_register_output(out); |
81b87f51 AT |
1076 | } |
1077 | ||
1078 | static void __exit hdmi_uninit_output(struct platform_device *pdev) | |
1079 | { | |
1f68d9c4 | 1080 | struct omap_dss_device *out = &hdmi.output; |
81b87f51 | 1081 | |
5d47dbc8 | 1082 | omapdss_unregister_output(out); |
81b87f51 AT |
1083 | } |
1084 | ||
c3198a5e | 1085 | /* HDMI HW IP initialisation */ |
17ae4e8c | 1086 | static int omapdss_hdmihw_probe(struct platform_device *pdev) |
c3198a5e | 1087 | { |
af23cb35 | 1088 | struct resource *res; |
38f3daf6 | 1089 | int r; |
c3198a5e | 1090 | |
c3198a5e M |
1091 | hdmi.pdev = pdev; |
1092 | ||
1093 | mutex_init(&hdmi.lock); | |
66a06b0c | 1094 | mutex_init(&hdmi.ip_data.lock); |
c3198a5e | 1095 | |
af23cb35 | 1096 | res = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0); |
c3198a5e M |
1097 | |
1098 | /* Base address taken from platform */ | |
bc3bad16 TR |
1099 | hdmi.ip_data.base_wp = devm_ioremap_resource(&pdev->dev, res); |
1100 | if (IS_ERR(hdmi.ip_data.base_wp)) | |
1101 | return PTR_ERR(hdmi.ip_data.base_wp); | |
c3198a5e | 1102 | |
ddb1d5ca TV |
1103 | hdmi.ip_data.irq = platform_get_irq(pdev, 0); |
1104 | if (hdmi.ip_data.irq < 0) { | |
1105 | DSSERR("platform_get_irq failed\n"); | |
1106 | return -ENODEV; | |
1107 | } | |
1108 | ||
4fbafaf3 TV |
1109 | r = hdmi_get_clocks(pdev); |
1110 | if (r) { | |
47e443bc | 1111 | DSSERR("can't get clocks\n"); |
4fbafaf3 TV |
1112 | return r; |
1113 | } | |
1114 | ||
1115 | pm_runtime_enable(&pdev->dev); | |
1116 | ||
95a8aeb6 M |
1117 | hdmi.ip_data.core_sys_offset = HDMI_CORE_SYS; |
1118 | hdmi.ip_data.core_av_offset = HDMI_CORE_AV; | |
1119 | hdmi.ip_data.pll_offset = HDMI_PLLCTRL; | |
1120 | hdmi.ip_data.phy_offset = HDMI_PHY; | |
7849398f | 1121 | |
002d368d TV |
1122 | hdmi_init_output(pdev); |
1123 | ||
e40402cf TV |
1124 | dss_debugfs_create_file("hdmi", hdmi_dump_regs); |
1125 | ||
cca35017 TV |
1126 | return 0; |
1127 | } | |
1128 | ||
6e7e8f06 | 1129 | static int __exit omapdss_hdmihw_remove(struct platform_device *pdev) |
c3198a5e | 1130 | { |
81b87f51 AT |
1131 | hdmi_uninit_output(pdev); |
1132 | ||
4fbafaf3 TV |
1133 | pm_runtime_disable(&pdev->dev); |
1134 | ||
c3198a5e M |
1135 | return 0; |
1136 | } | |
1137 | ||
4fbafaf3 TV |
1138 | static int hdmi_runtime_suspend(struct device *dev) |
1139 | { | |
f11766d1 | 1140 | clk_disable_unprepare(hdmi.sys_clk); |
4fbafaf3 TV |
1141 | |
1142 | dispc_runtime_put(); | |
4fbafaf3 TV |
1143 | |
1144 | return 0; | |
1145 | } | |
1146 | ||
1147 | static int hdmi_runtime_resume(struct device *dev) | |
1148 | { | |
1149 | int r; | |
1150 | ||
4fbafaf3 TV |
1151 | r = dispc_runtime_get(); |
1152 | if (r < 0) | |
852f0838 | 1153 | return r; |
4fbafaf3 | 1154 | |
f11766d1 | 1155 | clk_prepare_enable(hdmi.sys_clk); |
4fbafaf3 TV |
1156 | |
1157 | return 0; | |
4fbafaf3 TV |
1158 | } |
1159 | ||
1160 | static const struct dev_pm_ops hdmi_pm_ops = { | |
1161 | .runtime_suspend = hdmi_runtime_suspend, | |
1162 | .runtime_resume = hdmi_runtime_resume, | |
1163 | }; | |
1164 | ||
c3198a5e | 1165 | static struct platform_driver omapdss_hdmihw_driver = { |
17ae4e8c | 1166 | .probe = omapdss_hdmihw_probe, |
6e7e8f06 | 1167 | .remove = __exit_p(omapdss_hdmihw_remove), |
c3198a5e M |
1168 | .driver = { |
1169 | .name = "omapdss_hdmi", | |
1170 | .owner = THIS_MODULE, | |
4fbafaf3 | 1171 | .pm = &hdmi_pm_ops, |
c3198a5e M |
1172 | }, |
1173 | }; | |
1174 | ||
6e7e8f06 | 1175 | int __init hdmi_init_platform_driver(void) |
c3198a5e | 1176 | { |
17ae4e8c | 1177 | return platform_driver_register(&omapdss_hdmihw_driver); |
c3198a5e M |
1178 | } |
1179 | ||
6e7e8f06 | 1180 | void __exit hdmi_uninit_platform_driver(void) |
c3198a5e | 1181 | { |
04c742c3 | 1182 | platform_driver_unregister(&omapdss_hdmihw_driver); |
c3198a5e | 1183 | } |