Commit | Line | Data |
---|---|---|
c3198a5e M |
1 | /* |
2 | * hdmi.c | |
3 | * | |
4 | * HDMI interface DSS driver setting for TI's OMAP4 family of processor. | |
5 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ | |
6 | * Authors: Yong Zhi | |
7 | * Mythri pk <mythripk@ti.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License version 2 as published by | |
11 | * the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along with | |
19 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #define DSS_SUBSYS_NAME "HDMI" | |
23 | ||
24 | #include <linux/kernel.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/err.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/mutex.h> | |
30 | #include <linux/delay.h> | |
31 | #include <linux/string.h> | |
24e6289c | 32 | #include <linux/platform_device.h> |
4fbafaf3 TV |
33 | #include <linux/pm_runtime.h> |
34 | #include <linux/clk.h> | |
a0b38cc4 | 35 | #include <video/omapdss.h> |
ad44cc32 RN |
36 | #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \ |
37 | defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE) | |
38 | #include <sound/soc.h> | |
39 | #include <sound/pcm_params.h> | |
7334167b | 40 | #include "ti_hdmi_4xxx_ip.h" |
ad44cc32 | 41 | #endif |
c3198a5e | 42 | |
94c52987 | 43 | #include "ti_hdmi.h" |
c3198a5e | 44 | #include "dss.h" |
ad44cc32 | 45 | #include "dss_features.h" |
c3198a5e | 46 | |
95a8aeb6 M |
47 | #define HDMI_WP 0x0 |
48 | #define HDMI_CORE_SYS 0x400 | |
49 | #define HDMI_CORE_AV 0x900 | |
50 | #define HDMI_PLLCTRL 0x200 | |
51 | #define HDMI_PHY 0x300 | |
52 | ||
7c1f1eca M |
53 | /* HDMI EDID Length move this */ |
54 | #define HDMI_EDID_MAX_LENGTH 256 | |
55 | #define EDID_TIMING_DESCRIPTOR_SIZE 0x12 | |
56 | #define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36 | |
57 | #define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80 | |
58 | #define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4 | |
59 | #define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4 | |
60 | ||
61 | #define OMAP_HDMI_TIMINGS_NB 34 | |
62 | ||
b44e4582 | 63 | #define HDMI_DEFAULT_REGN 16 |
8d88767a TV |
64 | #define HDMI_DEFAULT_REGM2 1 |
65 | ||
c3198a5e M |
66 | static struct { |
67 | struct mutex lock; | |
68 | struct omap_display_platform_data *pdata; | |
69 | struct platform_device *pdev; | |
95a8aeb6 | 70 | struct hdmi_ip_data ip_data; |
c3198a5e M |
71 | int code; |
72 | int mode; | |
4fbafaf3 TV |
73 | |
74 | struct clk *sys_clk; | |
c3198a5e M |
75 | } hdmi; |
76 | ||
77 | /* | |
78 | * Logic for the below structure : | |
79 | * user enters the CEA or VESA timings by specifying the HDMI/DVI code. | |
80 | * There is a correspondence between CEA/VESA timing and code, please | |
81 | * refer to section 6.3 in HDMI 1.3 specification for timing code. | |
82 | * | |
83 | * In the below structure, cea_vesa_timings corresponds to all OMAP4 | |
84 | * supported CEA and VESA timing values.code_cea corresponds to the CEA | |
85 | * code, It is used to get the timing from cea_vesa_timing array.Similarly | |
86 | * with code_vesa. Code_index is used for back mapping, that is once EDID | |
87 | * is read from the TV, EDID is parsed to find the timing values and then | |
88 | * map it to corresponding CEA or VESA index. | |
89 | */ | |
90 | ||
91 | static const struct hdmi_timings cea_vesa_timings[OMAP_HDMI_TIMINGS_NB] = { | |
92 | { {640, 480, 25200, 96, 16, 48, 2, 10, 33} , 0 , 0}, | |
93 | { {1280, 720, 74250, 40, 440, 220, 5, 5, 20}, 1, 1}, | |
94 | { {1280, 720, 74250, 40, 110, 220, 5, 5, 20}, 1, 1}, | |
95 | { {720, 480, 27027, 62, 16, 60, 6, 9, 30}, 0, 0}, | |
96 | { {2880, 576, 108000, 256, 48, 272, 5, 5, 39}, 0, 0}, | |
97 | { {1440, 240, 27027, 124, 38, 114, 3, 4, 15}, 0, 0}, | |
98 | { {1440, 288, 27000, 126, 24, 138, 3, 2, 19}, 0, 0}, | |
99 | { {1920, 540, 74250, 44, 528, 148, 5, 2, 15}, 1, 1}, | |
100 | { {1920, 540, 74250, 44, 88, 148, 5, 2, 15}, 1, 1}, | |
101 | { {1920, 1080, 148500, 44, 88, 148, 5, 4, 36}, 1, 1}, | |
102 | { {720, 576, 27000, 64, 12, 68, 5, 5, 39}, 0, 0}, | |
103 | { {1440, 576, 54000, 128, 24, 136, 5, 5, 39}, 0, 0}, | |
104 | { {1920, 1080, 148500, 44, 528, 148, 5, 4, 36}, 1, 1}, | |
105 | { {2880, 480, 108108, 248, 64, 240, 6, 9, 30}, 0, 0}, | |
106 | { {1920, 1080, 74250, 44, 638, 148, 5, 4, 36}, 1, 1}, | |
107 | /* VESA From Here */ | |
108 | { {640, 480, 25175, 96, 16, 48, 2 , 11, 31}, 0, 0}, | |
109 | { {800, 600, 40000, 128, 40, 88, 4 , 1, 23}, 1, 1}, | |
110 | { {848, 480, 33750, 112, 16, 112, 8 , 6, 23}, 1, 1}, | |
111 | { {1280, 768, 79500, 128, 64, 192, 7 , 3, 20}, 1, 0}, | |
112 | { {1280, 800, 83500, 128, 72, 200, 6 , 3, 22}, 1, 0}, | |
113 | { {1360, 768, 85500, 112, 64, 256, 6 , 3, 18}, 1, 1}, | |
114 | { {1280, 960, 108000, 112, 96, 312, 3 , 1, 36}, 1, 1}, | |
115 | { {1280, 1024, 108000, 112, 48, 248, 3 , 1, 38}, 1, 1}, | |
116 | { {1024, 768, 65000, 136, 24, 160, 6, 3, 29}, 0, 0}, | |
117 | { {1400, 1050, 121750, 144, 88, 232, 4, 3, 32}, 1, 0}, | |
118 | { {1440, 900, 106500, 152, 80, 232, 6, 3, 25}, 1, 0}, | |
119 | { {1680, 1050, 146250, 176 , 104, 280, 6, 3, 30}, 1, 0}, | |
120 | { {1366, 768, 85500, 143, 70, 213, 3, 3, 24}, 1, 1}, | |
121 | { {1920, 1080, 148500, 44, 148, 80, 5, 4, 36}, 1, 1}, | |
122 | { {1280, 768, 68250, 32, 48, 80, 7, 3, 12}, 0, 1}, | |
123 | { {1400, 1050, 101000, 32, 48, 80, 4, 3, 23}, 0, 1}, | |
124 | { {1680, 1050, 119000, 32, 48, 80, 6, 3, 21}, 0, 1}, | |
125 | { {1280, 800, 79500, 32, 48, 80, 6, 3, 14}, 0, 1}, | |
126 | { {1280, 720, 74250, 40, 110, 220, 5, 5, 20}, 1, 1} | |
127 | }; | |
128 | ||
129 | /* | |
130 | * This is a static mapping array which maps the timing values | |
131 | * with corresponding CEA / VESA code | |
132 | */ | |
133 | static const int code_index[OMAP_HDMI_TIMINGS_NB] = { | |
134 | 1, 19, 4, 2, 37, 6, 21, 20, 5, 16, 17, 29, 31, 35, 32, | |
135 | /* <--15 CEA 17--> vesa*/ | |
136 | 4, 9, 0xE, 0x17, 0x1C, 0x27, 0x20, 0x23, 0x10, 0x2A, | |
137 | 0X2F, 0x3A, 0X51, 0X52, 0x16, 0x29, 0x39, 0x1B | |
138 | }; | |
139 | ||
140 | /* | |
141 | * This is reverse static mapping which maps the CEA / VESA code | |
142 | * to the corresponding timing values | |
143 | */ | |
144 | static const int code_cea[39] = { | |
145 | -1, 0, 3, 3, 2, 8, 5, 5, -1, -1, | |
146 | -1, -1, -1, -1, -1, -1, 9, 10, 10, 1, | |
147 | 7, 6, 6, -1, -1, -1, -1, -1, -1, 11, | |
148 | 11, 12, 14, -1, -1, 13, 13, 4, 4 | |
149 | }; | |
150 | ||
151 | static const int code_vesa[85] = { | |
152 | -1, -1, -1, -1, 15, -1, -1, -1, -1, 16, | |
153 | -1, -1, -1, -1, 17, -1, 23, -1, -1, -1, | |
154 | -1, -1, 29, 18, -1, -1, -1, 32, 19, -1, | |
155 | -1, -1, 21, -1, -1, 22, -1, -1, -1, 20, | |
156 | -1, 30, 24, -1, -1, -1, -1, 25, -1, -1, | |
157 | -1, -1, -1, -1, -1, -1, -1, 31, 26, -1, | |
158 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
159 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
160 | -1, 27, 28, -1, 33}; | |
161 | ||
4fbafaf3 TV |
162 | static int hdmi_runtime_get(void) |
163 | { | |
164 | int r; | |
165 | ||
166 | DSSDBG("hdmi_runtime_get\n"); | |
167 | ||
168 | r = pm_runtime_get_sync(&hdmi.pdev->dev); | |
169 | WARN_ON(r < 0); | |
170 | return r < 0 ? r : 0; | |
171 | } | |
172 | ||
173 | static void hdmi_runtime_put(void) | |
174 | { | |
175 | int r; | |
176 | ||
177 | DSSDBG("hdmi_runtime_put\n"); | |
178 | ||
179 | r = pm_runtime_put(&hdmi.pdev->dev); | |
180 | WARN_ON(r < 0); | |
181 | } | |
182 | ||
c3198a5e M |
183 | int hdmi_init_display(struct omap_dss_device *dssdev) |
184 | { | |
185 | DSSDBG("init_display\n"); | |
186 | ||
60634a28 | 187 | dss_init_hdmi_ip_ops(&hdmi.ip_data); |
c3198a5e M |
188 | return 0; |
189 | } | |
190 | ||
c3198a5e M |
191 | static int get_timings_index(void) |
192 | { | |
193 | int code; | |
194 | ||
195 | if (hdmi.mode == 0) | |
196 | code = code_vesa[hdmi.code]; | |
197 | else | |
198 | code = code_cea[hdmi.code]; | |
199 | ||
200 | if (code == -1) { | |
201 | /* HDMI code 4 corresponds to 640 * 480 VGA */ | |
202 | hdmi.code = 4; | |
203 | /* DVI mode 1 corresponds to HDMI 0 to DVI */ | |
204 | hdmi.mode = HDMI_DVI; | |
205 | ||
206 | code = code_vesa[hdmi.code]; | |
207 | } | |
208 | return code; | |
209 | } | |
210 | ||
211 | static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing) | |
212 | { | |
213 | int i = 0, code = -1, temp_vsync = 0, temp_hsync = 0; | |
214 | int timing_vsync = 0, timing_hsync = 0; | |
38863b7e | 215 | struct hdmi_video_timings temp; |
c3198a5e M |
216 | struct hdmi_cm cm = {-1}; |
217 | DSSDBG("hdmi_get_code\n"); | |
218 | ||
219 | for (i = 0; i < OMAP_HDMI_TIMINGS_NB; i++) { | |
220 | temp = cea_vesa_timings[i].timings; | |
221 | if ((temp.pixel_clock == timing->pixel_clock) && | |
222 | (temp.x_res == timing->x_res) && | |
223 | (temp.y_res == timing->y_res)) { | |
224 | ||
225 | temp_hsync = temp.hfp + temp.hsw + temp.hbp; | |
226 | timing_hsync = timing->hfp + timing->hsw + timing->hbp; | |
227 | temp_vsync = temp.vfp + temp.vsw + temp.vbp; | |
228 | timing_vsync = timing->vfp + timing->vsw + timing->vbp; | |
229 | ||
230 | DSSDBG("temp_hsync = %d , temp_vsync = %d" | |
231 | "timing_hsync = %d, timing_vsync = %d\n", | |
232 | temp_hsync, temp_hsync, | |
233 | timing_hsync, timing_vsync); | |
234 | ||
235 | if ((temp_hsync == timing_hsync) && | |
236 | (temp_vsync == timing_vsync)) { | |
237 | code = i; | |
238 | cm.code = code_index[i]; | |
239 | if (code < 14) | |
240 | cm.mode = HDMI_HDMI; | |
241 | else | |
242 | cm.mode = HDMI_DVI; | |
243 | DSSDBG("Hdmi_code = %d mode = %d\n", | |
244 | cm.code, cm.mode); | |
245 | break; | |
246 | } | |
247 | } | |
248 | } | |
249 | ||
250 | return cm; | |
251 | } | |
252 | ||
c3198a5e M |
253 | static void update_hdmi_timings(struct hdmi_config *cfg, |
254 | struct omap_video_timings *timings, int code) | |
255 | { | |
256 | cfg->timings.timings.x_res = timings->x_res; | |
257 | cfg->timings.timings.y_res = timings->y_res; | |
258 | cfg->timings.timings.hbp = timings->hbp; | |
259 | cfg->timings.timings.hfp = timings->hfp; | |
260 | cfg->timings.timings.hsw = timings->hsw; | |
261 | cfg->timings.timings.vbp = timings->vbp; | |
262 | cfg->timings.timings.vfp = timings->vfp; | |
263 | cfg->timings.timings.vsw = timings->vsw; | |
264 | cfg->timings.timings.pixel_clock = timings->pixel_clock; | |
265 | cfg->timings.vsync_pol = cea_vesa_timings[code].vsync_pol; | |
266 | cfg->timings.hsync_pol = cea_vesa_timings[code].hsync_pol; | |
267 | } | |
268 | ||
c3dc6a7a AT |
269 | unsigned long hdmi_get_pixel_clock(void) |
270 | { | |
271 | /* HDMI Pixel Clock in Mhz */ | |
272 | return hdmi.ip_data.cfg.timings.timings.pixel_clock * 10000; | |
273 | } | |
274 | ||
6cb07b25 AT |
275 | static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy, |
276 | struct hdmi_pll_info *pi) | |
c3198a5e | 277 | { |
6cb07b25 | 278 | unsigned long clkin, refclk; |
c3198a5e M |
279 | u32 mf; |
280 | ||
4fbafaf3 | 281 | clkin = clk_get_rate(hdmi.sys_clk) / 10000; |
c3198a5e M |
282 | /* |
283 | * Input clock is predivided by N + 1 | |
284 | * out put of which is reference clk | |
285 | */ | |
8d88767a TV |
286 | if (dssdev->clocks.hdmi.regn == 0) |
287 | pi->regn = HDMI_DEFAULT_REGN; | |
288 | else | |
289 | pi->regn = dssdev->clocks.hdmi.regn; | |
290 | ||
b44e4582 | 291 | refclk = clkin / pi->regn; |
c3198a5e M |
292 | |
293 | /* | |
294 | * multiplier is pixel_clk/ref_clk | |
295 | * Multiplying by 100 to avoid fractional part removal | |
296 | */ | |
6cb07b25 | 297 | pi->regm = (phy * 100 / (refclk)) / 100; |
8d88767a TV |
298 | |
299 | if (dssdev->clocks.hdmi.regm2 == 0) | |
300 | pi->regm2 = HDMI_DEFAULT_REGM2; | |
301 | else | |
302 | pi->regm2 = dssdev->clocks.hdmi.regm2; | |
c3198a5e M |
303 | |
304 | /* | |
305 | * fractional multiplier is remainder of the difference between | |
306 | * multiplier and actual phy(required pixel clock thus should be | |
307 | * multiplied by 2^18(262144) divided by the reference clock | |
308 | */ | |
309 | mf = (phy - pi->regm * refclk) * 262144; | |
6cb07b25 | 310 | pi->regmf = mf / (refclk); |
c3198a5e M |
311 | |
312 | /* | |
313 | * Dcofreq should be set to 1 if required pixel clock | |
314 | * is greater than 1000MHz | |
315 | */ | |
316 | pi->dcofreq = phy > 1000 * 100; | |
b44e4582 | 317 | pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10; |
c3198a5e | 318 | |
7b27da54 M |
319 | /* Set the reference clock to sysclk reference */ |
320 | pi->refsel = HDMI_REFSEL_SYSCLK; | |
321 | ||
c3198a5e M |
322 | DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf); |
323 | DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd); | |
324 | } | |
325 | ||
c3198a5e M |
326 | static int hdmi_power_on(struct omap_dss_device *dssdev) |
327 | { | |
328 | int r, code = 0; | |
c3198a5e | 329 | struct omap_video_timings *p; |
6cb07b25 | 330 | unsigned long phy; |
c3198a5e | 331 | |
4fbafaf3 TV |
332 | r = hdmi_runtime_get(); |
333 | if (r) | |
334 | return r; | |
c3198a5e | 335 | |
26d9dd0d | 336 | dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, 0); |
c3198a5e M |
337 | |
338 | p = &dssdev->panel.timings; | |
339 | ||
340 | DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", | |
341 | dssdev->panel.timings.x_res, | |
342 | dssdev->panel.timings.y_res); | |
343 | ||
c3198a5e | 344 | code = get_timings_index(); |
7b27da54 | 345 | update_hdmi_timings(&hdmi.ip_data.cfg, p, code); |
c3198a5e | 346 | |
c3198a5e M |
347 | phy = p->pixel_clock; |
348 | ||
7b27da54 | 349 | hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data); |
c3198a5e | 350 | |
60634a28 | 351 | hdmi.ip_data.ops->video_enable(&hdmi.ip_data, 0); |
c3198a5e | 352 | |
95a8aeb6 | 353 | /* config the PLL and PHY hdmi_set_pll_pwrfirst */ |
60634a28 | 354 | r = hdmi.ip_data.ops->pll_enable(&hdmi.ip_data); |
c3198a5e M |
355 | if (r) { |
356 | DSSDBG("Failed to lock PLL\n"); | |
357 | goto err; | |
358 | } | |
359 | ||
60634a28 | 360 | r = hdmi.ip_data.ops->phy_enable(&hdmi.ip_data); |
c3198a5e M |
361 | if (r) { |
362 | DSSDBG("Failed to start PHY\n"); | |
363 | goto err; | |
364 | } | |
365 | ||
7b27da54 M |
366 | hdmi.ip_data.cfg.cm.mode = hdmi.mode; |
367 | hdmi.ip_data.cfg.cm.code = hdmi.code; | |
60634a28 | 368 | hdmi.ip_data.ops->video_configure(&hdmi.ip_data); |
c3198a5e M |
369 | |
370 | /* Make selection of HDMI in DSS */ | |
371 | dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK); | |
372 | ||
373 | /* Select the dispc clock source as PRCM clock, to ensure that it is not | |
374 | * DSI PLL source as the clock selected by DSI PLL might not be | |
375 | * sufficient for the resolution selected / that can be changed | |
376 | * dynamically by user. This can be moved to single location , say | |
377 | * Boardfile. | |
378 | */ | |
6cb07b25 | 379 | dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src); |
c3198a5e M |
380 | |
381 | /* bypass TV gamma table */ | |
382 | dispc_enable_gamma_table(0); | |
383 | ||
384 | /* tv size */ | |
385 | dispc_set_digit_size(dssdev->panel.timings.x_res, | |
386 | dssdev->panel.timings.y_res); | |
387 | ||
60634a28 | 388 | hdmi.ip_data.ops->video_enable(&hdmi.ip_data, 1); |
c3198a5e | 389 | |
3870c909 TV |
390 | dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, 1); |
391 | ||
c3198a5e M |
392 | return 0; |
393 | err: | |
4fbafaf3 | 394 | hdmi_runtime_put(); |
c3198a5e M |
395 | return -EIO; |
396 | } | |
397 | ||
398 | static void hdmi_power_off(struct omap_dss_device *dssdev) | |
399 | { | |
26d9dd0d | 400 | dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, 0); |
c3198a5e | 401 | |
60634a28 M |
402 | hdmi.ip_data.ops->video_enable(&hdmi.ip_data, 0); |
403 | hdmi.ip_data.ops->phy_disable(&hdmi.ip_data); | |
404 | hdmi.ip_data.ops->pll_disable(&hdmi.ip_data); | |
4fbafaf3 | 405 | hdmi_runtime_put(); |
c3198a5e M |
406 | } |
407 | ||
408 | int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev, | |
409 | struct omap_video_timings *timings) | |
410 | { | |
411 | struct hdmi_cm cm; | |
412 | ||
413 | cm = hdmi_get_code(timings); | |
414 | if (cm.code == -1) { | |
c3198a5e M |
415 | return -EINVAL; |
416 | } | |
417 | ||
418 | return 0; | |
419 | ||
420 | } | |
421 | ||
422 | void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev) | |
423 | { | |
424 | struct hdmi_cm cm; | |
425 | ||
c3198a5e M |
426 | cm = hdmi_get_code(&dssdev->panel.timings); |
427 | hdmi.code = cm.code; | |
428 | hdmi.mode = cm.mode; | |
fa70dc5f TV |
429 | |
430 | if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) { | |
431 | int r; | |
432 | ||
433 | hdmi_power_off(dssdev); | |
434 | ||
435 | r = hdmi_power_on(dssdev); | |
436 | if (r) | |
437 | DSSERR("failed to power on device\n"); | |
438 | } | |
c3198a5e M |
439 | } |
440 | ||
162874d5 M |
441 | void hdmi_dump_regs(struct seq_file *s) |
442 | { | |
443 | mutex_lock(&hdmi.lock); | |
444 | ||
445 | if (hdmi_runtime_get()) | |
446 | return; | |
447 | ||
448 | hdmi.ip_data.ops->dump_wrapper(&hdmi.ip_data, s); | |
449 | hdmi.ip_data.ops->dump_pll(&hdmi.ip_data, s); | |
450 | hdmi.ip_data.ops->dump_phy(&hdmi.ip_data, s); | |
451 | hdmi.ip_data.ops->dump_core(&hdmi.ip_data, s); | |
452 | ||
453 | hdmi_runtime_put(); | |
454 | mutex_unlock(&hdmi.lock); | |
455 | } | |
456 | ||
47024565 TV |
457 | int omapdss_hdmi_read_edid(u8 *buf, int len) |
458 | { | |
459 | int r; | |
460 | ||
461 | mutex_lock(&hdmi.lock); | |
462 | ||
463 | r = hdmi_runtime_get(); | |
464 | BUG_ON(r); | |
465 | ||
466 | r = hdmi.ip_data.ops->read_edid(&hdmi.ip_data, buf, len); | |
467 | ||
468 | hdmi_runtime_put(); | |
469 | mutex_unlock(&hdmi.lock); | |
470 | ||
471 | return r; | |
472 | } | |
473 | ||
759593ff TV |
474 | bool omapdss_hdmi_detect(void) |
475 | { | |
476 | int r; | |
477 | ||
478 | mutex_lock(&hdmi.lock); | |
479 | ||
480 | r = hdmi_runtime_get(); | |
481 | BUG_ON(r); | |
482 | ||
483 | r = hdmi.ip_data.ops->detect(&hdmi.ip_data); | |
484 | ||
485 | hdmi_runtime_put(); | |
486 | mutex_unlock(&hdmi.lock); | |
487 | ||
488 | return r == 1; | |
489 | } | |
490 | ||
c3198a5e M |
491 | int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev) |
492 | { | |
493 | int r = 0; | |
494 | ||
495 | DSSDBG("ENTER hdmi_display_enable\n"); | |
496 | ||
497 | mutex_lock(&hdmi.lock); | |
498 | ||
05e1d606 TV |
499 | if (dssdev->manager == NULL) { |
500 | DSSERR("failed to enable display: no manager\n"); | |
501 | r = -ENODEV; | |
502 | goto err0; | |
503 | } | |
504 | ||
c3198a5e M |
505 | r = omap_dss_start_device(dssdev); |
506 | if (r) { | |
507 | DSSERR("failed to start device\n"); | |
508 | goto err0; | |
509 | } | |
510 | ||
511 | if (dssdev->platform_enable) { | |
512 | r = dssdev->platform_enable(dssdev); | |
513 | if (r) { | |
514 | DSSERR("failed to enable GPIO's\n"); | |
515 | goto err1; | |
516 | } | |
517 | } | |
518 | ||
519 | r = hdmi_power_on(dssdev); | |
520 | if (r) { | |
521 | DSSERR("failed to power on device\n"); | |
522 | goto err2; | |
523 | } | |
524 | ||
525 | mutex_unlock(&hdmi.lock); | |
526 | return 0; | |
527 | ||
528 | err2: | |
529 | if (dssdev->platform_disable) | |
530 | dssdev->platform_disable(dssdev); | |
531 | err1: | |
532 | omap_dss_stop_device(dssdev); | |
533 | err0: | |
534 | mutex_unlock(&hdmi.lock); | |
535 | return r; | |
536 | } | |
537 | ||
538 | void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev) | |
539 | { | |
540 | DSSDBG("Enter hdmi_display_disable\n"); | |
541 | ||
542 | mutex_lock(&hdmi.lock); | |
543 | ||
544 | hdmi_power_off(dssdev); | |
545 | ||
546 | if (dssdev->platform_disable) | |
547 | dssdev->platform_disable(dssdev); | |
548 | ||
549 | omap_dss_stop_device(dssdev); | |
550 | ||
551 | mutex_unlock(&hdmi.lock); | |
552 | } | |
553 | ||
82335c4c RN |
554 | #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \ |
555 | defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE) | |
ad44cc32 | 556 | |
95a8aeb6 M |
557 | static int hdmi_audio_hw_params(struct hdmi_ip_data *ip_data, |
558 | struct snd_pcm_substream *substream, | |
ad44cc32 RN |
559 | struct snd_pcm_hw_params *params, |
560 | struct snd_soc_dai *dai) | |
561 | { | |
562 | struct hdmi_audio_format audio_format; | |
563 | struct hdmi_audio_dma audio_dma; | |
564 | struct hdmi_core_audio_config core_cfg; | |
565 | struct hdmi_core_infoframe_audio aud_if_cfg; | |
566 | int err, n, cts; | |
567 | enum hdmi_core_audio_sample_freq sample_freq; | |
568 | ||
569 | switch (params_format(params)) { | |
570 | case SNDRV_PCM_FORMAT_S16_LE: | |
571 | core_cfg.i2s_cfg.word_max_length = | |
572 | HDMI_AUDIO_I2S_MAX_WORD_20BITS; | |
573 | core_cfg.i2s_cfg.word_length = HDMI_AUDIO_I2S_CHST_WORD_16_BITS; | |
574 | core_cfg.i2s_cfg.in_length_bits = | |
575 | HDMI_AUDIO_I2S_INPUT_LENGTH_16; | |
576 | core_cfg.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_LEFT; | |
577 | audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES; | |
578 | audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS; | |
579 | audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT; | |
580 | audio_dma.transfer_size = 0x10; | |
581 | break; | |
582 | case SNDRV_PCM_FORMAT_S24_LE: | |
583 | core_cfg.i2s_cfg.word_max_length = | |
584 | HDMI_AUDIO_I2S_MAX_WORD_24BITS; | |
585 | core_cfg.i2s_cfg.word_length = HDMI_AUDIO_I2S_CHST_WORD_24_BITS; | |
586 | core_cfg.i2s_cfg.in_length_bits = | |
587 | HDMI_AUDIO_I2S_INPUT_LENGTH_24; | |
588 | audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_ONESAMPLE; | |
589 | audio_format.sample_size = HDMI_AUDIO_SAMPLE_24BITS; | |
590 | audio_format.justification = HDMI_AUDIO_JUSTIFY_RIGHT; | |
591 | core_cfg.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_RIGHT; | |
592 | audio_dma.transfer_size = 0x20; | |
593 | break; | |
594 | default: | |
595 | return -EINVAL; | |
596 | } | |
597 | ||
598 | switch (params_rate(params)) { | |
599 | case 32000: | |
600 | sample_freq = HDMI_AUDIO_FS_32000; | |
601 | break; | |
602 | case 44100: | |
603 | sample_freq = HDMI_AUDIO_FS_44100; | |
604 | break; | |
605 | case 48000: | |
606 | sample_freq = HDMI_AUDIO_FS_48000; | |
607 | break; | |
608 | default: | |
609 | return -EINVAL; | |
610 | } | |
611 | ||
95a8aeb6 | 612 | err = hdmi_config_audio_acr(ip_data, params_rate(params), &n, &cts); |
ad44cc32 RN |
613 | if (err < 0) |
614 | return err; | |
615 | ||
616 | /* Audio wrapper config */ | |
617 | audio_format.stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL; | |
618 | audio_format.active_chnnls_msk = 0x03; | |
619 | audio_format.type = HDMI_AUDIO_TYPE_LPCM; | |
620 | audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST; | |
621 | /* Disable start/stop signals of IEC 60958 blocks */ | |
622 | audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF; | |
623 | ||
624 | audio_dma.block_size = 0xC0; | |
625 | audio_dma.mode = HDMI_AUDIO_TRANSF_DMA; | |
626 | audio_dma.fifo_threshold = 0x20; /* in number of samples */ | |
627 | ||
95a8aeb6 M |
628 | hdmi_wp_audio_config_dma(ip_data, &audio_dma); |
629 | hdmi_wp_audio_config_format(ip_data, &audio_format); | |
ad44cc32 RN |
630 | |
631 | /* | |
632 | * I2S config | |
633 | */ | |
634 | core_cfg.i2s_cfg.en_high_bitrate_aud = false; | |
635 | /* Only used with high bitrate audio */ | |
636 | core_cfg.i2s_cfg.cbit_order = false; | |
637 | /* Serial data and word select should change on sck rising edge */ | |
638 | core_cfg.i2s_cfg.sck_edge_mode = HDMI_AUDIO_I2S_SCK_EDGE_RISING; | |
639 | core_cfg.i2s_cfg.vbit = HDMI_AUDIO_I2S_VBIT_FOR_PCM; | |
640 | /* Set I2S word select polarity */ | |
641 | core_cfg.i2s_cfg.ws_polarity = HDMI_AUDIO_I2S_WS_POLARITY_LOW_IS_LEFT; | |
642 | core_cfg.i2s_cfg.direction = HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST; | |
643 | /* Set serial data to word select shift. See Phillips spec. */ | |
644 | core_cfg.i2s_cfg.shift = HDMI_AUDIO_I2S_FIRST_BIT_SHIFT; | |
645 | /* Enable one of the four available serial data channels */ | |
646 | core_cfg.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN; | |
647 | ||
648 | /* Core audio config */ | |
649 | core_cfg.freq_sample = sample_freq; | |
650 | core_cfg.n = n; | |
651 | core_cfg.cts = cts; | |
652 | if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) { | |
653 | core_cfg.aud_par_busclk = 0; | |
654 | core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_SW; | |
655 | core_cfg.use_mclk = false; | |
656 | } else { | |
657 | core_cfg.aud_par_busclk = (((128 * 31) - 1) << 8); | |
658 | core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_HW; | |
659 | core_cfg.use_mclk = true; | |
660 | core_cfg.mclk_mode = HDMI_AUDIO_MCLK_128FS; | |
661 | } | |
662 | core_cfg.layout = HDMI_AUDIO_LAYOUT_2CH; | |
663 | core_cfg.en_spdif = false; | |
664 | /* Use sample frequency from channel status word */ | |
665 | core_cfg.fs_override = true; | |
666 | /* Enable ACR packets */ | |
667 | core_cfg.en_acr_pkt = true; | |
668 | /* Disable direct streaming digital audio */ | |
669 | core_cfg.en_dsd_audio = false; | |
670 | /* Use parallel audio interface */ | |
671 | core_cfg.en_parallel_aud_input = true; | |
672 | ||
95a8aeb6 | 673 | hdmi_core_audio_config(ip_data, &core_cfg); |
ad44cc32 RN |
674 | |
675 | /* | |
676 | * Configure packet | |
677 | * info frame audio see doc CEA861-D page 74 | |
678 | */ | |
679 | aud_if_cfg.db1_coding_type = HDMI_INFOFRAME_AUDIO_DB1CT_FROM_STREAM; | |
680 | aud_if_cfg.db1_channel_count = 2; | |
681 | aud_if_cfg.db2_sample_freq = HDMI_INFOFRAME_AUDIO_DB2SF_FROM_STREAM; | |
682 | aud_if_cfg.db2_sample_size = HDMI_INFOFRAME_AUDIO_DB2SS_FROM_STREAM; | |
683 | aud_if_cfg.db4_channel_alloc = 0x00; | |
684 | aud_if_cfg.db5_downmix_inh = false; | |
685 | aud_if_cfg.db5_lsv = 0; | |
686 | ||
95a8aeb6 | 687 | hdmi_core_audio_infoframe_config(ip_data, &aud_if_cfg); |
ad44cc32 RN |
688 | return 0; |
689 | } | |
690 | ||
ad44cc32 RN |
691 | static int hdmi_audio_startup(struct snd_pcm_substream *substream, |
692 | struct snd_soc_dai *dai) | |
693 | { | |
694 | if (!hdmi.mode) { | |
695 | pr_err("Current video settings do not support audio.\n"); | |
696 | return -EIO; | |
697 | } | |
698 | return 0; | |
699 | } | |
700 | ||
701 | static struct snd_soc_codec_driver hdmi_audio_codec_drv = { | |
702 | }; | |
703 | ||
704 | static struct snd_soc_dai_ops hdmi_audio_codec_ops = { | |
705 | .hw_params = hdmi_audio_hw_params, | |
706 | .trigger = hdmi_audio_trigger, | |
707 | .startup = hdmi_audio_startup, | |
708 | }; | |
709 | ||
710 | static struct snd_soc_dai_driver hdmi_codec_dai_drv = { | |
711 | .name = "hdmi-audio-codec", | |
712 | .playback = { | |
713 | .channels_min = 2, | |
714 | .channels_max = 2, | |
715 | .rates = SNDRV_PCM_RATE_32000 | | |
716 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000, | |
717 | .formats = SNDRV_PCM_FMTBIT_S16_LE | | |
718 | SNDRV_PCM_FMTBIT_S24_LE, | |
719 | }, | |
720 | .ops = &hdmi_audio_codec_ops, | |
721 | }; | |
82335c4c RN |
722 | #endif |
723 | ||
4fbafaf3 TV |
724 | static int hdmi_get_clocks(struct platform_device *pdev) |
725 | { | |
726 | struct clk *clk; | |
727 | ||
728 | clk = clk_get(&pdev->dev, "sys_clk"); | |
729 | if (IS_ERR(clk)) { | |
730 | DSSERR("can't get sys_clk\n"); | |
731 | return PTR_ERR(clk); | |
732 | } | |
733 | ||
734 | hdmi.sys_clk = clk; | |
735 | ||
4fbafaf3 TV |
736 | return 0; |
737 | } | |
738 | ||
739 | static void hdmi_put_clocks(void) | |
740 | { | |
741 | if (hdmi.sys_clk) | |
742 | clk_put(hdmi.sys_clk); | |
4fbafaf3 TV |
743 | } |
744 | ||
c3198a5e M |
745 | /* HDMI HW IP initialisation */ |
746 | static int omapdss_hdmihw_probe(struct platform_device *pdev) | |
747 | { | |
748 | struct resource *hdmi_mem; | |
4fbafaf3 | 749 | int r; |
c3198a5e M |
750 | |
751 | hdmi.pdata = pdev->dev.platform_data; | |
752 | hdmi.pdev = pdev; | |
753 | ||
754 | mutex_init(&hdmi.lock); | |
755 | ||
756 | hdmi_mem = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0); | |
757 | if (!hdmi_mem) { | |
758 | DSSERR("can't get IORESOURCE_MEM HDMI\n"); | |
759 | return -EINVAL; | |
760 | } | |
761 | ||
762 | /* Base address taken from platform */ | |
95a8aeb6 M |
763 | hdmi.ip_data.base_wp = ioremap(hdmi_mem->start, |
764 | resource_size(hdmi_mem)); | |
765 | if (!hdmi.ip_data.base_wp) { | |
c3198a5e M |
766 | DSSERR("can't ioremap WP\n"); |
767 | return -ENOMEM; | |
768 | } | |
769 | ||
4fbafaf3 TV |
770 | r = hdmi_get_clocks(pdev); |
771 | if (r) { | |
95a8aeb6 | 772 | iounmap(hdmi.ip_data.base_wp); |
4fbafaf3 TV |
773 | return r; |
774 | } | |
775 | ||
776 | pm_runtime_enable(&pdev->dev); | |
777 | ||
95a8aeb6 M |
778 | hdmi.ip_data.core_sys_offset = HDMI_CORE_SYS; |
779 | hdmi.ip_data.core_av_offset = HDMI_CORE_AV; | |
780 | hdmi.ip_data.pll_offset = HDMI_PLLCTRL; | |
781 | hdmi.ip_data.phy_offset = HDMI_PHY; | |
782 | ||
c3198a5e M |
783 | hdmi_panel_init(); |
784 | ||
ad44cc32 RN |
785 | #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \ |
786 | defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE) | |
787 | ||
788 | /* Register ASoC codec DAI */ | |
4fbafaf3 | 789 | r = snd_soc_register_codec(&pdev->dev, &hdmi_audio_codec_drv, |
ad44cc32 | 790 | &hdmi_codec_dai_drv, 1); |
4fbafaf3 | 791 | if (r) { |
ad44cc32 | 792 | DSSERR("can't register ASoC HDMI audio codec\n"); |
4fbafaf3 | 793 | return r; |
ad44cc32 RN |
794 | } |
795 | #endif | |
c3198a5e M |
796 | return 0; |
797 | } | |
798 | ||
799 | static int omapdss_hdmihw_remove(struct platform_device *pdev) | |
800 | { | |
801 | hdmi_panel_exit(); | |
802 | ||
ad44cc32 RN |
803 | #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \ |
804 | defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE) | |
805 | snd_soc_unregister_codec(&pdev->dev); | |
806 | #endif | |
807 | ||
4fbafaf3 TV |
808 | pm_runtime_disable(&pdev->dev); |
809 | ||
810 | hdmi_put_clocks(); | |
811 | ||
95a8aeb6 | 812 | iounmap(hdmi.ip_data.base_wp); |
c3198a5e M |
813 | |
814 | return 0; | |
815 | } | |
816 | ||
4fbafaf3 TV |
817 | static int hdmi_runtime_suspend(struct device *dev) |
818 | { | |
4fbafaf3 TV |
819 | clk_disable(hdmi.sys_clk); |
820 | ||
821 | dispc_runtime_put(); | |
822 | dss_runtime_put(); | |
823 | ||
824 | return 0; | |
825 | } | |
826 | ||
827 | static int hdmi_runtime_resume(struct device *dev) | |
828 | { | |
829 | int r; | |
830 | ||
831 | r = dss_runtime_get(); | |
832 | if (r < 0) | |
833 | goto err_get_dss; | |
834 | ||
835 | r = dispc_runtime_get(); | |
836 | if (r < 0) | |
837 | goto err_get_dispc; | |
838 | ||
839 | ||
840 | clk_enable(hdmi.sys_clk); | |
4fbafaf3 TV |
841 | |
842 | return 0; | |
843 | ||
844 | err_get_dispc: | |
845 | dss_runtime_put(); | |
846 | err_get_dss: | |
847 | return r; | |
848 | } | |
849 | ||
850 | static const struct dev_pm_ops hdmi_pm_ops = { | |
851 | .runtime_suspend = hdmi_runtime_suspend, | |
852 | .runtime_resume = hdmi_runtime_resume, | |
853 | }; | |
854 | ||
c3198a5e M |
855 | static struct platform_driver omapdss_hdmihw_driver = { |
856 | .probe = omapdss_hdmihw_probe, | |
857 | .remove = omapdss_hdmihw_remove, | |
858 | .driver = { | |
859 | .name = "omapdss_hdmi", | |
860 | .owner = THIS_MODULE, | |
4fbafaf3 | 861 | .pm = &hdmi_pm_ops, |
c3198a5e M |
862 | }, |
863 | }; | |
864 | ||
865 | int hdmi_init_platform_driver(void) | |
866 | { | |
867 | return platform_driver_register(&omapdss_hdmihw_driver); | |
868 | } | |
869 | ||
870 | void hdmi_uninit_platform_driver(void) | |
871 | { | |
872 | return platform_driver_unregister(&omapdss_hdmihw_driver); | |
873 | } |