projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
OMAPDSS: Add panel dev pointer to dssdev
[deliverable/linux.git] / drivers / video / omap2 / dss / hdmi.c
CommitLineData
c3198a5e
M		 1/*
2 * hdmi.c
3 *
4 * HDMI interface DSS driver setting for TI's OMAP4 family of processor.
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
6 * Authors: Yong Zhi
7 * Mythri pk <mythripk@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#define DSS_SUBSYS_NAME "HDMI"
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/err.h>
27#include <linux/io.h>
28#include <linux/interrupt.h>
29#include <linux/mutex.h>
30#include <linux/delay.h>
31#include <linux/string.h>
24e6289c 32#include <linux/platform_device.h>
4fbafaf3
TV		 33#include <linux/pm_runtime.h>
34#include <linux/clk.h>
cca35017 35#include <linux/gpio.h>
17486943 36#include <linux/regulator/consumer.h>
a0b38cc4 37#include <video/omapdss.h>
c3198a5e 38
94c52987 39#include "ti_hdmi.h"
c3198a5e 40#include "dss.h"
ad44cc32 41#include "dss_features.h"
c3198a5e 42
95a8aeb6
M		 43#define HDMI_WP 0x0
44#define HDMI_CORE_SYS 0x400
45#define HDMI_CORE_AV 0x900
46#define HDMI_PLLCTRL 0x200
47#define HDMI_PHY 0x300
48
7c1f1eca
M		 49/* HDMI EDID Length move this */
50#define HDMI_EDID_MAX_LENGTH 256
51#define EDID_TIMING_DESCRIPTOR_SIZE 0x12
52#define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36
53#define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80
54#define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4
55#define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4
56
b44e4582 57#define HDMI_DEFAULT_REGN 16
8d88767a
TV		 58#define HDMI_DEFAULT_REGM2 1
59
c3198a5e
M		 60static struct {
61 struct mutex lock;
c3198a5e 62 struct platform_device *pdev;
66a06b0c 63
95a8aeb6 64 struct hdmi_ip_data ip_data;
4fbafaf3
TV		 65
66 struct clk *sys_clk;
17486943 67 struct regulator *vdda_hdmi_dac_reg;
cca35017
TV		 68
69 int ct_cp_hpd_gpio;
70 int ls_oe_gpio;
71 int hpd_gpio;
81b87f51
AT		 72
73 struct omap_dss_output output;
c3198a5e
M		 74} hdmi;
75
76/*
77 * Logic for the below structure :
78 * user enters the CEA or VESA timings by specifying the HDMI/DVI code.
79 * There is a correspondence between CEA/VESA timing and code, please
80 * refer to section 6.3 in HDMI 1.3 specification for timing code.
81 *
82 * In the below structure, cea_vesa_timings corresponds to all OMAP4
83 * supported CEA and VESA timing values.code_cea corresponds to the CEA
84 * code, It is used to get the timing from cea_vesa_timing array.Similarly
85 * with code_vesa. Code_index is used for back mapping, that is once EDID
86 * is read from the TV, EDID is parsed to find the timing values and then
87 * map it to corresponding CEA or VESA index.
88 */
89
46095b2d 90static const struct hdmi_config cea_timings[] = {
cc937e5e
AT		 91 {
92 { 640, 480, 25200, 96, 16, 48, 2, 10, 33,
93 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
94 false, },
95 { 1, HDMI_HDMI },
96 },
97 {
98 { 720, 480, 27027, 62, 16, 60, 6, 9, 30,
99 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
100 false, },
101 { 2, HDMI_HDMI },
102 },
103 {
104 { 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
105 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
106 false, },
107 { 4, HDMI_HDMI },
108 },
109 {
110 { 1920, 540, 74250, 44, 88, 148, 5, 2, 15,
111 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
112 true, },
113 { 5, HDMI_HDMI },
114 },
115 {
116 { 1440, 240, 27027, 124, 38, 114, 3, 4, 15,
117 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
118 true, },
119 { 6, HDMI_HDMI },
120 },
121 {
122 { 1920, 1080, 148500, 44, 88, 148, 5, 4, 36,
123 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
124 false, },
125 { 16, HDMI_HDMI },
126 },
127 {
128 { 720, 576, 27000, 64, 12, 68, 5, 5, 39,
129 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
130 false, },
131 { 17, HDMI_HDMI },
132 },
133 {
134 { 1280, 720, 74250, 40, 440, 220, 5, 5, 20,
135 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
136 false, },
137 { 19, HDMI_HDMI },
138 },
139 {
140 { 1920, 540, 74250, 44, 528, 148, 5, 2, 15,
141 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
142 true, },
143 { 20, HDMI_HDMI },
144 },
145 {
146 { 1440, 288, 27000, 126, 24, 138, 3, 2, 19,
147 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
148 true, },
149 { 21, HDMI_HDMI },
150 },
151 {
152 { 1440, 576, 54000, 128, 24, 136, 5, 5, 39,
153 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
154 false, },
155 { 29, HDMI_HDMI },
156 },
157 {
158 { 1920, 1080, 148500, 44, 528, 148, 5, 4, 36,
159 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
160 false, },
161 { 31, HDMI_HDMI },
162 },
163 {
164 { 1920, 1080, 74250, 44, 638, 148, 5, 4, 36,
165 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
166 false, },
167 { 32, HDMI_HDMI },
168 },
169 {
170 { 2880, 480, 108108, 248, 64, 240, 6, 9, 30,
171 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
172 false, },
173 { 35, HDMI_HDMI },
174 },
175 {
176 { 2880, 576, 108000, 256, 48, 272, 5, 5, 39,
177 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
178 false, },
179 { 37, HDMI_HDMI },
180 },
46095b2d 181};
cc937e5e 182
46095b2d 183static const struct hdmi_config vesa_timings[] = {
a05ce78f 184/* VESA From Here */
cc937e5e
AT		 185 {
186 { 640, 480, 25175, 96, 16, 48, 2, 11, 31,
187 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
188 false, },
189 { 4, HDMI_DVI },
190 },
191 {
192 { 800, 600, 40000, 128, 40, 88, 4, 1, 23,
193 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
194 false, },
195 { 9, HDMI_DVI },
196 },
197 {
198 { 848, 480, 33750, 112, 16, 112, 8, 6, 23,
199 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
200 false, },
201 { 0xE, HDMI_DVI },
202 },
203 {
204 { 1280, 768, 79500, 128, 64, 192, 7, 3, 20,
205 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
206 false, },
207 { 0x17, HDMI_DVI },
208 },
209 {
210 { 1280, 800, 83500, 128, 72, 200, 6, 3, 22,
211 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
212 false, },
213 { 0x1C, HDMI_DVI },
214 },
215 {
216 { 1360, 768, 85500, 112, 64, 256, 6, 3, 18,
217 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
218 false, },
219 { 0x27, HDMI_DVI },
220 },
221 {
222 { 1280, 960, 108000, 112, 96, 312, 3, 1, 36,
223 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
224 false, },
225 { 0x20, HDMI_DVI },
226 },
227 {
228 { 1280, 1024, 108000, 112, 48, 248, 3, 1, 38,
229 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
230 false, },
231 { 0x23, HDMI_DVI },
232 },
233 {
234 { 1024, 768, 65000, 136, 24, 160, 6, 3, 29,
235 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
236 false, },
237 { 0x10, HDMI_DVI },
238 },
239 {
240 { 1400, 1050, 121750, 144, 88, 232, 4, 3, 32,
241 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
242 false, },
243 { 0x2A, HDMI_DVI },
244 },
245 {
246 { 1440, 900, 106500, 152, 80, 232, 6, 3, 25,
247 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
248 false, },
249 { 0x2F, HDMI_DVI },
250 },
251 {
252 { 1680, 1050, 146250, 176 , 104, 280, 6, 3, 30,
253 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
254 false, },
255 { 0x3A, HDMI_DVI },
256 },
257 {
258 { 1366, 768, 85500, 143, 70, 213, 3, 3, 24,
259 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
260 false, },
261 { 0x51, HDMI_DVI },
262 },
263 {
264 { 1920, 1080, 148500, 44, 148, 80, 5, 4, 36,
265 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
266 false, },
267 { 0x52, HDMI_DVI },
268 },
269 {
270 { 1280, 768, 68250, 32, 48, 80, 7, 3, 12,
271 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
272 false, },
273 { 0x16, HDMI_DVI },
274 },
275 {
276 { 1400, 1050, 101000, 32, 48, 80, 4, 3, 23,
277 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
278 false, },
279 { 0x29, HDMI_DVI },
280 },
281 {
282 { 1680, 1050, 119000, 32, 48, 80, 6, 3, 21,
283 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
284 false, },
285 { 0x39, HDMI_DVI },
286 },
287 {
288 { 1280, 800, 79500, 32, 48, 80, 6, 3, 14,
289 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
290 false, },
291 { 0x1B, HDMI_DVI },
292 },
293 {
294 { 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
295 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
296 false, },
297 { 0x55, HDMI_DVI },
298 },
7a7ce2c7
TV		 299 {
300 { 1920, 1200, 154000, 32, 48, 80, 6, 3, 26,
301 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
302 false, },
303 { 0x44, HDMI_DVI },
304 },
c3198a5e
M		 305};
306
4fbafaf3
TV		 307static int hdmi_runtime_get(void)
308{
309 int r;
310
311 DSSDBG("hdmi_runtime_get\n");
312
313 r = pm_runtime_get_sync(&hdmi.pdev->dev);
314 WARN_ON(r < 0);
a247ce78 315 if (r < 0)
852f0838 316 return r;
a247ce78
AT		 317
318 return 0;
4fbafaf3
TV		 319}
320
321static void hdmi_runtime_put(void)
322{
323 int r;
324
325 DSSDBG("hdmi_runtime_put\n");
326
0eaf9f52 327 r = pm_runtime_put_sync(&hdmi.pdev->dev);
5be3aebd 328 WARN_ON(r < 0 && r != -ENOSYS);
4fbafaf3
TV		 329}
330
e25001d8
TV		 331static int hdmi_init_regulator(void)
332{
333 struct regulator *reg;
334
335 if (hdmi.vdda_hdmi_dac_reg != NULL)
336 return 0;
337
338 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda_hdmi_dac");
339
340 /* DT HACK: try VDAC to make omapdss work for o4 sdp/panda */
341 if (IS_ERR(reg))
342 reg = devm_regulator_get(&hdmi.pdev->dev, "VDAC");
343
344 if (IS_ERR(reg)) {
345 DSSERR("can't get VDDA_HDMI_DAC regulator\n");
346 return PTR_ERR(reg);
347 }
348
349 hdmi.vdda_hdmi_dac_reg = reg;
350
351 return 0;
352}
353
17ae4e8c 354static int hdmi_init_display(struct omap_dss_device *dssdev)
c3198a5e 355{
cca35017
TV		 356 int r;
357
358 struct gpio gpios[] = {
359 { hdmi.ct_cp_hpd_gpio, GPIOF_OUT_INIT_LOW, "hdmi_ct_cp_hpd" },
360 { hdmi.ls_oe_gpio, GPIOF_OUT_INIT_LOW, "hdmi_ls_oe" },
361 { hdmi.hpd_gpio, GPIOF_DIR_IN, "hdmi_hpd" },
362 };
363
c3198a5e
M		 364 DSSDBG("init_display\n");
365
b2c7d54f 366 dss_init_hdmi_ip_ops(&hdmi.ip_data, omapdss_get_version());
cca35017 367
e25001d8
TV		 368 r = hdmi_init_regulator();
369 if (r)
370 return r;
17486943 371
cca35017
TV		 372 r = gpio_request_array(gpios, ARRAY_SIZE(gpios));
373 if (r)
374 return r;
375
c3198a5e
M		 376 return 0;
377}
378
37584765 379static void hdmi_uninit_display(struct omap_dss_device *dssdev)
cca35017
TV		 380{
381 DSSDBG("uninit_display\n");
382
383 gpio_free(hdmi.ct_cp_hpd_gpio);
384 gpio_free(hdmi.ls_oe_gpio);
385 gpio_free(hdmi.hpd_gpio);
386}
387
46095b2d
M		 388static const struct hdmi_config *hdmi_find_timing(
389 const struct hdmi_config *timings_arr,
390 int len)
c3198a5e 391{
46095b2d 392 int i;
c3198a5e 393
46095b2d 394 for (i = 0; i < len; i++) {
9e4ed603 395 if (timings_arr[i].cm.code == hdmi.ip_data.cfg.cm.code)
46095b2d
M		 396 return &timings_arr[i];
397 }
398 return NULL;
399}
c3198a5e 400
46095b2d
M		 401static const struct hdmi_config *hdmi_get_timings(void)
402{
403 const struct hdmi_config *arr;
404 int len;
405
9e4ed603 406 if (hdmi.ip_data.cfg.cm.mode == HDMI_DVI) {
46095b2d
M		 407 arr = vesa_timings;
408 len = ARRAY_SIZE(vesa_timings);
409 } else {
410 arr = cea_timings;
411 len = ARRAY_SIZE(cea_timings);
412 }
413
414 return hdmi_find_timing(arr, len);
415}
416
417static bool hdmi_timings_compare(struct omap_video_timings *timing1,
cc937e5e 418 const struct omap_video_timings *timing2)
46095b2d
M		 419{
420 int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync;
421
f236b892
TV		 422 if ((DIV_ROUND_CLOSEST(timing2->pixel_clock, 1000) ==
423 DIV_ROUND_CLOSEST(timing1->pixel_clock, 1000)) &&
46095b2d
M		 424 (timing2->x_res == timing1->x_res) &&
425 (timing2->y_res == timing1->y_res)) {
c3198a5e 426
46095b2d
M		 427 timing2_hsync = timing2->hfp + timing2->hsw + timing2->hbp;
428 timing1_hsync = timing1->hfp + timing1->hsw + timing1->hbp;
429 timing2_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
430 timing1_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
431
432 DSSDBG("timing1_hsync = %d timing1_vsync = %d"\
433 "timing2_hsync = %d timing2_vsync = %d\n",
434 timing1_hsync, timing1_vsync,
435 timing2_hsync, timing2_vsync);
436
437 if ((timing1_hsync == timing2_hsync) &&
438 (timing1_vsync == timing2_vsync)) {
439 return true;
440 }
c3198a5e 441 }
46095b2d 442 return false;
c3198a5e
M		 443}
444
445static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing)
446{
46095b2d 447 int i;
c3198a5e
M		 448 struct hdmi_cm cm = {-1};
449 DSSDBG("hdmi_get_code\n");
450
46095b2d
M		 451 for (i = 0; i < ARRAY_SIZE(cea_timings); i++) {
452 if (hdmi_timings_compare(timing, &cea_timings[i].timings)) {
453 cm = cea_timings[i].cm;
454 goto end;
455 }
456 }
457 for (i = 0; i < ARRAY_SIZE(vesa_timings); i++) {
458 if (hdmi_timings_compare(timing, &vesa_timings[i].timings)) {
459 cm = vesa_timings[i].cm;
460 goto end;
c3198a5e
M		 461 }
462 }
463
46095b2d 464end: return cm;
c3198a5e 465
c3198a5e
M		 466}
467
c3dc6a7a
AT		 468unsigned long hdmi_get_pixel_clock(void)
469{
470 /* HDMI Pixel Clock in Mhz */
a05ce78f 471 return hdmi.ip_data.cfg.timings.pixel_clock * 1000;
c3dc6a7a
AT		 472}
473
6cb07b25
AT		 474static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
475 struct hdmi_pll_info *pi)
c3198a5e 476{
6cb07b25 477 unsigned long clkin, refclk;
c3198a5e
M		 478 u32 mf;
479
4fbafaf3 480 clkin = clk_get_rate(hdmi.sys_clk) / 10000;
c3198a5e
M		 481 /*
482 * Input clock is predivided by N + 1
483 * out put of which is reference clk
484 */
4fdfdf06
TV		 485
486 pi->regn = HDMI_DEFAULT_REGN;
8d88767a 487
b44e4582 488 refclk = clkin / pi->regn;
c3198a5e 489
4fdfdf06 490 pi->regm2 = HDMI_DEFAULT_REGM2;
c3198a5e 491
dd2116a3
M		 492 /*
493 * multiplier is pixel_clk/ref_clk
494 * Multiplying by 100 to avoid fractional part removal
495 */
496 pi->regm = phy * pi->regm2 / refclk;
497
c3198a5e
M		 498 /*
499 * fractional multiplier is remainder of the difference between
500 * multiplier and actual phy(required pixel clock thus should be
501 * multiplied by 2^18(262144) divided by the reference clock
502 */
dd2116a3
M		 503 mf = (phy - pi->regm / pi->regm2 * refclk) * 262144;
504 pi->regmf = pi->regm2 * mf / refclk;
c3198a5e
M		 505
506 /*
507 * Dcofreq should be set to 1 if required pixel clock
508 * is greater than 1000MHz
509 */
510 pi->dcofreq = phy > 1000 * 100;
b44e4582 511 pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10;
c3198a5e 512
7b27da54
M		 513 /* Set the reference clock to sysclk reference */
514 pi->refsel = HDMI_REFSEL_SYSCLK;
515
c3198a5e
M		 516 DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
517 DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
518}
519
bb426fc9 520static int hdmi_power_on_core(struct omap_dss_device *dssdev)
c3198a5e 521{
46095b2d 522 int r;
c3198a5e 523
cca35017
TV		 524 gpio_set_value(hdmi.ct_cp_hpd_gpio, 1);
525 gpio_set_value(hdmi.ls_oe_gpio, 1);
526
a84b2065
TV		 527 /* wait 300us after CT_CP_HPD for the 5V power output to reach 90% */
528 udelay(300);
529
17486943
TV		 530 r = regulator_enable(hdmi.vdda_hdmi_dac_reg);
531 if (r)
532 goto err_vdac_enable;
533
4fbafaf3
TV		 534 r = hdmi_runtime_get();
535 if (r)
cca35017 536 goto err_runtime_get;
c3198a5e 537
bb426fc9
TV		 538 /* Make selection of HDMI in DSS */
539 dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
540
bb426fc9
TV		 541 return 0;
542
543err_runtime_get:
544 regulator_disable(hdmi.vdda_hdmi_dac_reg);
545err_vdac_enable:
546 gpio_set_value(hdmi.ct_cp_hpd_gpio, 0);
547 gpio_set_value(hdmi.ls_oe_gpio, 0);
548 return r;
549}
550
551static void hdmi_power_off_core(struct omap_dss_device *dssdev)
552{
553 hdmi_runtime_put();
554 regulator_disable(hdmi.vdda_hdmi_dac_reg);
555 gpio_set_value(hdmi.ct_cp_hpd_gpio, 0);
556 gpio_set_value(hdmi.ls_oe_gpio, 0);
557}
558
559static int hdmi_power_on_full(struct omap_dss_device *dssdev)
560{
561 int r;
562 struct omap_video_timings *p;
7ae9a71e 563 struct omap_overlay_manager *mgr = hdmi.output.manager;
bb426fc9
TV		 564 unsigned long phy;
565
566 r = hdmi_power_on_core(dssdev);
567 if (r)
568 return r;
569
cea87b92 570 dss_mgr_disable(mgr);
c3198a5e 571
7849398f 572 p = &hdmi.ip_data.cfg.timings;
c3198a5e 573
7849398f 574 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
c3198a5e 575
c3198a5e
M		 576 phy = p->pixel_clock;
577
7b27da54 578 hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data);
c3198a5e 579
c0456be3 580 hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
c3198a5e 581
95a8aeb6 582 /* config the PLL and PHY hdmi_set_pll_pwrfirst */
60634a28 583 r = hdmi.ip_data.ops->pll_enable(&hdmi.ip_data);
c3198a5e
M		 584 if (r) {
585 DSSDBG("Failed to lock PLL\n");
cca35017 586 goto err_pll_enable;
c3198a5e
M		 587 }
588
60634a28 589 r = hdmi.ip_data.ops->phy_enable(&hdmi.ip_data);
c3198a5e
M		 590 if (r) {
591 DSSDBG("Failed to start PHY\n");
d3b4aa51 592 goto err_phy_enable;
c3198a5e
M		 593 }
594
60634a28 595 hdmi.ip_data.ops->video_configure(&hdmi.ip_data);
c3198a5e 596
c3198a5e
M		 597 /* bypass TV gamma table */
598 dispc_enable_gamma_table(0);
599
600 /* tv size */
cea87b92 601 dss_mgr_set_timings(mgr, p);
c3198a5e 602
c0456be3
RN		 603 r = hdmi.ip_data.ops->video_enable(&hdmi.ip_data);
604 if (r)
605 goto err_vid_enable;
c3198a5e 606
cea87b92 607 r = dss_mgr_enable(mgr);
33ca237f
TV		 608 if (r)
609 goto err_mgr_enable;
3870c909 610
c3198a5e 611 return 0;
33ca237f
TV		 612
613err_mgr_enable:
c0456be3
RN		 614 hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
615err_vid_enable:
33ca237f 616 hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
d3b4aa51 617err_phy_enable:
33ca237f 618 hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
cca35017 619err_pll_enable:
bb426fc9 620 hdmi_power_off_core(dssdev);
c3198a5e
M		 621 return -EIO;
622}
623
bb426fc9 624static void hdmi_power_off_full(struct omap_dss_device *dssdev)
c3198a5e 625{
7ae9a71e 626 struct omap_overlay_manager *mgr = hdmi.output.manager;
cea87b92
AT		 627
628 dss_mgr_disable(mgr);
c3198a5e 629
c0456be3 630 hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
60634a28
M		 631 hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
632 hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
17486943 633
bb426fc9 634 hdmi_power_off_core(dssdev);
c3198a5e
M		 635}
636
637int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
638 struct omap_video_timings *timings)
639{
640 struct hdmi_cm cm;
641
642 cm = hdmi_get_code(timings);
643 if (cm.code == -1) {
c3198a5e
M		 644 return -EINVAL;
645 }
646
647 return 0;
648
649}
650
7849398f
AT		 651void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev,
652 struct omap_video_timings *timings)
c3198a5e
M		 653{
654 struct hdmi_cm cm;
7849398f 655 const struct hdmi_config *t;
c3198a5e 656
ed1aa900
AT		 657 mutex_lock(&hdmi.lock);
658
7849398f
AT		 659 cm = hdmi_get_code(timings);
660 hdmi.ip_data.cfg.cm = cm;
661
662 t = hdmi_get_timings();
663 if (t != NULL)
664 hdmi.ip_data.cfg = *t;
fa70dc5f 665
ed1aa900 666 mutex_unlock(&hdmi.lock);
c3198a5e
M		 667}
668
e40402cf 669static void hdmi_dump_regs(struct seq_file *s)
162874d5
M		 670{
671 mutex_lock(&hdmi.lock);
672
f8fb7d7b
WY		 673 if (hdmi_runtime_get()) {
674 mutex_unlock(&hdmi.lock);
162874d5 675 return;
f8fb7d7b 676 }
162874d5
M		 677
678 hdmi.ip_data.ops->dump_wrapper(&hdmi.ip_data, s);
679 hdmi.ip_data.ops->dump_pll(&hdmi.ip_data, s);
680 hdmi.ip_data.ops->dump_phy(&hdmi.ip_data, s);
681 hdmi.ip_data.ops->dump_core(&hdmi.ip_data, s);
682
683 hdmi_runtime_put();
684 mutex_unlock(&hdmi.lock);
685}
686
47024565
TV		 687int omapdss_hdmi_read_edid(u8 *buf, int len)
688{
689 int r;
690
691 mutex_lock(&hdmi.lock);
692
693 r = hdmi_runtime_get();
694 BUG_ON(r);
695
696 r = hdmi.ip_data.ops->read_edid(&hdmi.ip_data, buf, len);
697
698 hdmi_runtime_put();
699 mutex_unlock(&hdmi.lock);
700
701 return r;
702}
703
759593ff
TV		 704bool omapdss_hdmi_detect(void)
705{
706 int r;
707
708 mutex_lock(&hdmi.lock);
709
710 r = hdmi_runtime_get();
711 BUG_ON(r);
712
713 r = hdmi.ip_data.ops->detect(&hdmi.ip_data);
714
715 hdmi_runtime_put();
716 mutex_unlock(&hdmi.lock);
717
718 return r == 1;
719}
720
c3198a5e
M		 721int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev)
722{
7ae9a71e 723 struct omap_dss_output *out = &hdmi.output;
c3198a5e
M		 724 int r = 0;
725
726 DSSDBG("ENTER hdmi_display_enable\n");
727
728 mutex_lock(&hdmi.lock);
729
cea87b92
AT		 730 if (out == NULL || out->manager == NULL) {
731 DSSERR("failed to enable display: no output/manager\n");
05e1d606
TV		 732 r = -ENODEV;
733 goto err0;
734 }
735
cca35017 736 hdmi.ip_data.hpd_gpio = hdmi.hpd_gpio;
c49d005b 737
c3198a5e
M		 738 r = omap_dss_start_device(dssdev);
739 if (r) {
740 DSSERR("failed to start device\n");
741 goto err0;
742 }
743
bb426fc9 744 r = hdmi_power_on_full(dssdev);
c3198a5e
M		 745 if (r) {
746 DSSERR("failed to power on device\n");
cca35017 747 goto err1;
c3198a5e
M		 748 }
749
750 mutex_unlock(&hdmi.lock);
751 return 0;
752
c3198a5e
M		 753err1:
754 omap_dss_stop_device(dssdev);
755err0:
756 mutex_unlock(&hdmi.lock);
757 return r;
758}
759
760void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev)
761{
762 DSSDBG("Enter hdmi_display_disable\n");
763
764 mutex_lock(&hdmi.lock);
765
bb426fc9 766 hdmi_power_off_full(dssdev);
c3198a5e 767
c3198a5e
M		 768 omap_dss_stop_device(dssdev);
769
770 mutex_unlock(&hdmi.lock);
771}
772
4489823c
TV		 773int omapdss_hdmi_core_enable(struct omap_dss_device *dssdev)
774{
775 int r = 0;
776
777 DSSDBG("ENTER omapdss_hdmi_core_enable\n");
778
779 mutex_lock(&hdmi.lock);
780
781 hdmi.ip_data.hpd_gpio = hdmi.hpd_gpio;
782
783 r = hdmi_power_on_core(dssdev);
784 if (r) {
785 DSSERR("failed to power on device\n");
786 goto err0;
787 }
788
789 mutex_unlock(&hdmi.lock);
790 return 0;
791
792err0:
793 mutex_unlock(&hdmi.lock);
794 return r;
795}
796
797void omapdss_hdmi_core_disable(struct omap_dss_device *dssdev)
798{
799 DSSDBG("Enter omapdss_hdmi_core_disable\n");
800
801 mutex_lock(&hdmi.lock);
802
803 hdmi_power_off_core(dssdev);
804
805 mutex_unlock(&hdmi.lock);
806}
807
4fbafaf3
TV		 808static int hdmi_get_clocks(struct platform_device *pdev)
809{
810 struct clk *clk;
811
b2c9c8ee 812 clk = devm_clk_get(&pdev->dev, "sys_clk");
4fbafaf3
TV		 813 if (IS_ERR(clk)) {
814 DSSERR("can't get sys_clk\n");
815 return PTR_ERR(clk);
816 }
817
818 hdmi.sys_clk = clk;
819
4fbafaf3
TV		 820 return 0;
821}
822
35547626
RN		 823#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
824int hdmi_compute_acr(u32 sample_freq, u32 *n, u32 *cts)
825{
826 u32 deep_color;
25a65359 827 bool deep_color_correct = false;
35547626
RN		 828 u32 pclk = hdmi.ip_data.cfg.timings.pixel_clock;
829
830 if (n == NULL || cts == NULL)
831 return -EINVAL;
832
833 /* TODO: When implemented, query deep color mode here. */
834 deep_color = 100;
835
25a65359
RN		 836 /*
837 * When using deep color, the default N value (as in the HDMI
838 * specification) yields to an non-integer CTS. Hence, we
839 * modify it while keeping the restrictions described in
840 * section 7.2.1 of the HDMI 1.4a specification.
841 */
35547626
RN		 842 switch (sample_freq) {
843 case 32000:
25a65359
RN		 844 case 48000:
845 case 96000:
846 case 192000:
847 if (deep_color == 125)
848 if (pclk == 27027 || pclk == 74250)
849 deep_color_correct = true;
850 if (deep_color == 150)
851 if (pclk == 27027)
852 deep_color_correct = true;
35547626
RN		 853 break;
854 case 44100:
25a65359
RN		 855 case 88200:
856 case 176400:
857 if (deep_color == 125)
858 if (pclk == 27027)
859 deep_color_correct = true;
35547626
RN		 860 break;
861 default:
35547626
RN		 862 return -EINVAL;
863 }
864
25a65359
RN		 865 if (deep_color_correct) {
866 switch (sample_freq) {
867 case 32000:
868 *n = 8192;
869 break;
870 case 44100:
871 *n = 12544;
872 break;
873 case 48000:
874 *n = 8192;
875 break;
876 case 88200:
877 *n = 25088;
878 break;
879 case 96000:
880 *n = 16384;
881 break;
882 case 176400:
883 *n = 50176;
884 break;
885 case 192000:
886 *n = 32768;
887 break;
888 default:
889 return -EINVAL;
890 }
891 } else {
892 switch (sample_freq) {
893 case 32000:
894 *n = 4096;
895 break;
896 case 44100:
897 *n = 6272;
898 break;
899 case 48000:
900 *n = 6144;
901 break;
902 case 88200:
903 *n = 12544;
904 break;
905 case 96000:
906 *n = 12288;
907 break;
908 case 176400:
909 *n = 25088;
910 break;
911 case 192000:
912 *n = 24576;
913 break;
914 default:
915 return -EINVAL;
916 }
917 }
35547626
RN		 918 /* Calculate CTS. See HDMI 1.3a or 1.4a specifications */
919 *cts = pclk * (*n / 128) * deep_color / (sample_freq / 10);
920
921 return 0;
922}
f3a97491
RN		 923
924int hdmi_audio_enable(void)
925{
926 DSSDBG("audio_enable\n");
927
928 return hdmi.ip_data.ops->audio_enable(&hdmi.ip_data);
929}
930
931void hdmi_audio_disable(void)
932{
933 DSSDBG("audio_disable\n");
934
935 hdmi.ip_data.ops->audio_disable(&hdmi.ip_data);
936}
937
938int hdmi_audio_start(void)
939{
940 DSSDBG("audio_start\n");
941
942 return hdmi.ip_data.ops->audio_start(&hdmi.ip_data);
943}
944
945void hdmi_audio_stop(void)
946{
947 DSSDBG("audio_stop\n");
948
949 hdmi.ip_data.ops->audio_stop(&hdmi.ip_data);
950}
951
952bool hdmi_mode_has_audio(void)
953{
954 if (hdmi.ip_data.cfg.cm.mode == HDMI_HDMI)
955 return true;
956 else
957 return false;
958}
959
960int hdmi_audio_config(struct omap_dss_audio *audio)
961{
962 return hdmi.ip_data.ops->audio_config(&hdmi.ip_data, audio);
963}
964
35547626
RN		 965#endif
966
17ae4e8c 967static struct omap_dss_device *hdmi_find_dssdev(struct platform_device *pdev)
38f3daf6
TV		 968{
969 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
2bbcce5e 970 const char *def_disp_name = omapdss_get_default_display_name();
1521653c
TV		 971 struct omap_dss_device *def_dssdev;
972 int i;
973
974 def_dssdev = NULL;
38f3daf6
TV		 975
976 for (i = 0; i < pdata->num_devices; ++i) {
977 struct omap_dss_device *dssdev = pdata->devices[i];
978
979 if (dssdev->type != OMAP_DISPLAY_TYPE_HDMI)
980 continue;
981
1521653c
TV		 982 if (def_dssdev == NULL)
983 def_dssdev = dssdev;
cca35017 984
1521653c
TV		 985 if (def_disp_name != NULL &&
986 strcmp(dssdev->name, def_disp_name) == 0) {
987 def_dssdev = dssdev;
988 break;
38f3daf6 989 }
1521653c
TV		 990 }
991
992 return def_dssdev;
993}
994
c0980297 995static int hdmi_probe_pdata(struct platform_device *pdev)
1521653c 996{
5274484b 997 struct omap_dss_device *plat_dssdev;
1521653c
TV		 998 struct omap_dss_device *dssdev;
999 struct omap_dss_hdmi_data *priv;
1000 int r;
38f3daf6 1001
5274484b 1002 plat_dssdev = hdmi_find_dssdev(pdev);
1521653c 1003
5274484b 1004 if (!plat_dssdev)
c0980297 1005 return 0;
5274484b
TV		 1006
1007 dssdev = dss_alloc_and_init_device(&pdev->dev);
1521653c 1008 if (!dssdev)
c0980297 1009 return -ENOMEM;
1521653c 1010
5274484b
TV		 1011 dss_copy_device_pdata(dssdev, plat_dssdev);
1012
1521653c
TV		 1013 priv = dssdev->data;
1014
1015 hdmi.ct_cp_hpd_gpio = priv->ct_cp_hpd_gpio;
1016 hdmi.ls_oe_gpio = priv->ls_oe_gpio;
1017 hdmi.hpd_gpio = priv->hpd_gpio;
1018
1019 r = hdmi_init_display(dssdev);
1020 if (r) {
1021 DSSERR("device %s init failed: %d\n", dssdev->name, r);
5274484b 1022 dss_put_device(dssdev);
c0980297 1023 return r;
1521653c
TV		 1024 }
1025
486c0e17
TV		 1026 r = omapdss_output_set_device(&hdmi.output, dssdev);
1027 if (r) {
1028 DSSERR("failed to connect output to new device: %s\n",
1029 dssdev->name);
1030 dss_put_device(dssdev);
c0980297 1031 return r;
486c0e17
TV		 1032 }
1033
5274484b 1034 r = dss_add_device(dssdev);
1521653c
TV		 1035 if (r) {
1036 DSSERR("device %s register failed: %d\n", dssdev->name, r);
486c0e17 1037 omapdss_output_unset_device(&hdmi.output);
d18bc455 1038 hdmi_uninit_display(dssdev);
5274484b 1039 dss_put_device(dssdev);
c0980297 1040 return r;
38f3daf6 1041 }
c0980297
TV		 1042
1043 return 0;
38f3daf6
TV		 1044}
1045
17ae4e8c 1046static void hdmi_init_output(struct platform_device *pdev)
81b87f51
AT		 1047{
1048 struct omap_dss_output *out = &hdmi.output;
1049
1050 out->pdev = pdev;
1051 out->id = OMAP_DSS_OUTPUT_HDMI;
1052 out->type = OMAP_DISPLAY_TYPE_HDMI;
7286a08f 1053 out->name = "hdmi.0";
2eea5ae6 1054 out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
81b87f51
AT		 1055
1056 dss_register_output(out);
1057}
1058
1059static void __exit hdmi_uninit_output(struct platform_device *pdev)
1060{
1061 struct omap_dss_output *out = &hdmi.output;
1062
1063 dss_unregister_output(out);
1064}
1065
c3198a5e 1066/* HDMI HW IP initialisation */
17ae4e8c 1067static int omapdss_hdmihw_probe(struct platform_device *pdev)
c3198a5e 1068{
af23cb35 1069 struct resource *res;
38f3daf6 1070 int r;
c3198a5e 1071
c3198a5e
M		 1072 hdmi.pdev = pdev;
1073
1074 mutex_init(&hdmi.lock);
66a06b0c 1075 mutex_init(&hdmi.ip_data.lock);
c3198a5e 1076
af23cb35 1077 res = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0);
c3198a5e
M		 1078
1079 /* Base address taken from platform */
bc3bad16
TR		 1080 hdmi.ip_data.base_wp = devm_ioremap_resource(&pdev->dev, res);
1081 if (IS_ERR(hdmi.ip_data.base_wp))
1082 return PTR_ERR(hdmi.ip_data.base_wp);
c3198a5e 1083
4fbafaf3
TV		 1084 r = hdmi_get_clocks(pdev);
1085 if (r) {
47e443bc 1086 DSSERR("can't get clocks\n");
4fbafaf3
TV		 1087 return r;
1088 }
1089
1090 pm_runtime_enable(&pdev->dev);
1091
95a8aeb6
M		 1092 hdmi.ip_data.core_sys_offset = HDMI_CORE_SYS;
1093 hdmi.ip_data.core_av_offset = HDMI_CORE_AV;
1094 hdmi.ip_data.pll_offset = HDMI_PLLCTRL;
1095 hdmi.ip_data.phy_offset = HDMI_PHY;
7849398f 1096
002d368d
TV		 1097 hdmi_init_output(pdev);
1098
66a06b0c
RN		 1099 r = hdmi_panel_init();
1100 if (r) {
1101 DSSERR("can't init panel\n");
b2c9c8ee 1102 return r;
66a06b0c 1103 }
c3198a5e 1104
e40402cf
TV		 1105 dss_debugfs_create_file("hdmi", hdmi_dump_regs);
1106
c6ca5b22
TV		 1107 if (pdev->dev.platform_data) {
1108 r = hdmi_probe_pdata(pdev);
1109 if (r)
1110 goto err_probe;
c0980297 1111 }
35deca3d 1112
c3198a5e 1113 return 0;
c6ca5b22
TV		 1114
1115err_probe:
1116 hdmi_panel_exit();
1117 hdmi_uninit_output(pdev);
1118 pm_runtime_disable(&pdev->dev);
1119 return r;
c3198a5e
M		 1120}
1121
cca35017
TV		 1122static int __exit hdmi_remove_child(struct device *dev, void *data)
1123{
1124 struct omap_dss_device *dssdev = to_dss_device(dev);
1125 hdmi_uninit_display(dssdev);
1126 return 0;
1127}
1128
6e7e8f06 1129static int __exit omapdss_hdmihw_remove(struct platform_device *pdev)
c3198a5e 1130{
cca35017
TV		 1131 device_for_each_child(&pdev->dev, NULL, hdmi_remove_child);
1132
5274484b 1133 dss_unregister_child_devices(&pdev->dev);
35deca3d 1134
c3198a5e
M		 1135 hdmi_panel_exit();
1136
81b87f51
AT		 1137 hdmi_uninit_output(pdev);
1138
4fbafaf3
TV		 1139 pm_runtime_disable(&pdev->dev);
1140
c3198a5e
M		 1141 return 0;
1142}
1143
4fbafaf3
TV		 1144static int hdmi_runtime_suspend(struct device *dev)
1145{
f11766d1 1146 clk_disable_unprepare(hdmi.sys_clk);
4fbafaf3
TV		 1147
1148 dispc_runtime_put();
4fbafaf3
TV		 1149
1150 return 0;
1151}
1152
1153static int hdmi_runtime_resume(struct device *dev)
1154{
1155 int r;
1156
4fbafaf3
TV		 1157 r = dispc_runtime_get();
1158 if (r < 0)
852f0838 1159 return r;
4fbafaf3 1160
f11766d1 1161 clk_prepare_enable(hdmi.sys_clk);
4fbafaf3
TV		 1162
1163 return 0;
4fbafaf3
TV		 1164}
1165
1166static const struct dev_pm_ops hdmi_pm_ops = {
1167 .runtime_suspend = hdmi_runtime_suspend,
1168 .runtime_resume = hdmi_runtime_resume,
1169};
1170
c3198a5e 1171static struct platform_driver omapdss_hdmihw_driver = {
17ae4e8c 1172 .probe = omapdss_hdmihw_probe,
6e7e8f06 1173 .remove = __exit_p(omapdss_hdmihw_remove),
c3198a5e
M		 1174 .driver = {
1175 .name = "omapdss_hdmi",
1176 .owner = THIS_MODULE,
4fbafaf3 1177 .pm = &hdmi_pm_ops,
c3198a5e
M		 1178 },
1179};
1180
6e7e8f06 1181int __init hdmi_init_platform_driver(void)
c3198a5e 1182{
17ae4e8c 1183 return platform_driver_register(&omapdss_hdmihw_driver);
c3198a5e
M		 1184}
1185
6e7e8f06 1186void __exit hdmi_uninit_platform_driver(void)
c3198a5e 1187{
04c742c3 1188 platform_driver_unregister(&omapdss_hdmihw_driver);
c3198a5e 1189}
Linux kernel - Deliverables
This page took 0.334524 seconds and 5 git commands to generate.