Commit | Line | Data |
---|---|---|
c3198a5e M |
1 | /* |
2 | * hdmi.c | |
3 | * | |
4 | * HDMI interface DSS driver setting for TI's OMAP4 family of processor. | |
5 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ | |
6 | * Authors: Yong Zhi | |
7 | * Mythri pk <mythripk@ti.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License version 2 as published by | |
11 | * the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along with | |
19 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #define DSS_SUBSYS_NAME "HDMI" | |
23 | ||
24 | #include <linux/kernel.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/err.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/mutex.h> | |
30 | #include <linux/delay.h> | |
31 | #include <linux/string.h> | |
24e6289c | 32 | #include <linux/platform_device.h> |
4fbafaf3 TV |
33 | #include <linux/pm_runtime.h> |
34 | #include <linux/clk.h> | |
a0b38cc4 | 35 | #include <video/omapdss.h> |
c3198a5e | 36 | |
94c52987 | 37 | #include "ti_hdmi.h" |
c3198a5e | 38 | #include "dss.h" |
ad44cc32 | 39 | #include "dss_features.h" |
c3198a5e | 40 | |
95a8aeb6 M |
41 | #define HDMI_WP 0x0 |
42 | #define HDMI_CORE_SYS 0x400 | |
43 | #define HDMI_CORE_AV 0x900 | |
44 | #define HDMI_PLLCTRL 0x200 | |
45 | #define HDMI_PHY 0x300 | |
46 | ||
7c1f1eca M |
47 | /* HDMI EDID Length move this */ |
48 | #define HDMI_EDID_MAX_LENGTH 256 | |
49 | #define EDID_TIMING_DESCRIPTOR_SIZE 0x12 | |
50 | #define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36 | |
51 | #define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80 | |
52 | #define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4 | |
53 | #define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4 | |
54 | ||
b44e4582 | 55 | #define HDMI_DEFAULT_REGN 16 |
8d88767a TV |
56 | #define HDMI_DEFAULT_REGM2 1 |
57 | ||
c3198a5e M |
58 | static struct { |
59 | struct mutex lock; | |
c3198a5e | 60 | struct platform_device *pdev; |
95a8aeb6 | 61 | struct hdmi_ip_data ip_data; |
4fbafaf3 TV |
62 | |
63 | struct clk *sys_clk; | |
c3198a5e M |
64 | } hdmi; |
65 | ||
66 | /* | |
67 | * Logic for the below structure : | |
68 | * user enters the CEA or VESA timings by specifying the HDMI/DVI code. | |
69 | * There is a correspondence between CEA/VESA timing and code, please | |
70 | * refer to section 6.3 in HDMI 1.3 specification for timing code. | |
71 | * | |
72 | * In the below structure, cea_vesa_timings corresponds to all OMAP4 | |
73 | * supported CEA and VESA timing values.code_cea corresponds to the CEA | |
74 | * code, It is used to get the timing from cea_vesa_timing array.Similarly | |
75 | * with code_vesa. Code_index is used for back mapping, that is once EDID | |
76 | * is read from the TV, EDID is parsed to find the timing values and then | |
77 | * map it to corresponding CEA or VESA index. | |
78 | */ | |
79 | ||
46095b2d | 80 | static const struct hdmi_config cea_timings[] = { |
cc937e5e AT |
81 | { |
82 | { 640, 480, 25200, 96, 16, 48, 2, 10, 33, | |
83 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
84 | false, }, | |
85 | { 1, HDMI_HDMI }, | |
86 | }, | |
87 | { | |
88 | { 720, 480, 27027, 62, 16, 60, 6, 9, 30, | |
89 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
90 | false, }, | |
91 | { 2, HDMI_HDMI }, | |
92 | }, | |
93 | { | |
94 | { 1280, 720, 74250, 40, 110, 220, 5, 5, 20, | |
95 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
96 | false, }, | |
97 | { 4, HDMI_HDMI }, | |
98 | }, | |
99 | { | |
100 | { 1920, 540, 74250, 44, 88, 148, 5, 2, 15, | |
101 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
102 | true, }, | |
103 | { 5, HDMI_HDMI }, | |
104 | }, | |
105 | { | |
106 | { 1440, 240, 27027, 124, 38, 114, 3, 4, 15, | |
107 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
108 | true, }, | |
109 | { 6, HDMI_HDMI }, | |
110 | }, | |
111 | { | |
112 | { 1920, 1080, 148500, 44, 88, 148, 5, 4, 36, | |
113 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
114 | false, }, | |
115 | { 16, HDMI_HDMI }, | |
116 | }, | |
117 | { | |
118 | { 720, 576, 27000, 64, 12, 68, 5, 5, 39, | |
119 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
120 | false, }, | |
121 | { 17, HDMI_HDMI }, | |
122 | }, | |
123 | { | |
124 | { 1280, 720, 74250, 40, 440, 220, 5, 5, 20, | |
125 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
126 | false, }, | |
127 | { 19, HDMI_HDMI }, | |
128 | }, | |
129 | { | |
130 | { 1920, 540, 74250, 44, 528, 148, 5, 2, 15, | |
131 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
132 | true, }, | |
133 | { 20, HDMI_HDMI }, | |
134 | }, | |
135 | { | |
136 | { 1440, 288, 27000, 126, 24, 138, 3, 2, 19, | |
137 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
138 | true, }, | |
139 | { 21, HDMI_HDMI }, | |
140 | }, | |
141 | { | |
142 | { 1440, 576, 54000, 128, 24, 136, 5, 5, 39, | |
143 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
144 | false, }, | |
145 | { 29, HDMI_HDMI }, | |
146 | }, | |
147 | { | |
148 | { 1920, 1080, 148500, 44, 528, 148, 5, 4, 36, | |
149 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
150 | false, }, | |
151 | { 31, HDMI_HDMI }, | |
152 | }, | |
153 | { | |
154 | { 1920, 1080, 74250, 44, 638, 148, 5, 4, 36, | |
155 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
156 | false, }, | |
157 | { 32, HDMI_HDMI }, | |
158 | }, | |
159 | { | |
160 | { 2880, 480, 108108, 248, 64, 240, 6, 9, 30, | |
161 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
162 | false, }, | |
163 | { 35, HDMI_HDMI }, | |
164 | }, | |
165 | { | |
166 | { 2880, 576, 108000, 256, 48, 272, 5, 5, 39, | |
167 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
168 | false, }, | |
169 | { 37, HDMI_HDMI }, | |
170 | }, | |
46095b2d | 171 | }; |
cc937e5e | 172 | |
46095b2d | 173 | static const struct hdmi_config vesa_timings[] = { |
a05ce78f | 174 | /* VESA From Here */ |
cc937e5e AT |
175 | { |
176 | { 640, 480, 25175, 96, 16, 48, 2, 11, 31, | |
177 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
178 | false, }, | |
179 | { 4, HDMI_DVI }, | |
180 | }, | |
181 | { | |
182 | { 800, 600, 40000, 128, 40, 88, 4, 1, 23, | |
183 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
184 | false, }, | |
185 | { 9, HDMI_DVI }, | |
186 | }, | |
187 | { | |
188 | { 848, 480, 33750, 112, 16, 112, 8, 6, 23, | |
189 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
190 | false, }, | |
191 | { 0xE, HDMI_DVI }, | |
192 | }, | |
193 | { | |
194 | { 1280, 768, 79500, 128, 64, 192, 7, 3, 20, | |
195 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, | |
196 | false, }, | |
197 | { 0x17, HDMI_DVI }, | |
198 | }, | |
199 | { | |
200 | { 1280, 800, 83500, 128, 72, 200, 6, 3, 22, | |
201 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, | |
202 | false, }, | |
203 | { 0x1C, HDMI_DVI }, | |
204 | }, | |
205 | { | |
206 | { 1360, 768, 85500, 112, 64, 256, 6, 3, 18, | |
207 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
208 | false, }, | |
209 | { 0x27, HDMI_DVI }, | |
210 | }, | |
211 | { | |
212 | { 1280, 960, 108000, 112, 96, 312, 3, 1, 36, | |
213 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
214 | false, }, | |
215 | { 0x20, HDMI_DVI }, | |
216 | }, | |
217 | { | |
218 | { 1280, 1024, 108000, 112, 48, 248, 3, 1, 38, | |
219 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
220 | false, }, | |
221 | { 0x23, HDMI_DVI }, | |
222 | }, | |
223 | { | |
224 | { 1024, 768, 65000, 136, 24, 160, 6, 3, 29, | |
225 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
226 | false, }, | |
227 | { 0x10, HDMI_DVI }, | |
228 | }, | |
229 | { | |
230 | { 1400, 1050, 121750, 144, 88, 232, 4, 3, 32, | |
231 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, | |
232 | false, }, | |
233 | { 0x2A, HDMI_DVI }, | |
234 | }, | |
235 | { | |
236 | { 1440, 900, 106500, 152, 80, 232, 6, 3, 25, | |
237 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, | |
238 | false, }, | |
239 | { 0x2F, HDMI_DVI }, | |
240 | }, | |
241 | { | |
242 | { 1680, 1050, 146250, 176 , 104, 280, 6, 3, 30, | |
243 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, | |
244 | false, }, | |
245 | { 0x3A, HDMI_DVI }, | |
246 | }, | |
247 | { | |
248 | { 1366, 768, 85500, 143, 70, 213, 3, 3, 24, | |
249 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
250 | false, }, | |
251 | { 0x51, HDMI_DVI }, | |
252 | }, | |
253 | { | |
254 | { 1920, 1080, 148500, 44, 148, 80, 5, 4, 36, | |
255 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
256 | false, }, | |
257 | { 0x52, HDMI_DVI }, | |
258 | }, | |
259 | { | |
260 | { 1280, 768, 68250, 32, 48, 80, 7, 3, 12, | |
261 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, | |
262 | false, }, | |
263 | { 0x16, HDMI_DVI }, | |
264 | }, | |
265 | { | |
266 | { 1400, 1050, 101000, 32, 48, 80, 4, 3, 23, | |
267 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, | |
268 | false, }, | |
269 | { 0x29, HDMI_DVI }, | |
270 | }, | |
271 | { | |
272 | { 1680, 1050, 119000, 32, 48, 80, 6, 3, 21, | |
273 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, | |
274 | false, }, | |
275 | { 0x39, HDMI_DVI }, | |
276 | }, | |
277 | { | |
278 | { 1280, 800, 79500, 32, 48, 80, 6, 3, 14, | |
279 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, | |
280 | false, }, | |
281 | { 0x1B, HDMI_DVI }, | |
282 | }, | |
283 | { | |
284 | { 1280, 720, 74250, 40, 110, 220, 5, 5, 20, | |
285 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
286 | false, }, | |
287 | { 0x55, HDMI_DVI }, | |
288 | }, | |
c3198a5e M |
289 | }; |
290 | ||
4fbafaf3 TV |
291 | static int hdmi_runtime_get(void) |
292 | { | |
293 | int r; | |
294 | ||
295 | DSSDBG("hdmi_runtime_get\n"); | |
296 | ||
297 | r = pm_runtime_get_sync(&hdmi.pdev->dev); | |
298 | WARN_ON(r < 0); | |
a247ce78 | 299 | if (r < 0) |
852f0838 | 300 | return r; |
a247ce78 AT |
301 | |
302 | return 0; | |
4fbafaf3 TV |
303 | } |
304 | ||
305 | static void hdmi_runtime_put(void) | |
306 | { | |
307 | int r; | |
308 | ||
309 | DSSDBG("hdmi_runtime_put\n"); | |
310 | ||
0eaf9f52 | 311 | r = pm_runtime_put_sync(&hdmi.pdev->dev); |
5be3aebd | 312 | WARN_ON(r < 0 && r != -ENOSYS); |
4fbafaf3 TV |
313 | } |
314 | ||
9d8232a7 | 315 | static int __init hdmi_init_display(struct omap_dss_device *dssdev) |
c3198a5e M |
316 | { |
317 | DSSDBG("init_display\n"); | |
318 | ||
60634a28 | 319 | dss_init_hdmi_ip_ops(&hdmi.ip_data); |
c3198a5e M |
320 | return 0; |
321 | } | |
322 | ||
46095b2d M |
323 | static const struct hdmi_config *hdmi_find_timing( |
324 | const struct hdmi_config *timings_arr, | |
325 | int len) | |
c3198a5e | 326 | { |
46095b2d | 327 | int i; |
c3198a5e | 328 | |
46095b2d | 329 | for (i = 0; i < len; i++) { |
9e4ed603 | 330 | if (timings_arr[i].cm.code == hdmi.ip_data.cfg.cm.code) |
46095b2d M |
331 | return &timings_arr[i]; |
332 | } | |
333 | return NULL; | |
334 | } | |
c3198a5e | 335 | |
46095b2d M |
336 | static const struct hdmi_config *hdmi_get_timings(void) |
337 | { | |
338 | const struct hdmi_config *arr; | |
339 | int len; | |
340 | ||
9e4ed603 | 341 | if (hdmi.ip_data.cfg.cm.mode == HDMI_DVI) { |
46095b2d M |
342 | arr = vesa_timings; |
343 | len = ARRAY_SIZE(vesa_timings); | |
344 | } else { | |
345 | arr = cea_timings; | |
346 | len = ARRAY_SIZE(cea_timings); | |
347 | } | |
348 | ||
349 | return hdmi_find_timing(arr, len); | |
350 | } | |
351 | ||
352 | static bool hdmi_timings_compare(struct omap_video_timings *timing1, | |
cc937e5e | 353 | const struct omap_video_timings *timing2) |
46095b2d M |
354 | { |
355 | int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync; | |
356 | ||
357 | if ((timing2->pixel_clock == timing1->pixel_clock) && | |
358 | (timing2->x_res == timing1->x_res) && | |
359 | (timing2->y_res == timing1->y_res)) { | |
c3198a5e | 360 | |
46095b2d M |
361 | timing2_hsync = timing2->hfp + timing2->hsw + timing2->hbp; |
362 | timing1_hsync = timing1->hfp + timing1->hsw + timing1->hbp; | |
363 | timing2_vsync = timing2->vfp + timing2->vsw + timing2->vbp; | |
364 | timing1_vsync = timing2->vfp + timing2->vsw + timing2->vbp; | |
365 | ||
366 | DSSDBG("timing1_hsync = %d timing1_vsync = %d"\ | |
367 | "timing2_hsync = %d timing2_vsync = %d\n", | |
368 | timing1_hsync, timing1_vsync, | |
369 | timing2_hsync, timing2_vsync); | |
370 | ||
371 | if ((timing1_hsync == timing2_hsync) && | |
372 | (timing1_vsync == timing2_vsync)) { | |
373 | return true; | |
374 | } | |
c3198a5e | 375 | } |
46095b2d | 376 | return false; |
c3198a5e M |
377 | } |
378 | ||
379 | static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing) | |
380 | { | |
46095b2d | 381 | int i; |
c3198a5e M |
382 | struct hdmi_cm cm = {-1}; |
383 | DSSDBG("hdmi_get_code\n"); | |
384 | ||
46095b2d M |
385 | for (i = 0; i < ARRAY_SIZE(cea_timings); i++) { |
386 | if (hdmi_timings_compare(timing, &cea_timings[i].timings)) { | |
387 | cm = cea_timings[i].cm; | |
388 | goto end; | |
389 | } | |
390 | } | |
391 | for (i = 0; i < ARRAY_SIZE(vesa_timings); i++) { | |
392 | if (hdmi_timings_compare(timing, &vesa_timings[i].timings)) { | |
393 | cm = vesa_timings[i].cm; | |
394 | goto end; | |
c3198a5e M |
395 | } |
396 | } | |
397 | ||
46095b2d | 398 | end: return cm; |
c3198a5e | 399 | |
c3198a5e M |
400 | } |
401 | ||
c3dc6a7a AT |
402 | unsigned long hdmi_get_pixel_clock(void) |
403 | { | |
404 | /* HDMI Pixel Clock in Mhz */ | |
a05ce78f | 405 | return hdmi.ip_data.cfg.timings.pixel_clock * 1000; |
c3dc6a7a AT |
406 | } |
407 | ||
6cb07b25 AT |
408 | static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy, |
409 | struct hdmi_pll_info *pi) | |
c3198a5e | 410 | { |
6cb07b25 | 411 | unsigned long clkin, refclk; |
c3198a5e M |
412 | u32 mf; |
413 | ||
4fbafaf3 | 414 | clkin = clk_get_rate(hdmi.sys_clk) / 10000; |
c3198a5e M |
415 | /* |
416 | * Input clock is predivided by N + 1 | |
417 | * out put of which is reference clk | |
418 | */ | |
8d88767a TV |
419 | if (dssdev->clocks.hdmi.regn == 0) |
420 | pi->regn = HDMI_DEFAULT_REGN; | |
421 | else | |
422 | pi->regn = dssdev->clocks.hdmi.regn; | |
423 | ||
b44e4582 | 424 | refclk = clkin / pi->regn; |
c3198a5e | 425 | |
8d88767a TV |
426 | if (dssdev->clocks.hdmi.regm2 == 0) |
427 | pi->regm2 = HDMI_DEFAULT_REGM2; | |
428 | else | |
429 | pi->regm2 = dssdev->clocks.hdmi.regm2; | |
c3198a5e | 430 | |
dd2116a3 M |
431 | /* |
432 | * multiplier is pixel_clk/ref_clk | |
433 | * Multiplying by 100 to avoid fractional part removal | |
434 | */ | |
435 | pi->regm = phy * pi->regm2 / refclk; | |
436 | ||
c3198a5e M |
437 | /* |
438 | * fractional multiplier is remainder of the difference between | |
439 | * multiplier and actual phy(required pixel clock thus should be | |
440 | * multiplied by 2^18(262144) divided by the reference clock | |
441 | */ | |
dd2116a3 M |
442 | mf = (phy - pi->regm / pi->regm2 * refclk) * 262144; |
443 | pi->regmf = pi->regm2 * mf / refclk; | |
c3198a5e M |
444 | |
445 | /* | |
446 | * Dcofreq should be set to 1 if required pixel clock | |
447 | * is greater than 1000MHz | |
448 | */ | |
449 | pi->dcofreq = phy > 1000 * 100; | |
b44e4582 | 450 | pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10; |
c3198a5e | 451 | |
7b27da54 M |
452 | /* Set the reference clock to sysclk reference */ |
453 | pi->refsel = HDMI_REFSEL_SYSCLK; | |
454 | ||
c3198a5e M |
455 | DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf); |
456 | DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd); | |
457 | } | |
458 | ||
c3198a5e M |
459 | static int hdmi_power_on(struct omap_dss_device *dssdev) |
460 | { | |
46095b2d | 461 | int r; |
c3198a5e | 462 | struct omap_video_timings *p; |
6cb07b25 | 463 | unsigned long phy; |
c3198a5e | 464 | |
4fbafaf3 TV |
465 | r = hdmi_runtime_get(); |
466 | if (r) | |
467 | return r; | |
c3198a5e | 468 | |
7797c6da | 469 | dss_mgr_disable(dssdev->manager); |
c3198a5e | 470 | |
7849398f | 471 | p = &hdmi.ip_data.cfg.timings; |
c3198a5e | 472 | |
7849398f | 473 | DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res); |
c3198a5e | 474 | |
c3198a5e M |
475 | phy = p->pixel_clock; |
476 | ||
7b27da54 | 477 | hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data); |
c3198a5e | 478 | |
c0456be3 | 479 | hdmi.ip_data.ops->video_disable(&hdmi.ip_data); |
c3198a5e | 480 | |
95a8aeb6 | 481 | /* config the PLL and PHY hdmi_set_pll_pwrfirst */ |
60634a28 | 482 | r = hdmi.ip_data.ops->pll_enable(&hdmi.ip_data); |
c3198a5e M |
483 | if (r) { |
484 | DSSDBG("Failed to lock PLL\n"); | |
485 | goto err; | |
486 | } | |
487 | ||
60634a28 | 488 | r = hdmi.ip_data.ops->phy_enable(&hdmi.ip_data); |
c3198a5e M |
489 | if (r) { |
490 | DSSDBG("Failed to start PHY\n"); | |
d3b4aa51 | 491 | goto err_phy_enable; |
c3198a5e M |
492 | } |
493 | ||
60634a28 | 494 | hdmi.ip_data.ops->video_configure(&hdmi.ip_data); |
c3198a5e M |
495 | |
496 | /* Make selection of HDMI in DSS */ | |
497 | dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK); | |
498 | ||
499 | /* Select the dispc clock source as PRCM clock, to ensure that it is not | |
500 | * DSI PLL source as the clock selected by DSI PLL might not be | |
501 | * sufficient for the resolution selected / that can be changed | |
502 | * dynamically by user. This can be moved to single location , say | |
503 | * Boardfile. | |
504 | */ | |
6cb07b25 | 505 | dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src); |
c3198a5e M |
506 | |
507 | /* bypass TV gamma table */ | |
508 | dispc_enable_gamma_table(0); | |
509 | ||
510 | /* tv size */ | |
7849398f | 511 | dss_mgr_set_timings(dssdev->manager, p); |
c3198a5e | 512 | |
c0456be3 RN |
513 | r = hdmi.ip_data.ops->video_enable(&hdmi.ip_data); |
514 | if (r) | |
515 | goto err_vid_enable; | |
c3198a5e | 516 | |
33ca237f TV |
517 | r = dss_mgr_enable(dssdev->manager); |
518 | if (r) | |
519 | goto err_mgr_enable; | |
3870c909 | 520 | |
c3198a5e | 521 | return 0; |
33ca237f TV |
522 | |
523 | err_mgr_enable: | |
c0456be3 RN |
524 | hdmi.ip_data.ops->video_disable(&hdmi.ip_data); |
525 | err_vid_enable: | |
33ca237f | 526 | hdmi.ip_data.ops->phy_disable(&hdmi.ip_data); |
d3b4aa51 | 527 | err_phy_enable: |
33ca237f | 528 | hdmi.ip_data.ops->pll_disable(&hdmi.ip_data); |
c3198a5e | 529 | err: |
4fbafaf3 | 530 | hdmi_runtime_put(); |
c3198a5e M |
531 | return -EIO; |
532 | } | |
533 | ||
534 | static void hdmi_power_off(struct omap_dss_device *dssdev) | |
535 | { | |
7797c6da | 536 | dss_mgr_disable(dssdev->manager); |
c3198a5e | 537 | |
c0456be3 | 538 | hdmi.ip_data.ops->video_disable(&hdmi.ip_data); |
60634a28 M |
539 | hdmi.ip_data.ops->phy_disable(&hdmi.ip_data); |
540 | hdmi.ip_data.ops->pll_disable(&hdmi.ip_data); | |
4fbafaf3 | 541 | hdmi_runtime_put(); |
c3198a5e M |
542 | } |
543 | ||
544 | int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev, | |
545 | struct omap_video_timings *timings) | |
546 | { | |
547 | struct hdmi_cm cm; | |
548 | ||
549 | cm = hdmi_get_code(timings); | |
550 | if (cm.code == -1) { | |
c3198a5e M |
551 | return -EINVAL; |
552 | } | |
553 | ||
554 | return 0; | |
555 | ||
556 | } | |
557 | ||
7849398f AT |
558 | void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev, |
559 | struct omap_video_timings *timings) | |
c3198a5e M |
560 | { |
561 | struct hdmi_cm cm; | |
7849398f | 562 | const struct hdmi_config *t; |
c3198a5e | 563 | |
ed1aa900 AT |
564 | mutex_lock(&hdmi.lock); |
565 | ||
7849398f AT |
566 | cm = hdmi_get_code(timings); |
567 | hdmi.ip_data.cfg.cm = cm; | |
568 | ||
569 | t = hdmi_get_timings(); | |
570 | if (t != NULL) | |
571 | hdmi.ip_data.cfg = *t; | |
fa70dc5f TV |
572 | |
573 | if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) { | |
574 | int r; | |
575 | ||
576 | hdmi_power_off(dssdev); | |
577 | ||
578 | r = hdmi_power_on(dssdev); | |
579 | if (r) | |
580 | DSSERR("failed to power on device\n"); | |
fcc36619 | 581 | } else { |
7849398f | 582 | dss_mgr_set_timings(dssdev->manager, &t->timings); |
fa70dc5f | 583 | } |
ed1aa900 AT |
584 | |
585 | mutex_unlock(&hdmi.lock); | |
c3198a5e M |
586 | } |
587 | ||
e40402cf | 588 | static void hdmi_dump_regs(struct seq_file *s) |
162874d5 M |
589 | { |
590 | mutex_lock(&hdmi.lock); | |
591 | ||
592 | if (hdmi_runtime_get()) | |
593 | return; | |
594 | ||
595 | hdmi.ip_data.ops->dump_wrapper(&hdmi.ip_data, s); | |
596 | hdmi.ip_data.ops->dump_pll(&hdmi.ip_data, s); | |
597 | hdmi.ip_data.ops->dump_phy(&hdmi.ip_data, s); | |
598 | hdmi.ip_data.ops->dump_core(&hdmi.ip_data, s); | |
599 | ||
600 | hdmi_runtime_put(); | |
601 | mutex_unlock(&hdmi.lock); | |
602 | } | |
603 | ||
47024565 TV |
604 | int omapdss_hdmi_read_edid(u8 *buf, int len) |
605 | { | |
606 | int r; | |
607 | ||
608 | mutex_lock(&hdmi.lock); | |
609 | ||
610 | r = hdmi_runtime_get(); | |
611 | BUG_ON(r); | |
612 | ||
613 | r = hdmi.ip_data.ops->read_edid(&hdmi.ip_data, buf, len); | |
614 | ||
615 | hdmi_runtime_put(); | |
616 | mutex_unlock(&hdmi.lock); | |
617 | ||
618 | return r; | |
619 | } | |
620 | ||
759593ff TV |
621 | bool omapdss_hdmi_detect(void) |
622 | { | |
623 | int r; | |
624 | ||
625 | mutex_lock(&hdmi.lock); | |
626 | ||
627 | r = hdmi_runtime_get(); | |
628 | BUG_ON(r); | |
629 | ||
630 | r = hdmi.ip_data.ops->detect(&hdmi.ip_data); | |
631 | ||
632 | hdmi_runtime_put(); | |
633 | mutex_unlock(&hdmi.lock); | |
634 | ||
635 | return r == 1; | |
636 | } | |
637 | ||
c3198a5e M |
638 | int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev) |
639 | { | |
c49d005b | 640 | struct omap_dss_hdmi_data *priv = dssdev->data; |
c3198a5e M |
641 | int r = 0; |
642 | ||
643 | DSSDBG("ENTER hdmi_display_enable\n"); | |
644 | ||
645 | mutex_lock(&hdmi.lock); | |
646 | ||
05e1d606 TV |
647 | if (dssdev->manager == NULL) { |
648 | DSSERR("failed to enable display: no manager\n"); | |
649 | r = -ENODEV; | |
650 | goto err0; | |
651 | } | |
652 | ||
c49d005b TV |
653 | hdmi.ip_data.hpd_gpio = priv->hpd_gpio; |
654 | ||
c3198a5e M |
655 | r = omap_dss_start_device(dssdev); |
656 | if (r) { | |
657 | DSSERR("failed to start device\n"); | |
658 | goto err0; | |
659 | } | |
660 | ||
661 | if (dssdev->platform_enable) { | |
662 | r = dssdev->platform_enable(dssdev); | |
663 | if (r) { | |
664 | DSSERR("failed to enable GPIO's\n"); | |
665 | goto err1; | |
666 | } | |
667 | } | |
668 | ||
669 | r = hdmi_power_on(dssdev); | |
670 | if (r) { | |
671 | DSSERR("failed to power on device\n"); | |
672 | goto err2; | |
673 | } | |
674 | ||
675 | mutex_unlock(&hdmi.lock); | |
676 | return 0; | |
677 | ||
678 | err2: | |
679 | if (dssdev->platform_disable) | |
680 | dssdev->platform_disable(dssdev); | |
681 | err1: | |
682 | omap_dss_stop_device(dssdev); | |
683 | err0: | |
684 | mutex_unlock(&hdmi.lock); | |
685 | return r; | |
686 | } | |
687 | ||
688 | void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev) | |
689 | { | |
690 | DSSDBG("Enter hdmi_display_disable\n"); | |
691 | ||
692 | mutex_lock(&hdmi.lock); | |
693 | ||
694 | hdmi_power_off(dssdev); | |
695 | ||
696 | if (dssdev->platform_disable) | |
697 | dssdev->platform_disable(dssdev); | |
698 | ||
699 | omap_dss_stop_device(dssdev); | |
700 | ||
701 | mutex_unlock(&hdmi.lock); | |
702 | } | |
703 | ||
4fbafaf3 TV |
704 | static int hdmi_get_clocks(struct platform_device *pdev) |
705 | { | |
706 | struct clk *clk; | |
707 | ||
708 | clk = clk_get(&pdev->dev, "sys_clk"); | |
709 | if (IS_ERR(clk)) { | |
710 | DSSERR("can't get sys_clk\n"); | |
711 | return PTR_ERR(clk); | |
712 | } | |
713 | ||
714 | hdmi.sys_clk = clk; | |
715 | ||
4fbafaf3 TV |
716 | return 0; |
717 | } | |
718 | ||
719 | static void hdmi_put_clocks(void) | |
720 | { | |
721 | if (hdmi.sys_clk) | |
722 | clk_put(hdmi.sys_clk); | |
4fbafaf3 TV |
723 | } |
724 | ||
35547626 RN |
725 | #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) |
726 | int hdmi_compute_acr(u32 sample_freq, u32 *n, u32 *cts) | |
727 | { | |
728 | u32 deep_color; | |
25a65359 | 729 | bool deep_color_correct = false; |
35547626 RN |
730 | u32 pclk = hdmi.ip_data.cfg.timings.pixel_clock; |
731 | ||
732 | if (n == NULL || cts == NULL) | |
733 | return -EINVAL; | |
734 | ||
735 | /* TODO: When implemented, query deep color mode here. */ | |
736 | deep_color = 100; | |
737 | ||
25a65359 RN |
738 | /* |
739 | * When using deep color, the default N value (as in the HDMI | |
740 | * specification) yields to an non-integer CTS. Hence, we | |
741 | * modify it while keeping the restrictions described in | |
742 | * section 7.2.1 of the HDMI 1.4a specification. | |
743 | */ | |
35547626 RN |
744 | switch (sample_freq) { |
745 | case 32000: | |
25a65359 RN |
746 | case 48000: |
747 | case 96000: | |
748 | case 192000: | |
749 | if (deep_color == 125) | |
750 | if (pclk == 27027 || pclk == 74250) | |
751 | deep_color_correct = true; | |
752 | if (deep_color == 150) | |
753 | if (pclk == 27027) | |
754 | deep_color_correct = true; | |
35547626 RN |
755 | break; |
756 | case 44100: | |
25a65359 RN |
757 | case 88200: |
758 | case 176400: | |
759 | if (deep_color == 125) | |
760 | if (pclk == 27027) | |
761 | deep_color_correct = true; | |
35547626 RN |
762 | break; |
763 | default: | |
35547626 RN |
764 | return -EINVAL; |
765 | } | |
766 | ||
25a65359 RN |
767 | if (deep_color_correct) { |
768 | switch (sample_freq) { | |
769 | case 32000: | |
770 | *n = 8192; | |
771 | break; | |
772 | case 44100: | |
773 | *n = 12544; | |
774 | break; | |
775 | case 48000: | |
776 | *n = 8192; | |
777 | break; | |
778 | case 88200: | |
779 | *n = 25088; | |
780 | break; | |
781 | case 96000: | |
782 | *n = 16384; | |
783 | break; | |
784 | case 176400: | |
785 | *n = 50176; | |
786 | break; | |
787 | case 192000: | |
788 | *n = 32768; | |
789 | break; | |
790 | default: | |
791 | return -EINVAL; | |
792 | } | |
793 | } else { | |
794 | switch (sample_freq) { | |
795 | case 32000: | |
796 | *n = 4096; | |
797 | break; | |
798 | case 44100: | |
799 | *n = 6272; | |
800 | break; | |
801 | case 48000: | |
802 | *n = 6144; | |
803 | break; | |
804 | case 88200: | |
805 | *n = 12544; | |
806 | break; | |
807 | case 96000: | |
808 | *n = 12288; | |
809 | break; | |
810 | case 176400: | |
811 | *n = 25088; | |
812 | break; | |
813 | case 192000: | |
814 | *n = 24576; | |
815 | break; | |
816 | default: | |
817 | return -EINVAL; | |
818 | } | |
819 | } | |
35547626 RN |
820 | /* Calculate CTS. See HDMI 1.3a or 1.4a specifications */ |
821 | *cts = pclk * (*n / 128) * deep_color / (sample_freq / 10); | |
822 | ||
823 | return 0; | |
824 | } | |
f3a97491 RN |
825 | |
826 | int hdmi_audio_enable(void) | |
827 | { | |
828 | DSSDBG("audio_enable\n"); | |
829 | ||
830 | return hdmi.ip_data.ops->audio_enable(&hdmi.ip_data); | |
831 | } | |
832 | ||
833 | void hdmi_audio_disable(void) | |
834 | { | |
835 | DSSDBG("audio_disable\n"); | |
836 | ||
837 | hdmi.ip_data.ops->audio_disable(&hdmi.ip_data); | |
838 | } | |
839 | ||
840 | int hdmi_audio_start(void) | |
841 | { | |
842 | DSSDBG("audio_start\n"); | |
843 | ||
844 | return hdmi.ip_data.ops->audio_start(&hdmi.ip_data); | |
845 | } | |
846 | ||
847 | void hdmi_audio_stop(void) | |
848 | { | |
849 | DSSDBG("audio_stop\n"); | |
850 | ||
851 | hdmi.ip_data.ops->audio_stop(&hdmi.ip_data); | |
852 | } | |
853 | ||
854 | bool hdmi_mode_has_audio(void) | |
855 | { | |
856 | if (hdmi.ip_data.cfg.cm.mode == HDMI_HDMI) | |
857 | return true; | |
858 | else | |
859 | return false; | |
860 | } | |
861 | ||
862 | int hdmi_audio_config(struct omap_dss_audio *audio) | |
863 | { | |
864 | return hdmi.ip_data.ops->audio_config(&hdmi.ip_data, audio); | |
865 | } | |
866 | ||
35547626 RN |
867 | #endif |
868 | ||
38f3daf6 TV |
869 | static void __init hdmi_probe_pdata(struct platform_device *pdev) |
870 | { | |
871 | struct omap_dss_board_info *pdata = pdev->dev.platform_data; | |
872 | int r, i; | |
873 | ||
874 | for (i = 0; i < pdata->num_devices; ++i) { | |
875 | struct omap_dss_device *dssdev = pdata->devices[i]; | |
876 | ||
877 | if (dssdev->type != OMAP_DISPLAY_TYPE_HDMI) | |
878 | continue; | |
879 | ||
880 | r = hdmi_init_display(dssdev); | |
881 | if (r) { | |
882 | DSSERR("device %s init failed: %d\n", dssdev->name, r); | |
883 | continue; | |
884 | } | |
885 | ||
886 | r = omap_dss_register_device(dssdev, &pdev->dev, i); | |
887 | if (r) | |
888 | DSSERR("device %s register failed: %d\n", | |
889 | dssdev->name, r); | |
890 | } | |
891 | } | |
892 | ||
c3198a5e | 893 | /* HDMI HW IP initialisation */ |
6e7e8f06 | 894 | static int __init omapdss_hdmihw_probe(struct platform_device *pdev) |
c3198a5e M |
895 | { |
896 | struct resource *hdmi_mem; | |
38f3daf6 | 897 | int r; |
c3198a5e | 898 | |
c3198a5e M |
899 | hdmi.pdev = pdev; |
900 | ||
901 | mutex_init(&hdmi.lock); | |
902 | ||
903 | hdmi_mem = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0); | |
904 | if (!hdmi_mem) { | |
905 | DSSERR("can't get IORESOURCE_MEM HDMI\n"); | |
906 | return -EINVAL; | |
907 | } | |
908 | ||
909 | /* Base address taken from platform */ | |
95a8aeb6 M |
910 | hdmi.ip_data.base_wp = ioremap(hdmi_mem->start, |
911 | resource_size(hdmi_mem)); | |
912 | if (!hdmi.ip_data.base_wp) { | |
c3198a5e M |
913 | DSSERR("can't ioremap WP\n"); |
914 | return -ENOMEM; | |
915 | } | |
916 | ||
4fbafaf3 TV |
917 | r = hdmi_get_clocks(pdev); |
918 | if (r) { | |
95a8aeb6 | 919 | iounmap(hdmi.ip_data.base_wp); |
4fbafaf3 TV |
920 | return r; |
921 | } | |
922 | ||
923 | pm_runtime_enable(&pdev->dev); | |
924 | ||
95a8aeb6 M |
925 | hdmi.ip_data.core_sys_offset = HDMI_CORE_SYS; |
926 | hdmi.ip_data.core_av_offset = HDMI_CORE_AV; | |
927 | hdmi.ip_data.pll_offset = HDMI_PLLCTRL; | |
928 | hdmi.ip_data.phy_offset = HDMI_PHY; | |
7849398f | 929 | |
3a5383a2 | 930 | mutex_init(&hdmi.ip_data.lock); |
95a8aeb6 | 931 | |
c3198a5e M |
932 | hdmi_panel_init(); |
933 | ||
e40402cf TV |
934 | dss_debugfs_create_file("hdmi", hdmi_dump_regs); |
935 | ||
38f3daf6 | 936 | hdmi_probe_pdata(pdev); |
35deca3d | 937 | |
c3198a5e M |
938 | return 0; |
939 | } | |
940 | ||
6e7e8f06 | 941 | static int __exit omapdss_hdmihw_remove(struct platform_device *pdev) |
c3198a5e | 942 | { |
35deca3d TV |
943 | omap_dss_unregister_child_devices(&pdev->dev); |
944 | ||
c3198a5e M |
945 | hdmi_panel_exit(); |
946 | ||
4fbafaf3 TV |
947 | pm_runtime_disable(&pdev->dev); |
948 | ||
949 | hdmi_put_clocks(); | |
950 | ||
95a8aeb6 | 951 | iounmap(hdmi.ip_data.base_wp); |
c3198a5e M |
952 | |
953 | return 0; | |
954 | } | |
955 | ||
4fbafaf3 TV |
956 | static int hdmi_runtime_suspend(struct device *dev) |
957 | { | |
f11766d1 | 958 | clk_disable_unprepare(hdmi.sys_clk); |
4fbafaf3 TV |
959 | |
960 | dispc_runtime_put(); | |
4fbafaf3 TV |
961 | |
962 | return 0; | |
963 | } | |
964 | ||
965 | static int hdmi_runtime_resume(struct device *dev) | |
966 | { | |
967 | int r; | |
968 | ||
4fbafaf3 TV |
969 | r = dispc_runtime_get(); |
970 | if (r < 0) | |
852f0838 | 971 | return r; |
4fbafaf3 | 972 | |
f11766d1 | 973 | clk_prepare_enable(hdmi.sys_clk); |
4fbafaf3 TV |
974 | |
975 | return 0; | |
4fbafaf3 TV |
976 | } |
977 | ||
978 | static const struct dev_pm_ops hdmi_pm_ops = { | |
979 | .runtime_suspend = hdmi_runtime_suspend, | |
980 | .runtime_resume = hdmi_runtime_resume, | |
981 | }; | |
982 | ||
c3198a5e | 983 | static struct platform_driver omapdss_hdmihw_driver = { |
6e7e8f06 | 984 | .remove = __exit_p(omapdss_hdmihw_remove), |
c3198a5e M |
985 | .driver = { |
986 | .name = "omapdss_hdmi", | |
987 | .owner = THIS_MODULE, | |
4fbafaf3 | 988 | .pm = &hdmi_pm_ops, |
c3198a5e M |
989 | }, |
990 | }; | |
991 | ||
6e7e8f06 | 992 | int __init hdmi_init_platform_driver(void) |
c3198a5e | 993 | { |
61055d4b | 994 | return platform_driver_probe(&omapdss_hdmihw_driver, omapdss_hdmihw_probe); |
c3198a5e M |
995 | } |
996 | ||
6e7e8f06 | 997 | void __exit hdmi_uninit_platform_driver(void) |
c3198a5e | 998 | { |
04c742c3 | 999 | platform_driver_unregister(&omapdss_hdmihw_driver); |
c3198a5e | 1000 | } |