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OMAP: DSS2: HDMI: make set_timing saner
[deliverable/linux.git] / drivers / video / omap2 / dss / hdmi.c
CommitLineData
c3198a5e
M		 1/*
2 * hdmi.c
3 *
4 * HDMI interface DSS driver setting for TI's OMAP4 family of processor.
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
6 * Authors: Yong Zhi
7 * Mythri pk <mythripk@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#define DSS_SUBSYS_NAME "HDMI"
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/err.h>
27#include <linux/io.h>
28#include <linux/interrupt.h>
29#include <linux/mutex.h>
30#include <linux/delay.h>
31#include <linux/string.h>
24e6289c 32#include <linux/platform_device.h>
4fbafaf3
TV		 33#include <linux/pm_runtime.h>
34#include <linux/clk.h>
a0b38cc4 35#include <video/omapdss.h>
ad44cc32
RN		 36#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
37 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
38#include <sound/soc.h>
39#include <sound/pcm_params.h>
7334167b 40#include "ti_hdmi_4xxx_ip.h"
ad44cc32 41#endif
c3198a5e 42
94c52987 43#include "ti_hdmi.h"
c3198a5e 44#include "dss.h"
ad44cc32 45#include "dss_features.h"
c3198a5e 46
95a8aeb6
M		 47#define HDMI_WP 0x0
48#define HDMI_CORE_SYS 0x400
49#define HDMI_CORE_AV 0x900
50#define HDMI_PLLCTRL 0x200
51#define HDMI_PHY 0x300
52
7c1f1eca
M		 53/* HDMI EDID Length move this */
54#define HDMI_EDID_MAX_LENGTH 256
55#define EDID_TIMING_DESCRIPTOR_SIZE 0x12
56#define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36
57#define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80
58#define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4
59#define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4
60
61#define OMAP_HDMI_TIMINGS_NB 34
62
b44e4582 63#define HDMI_DEFAULT_REGN 16
8d88767a
TV		 64#define HDMI_DEFAULT_REGM2 1
65
c3198a5e
M		 66static struct {
67 struct mutex lock;
68 struct omap_display_platform_data *pdata;
69 struct platform_device *pdev;
95a8aeb6 70 struct hdmi_ip_data ip_data;
c3198a5e
M		 71 int code;
72 int mode;
73 u8 edid[HDMI_EDID_MAX_LENGTH];
74 u8 edid_set;
75 bool custom_set;
4fbafaf3
TV		 76
77 struct clk *sys_clk;
c3198a5e
M		 78} hdmi;
79
80/*
81 * Logic for the below structure :
82 * user enters the CEA or VESA timings by specifying the HDMI/DVI code.
83 * There is a correspondence between CEA/VESA timing and code, please
84 * refer to section 6.3 in HDMI 1.3 specification for timing code.
85 *
86 * In the below structure, cea_vesa_timings corresponds to all OMAP4
87 * supported CEA and VESA timing values.code_cea corresponds to the CEA
88 * code, It is used to get the timing from cea_vesa_timing array.Similarly
89 * with code_vesa. Code_index is used for back mapping, that is once EDID
90 * is read from the TV, EDID is parsed to find the timing values and then
91 * map it to corresponding CEA or VESA index.
92 */
93
94static const struct hdmi_timings cea_vesa_timings[OMAP_HDMI_TIMINGS_NB] = {
95 { {640, 480, 25200, 96, 16, 48, 2, 10, 33} , 0 , 0},
96 { {1280, 720, 74250, 40, 440, 220, 5, 5, 20}, 1, 1},
97 { {1280, 720, 74250, 40, 110, 220, 5, 5, 20}, 1, 1},
98 { {720, 480, 27027, 62, 16, 60, 6, 9, 30}, 0, 0},
99 { {2880, 576, 108000, 256, 48, 272, 5, 5, 39}, 0, 0},
100 { {1440, 240, 27027, 124, 38, 114, 3, 4, 15}, 0, 0},
101 { {1440, 288, 27000, 126, 24, 138, 3, 2, 19}, 0, 0},
102 { {1920, 540, 74250, 44, 528, 148, 5, 2, 15}, 1, 1},
103 { {1920, 540, 74250, 44, 88, 148, 5, 2, 15}, 1, 1},
104 { {1920, 1080, 148500, 44, 88, 148, 5, 4, 36}, 1, 1},
105 { {720, 576, 27000, 64, 12, 68, 5, 5, 39}, 0, 0},
106 { {1440, 576, 54000, 128, 24, 136, 5, 5, 39}, 0, 0},
107 { {1920, 1080, 148500, 44, 528, 148, 5, 4, 36}, 1, 1},
108 { {2880, 480, 108108, 248, 64, 240, 6, 9, 30}, 0, 0},
109 { {1920, 1080, 74250, 44, 638, 148, 5, 4, 36}, 1, 1},
110 /* VESA From Here */
111 { {640, 480, 25175, 96, 16, 48, 2 , 11, 31}, 0, 0},
112 { {800, 600, 40000, 128, 40, 88, 4 , 1, 23}, 1, 1},
113 { {848, 480, 33750, 112, 16, 112, 8 , 6, 23}, 1, 1},
114 { {1280, 768, 79500, 128, 64, 192, 7 , 3, 20}, 1, 0},
115 { {1280, 800, 83500, 128, 72, 200, 6 , 3, 22}, 1, 0},
116 { {1360, 768, 85500, 112, 64, 256, 6 , 3, 18}, 1, 1},
117 { {1280, 960, 108000, 112, 96, 312, 3 , 1, 36}, 1, 1},
118 { {1280, 1024, 108000, 112, 48, 248, 3 , 1, 38}, 1, 1},
119 { {1024, 768, 65000, 136, 24, 160, 6, 3, 29}, 0, 0},
120 { {1400, 1050, 121750, 144, 88, 232, 4, 3, 32}, 1, 0},
121 { {1440, 900, 106500, 152, 80, 232, 6, 3, 25}, 1, 0},
122 { {1680, 1050, 146250, 176 , 104, 280, 6, 3, 30}, 1, 0},
123 { {1366, 768, 85500, 143, 70, 213, 3, 3, 24}, 1, 1},
124 { {1920, 1080, 148500, 44, 148, 80, 5, 4, 36}, 1, 1},
125 { {1280, 768, 68250, 32, 48, 80, 7, 3, 12}, 0, 1},
126 { {1400, 1050, 101000, 32, 48, 80, 4, 3, 23}, 0, 1},
127 { {1680, 1050, 119000, 32, 48, 80, 6, 3, 21}, 0, 1},
128 { {1280, 800, 79500, 32, 48, 80, 6, 3, 14}, 0, 1},
129 { {1280, 720, 74250, 40, 110, 220, 5, 5, 20}, 1, 1}
130};
131
132/*
133 * This is a static mapping array which maps the timing values
134 * with corresponding CEA / VESA code
135 */
136static const int code_index[OMAP_HDMI_TIMINGS_NB] = {
137 1, 19, 4, 2, 37, 6, 21, 20, 5, 16, 17, 29, 31, 35, 32,
138 /* <--15 CEA 17--> vesa*/
139 4, 9, 0xE, 0x17, 0x1C, 0x27, 0x20, 0x23, 0x10, 0x2A,
140 0X2F, 0x3A, 0X51, 0X52, 0x16, 0x29, 0x39, 0x1B
141};
142
143/*
144 * This is reverse static mapping which maps the CEA / VESA code
145 * to the corresponding timing values
146 */
147static const int code_cea[39] = {
148 -1, 0, 3, 3, 2, 8, 5, 5, -1, -1,
149 -1, -1, -1, -1, -1, -1, 9, 10, 10, 1,
150 7, 6, 6, -1, -1, -1, -1, -1, -1, 11,
151 11, 12, 14, -1, -1, 13, 13, 4, 4
152};
153
154static const int code_vesa[85] = {
155 -1, -1, -1, -1, 15, -1, -1, -1, -1, 16,
156 -1, -1, -1, -1, 17, -1, 23, -1, -1, -1,
157 -1, -1, 29, 18, -1, -1, -1, 32, 19, -1,
158 -1, -1, 21, -1, -1, 22, -1, -1, -1, 20,
159 -1, 30, 24, -1, -1, -1, -1, 25, -1, -1,
160 -1, -1, -1, -1, -1, -1, -1, 31, 26, -1,
161 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
162 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
163 -1, 27, 28, -1, 33};
164
165static const u8 edid_header[8] = {0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0};
166
4fbafaf3
TV		 167static int hdmi_runtime_get(void)
168{
169 int r;
170
171 DSSDBG("hdmi_runtime_get\n");
172
173 r = pm_runtime_get_sync(&hdmi.pdev->dev);
174 WARN_ON(r < 0);
175 return r < 0 ? r : 0;
176}
177
178static void hdmi_runtime_put(void)
179{
180 int r;
181
182 DSSDBG("hdmi_runtime_put\n");
183
184 r = pm_runtime_put(&hdmi.pdev->dev);
185 WARN_ON(r < 0);
186}
187
c3198a5e
M		 188int hdmi_init_display(struct omap_dss_device *dssdev)
189{
190 DSSDBG("init_display\n");
191
60634a28 192 dss_init_hdmi_ip_ops(&hdmi.ip_data);
c3198a5e
M		 193 return 0;
194}
195
38863b7e
M		 196static void copy_hdmi_to_dss_timings(
197 const struct hdmi_video_timings *hdmi_timings,
198 struct omap_video_timings *timings)
199{
200 timings->x_res = hdmi_timings->x_res;
201 timings->y_res = hdmi_timings->y_res;
202 timings->pixel_clock = hdmi_timings->pixel_clock;
203 timings->hbp = hdmi_timings->hbp;
204 timings->hfp = hdmi_timings->hfp;
205 timings->hsw = hdmi_timings->hsw;
206 timings->vbp = hdmi_timings->vbp;
207 timings->vfp = hdmi_timings->vfp;
208 timings->vsw = hdmi_timings->vsw;
209}
210
c3198a5e
M		 211static int get_timings_index(void)
212{
213 int code;
214
215 if (hdmi.mode == 0)
216 code = code_vesa[hdmi.code];
217 else
218 code = code_cea[hdmi.code];
219
220 if (code == -1) {
221 /* HDMI code 4 corresponds to 640 * 480 VGA */
222 hdmi.code = 4;
223 /* DVI mode 1 corresponds to HDMI 0 to DVI */
224 hdmi.mode = HDMI_DVI;
225
226 code = code_vesa[hdmi.code];
227 }
228 return code;
229}
230
231static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing)
232{
233 int i = 0, code = -1, temp_vsync = 0, temp_hsync = 0;
234 int timing_vsync = 0, timing_hsync = 0;
38863b7e 235 struct hdmi_video_timings temp;
c3198a5e
M		 236 struct hdmi_cm cm = {-1};
237 DSSDBG("hdmi_get_code\n");
238
239 for (i = 0; i < OMAP_HDMI_TIMINGS_NB; i++) {
240 temp = cea_vesa_timings[i].timings;
241 if ((temp.pixel_clock == timing->pixel_clock) &&
242 (temp.x_res == timing->x_res) &&
243 (temp.y_res == timing->y_res)) {
244
245 temp_hsync = temp.hfp + temp.hsw + temp.hbp;
246 timing_hsync = timing->hfp + timing->hsw + timing->hbp;
247 temp_vsync = temp.vfp + temp.vsw + temp.vbp;
248 timing_vsync = timing->vfp + timing->vsw + timing->vbp;
249
250 DSSDBG("temp_hsync = %d , temp_vsync = %d"
251 "timing_hsync = %d, timing_vsync = %d\n",
252 temp_hsync, temp_hsync,
253 timing_hsync, timing_vsync);
254
255 if ((temp_hsync == timing_hsync) &&
256 (temp_vsync == timing_vsync)) {
257 code = i;
258 cm.code = code_index[i];
259 if (code < 14)
260 cm.mode = HDMI_HDMI;
261 else
262 cm.mode = HDMI_DVI;
263 DSSDBG("Hdmi_code = %d mode = %d\n",
264 cm.code, cm.mode);
265 break;
266 }
267 }
268 }
269
270 return cm;
271}
272
273static void get_horz_vert_timing_info(int current_descriptor_addrs, u8 *edid ,
274 struct omap_video_timings *timings)
275{
276 /* X and Y resolution */
277 timings->x_res = (((edid[current_descriptor_addrs + 4] & 0xF0) << 4) |
278 edid[current_descriptor_addrs + 2]);
279 timings->y_res = (((edid[current_descriptor_addrs + 7] & 0xF0) << 4) |
280 edid[current_descriptor_addrs + 5]);
281
282 timings->pixel_clock = ((edid[current_descriptor_addrs + 1] << 8) |
283 edid[current_descriptor_addrs]);
284
285 timings->pixel_clock = 10 * timings->pixel_clock;
286
287 /* HORIZONTAL FRONT PORCH */
288 timings->hfp = edid[current_descriptor_addrs + 8] |
289 ((edid[current_descriptor_addrs + 11] & 0xc0) << 2);
290 /* HORIZONTAL SYNC WIDTH */
291 timings->hsw = edid[current_descriptor_addrs + 9] |
292 ((edid[current_descriptor_addrs + 11] & 0x30) << 4);
293 /* HORIZONTAL BACK PORCH */
294 timings->hbp = (((edid[current_descriptor_addrs + 4] & 0x0F) << 8) |
295 edid[current_descriptor_addrs + 3]) -
296 (timings->hfp + timings->hsw);
297 /* VERTICAL FRONT PORCH */
298 timings->vfp = ((edid[current_descriptor_addrs + 10] & 0xF0) >> 4) |
299 ((edid[current_descriptor_addrs + 11] & 0x0f) << 2);
300 /* VERTICAL SYNC WIDTH */
301 timings->vsw = (edid[current_descriptor_addrs + 10] & 0x0F) |
302 ((edid[current_descriptor_addrs + 11] & 0x03) << 4);
303 /* VERTICAL BACK PORCH */
304 timings->vbp = (((edid[current_descriptor_addrs + 7] & 0x0F) << 8) |
305 edid[current_descriptor_addrs + 6]) -
306 (timings->vfp + timings->vsw);
307
308}
309
310/* Description : This function gets the resolution information from EDID */
311static void get_edid_timing_data(u8 *edid)
312{
313 u8 count;
314 u16 current_descriptor_addrs;
315 struct hdmi_cm cm;
316 struct omap_video_timings edid_timings;
317
25985edc 318 /* search block 0, there are 4 DTDs arranged in priority order */
c3198a5e
M		 319 for (count = 0; count < EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR; count++) {
320 current_descriptor_addrs =
321 EDID_DESCRIPTOR_BLOCK0_ADDRESS +
322 count * EDID_TIMING_DESCRIPTOR_SIZE;
323 get_horz_vert_timing_info(current_descriptor_addrs,
324 edid, &edid_timings);
325 cm = hdmi_get_code(&edid_timings);
326 DSSDBG("Block0[%d] value matches code = %d , mode = %d\n",
327 count, cm.code, cm.mode);
328 if (cm.code == -1) {
329 continue;
330 } else {
331 hdmi.code = cm.code;
332 hdmi.mode = cm.mode;
333 DSSDBG("code = %d , mode = %d\n",
334 hdmi.code, hdmi.mode);
335 return;
336 }
337 }
338 if (edid[0x7e] != 0x00) {
339 for (count = 0; count < EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR;
340 count++) {
341 current_descriptor_addrs =
342 EDID_DESCRIPTOR_BLOCK1_ADDRESS +
343 count * EDID_TIMING_DESCRIPTOR_SIZE;
344 get_horz_vert_timing_info(current_descriptor_addrs,
345 edid, &edid_timings);
346 cm = hdmi_get_code(&edid_timings);
347 DSSDBG("Block1[%d] value matches code = %d, mode = %d",
348 count, cm.code, cm.mode);
349 if (cm.code == -1) {
350 continue;
351 } else {
352 hdmi.code = cm.code;
353 hdmi.mode = cm.mode;
354 DSSDBG("code = %d , mode = %d\n",
355 hdmi.code, hdmi.mode);
356 return;
357 }
358 }
359 }
360
361 DSSINFO("no valid timing found , falling back to VGA\n");
362 hdmi.code = 4; /* setting default value of 640 480 VGA */
363 hdmi.mode = HDMI_DVI;
364}
365
366static void hdmi_read_edid(struct omap_video_timings *dp)
367{
368 int ret = 0, code;
369
370 memset(hdmi.edid, 0, HDMI_EDID_MAX_LENGTH);
371
372 if (!hdmi.edid_set)
60634a28 373 ret = hdmi.ip_data.ops->read_edid(&hdmi.ip_data, hdmi.edid,
95a8aeb6 374 HDMI_EDID_MAX_LENGTH);
c3198a5e
M		 375 if (!ret) {
376 if (!memcmp(hdmi.edid, edid_header, sizeof(edid_header))) {
377 /* search for timings of default resolution */
378 get_edid_timing_data(hdmi.edid);
379 hdmi.edid_set = true;
380 }
381 } else {
382 DSSWARN("failed to read E-EDID\n");
383 }
384
385 if (!hdmi.edid_set) {
386 DSSINFO("fallback to VGA\n");
387 hdmi.code = 4; /* setting default value of 640 480 VGA */
388 hdmi.mode = HDMI_DVI;
389 }
390
391 code = get_timings_index();
392
38863b7e
M		 393 copy_hdmi_to_dss_timings(&cea_vesa_timings[code].timings, dp);
394
c3198a5e
M		 395}
396
c3198a5e
M		 397static void update_hdmi_timings(struct hdmi_config *cfg,
398 struct omap_video_timings *timings, int code)
399{
400 cfg->timings.timings.x_res = timings->x_res;
401 cfg->timings.timings.y_res = timings->y_res;
402 cfg->timings.timings.hbp = timings->hbp;
403 cfg->timings.timings.hfp = timings->hfp;
404 cfg->timings.timings.hsw = timings->hsw;
405 cfg->timings.timings.vbp = timings->vbp;
406 cfg->timings.timings.vfp = timings->vfp;
407 cfg->timings.timings.vsw = timings->vsw;
408 cfg->timings.timings.pixel_clock = timings->pixel_clock;
409 cfg->timings.vsync_pol = cea_vesa_timings[code].vsync_pol;
410 cfg->timings.hsync_pol = cea_vesa_timings[code].hsync_pol;
411}
412
6cb07b25
AT		 413static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
414 struct hdmi_pll_info *pi)
c3198a5e 415{
6cb07b25 416 unsigned long clkin, refclk;
c3198a5e
M		 417 u32 mf;
418
4fbafaf3 419 clkin = clk_get_rate(hdmi.sys_clk) / 10000;
c3198a5e
M		 420 /*
421 * Input clock is predivided by N + 1
422 * out put of which is reference clk
423 */
8d88767a
TV		 424 if (dssdev->clocks.hdmi.regn == 0)
425 pi->regn = HDMI_DEFAULT_REGN;
426 else
427 pi->regn = dssdev->clocks.hdmi.regn;
428
b44e4582 429 refclk = clkin / pi->regn;
c3198a5e
M		 430
431 /*
432 * multiplier is pixel_clk/ref_clk
433 * Multiplying by 100 to avoid fractional part removal
434 */
6cb07b25 435 pi->regm = (phy * 100 / (refclk)) / 100;
8d88767a
TV		 436
437 if (dssdev->clocks.hdmi.regm2 == 0)
438 pi->regm2 = HDMI_DEFAULT_REGM2;
439 else
440 pi->regm2 = dssdev->clocks.hdmi.regm2;
c3198a5e
M		 441
442 /*
443 * fractional multiplier is remainder of the difference between
444 * multiplier and actual phy(required pixel clock thus should be
445 * multiplied by 2^18(262144) divided by the reference clock
446 */
447 mf = (phy - pi->regm * refclk) * 262144;
6cb07b25 448 pi->regmf = mf / (refclk);
c3198a5e
M		 449
450 /*
451 * Dcofreq should be set to 1 if required pixel clock
452 * is greater than 1000MHz
453 */
454 pi->dcofreq = phy > 1000 * 100;
b44e4582 455 pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10;
c3198a5e 456
7b27da54
M		 457 /* Set the reference clock to sysclk reference */
458 pi->refsel = HDMI_REFSEL_SYSCLK;
459
c3198a5e
M		 460 DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
461 DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
462}
463
c3198a5e
M		 464static int hdmi_power_on(struct omap_dss_device *dssdev)
465{
466 int r, code = 0;
c3198a5e 467 struct omap_video_timings *p;
6cb07b25 468 unsigned long phy;
c3198a5e 469
4fbafaf3
TV		 470 r = hdmi_runtime_get();
471 if (r)
472 return r;
c3198a5e 473
26d9dd0d 474 dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, 0);
c3198a5e
M		 475
476 p = &dssdev->panel.timings;
477
478 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n",
479 dssdev->panel.timings.x_res,
480 dssdev->panel.timings.y_res);
481
482 if (!hdmi.custom_set) {
483 DSSDBG("Read EDID as no EDID is not set on poweron\n");
484 hdmi_read_edid(p);
485 }
486 code = get_timings_index();
38863b7e
M		 487 copy_hdmi_to_dss_timings(&cea_vesa_timings[code].timings,
488 &dssdev->panel.timings);
7b27da54 489 update_hdmi_timings(&hdmi.ip_data.cfg, p, code);
c3198a5e 490
c3198a5e
M		 491 phy = p->pixel_clock;
492
7b27da54 493 hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data);
c3198a5e 494
60634a28 495 hdmi.ip_data.ops->video_enable(&hdmi.ip_data, 0);
c3198a5e 496
95a8aeb6 497 /* config the PLL and PHY hdmi_set_pll_pwrfirst */
60634a28 498 r = hdmi.ip_data.ops->pll_enable(&hdmi.ip_data);
c3198a5e
M		 499 if (r) {
500 DSSDBG("Failed to lock PLL\n");
501 goto err;
502 }
503
60634a28 504 r = hdmi.ip_data.ops->phy_enable(&hdmi.ip_data);
c3198a5e
M		 505 if (r) {
506 DSSDBG("Failed to start PHY\n");
507 goto err;
508 }
509
7b27da54
M		 510 hdmi.ip_data.cfg.cm.mode = hdmi.mode;
511 hdmi.ip_data.cfg.cm.code = hdmi.code;
60634a28 512 hdmi.ip_data.ops->video_configure(&hdmi.ip_data);
c3198a5e
M		 513
514 /* Make selection of HDMI in DSS */
515 dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
516
517 /* Select the dispc clock source as PRCM clock, to ensure that it is not
518 * DSI PLL source as the clock selected by DSI PLL might not be
519 * sufficient for the resolution selected / that can be changed
520 * dynamically by user. This can be moved to single location , say
521 * Boardfile.
522 */
6cb07b25 523 dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
c3198a5e
M		 524
525 /* bypass TV gamma table */
526 dispc_enable_gamma_table(0);
527
528 /* tv size */
529 dispc_set_digit_size(dssdev->panel.timings.x_res,
530 dssdev->panel.timings.y_res);
531
60634a28 532 hdmi.ip_data.ops->video_enable(&hdmi.ip_data, 1);
c3198a5e 533
3870c909
TV		 534 dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, 1);
535
c3198a5e
M		 536 return 0;
537err:
4fbafaf3 538 hdmi_runtime_put();
c3198a5e
M		 539 return -EIO;
540}
541
542static void hdmi_power_off(struct omap_dss_device *dssdev)
543{
26d9dd0d 544 dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, 0);
c3198a5e 545
60634a28
M		 546 hdmi.ip_data.ops->video_enable(&hdmi.ip_data, 0);
547 hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
548 hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
4fbafaf3 549 hdmi_runtime_put();
c3198a5e
M		 550
551 hdmi.edid_set = 0;
552}
553
554int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
555 struct omap_video_timings *timings)
556{
557 struct hdmi_cm cm;
558
559 cm = hdmi_get_code(timings);
560 if (cm.code == -1) {
561 DSSERR("Invalid timing entered\n");
562 return -EINVAL;
563 }
564
565 return 0;
566
567}
568
569void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev)
570{
571 struct hdmi_cm cm;
572
573 hdmi.custom_set = 1;
fa70dc5f 574
c3198a5e
M		 575 cm = hdmi_get_code(&dssdev->panel.timings);
576 hdmi.code = cm.code;
577 hdmi.mode = cm.mode;
fa70dc5f
TV		 578
579 if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
580 int r;
581
582 hdmi_power_off(dssdev);
583
584 r = hdmi_power_on(dssdev);
585 if (r)
586 DSSERR("failed to power on device\n");
587 }
c3198a5e
M		 588}
589
590int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev)
591{
592 int r = 0;
593
594 DSSDBG("ENTER hdmi_display_enable\n");
595
596 mutex_lock(&hdmi.lock);
597
05e1d606
TV		 598 if (dssdev->manager == NULL) {
599 DSSERR("failed to enable display: no manager\n");
600 r = -ENODEV;
601 goto err0;
602 }
603
c3198a5e
M		 604 r = omap_dss_start_device(dssdev);
605 if (r) {
606 DSSERR("failed to start device\n");
607 goto err0;
608 }
609
610 if (dssdev->platform_enable) {
611 r = dssdev->platform_enable(dssdev);
612 if (r) {
613 DSSERR("failed to enable GPIO's\n");
614 goto err1;
615 }
616 }
617
618 r = hdmi_power_on(dssdev);
619 if (r) {
620 DSSERR("failed to power on device\n");
621 goto err2;
622 }
623
624 mutex_unlock(&hdmi.lock);
625 return 0;
626
627err2:
628 if (dssdev->platform_disable)
629 dssdev->platform_disable(dssdev);
630err1:
631 omap_dss_stop_device(dssdev);
632err0:
633 mutex_unlock(&hdmi.lock);
634 return r;
635}
636
637void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev)
638{
639 DSSDBG("Enter hdmi_display_disable\n");
640
641 mutex_lock(&hdmi.lock);
642
643 hdmi_power_off(dssdev);
644
645 if (dssdev->platform_disable)
646 dssdev->platform_disable(dssdev);
647
648 omap_dss_stop_device(dssdev);
649
650 mutex_unlock(&hdmi.lock);
651}
652
82335c4c
RN		 653#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
654 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
ad44cc32 655
95a8aeb6
M		 656static int hdmi_audio_hw_params(struct hdmi_ip_data *ip_data,
657 struct snd_pcm_substream *substream,
ad44cc32
RN		 658 struct snd_pcm_hw_params *params,
659 struct snd_soc_dai *dai)
660{
661 struct hdmi_audio_format audio_format;
662 struct hdmi_audio_dma audio_dma;
663 struct hdmi_core_audio_config core_cfg;
664 struct hdmi_core_infoframe_audio aud_if_cfg;
665 int err, n, cts;
666 enum hdmi_core_audio_sample_freq sample_freq;
667
668 switch (params_format(params)) {
669 case SNDRV_PCM_FORMAT_S16_LE:
670 core_cfg.i2s_cfg.word_max_length =
671 HDMI_AUDIO_I2S_MAX_WORD_20BITS;
672 core_cfg.i2s_cfg.word_length = HDMI_AUDIO_I2S_CHST_WORD_16_BITS;
673 core_cfg.i2s_cfg.in_length_bits =
674 HDMI_AUDIO_I2S_INPUT_LENGTH_16;
675 core_cfg.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_LEFT;
676 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES;
677 audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS;
678 audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT;
679 audio_dma.transfer_size = 0x10;
680 break;
681 case SNDRV_PCM_FORMAT_S24_LE:
682 core_cfg.i2s_cfg.word_max_length =
683 HDMI_AUDIO_I2S_MAX_WORD_24BITS;
684 core_cfg.i2s_cfg.word_length = HDMI_AUDIO_I2S_CHST_WORD_24_BITS;
685 core_cfg.i2s_cfg.in_length_bits =
686 HDMI_AUDIO_I2S_INPUT_LENGTH_24;
687 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_ONESAMPLE;
688 audio_format.sample_size = HDMI_AUDIO_SAMPLE_24BITS;
689 audio_format.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
690 core_cfg.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
691 audio_dma.transfer_size = 0x20;
692 break;
693 default:
694 return -EINVAL;
695 }
696
697 switch (params_rate(params)) {
698 case 32000:
699 sample_freq = HDMI_AUDIO_FS_32000;
700 break;
701 case 44100:
702 sample_freq = HDMI_AUDIO_FS_44100;
703 break;
704 case 48000:
705 sample_freq = HDMI_AUDIO_FS_48000;
706 break;
707 default:
708 return -EINVAL;
709 }
710
95a8aeb6 711 err = hdmi_config_audio_acr(ip_data, params_rate(params), &n, &cts);
ad44cc32
RN		 712 if (err < 0)
713 return err;
714
715 /* Audio wrapper config */
716 audio_format.stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL;
717 audio_format.active_chnnls_msk = 0x03;
718 audio_format.type = HDMI_AUDIO_TYPE_LPCM;
719 audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
720 /* Disable start/stop signals of IEC 60958 blocks */
721 audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF;
722
723 audio_dma.block_size = 0xC0;
724 audio_dma.mode = HDMI_AUDIO_TRANSF_DMA;
725 audio_dma.fifo_threshold = 0x20; /* in number of samples */
726
95a8aeb6
M		 727 hdmi_wp_audio_config_dma(ip_data, &audio_dma);
728 hdmi_wp_audio_config_format(ip_data, &audio_format);
ad44cc32
RN		 729
730 /*
731 * I2S config
732 */
733 core_cfg.i2s_cfg.en_high_bitrate_aud = false;
734 /* Only used with high bitrate audio */
735 core_cfg.i2s_cfg.cbit_order = false;
736 /* Serial data and word select should change on sck rising edge */
737 core_cfg.i2s_cfg.sck_edge_mode = HDMI_AUDIO_I2S_SCK_EDGE_RISING;
738 core_cfg.i2s_cfg.vbit = HDMI_AUDIO_I2S_VBIT_FOR_PCM;
739 /* Set I2S word select polarity */
740 core_cfg.i2s_cfg.ws_polarity = HDMI_AUDIO_I2S_WS_POLARITY_LOW_IS_LEFT;
741 core_cfg.i2s_cfg.direction = HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST;
742 /* Set serial data to word select shift. See Phillips spec. */
743 core_cfg.i2s_cfg.shift = HDMI_AUDIO_I2S_FIRST_BIT_SHIFT;
744 /* Enable one of the four available serial data channels */
745 core_cfg.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN;
746
747 /* Core audio config */
748 core_cfg.freq_sample = sample_freq;
749 core_cfg.n = n;
750 core_cfg.cts = cts;
751 if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) {
752 core_cfg.aud_par_busclk = 0;
753 core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_SW;
754 core_cfg.use_mclk = false;
755 } else {
756 core_cfg.aud_par_busclk = (((128 * 31) - 1) << 8);
757 core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_HW;
758 core_cfg.use_mclk = true;
759 core_cfg.mclk_mode = HDMI_AUDIO_MCLK_128FS;
760 }
761 core_cfg.layout = HDMI_AUDIO_LAYOUT_2CH;
762 core_cfg.en_spdif = false;
763 /* Use sample frequency from channel status word */
764 core_cfg.fs_override = true;
765 /* Enable ACR packets */
766 core_cfg.en_acr_pkt = true;
767 /* Disable direct streaming digital audio */
768 core_cfg.en_dsd_audio = false;
769 /* Use parallel audio interface */
770 core_cfg.en_parallel_aud_input = true;
771
95a8aeb6 772 hdmi_core_audio_config(ip_data, &core_cfg);
ad44cc32
RN		 773
774 /*
775 * Configure packet
776 * info frame audio see doc CEA861-D page 74
777 */
778 aud_if_cfg.db1_coding_type = HDMI_INFOFRAME_AUDIO_DB1CT_FROM_STREAM;
779 aud_if_cfg.db1_channel_count = 2;
780 aud_if_cfg.db2_sample_freq = HDMI_INFOFRAME_AUDIO_DB2SF_FROM_STREAM;
781 aud_if_cfg.db2_sample_size = HDMI_INFOFRAME_AUDIO_DB2SS_FROM_STREAM;
782 aud_if_cfg.db4_channel_alloc = 0x00;
783 aud_if_cfg.db5_downmix_inh = false;
784 aud_if_cfg.db5_lsv = 0;
785
95a8aeb6 786 hdmi_core_audio_infoframe_config(ip_data, &aud_if_cfg);
ad44cc32
RN		 787 return 0;
788}
789
ad44cc32
RN		 790static int hdmi_audio_startup(struct snd_pcm_substream *substream,
791 struct snd_soc_dai *dai)
792{
793 if (!hdmi.mode) {
794 pr_err("Current video settings do not support audio.\n");
795 return -EIO;
796 }
797 return 0;
798}
799
800static struct snd_soc_codec_driver hdmi_audio_codec_drv = {
801};
802
803static struct snd_soc_dai_ops hdmi_audio_codec_ops = {
804 .hw_params = hdmi_audio_hw_params,
805 .trigger = hdmi_audio_trigger,
806 .startup = hdmi_audio_startup,
807};
808
809static struct snd_soc_dai_driver hdmi_codec_dai_drv = {
810 .name = "hdmi-audio-codec",
811 .playback = {
812 .channels_min = 2,
813 .channels_max = 2,
814 .rates = SNDRV_PCM_RATE_32000 |
815 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
816 .formats = SNDRV_PCM_FMTBIT_S16_LE |
817 SNDRV_PCM_FMTBIT_S24_LE,
818 },
819 .ops = &hdmi_audio_codec_ops,
820};
82335c4c
RN		 821#endif
822
4fbafaf3
TV		 823static int hdmi_get_clocks(struct platform_device *pdev)
824{
825 struct clk *clk;
826
827 clk = clk_get(&pdev->dev, "sys_clk");
828 if (IS_ERR(clk)) {
829 DSSERR("can't get sys_clk\n");
830 return PTR_ERR(clk);
831 }
832
833 hdmi.sys_clk = clk;
834
4fbafaf3
TV		 835 return 0;
836}
837
838static void hdmi_put_clocks(void)
839{
840 if (hdmi.sys_clk)
841 clk_put(hdmi.sys_clk);
4fbafaf3
TV		 842}
843
c3198a5e
M		 844/* HDMI HW IP initialisation */
845static int omapdss_hdmihw_probe(struct platform_device *pdev)
846{
847 struct resource *hdmi_mem;
4fbafaf3 848 int r;
c3198a5e
M		 849
850 hdmi.pdata = pdev->dev.platform_data;
851 hdmi.pdev = pdev;
852
853 mutex_init(&hdmi.lock);
854
855 hdmi_mem = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0);
856 if (!hdmi_mem) {
857 DSSERR("can't get IORESOURCE_MEM HDMI\n");
858 return -EINVAL;
859 }
860
861 /* Base address taken from platform */
95a8aeb6
M		 862 hdmi.ip_data.base_wp = ioremap(hdmi_mem->start,
863 resource_size(hdmi_mem));
864 if (!hdmi.ip_data.base_wp) {
c3198a5e
M		 865 DSSERR("can't ioremap WP\n");
866 return -ENOMEM;
867 }
868
4fbafaf3
TV		 869 r = hdmi_get_clocks(pdev);
870 if (r) {
95a8aeb6 871 iounmap(hdmi.ip_data.base_wp);
4fbafaf3
TV		 872 return r;
873 }
874
875 pm_runtime_enable(&pdev->dev);
876
95a8aeb6
M		 877 hdmi.ip_data.core_sys_offset = HDMI_CORE_SYS;
878 hdmi.ip_data.core_av_offset = HDMI_CORE_AV;
879 hdmi.ip_data.pll_offset = HDMI_PLLCTRL;
880 hdmi.ip_data.phy_offset = HDMI_PHY;
881
c3198a5e
M		 882 hdmi_panel_init();
883
ad44cc32
RN		 884#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
885 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
886
887 /* Register ASoC codec DAI */
4fbafaf3 888 r = snd_soc_register_codec(&pdev->dev, &hdmi_audio_codec_drv,
ad44cc32 889 &hdmi_codec_dai_drv, 1);
4fbafaf3 890 if (r) {
ad44cc32 891 DSSERR("can't register ASoC HDMI audio codec\n");
4fbafaf3 892 return r;
ad44cc32
RN		 893 }
894#endif
c3198a5e
M		 895 return 0;
896}
897
898static int omapdss_hdmihw_remove(struct platform_device *pdev)
899{
900 hdmi_panel_exit();
901
ad44cc32
RN		 902#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
903 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
904 snd_soc_unregister_codec(&pdev->dev);
905#endif
906
4fbafaf3
TV		 907 pm_runtime_disable(&pdev->dev);
908
909 hdmi_put_clocks();
910
95a8aeb6 911 iounmap(hdmi.ip_data.base_wp);
c3198a5e
M		 912
913 return 0;
914}
915
4fbafaf3
TV		 916static int hdmi_runtime_suspend(struct device *dev)
917{
4fbafaf3
TV		 918 clk_disable(hdmi.sys_clk);
919
920 dispc_runtime_put();
921 dss_runtime_put();
922
923 return 0;
924}
925
926static int hdmi_runtime_resume(struct device *dev)
927{
928 int r;
929
930 r = dss_runtime_get();
931 if (r < 0)
932 goto err_get_dss;
933
934 r = dispc_runtime_get();
935 if (r < 0)
936 goto err_get_dispc;
937
938
939 clk_enable(hdmi.sys_clk);
4fbafaf3
TV		 940
941 return 0;
942
943err_get_dispc:
944 dss_runtime_put();
945err_get_dss:
946 return r;
947}
948
949static const struct dev_pm_ops hdmi_pm_ops = {
950 .runtime_suspend = hdmi_runtime_suspend,
951 .runtime_resume = hdmi_runtime_resume,
952};
953
c3198a5e
M		 954static struct platform_driver omapdss_hdmihw_driver = {
955 .probe = omapdss_hdmihw_probe,
956 .remove = omapdss_hdmihw_remove,
957 .driver = {
958 .name = "omapdss_hdmi",
959 .owner = THIS_MODULE,
4fbafaf3 960 .pm = &hdmi_pm_ops,
c3198a5e
M		 961 },
962};
963
964int hdmi_init_platform_driver(void)
965{
966 return platform_driver_register(&omapdss_hdmihw_driver);
967}
968
969void hdmi_uninit_platform_driver(void)
970{
971 return platform_driver_unregister(&omapdss_hdmihw_driver);
972}
Linux kernel - Deliverables
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