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OMAPDSS: DPI/HDMI: Apply manager timings even if panel is disabled
[deliverable/linux.git] / drivers / video / omap2 / dss / hdmi.c
CommitLineData
c3198a5e
M		 1/*
2 * hdmi.c
3 *
4 * HDMI interface DSS driver setting for TI's OMAP4 family of processor.
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
6 * Authors: Yong Zhi
7 * Mythri pk <mythripk@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#define DSS_SUBSYS_NAME "HDMI"
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/err.h>
27#include <linux/io.h>
28#include <linux/interrupt.h>
29#include <linux/mutex.h>
30#include <linux/delay.h>
31#include <linux/string.h>
24e6289c 32#include <linux/platform_device.h>
4fbafaf3
TV		 33#include <linux/pm_runtime.h>
34#include <linux/clk.h>
a0b38cc4 35#include <video/omapdss.h>
ad44cc32
RN		 36#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
37 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
38#include <sound/soc.h>
39#include <sound/pcm_params.h>
7334167b 40#include "ti_hdmi_4xxx_ip.h"
ad44cc32 41#endif
c3198a5e 42
94c52987 43#include "ti_hdmi.h"
c3198a5e 44#include "dss.h"
ad44cc32 45#include "dss_features.h"
c3198a5e 46
95a8aeb6
M		 47#define HDMI_WP 0x0
48#define HDMI_CORE_SYS 0x400
49#define HDMI_CORE_AV 0x900
50#define HDMI_PLLCTRL 0x200
51#define HDMI_PHY 0x300
52
7c1f1eca
M		 53/* HDMI EDID Length move this */
54#define HDMI_EDID_MAX_LENGTH 256
55#define EDID_TIMING_DESCRIPTOR_SIZE 0x12
56#define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36
57#define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80
58#define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4
59#define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4
60
b44e4582 61#define HDMI_DEFAULT_REGN 16
8d88767a
TV		 62#define HDMI_DEFAULT_REGM2 1
63
c3198a5e
M		 64static struct {
65 struct mutex lock;
66 struct omap_display_platform_data *pdata;
67 struct platform_device *pdev;
95a8aeb6 68 struct hdmi_ip_data ip_data;
4fbafaf3
TV		 69
70 struct clk *sys_clk;
c3198a5e
M		 71} hdmi;
72
73/*
74 * Logic for the below structure :
75 * user enters the CEA or VESA timings by specifying the HDMI/DVI code.
76 * There is a correspondence between CEA/VESA timing and code, please
77 * refer to section 6.3 in HDMI 1.3 specification for timing code.
78 *
79 * In the below structure, cea_vesa_timings corresponds to all OMAP4
80 * supported CEA and VESA timing values.code_cea corresponds to the CEA
81 * code, It is used to get the timing from cea_vesa_timing array.Similarly
82 * with code_vesa. Code_index is used for back mapping, that is once EDID
83 * is read from the TV, EDID is parsed to find the timing values and then
84 * map it to corresponding CEA or VESA index.
85 */
86
46095b2d 87static const struct hdmi_config cea_timings[] = {
a05ce78f
M		 88{ {640, 480, 25200, 96, 16, 48, 2, 10, 33, 0, 0, 0}, {1, HDMI_HDMI} },
89{ {720, 480, 27027, 62, 16, 60, 6, 9, 30, 0, 0, 0}, {2, HDMI_HDMI} },
90{ {1280, 720, 74250, 40, 110, 220, 5, 5, 20, 1, 1, 0}, {4, HDMI_HDMI} },
91{ {1920, 540, 74250, 44, 88, 148, 5, 2, 15, 1, 1, 1}, {5, HDMI_HDMI} },
92{ {1440, 240, 27027, 124, 38, 114, 3, 4, 15, 0, 0, 1}, {6, HDMI_HDMI} },
93{ {1920, 1080, 148500, 44, 88, 148, 5, 4, 36, 1, 1, 0}, {16, HDMI_HDMI} },
94{ {720, 576, 27000, 64, 12, 68, 5, 5, 39, 0, 0, 0}, {17, HDMI_HDMI} },
95{ {1280, 720, 74250, 40, 440, 220, 5, 5, 20, 1, 1, 0}, {19, HDMI_HDMI} },
96{ {1920, 540, 74250, 44, 528, 148, 5, 2, 15, 1, 1, 1}, {20, HDMI_HDMI} },
97{ {1440, 288, 27000, 126, 24, 138, 3, 2, 19, 0, 0, 1}, {21, HDMI_HDMI} },
98{ {1440, 576, 54000, 128, 24, 136, 5, 5, 39, 0, 0, 0}, {29, HDMI_HDMI} },
99{ {1920, 1080, 148500, 44, 528, 148, 5, 4, 36, 1, 1, 0}, {31, HDMI_HDMI} },
100{ {1920, 1080, 74250, 44, 638, 148, 5, 4, 36, 1, 1, 0}, {32, HDMI_HDMI} },
101{ {2880, 480, 108108, 248, 64, 240, 6, 9, 30, 0, 0, 0}, {35, HDMI_HDMI} },
102{ {2880, 576, 108000, 256, 48, 272, 5, 5, 39, 0, 0, 0}, {37, HDMI_HDMI} },
46095b2d
M		 103};
104static const struct hdmi_config vesa_timings[] = {
a05ce78f
M		 105/* VESA From Here */
106{ {640, 480, 25175, 96, 16, 48, 2 , 11, 31, 0, 0, 0}, {4, HDMI_DVI} },
107{ {800, 600, 40000, 128, 40, 88, 4 , 1, 23, 1, 1, 0}, {9, HDMI_DVI} },
108{ {848, 480, 33750, 112, 16, 112, 8 , 6, 23, 1, 1, 0}, {0xE, HDMI_DVI} },
109{ {1280, 768, 79500, 128, 64, 192, 7 , 3, 20, 1, 0, 0}, {0x17, HDMI_DVI} },
110{ {1280, 800, 83500, 128, 72, 200, 6 , 3, 22, 1, 0, 0}, {0x1C, HDMI_DVI} },
111{ {1360, 768, 85500, 112, 64, 256, 6 , 3, 18, 1, 1, 0}, {0x27, HDMI_DVI} },
112{ {1280, 960, 108000, 112, 96, 312, 3 , 1, 36, 1, 1, 0}, {0x20, HDMI_DVI} },
113{ {1280, 1024, 108000, 112, 48, 248, 3 , 1, 38, 1, 1, 0}, {0x23, HDMI_DVI} },
114{ {1024, 768, 65000, 136, 24, 160, 6, 3, 29, 0, 0, 0}, {0x10, HDMI_DVI} },
115{ {1400, 1050, 121750, 144, 88, 232, 4, 3, 32, 1, 0, 0}, {0x2A, HDMI_DVI} },
116{ {1440, 900, 106500, 152, 80, 232, 6, 3, 25, 1, 0, 0}, {0x2F, HDMI_DVI} },
117{ {1680, 1050, 146250, 176 , 104, 280, 6, 3, 30, 1, 0, 0}, {0x3A, HDMI_DVI} },
118{ {1366, 768, 85500, 143, 70, 213, 3, 3, 24, 1, 1, 0}, {0x51, HDMI_DVI} },
119{ {1920, 1080, 148500, 44, 148, 80, 5, 4, 36, 1, 1, 0}, {0x52, HDMI_DVI} },
120{ {1280, 768, 68250, 32, 48, 80, 7, 3, 12, 0, 1, 0}, {0x16, HDMI_DVI} },
121{ {1400, 1050, 101000, 32, 48, 80, 4, 3, 23, 0, 1, 0}, {0x29, HDMI_DVI} },
122{ {1680, 1050, 119000, 32, 48, 80, 6, 3, 21, 0, 1, 0}, {0x39, HDMI_DVI} },
123{ {1280, 800, 79500, 32, 48, 80, 6, 3, 14, 0, 1, 0}, {0x1B, HDMI_DVI} },
124{ {1280, 720, 74250, 40, 110, 220, 5, 5, 20, 1, 1, 0}, {0x55, HDMI_DVI} }
c3198a5e
M		 125};
126
4fbafaf3
TV		 127static int hdmi_runtime_get(void)
128{
129 int r;
130
131 DSSDBG("hdmi_runtime_get\n");
132
a247ce78
AT		 133 /*
134 * HACK: Add dss_runtime_get() to ensure DSS clock domain is enabled.
135 * This should be removed later.
136 */
137 r = dss_runtime_get();
138 if (r < 0)
139 goto err_get_dss;
140
4fbafaf3
TV		 141 r = pm_runtime_get_sync(&hdmi.pdev->dev);
142 WARN_ON(r < 0);
a247ce78
AT		 143 if (r < 0)
144 goto err_get_hdmi;
145
146 return 0;
147
148err_get_hdmi:
149 dss_runtime_put();
150err_get_dss:
151 return r;
4fbafaf3
TV		 152}
153
154static void hdmi_runtime_put(void)
155{
156 int r;
157
158 DSSDBG("hdmi_runtime_put\n");
159
0eaf9f52 160 r = pm_runtime_put_sync(&hdmi.pdev->dev);
4fbafaf3 161 WARN_ON(r < 0);
a247ce78
AT		 162
163 /*
164 * HACK: This is added to complement the dss_runtime_get() call in
165 * hdmi_runtime_get(). This should be removed later.
166 */
167 dss_runtime_put();
4fbafaf3
TV		 168}
169
c3198a5e
M		 170int hdmi_init_display(struct omap_dss_device *dssdev)
171{
172 DSSDBG("init_display\n");
173
60634a28 174 dss_init_hdmi_ip_ops(&hdmi.ip_data);
c3198a5e
M		 175 return 0;
176}
177
46095b2d
M		 178static const struct hdmi_config *hdmi_find_timing(
179 const struct hdmi_config *timings_arr,
180 int len)
c3198a5e 181{
46095b2d 182 int i;
c3198a5e 183
46095b2d 184 for (i = 0; i < len; i++) {
9e4ed603 185 if (timings_arr[i].cm.code == hdmi.ip_data.cfg.cm.code)
46095b2d
M		 186 return &timings_arr[i];
187 }
188 return NULL;
189}
c3198a5e 190
46095b2d
M		 191static const struct hdmi_config *hdmi_get_timings(void)
192{
193 const struct hdmi_config *arr;
194 int len;
195
9e4ed603 196 if (hdmi.ip_data.cfg.cm.mode == HDMI_DVI) {
46095b2d
M		 197 arr = vesa_timings;
198 len = ARRAY_SIZE(vesa_timings);
199 } else {
200 arr = cea_timings;
201 len = ARRAY_SIZE(cea_timings);
202 }
203
204 return hdmi_find_timing(arr, len);
205}
206
207static bool hdmi_timings_compare(struct omap_video_timings *timing1,
208 const struct hdmi_video_timings *timing2)
209{
210 int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync;
211
212 if ((timing2->pixel_clock == timing1->pixel_clock) &&
213 (timing2->x_res == timing1->x_res) &&
214 (timing2->y_res == timing1->y_res)) {
c3198a5e 215
46095b2d
M		 216 timing2_hsync = timing2->hfp + timing2->hsw + timing2->hbp;
217 timing1_hsync = timing1->hfp + timing1->hsw + timing1->hbp;
218 timing2_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
219 timing1_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
220
221 DSSDBG("timing1_hsync = %d timing1_vsync = %d"\
222 "timing2_hsync = %d timing2_vsync = %d\n",
223 timing1_hsync, timing1_vsync,
224 timing2_hsync, timing2_vsync);
225
226 if ((timing1_hsync == timing2_hsync) &&
227 (timing1_vsync == timing2_vsync)) {
228 return true;
229 }
c3198a5e 230 }
46095b2d 231 return false;
c3198a5e
M		 232}
233
234static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing)
235{
46095b2d 236 int i;
c3198a5e
M		 237 struct hdmi_cm cm = {-1};
238 DSSDBG("hdmi_get_code\n");
239
46095b2d
M		 240 for (i = 0; i < ARRAY_SIZE(cea_timings); i++) {
241 if (hdmi_timings_compare(timing, &cea_timings[i].timings)) {
242 cm = cea_timings[i].cm;
243 goto end;
244 }
245 }
246 for (i = 0; i < ARRAY_SIZE(vesa_timings); i++) {
247 if (hdmi_timings_compare(timing, &vesa_timings[i].timings)) {
248 cm = vesa_timings[i].cm;
249 goto end;
c3198a5e
M		 250 }
251 }
252
46095b2d 253end: return cm;
c3198a5e 254
c3198a5e
M		 255}
256
c3dc6a7a
AT		 257unsigned long hdmi_get_pixel_clock(void)
258{
259 /* HDMI Pixel Clock in Mhz */
a05ce78f 260 return hdmi.ip_data.cfg.timings.pixel_clock * 1000;
c3dc6a7a
AT		 261}
262
6cb07b25
AT		 263static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
264 struct hdmi_pll_info *pi)
c3198a5e 265{
6cb07b25 266 unsigned long clkin, refclk;
c3198a5e
M		 267 u32 mf;
268
4fbafaf3 269 clkin = clk_get_rate(hdmi.sys_clk) / 10000;
c3198a5e
M		 270 /*
271 * Input clock is predivided by N + 1
272 * out put of which is reference clk
273 */
8d88767a
TV		 274 if (dssdev->clocks.hdmi.regn == 0)
275 pi->regn = HDMI_DEFAULT_REGN;
276 else
277 pi->regn = dssdev->clocks.hdmi.regn;
278
b44e4582 279 refclk = clkin / pi->regn;
c3198a5e 280
8d88767a
TV		 281 if (dssdev->clocks.hdmi.regm2 == 0)
282 pi->regm2 = HDMI_DEFAULT_REGM2;
283 else
284 pi->regm2 = dssdev->clocks.hdmi.regm2;
c3198a5e 285
dd2116a3
M		 286 /*
287 * multiplier is pixel_clk/ref_clk
288 * Multiplying by 100 to avoid fractional part removal
289 */
290 pi->regm = phy * pi->regm2 / refclk;
291
c3198a5e
M		 292 /*
293 * fractional multiplier is remainder of the difference between
294 * multiplier and actual phy(required pixel clock thus should be
295 * multiplied by 2^18(262144) divided by the reference clock
296 */
dd2116a3
M		 297 mf = (phy - pi->regm / pi->regm2 * refclk) * 262144;
298 pi->regmf = pi->regm2 * mf / refclk;
c3198a5e
M		 299
300 /*
301 * Dcofreq should be set to 1 if required pixel clock
302 * is greater than 1000MHz
303 */
304 pi->dcofreq = phy > 1000 * 100;
b44e4582 305 pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10;
c3198a5e 306
7b27da54
M		 307 /* Set the reference clock to sysclk reference */
308 pi->refsel = HDMI_REFSEL_SYSCLK;
309
c3198a5e
M		 310 DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
311 DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
312}
313
c3198a5e
M		 314static int hdmi_power_on(struct omap_dss_device *dssdev)
315{
46095b2d
M		 316 int r;
317 const struct hdmi_config *timing;
c3198a5e 318 struct omap_video_timings *p;
6cb07b25 319 unsigned long phy;
c3198a5e 320
4fbafaf3
TV		 321 r = hdmi_runtime_get();
322 if (r)
323 return r;
c3198a5e 324
7797c6da 325 dss_mgr_disable(dssdev->manager);
c3198a5e
M		 326
327 p = &dssdev->panel.timings;
328
329 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n",
330 dssdev->panel.timings.x_res,
331 dssdev->panel.timings.y_res);
332
46095b2d
M		 333 timing = hdmi_get_timings();
334 if (timing == NULL) {
335 /* HDMI code 4 corresponds to 640 * 480 VGA */
9e4ed603 336 hdmi.ip_data.cfg.cm.code = 4;
46095b2d 337 /* DVI mode 1 corresponds to HDMI 0 to DVI */
9e4ed603 338 hdmi.ip_data.cfg.cm.mode = HDMI_DVI;
46095b2d
M		 339 hdmi.ip_data.cfg = vesa_timings[0];
340 } else {
341 hdmi.ip_data.cfg = *timing;
342 }
c3198a5e
M		 343 phy = p->pixel_clock;
344
7b27da54 345 hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data);
c3198a5e 346
60634a28 347 hdmi.ip_data.ops->video_enable(&hdmi.ip_data, 0);
c3198a5e 348
95a8aeb6 349 /* config the PLL and PHY hdmi_set_pll_pwrfirst */
60634a28 350 r = hdmi.ip_data.ops->pll_enable(&hdmi.ip_data);
c3198a5e
M		 351 if (r) {
352 DSSDBG("Failed to lock PLL\n");
353 goto err;
354 }
355
60634a28 356 r = hdmi.ip_data.ops->phy_enable(&hdmi.ip_data);
c3198a5e
M		 357 if (r) {
358 DSSDBG("Failed to start PHY\n");
359 goto err;
360 }
361
60634a28 362 hdmi.ip_data.ops->video_configure(&hdmi.ip_data);
c3198a5e
M		 363
364 /* Make selection of HDMI in DSS */
365 dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
366
367 /* Select the dispc clock source as PRCM clock, to ensure that it is not
368 * DSI PLL source as the clock selected by DSI PLL might not be
369 * sufficient for the resolution selected / that can be changed
370 * dynamically by user. This can be moved to single location , say
371 * Boardfile.
372 */
6cb07b25 373 dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
c3198a5e
M		 374
375 /* bypass TV gamma table */
376 dispc_enable_gamma_table(0);
377
378 /* tv size */
41721163 379 dss_mgr_set_timings(dssdev->manager, &dssdev->panel.timings);
c3198a5e 380
60634a28 381 hdmi.ip_data.ops->video_enable(&hdmi.ip_data, 1);
c3198a5e 382
33ca237f
TV		 383 r = dss_mgr_enable(dssdev->manager);
384 if (r)
385 goto err_mgr_enable;
3870c909 386
c3198a5e 387 return 0;
33ca237f
TV		 388
389err_mgr_enable:
390 hdmi.ip_data.ops->video_enable(&hdmi.ip_data, 0);
391 hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
392 hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
c3198a5e 393err:
4fbafaf3 394 hdmi_runtime_put();
c3198a5e
M		 395 return -EIO;
396}
397
398static void hdmi_power_off(struct omap_dss_device *dssdev)
399{
7797c6da 400 dss_mgr_disable(dssdev->manager);
c3198a5e 401
60634a28
M		 402 hdmi.ip_data.ops->video_enable(&hdmi.ip_data, 0);
403 hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
404 hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
4fbafaf3 405 hdmi_runtime_put();
c3198a5e
M		 406}
407
408int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
409 struct omap_video_timings *timings)
410{
411 struct hdmi_cm cm;
412
413 cm = hdmi_get_code(timings);
414 if (cm.code == -1) {
c3198a5e
M		 415 return -EINVAL;
416 }
417
418 return 0;
419
420}
421
422void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev)
423{
424 struct hdmi_cm cm;
425
c3198a5e 426 cm = hdmi_get_code(&dssdev->panel.timings);
9e4ed603
M		 427 hdmi.ip_data.cfg.cm.code = cm.code;
428 hdmi.ip_data.cfg.cm.mode = cm.mode;
fa70dc5f
TV		 429
430 if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
431 int r;
432
433 hdmi_power_off(dssdev);
434
435 r = hdmi_power_on(dssdev);
436 if (r)
437 DSSERR("failed to power on device\n");
fcc36619
AT		 438 } else {
439 dss_mgr_set_timings(dssdev->manager, &dssdev->panel.timings);
fa70dc5f 440 }
c3198a5e
M		 441}
442
162874d5
M		 443void hdmi_dump_regs(struct seq_file *s)
444{
445 mutex_lock(&hdmi.lock);
446
447 if (hdmi_runtime_get())
448 return;
449
450 hdmi.ip_data.ops->dump_wrapper(&hdmi.ip_data, s);
451 hdmi.ip_data.ops->dump_pll(&hdmi.ip_data, s);
452 hdmi.ip_data.ops->dump_phy(&hdmi.ip_data, s);
453 hdmi.ip_data.ops->dump_core(&hdmi.ip_data, s);
454
455 hdmi_runtime_put();
456 mutex_unlock(&hdmi.lock);
457}
458
47024565
TV		 459int omapdss_hdmi_read_edid(u8 *buf, int len)
460{
461 int r;
462
463 mutex_lock(&hdmi.lock);
464
465 r = hdmi_runtime_get();
466 BUG_ON(r);
467
468 r = hdmi.ip_data.ops->read_edid(&hdmi.ip_data, buf, len);
469
470 hdmi_runtime_put();
471 mutex_unlock(&hdmi.lock);
472
473 return r;
474}
475
759593ff
TV		 476bool omapdss_hdmi_detect(void)
477{
478 int r;
479
480 mutex_lock(&hdmi.lock);
481
482 r = hdmi_runtime_get();
483 BUG_ON(r);
484
485 r = hdmi.ip_data.ops->detect(&hdmi.ip_data);
486
487 hdmi_runtime_put();
488 mutex_unlock(&hdmi.lock);
489
490 return r == 1;
491}
492
c3198a5e
M		 493int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev)
494{
c49d005b 495 struct omap_dss_hdmi_data *priv = dssdev->data;
c3198a5e
M		 496 int r = 0;
497
498 DSSDBG("ENTER hdmi_display_enable\n");
499
500 mutex_lock(&hdmi.lock);
501
05e1d606
TV		 502 if (dssdev->manager == NULL) {
503 DSSERR("failed to enable display: no manager\n");
504 r = -ENODEV;
505 goto err0;
506 }
507
c49d005b
TV		 508 hdmi.ip_data.hpd_gpio = priv->hpd_gpio;
509
c3198a5e
M		 510 r = omap_dss_start_device(dssdev);
511 if (r) {
512 DSSERR("failed to start device\n");
513 goto err0;
514 }
515
516 if (dssdev->platform_enable) {
517 r = dssdev->platform_enable(dssdev);
518 if (r) {
519 DSSERR("failed to enable GPIO's\n");
520 goto err1;
521 }
522 }
523
524 r = hdmi_power_on(dssdev);
525 if (r) {
526 DSSERR("failed to power on device\n");
527 goto err2;
528 }
529
530 mutex_unlock(&hdmi.lock);
531 return 0;
532
533err2:
534 if (dssdev->platform_disable)
535 dssdev->platform_disable(dssdev);
536err1:
537 omap_dss_stop_device(dssdev);
538err0:
539 mutex_unlock(&hdmi.lock);
540 return r;
541}
542
543void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev)
544{
545 DSSDBG("Enter hdmi_display_disable\n");
546
547 mutex_lock(&hdmi.lock);
548
549 hdmi_power_off(dssdev);
550
551 if (dssdev->platform_disable)
552 dssdev->platform_disable(dssdev);
553
554 omap_dss_stop_device(dssdev);
555
556 mutex_unlock(&hdmi.lock);
557}
558
82335c4c
RN		 559#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
560 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
ad44cc32 561
edefcdad
RN		 562static int hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd,
563 struct snd_soc_dai *dai)
564{
565 struct snd_soc_pcm_runtime *rtd = substream->private_data;
566 struct snd_soc_codec *codec = rtd->codec;
567 struct platform_device *pdev = to_platform_device(codec->dev);
568 struct hdmi_ip_data *ip_data = snd_soc_codec_get_drvdata(codec);
569 int err = 0;
570
571 if (!(ip_data->ops) && !(ip_data->ops->audio_enable)) {
572 dev_err(&pdev->dev, "Cannot enable/disable audio\n");
573 return -ENODEV;
574 }
575
576 switch (cmd) {
577 case SNDRV_PCM_TRIGGER_START:
578 case SNDRV_PCM_TRIGGER_RESUME:
579 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
580 ip_data->ops->audio_enable(ip_data, true);
581 break;
582 case SNDRV_PCM_TRIGGER_STOP:
583 case SNDRV_PCM_TRIGGER_SUSPEND:
584 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
585 ip_data->ops->audio_enable(ip_data, false);
586 break;
587 default:
588 err = -EINVAL;
589 }
590 return err;
591}
592
284cb318 593static int hdmi_audio_hw_params(struct snd_pcm_substream *substream,
ad44cc32
RN		 594 struct snd_pcm_hw_params *params,
595 struct snd_soc_dai *dai)
596{
284cb318
RN		 597 struct snd_soc_pcm_runtime *rtd = substream->private_data;
598 struct snd_soc_codec *codec = rtd->codec;
599 struct hdmi_ip_data *ip_data = snd_soc_codec_get_drvdata(codec);
ad44cc32
RN		 600 struct hdmi_audio_format audio_format;
601 struct hdmi_audio_dma audio_dma;
602 struct hdmi_core_audio_config core_cfg;
603 struct hdmi_core_infoframe_audio aud_if_cfg;
604 int err, n, cts;
605 enum hdmi_core_audio_sample_freq sample_freq;
606
607 switch (params_format(params)) {
608 case SNDRV_PCM_FORMAT_S16_LE:
609 core_cfg.i2s_cfg.word_max_length =
610 HDMI_AUDIO_I2S_MAX_WORD_20BITS;
611 core_cfg.i2s_cfg.word_length = HDMI_AUDIO_I2S_CHST_WORD_16_BITS;
612 core_cfg.i2s_cfg.in_length_bits =
613 HDMI_AUDIO_I2S_INPUT_LENGTH_16;
614 core_cfg.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_LEFT;
615 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES;
616 audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS;
617 audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT;
618 audio_dma.transfer_size = 0x10;
619 break;
620 case SNDRV_PCM_FORMAT_S24_LE:
621 core_cfg.i2s_cfg.word_max_length =
622 HDMI_AUDIO_I2S_MAX_WORD_24BITS;
623 core_cfg.i2s_cfg.word_length = HDMI_AUDIO_I2S_CHST_WORD_24_BITS;
624 core_cfg.i2s_cfg.in_length_bits =
625 HDMI_AUDIO_I2S_INPUT_LENGTH_24;
626 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_ONESAMPLE;
627 audio_format.sample_size = HDMI_AUDIO_SAMPLE_24BITS;
628 audio_format.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
629 core_cfg.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
630 audio_dma.transfer_size = 0x20;
631 break;
632 default:
633 return -EINVAL;
634 }
635
636 switch (params_rate(params)) {
637 case 32000:
638 sample_freq = HDMI_AUDIO_FS_32000;
639 break;
640 case 44100:
641 sample_freq = HDMI_AUDIO_FS_44100;
642 break;
643 case 48000:
644 sample_freq = HDMI_AUDIO_FS_48000;
645 break;
646 default:
647 return -EINVAL;
648 }
649
95a8aeb6 650 err = hdmi_config_audio_acr(ip_data, params_rate(params), &n, &cts);
ad44cc32
RN		 651 if (err < 0)
652 return err;
653
654 /* Audio wrapper config */
655 audio_format.stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL;
656 audio_format.active_chnnls_msk = 0x03;
657 audio_format.type = HDMI_AUDIO_TYPE_LPCM;
658 audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
659 /* Disable start/stop signals of IEC 60958 blocks */
660 audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF;
661
662 audio_dma.block_size = 0xC0;
663 audio_dma.mode = HDMI_AUDIO_TRANSF_DMA;
664 audio_dma.fifo_threshold = 0x20; /* in number of samples */
665
95a8aeb6
M		 666 hdmi_wp_audio_config_dma(ip_data, &audio_dma);
667 hdmi_wp_audio_config_format(ip_data, &audio_format);
ad44cc32
RN		 668
669 /*
670 * I2S config
671 */
672 core_cfg.i2s_cfg.en_high_bitrate_aud = false;
673 /* Only used with high bitrate audio */
674 core_cfg.i2s_cfg.cbit_order = false;
675 /* Serial data and word select should change on sck rising edge */
676 core_cfg.i2s_cfg.sck_edge_mode = HDMI_AUDIO_I2S_SCK_EDGE_RISING;
677 core_cfg.i2s_cfg.vbit = HDMI_AUDIO_I2S_VBIT_FOR_PCM;
678 /* Set I2S word select polarity */
679 core_cfg.i2s_cfg.ws_polarity = HDMI_AUDIO_I2S_WS_POLARITY_LOW_IS_LEFT;
680 core_cfg.i2s_cfg.direction = HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST;
681 /* Set serial data to word select shift. See Phillips spec. */
682 core_cfg.i2s_cfg.shift = HDMI_AUDIO_I2S_FIRST_BIT_SHIFT;
683 /* Enable one of the four available serial data channels */
684 core_cfg.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN;
685
686 /* Core audio config */
687 core_cfg.freq_sample = sample_freq;
688 core_cfg.n = n;
689 core_cfg.cts = cts;
690 if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) {
691 core_cfg.aud_par_busclk = 0;
692 core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_SW;
f15511e2 693 core_cfg.use_mclk = dss_has_feature(FEAT_HDMI_AUDIO_USE_MCLK);
ad44cc32
RN		 694 } else {
695 core_cfg.aud_par_busclk = (((128 * 31) - 1) << 8);
696 core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_HW;
697 core_cfg.use_mclk = true;
ad44cc32 698 }
f15511e2
RN		 699
700 if (core_cfg.use_mclk)
701 core_cfg.mclk_mode = HDMI_AUDIO_MCLK_128FS;
ad44cc32
RN		 702 core_cfg.layout = HDMI_AUDIO_LAYOUT_2CH;
703 core_cfg.en_spdif = false;
704 /* Use sample frequency from channel status word */
705 core_cfg.fs_override = true;
706 /* Enable ACR packets */
707 core_cfg.en_acr_pkt = true;
708 /* Disable direct streaming digital audio */
709 core_cfg.en_dsd_audio = false;
710 /* Use parallel audio interface */
711 core_cfg.en_parallel_aud_input = true;
712
95a8aeb6 713 hdmi_core_audio_config(ip_data, &core_cfg);
ad44cc32
RN		 714
715 /*
716 * Configure packet
717 * info frame audio see doc CEA861-D page 74
718 */
719 aud_if_cfg.db1_coding_type = HDMI_INFOFRAME_AUDIO_DB1CT_FROM_STREAM;
720 aud_if_cfg.db1_channel_count = 2;
721 aud_if_cfg.db2_sample_freq = HDMI_INFOFRAME_AUDIO_DB2SF_FROM_STREAM;
722 aud_if_cfg.db2_sample_size = HDMI_INFOFRAME_AUDIO_DB2SS_FROM_STREAM;
723 aud_if_cfg.db4_channel_alloc = 0x00;
724 aud_if_cfg.db5_downmix_inh = false;
725 aud_if_cfg.db5_lsv = 0;
726
95a8aeb6 727 hdmi_core_audio_infoframe_config(ip_data, &aud_if_cfg);
ad44cc32
RN		 728 return 0;
729}
730
ad44cc32
RN		 731static int hdmi_audio_startup(struct snd_pcm_substream *substream,
732 struct snd_soc_dai *dai)
733{
9e4ed603 734 if (!hdmi.ip_data.cfg.cm.mode) {
ad44cc32
RN		 735 pr_err("Current video settings do not support audio.\n");
736 return -EIO;
737 }
738 return 0;
739}
740
b17ce117
RN		 741static int hdmi_audio_codec_probe(struct snd_soc_codec *codec)
742{
743 struct hdmi_ip_data *priv = &hdmi.ip_data;
744
745 snd_soc_codec_set_drvdata(codec, priv);
746 return 0;
747}
748
ad44cc32 749static struct snd_soc_codec_driver hdmi_audio_codec_drv = {
b17ce117 750 .probe = hdmi_audio_codec_probe,
ad44cc32
RN		 751};
752
753static struct snd_soc_dai_ops hdmi_audio_codec_ops = {
754 .hw_params = hdmi_audio_hw_params,
755 .trigger = hdmi_audio_trigger,
756 .startup = hdmi_audio_startup,
757};
758
759static struct snd_soc_dai_driver hdmi_codec_dai_drv = {
760 .name = "hdmi-audio-codec",
761 .playback = {
762 .channels_min = 2,
763 .channels_max = 2,
764 .rates = SNDRV_PCM_RATE_32000 |
765 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
766 .formats = SNDRV_PCM_FMTBIT_S16_LE |
767 SNDRV_PCM_FMTBIT_S24_LE,
768 },
769 .ops = &hdmi_audio_codec_ops,
770};
82335c4c
RN		 771#endif
772
4fbafaf3
TV		 773static int hdmi_get_clocks(struct platform_device *pdev)
774{
775 struct clk *clk;
776
777 clk = clk_get(&pdev->dev, "sys_clk");
778 if (IS_ERR(clk)) {
779 DSSERR("can't get sys_clk\n");
780 return PTR_ERR(clk);
781 }
782
783 hdmi.sys_clk = clk;
784
4fbafaf3
TV		 785 return 0;
786}
787
788static void hdmi_put_clocks(void)
789{
790 if (hdmi.sys_clk)
791 clk_put(hdmi.sys_clk);
4fbafaf3
TV		 792}
793
c3198a5e
M		 794/* HDMI HW IP initialisation */
795static int omapdss_hdmihw_probe(struct platform_device *pdev)
796{
797 struct resource *hdmi_mem;
4fbafaf3 798 int r;
c3198a5e
M		 799
800 hdmi.pdata = pdev->dev.platform_data;
801 hdmi.pdev = pdev;
802
803 mutex_init(&hdmi.lock);
804
805 hdmi_mem = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0);
806 if (!hdmi_mem) {
807 DSSERR("can't get IORESOURCE_MEM HDMI\n");
808 return -EINVAL;
809 }
810
811 /* Base address taken from platform */
95a8aeb6
M		 812 hdmi.ip_data.base_wp = ioremap(hdmi_mem->start,
813 resource_size(hdmi_mem));
814 if (!hdmi.ip_data.base_wp) {
c3198a5e
M		 815 DSSERR("can't ioremap WP\n");
816 return -ENOMEM;
817 }
818
4fbafaf3
TV		 819 r = hdmi_get_clocks(pdev);
820 if (r) {
95a8aeb6 821 iounmap(hdmi.ip_data.base_wp);
4fbafaf3
TV		 822 return r;
823 }
824
825 pm_runtime_enable(&pdev->dev);
826
95a8aeb6
M		 827 hdmi.ip_data.core_sys_offset = HDMI_CORE_SYS;
828 hdmi.ip_data.core_av_offset = HDMI_CORE_AV;
829 hdmi.ip_data.pll_offset = HDMI_PLLCTRL;
830 hdmi.ip_data.phy_offset = HDMI_PHY;
831
c3198a5e
M		 832 hdmi_panel_init();
833
ad44cc32
RN		 834#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
835 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
836
837 /* Register ASoC codec DAI */
4fbafaf3 838 r = snd_soc_register_codec(&pdev->dev, &hdmi_audio_codec_drv,
ad44cc32 839 &hdmi_codec_dai_drv, 1);
4fbafaf3 840 if (r) {
ad44cc32 841 DSSERR("can't register ASoC HDMI audio codec\n");
4fbafaf3 842 return r;
ad44cc32
RN		 843 }
844#endif
c3198a5e
M		 845 return 0;
846}
847
848static int omapdss_hdmihw_remove(struct platform_device *pdev)
849{
850 hdmi_panel_exit();
851
ad44cc32
RN		 852#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
853 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
854 snd_soc_unregister_codec(&pdev->dev);
855#endif
856
4fbafaf3
TV		 857 pm_runtime_disable(&pdev->dev);
858
859 hdmi_put_clocks();
860
95a8aeb6 861 iounmap(hdmi.ip_data.base_wp);
c3198a5e
M		 862
863 return 0;
864}
865
4fbafaf3
TV		 866static int hdmi_runtime_suspend(struct device *dev)
867{
4fbafaf3
TV		 868 clk_disable(hdmi.sys_clk);
869
870 dispc_runtime_put();
871 dss_runtime_put();
872
873 return 0;
874}
875
876static int hdmi_runtime_resume(struct device *dev)
877{
878 int r;
879
880 r = dss_runtime_get();
881 if (r < 0)
882 goto err_get_dss;
883
884 r = dispc_runtime_get();
885 if (r < 0)
886 goto err_get_dispc;
887
888
889 clk_enable(hdmi.sys_clk);
4fbafaf3
TV		 890
891 return 0;
892
893err_get_dispc:
894 dss_runtime_put();
895err_get_dss:
896 return r;
897}
898
899static const struct dev_pm_ops hdmi_pm_ops = {
900 .runtime_suspend = hdmi_runtime_suspend,
901 .runtime_resume = hdmi_runtime_resume,
902};
903
c3198a5e
M		 904static struct platform_driver omapdss_hdmihw_driver = {
905 .probe = omapdss_hdmihw_probe,
906 .remove = omapdss_hdmihw_remove,
907 .driver = {
908 .name = "omapdss_hdmi",
909 .owner = THIS_MODULE,
4fbafaf3 910 .pm = &hdmi_pm_ops,
c3198a5e
M		 911 },
912};
913
914int hdmi_init_platform_driver(void)
915{
916 return platform_driver_register(&omapdss_hdmihw_driver);
917}
918
919void hdmi_uninit_platform_driver(void)
920{
921 return platform_driver_unregister(&omapdss_hdmihw_driver);
922}
Linux kernel - Deliverables
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