[deliverable/linux.git] / drivers / video / omap2 / dss / hdmi.h

/*
 * hdmi.h
 *
 * HDMI driver definition for TI OMAP4 processors.
 *
 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef _OMAP4_DSS_HDMI_H_
#define _OMAP4_DSS_HDMI_H_

#include <linux/string.h>
#include <video/omapdss.h>

struct hdmi_reg { u16 idx; };

#define HDMI_REG(idx)			((const struct hdmi_reg) { idx })

/* HDMI Wrapper */

#define HDMI_WP_REVISION			HDMI_REG(0x0)
#define HDMI_WP_SYSCONFIG			HDMI_REG(0x10)
#define HDMI_WP_IRQSTATUS_RAW			HDMI_REG(0x24)
#define HDMI_WP_IRQSTATUS			HDMI_REG(0x28)
#define HDMI_WP_PWR_CTRL			HDMI_REG(0x40)
#define HDMI_WP_IRQENABLE_SET			HDMI_REG(0x2C)
#define HDMI_WP_VIDEO_CFG			HDMI_REG(0x50)
#define HDMI_WP_VIDEO_SIZE			HDMI_REG(0x60)
#define HDMI_WP_VIDEO_TIMING_H			HDMI_REG(0x68)
#define HDMI_WP_VIDEO_TIMING_V			HDMI_REG(0x6C)
#define HDMI_WP_WP_CLK				HDMI_REG(0x70)
#define HDMI_WP_AUDIO_CFG			HDMI_REG(0x80)
#define HDMI_WP_AUDIO_CFG2			HDMI_REG(0x84)
#define HDMI_WP_AUDIO_CTRL			HDMI_REG(0x88)
#define HDMI_WP_AUDIO_DATA			HDMI_REG(0x8C)

/* HDMI IP Core System */

#define HDMI_CORE_SYS_VND_IDL			HDMI_REG(0x0)
#define HDMI_CORE_SYS_DEV_IDL			HDMI_REG(0x8)
#define HDMI_CORE_SYS_DEV_IDH			HDMI_REG(0xC)
#define HDMI_CORE_SYS_DEV_REV			HDMI_REG(0x10)
#define HDMI_CORE_SYS_SRST			HDMI_REG(0x14)
#define HDMI_CORE_CTRL1				HDMI_REG(0x20)
#define HDMI_CORE_SYS_SYS_STAT			HDMI_REG(0x24)
#define HDMI_CORE_SYS_VID_ACEN			HDMI_REG(0x124)
#define HDMI_CORE_SYS_VID_MODE			HDMI_REG(0x128)
#define HDMI_CORE_SYS_INTR_STATE		HDMI_REG(0x1C0)
#define HDMI_CORE_SYS_INTR1			HDMI_REG(0x1C4)
#define HDMI_CORE_SYS_INTR2			HDMI_REG(0x1C8)
#define HDMI_CORE_SYS_INTR3			HDMI_REG(0x1CC)
#define HDMI_CORE_SYS_INTR4			HDMI_REG(0x1D0)
#define HDMI_CORE_SYS_UMASK1			HDMI_REG(0x1D4)
#define HDMI_CORE_SYS_TMDS_CTRL			HDMI_REG(0x208)
#define HDMI_CORE_SYS_DE_DLY			HDMI_REG(0xC8)
#define HDMI_CORE_SYS_DE_CTRL			HDMI_REG(0xCC)
#define HDMI_CORE_SYS_DE_TOP			HDMI_REG(0xD0)
#define HDMI_CORE_SYS_DE_CNTL			HDMI_REG(0xD8)
#define HDMI_CORE_SYS_DE_CNTH			HDMI_REG(0xDC)
#define HDMI_CORE_SYS_DE_LINL			HDMI_REG(0xE0)
#define HDMI_CORE_SYS_DE_LINH_1			HDMI_REG(0xE4)
#define HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC	0x1
#define HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC	0x1
#define HDMI_CORE_CTRL1_BSEL_24BITBUS		0x1
#define HDMI_CORE_CTRL1_EDGE_RISINGEDGE	0x1

/* HDMI DDC E-DID */
#define HDMI_CORE_DDC_CMD			HDMI_REG(0x3CC)
#define HDMI_CORE_DDC_STATUS			HDMI_REG(0x3C8)
#define HDMI_CORE_DDC_ADDR			HDMI_REG(0x3B4)
#define HDMI_CORE_DDC_OFFSET			HDMI_REG(0x3BC)
#define HDMI_CORE_DDC_COUNT1			HDMI_REG(0x3C0)
#define HDMI_CORE_DDC_COUNT2			HDMI_REG(0x3C4)
#define HDMI_CORE_DDC_DATA			HDMI_REG(0x3D0)
#define HDMI_CORE_DDC_SEGM			HDMI_REG(0x3B8)

/* HDMI IP Core Audio Video */

#define HDMI_CORE_AV_HDMI_CTRL			HDMI_REG(0xBC)
#define HDMI_CORE_AV_DPD			HDMI_REG(0xF4)
#define HDMI_CORE_AV_PB_CTRL1			HDMI_REG(0xF8)
#define HDMI_CORE_AV_PB_CTRL2			HDMI_REG(0xFC)
#define HDMI_CORE_AV_AVI_TYPE			HDMI_REG(0x100)
#define HDMI_CORE_AV_AVI_VERS			HDMI_REG(0x104)
#define HDMI_CORE_AV_AVI_LEN			HDMI_REG(0x108)
#define HDMI_CORE_AV_AVI_CHSUM			HDMI_REG(0x10C)
#define HDMI_CORE_AV_AVI_DBYTE(n)		HDMI_REG(n * 4 + 0x110)
#define HDMI_CORE_AV_AVI_DBYTE_NELEMS		HDMI_REG(15)
#define HDMI_CORE_AV_SPD_DBYTE			HDMI_REG(0x190)
#define HDMI_CORE_AV_SPD_DBYTE_NELEMS		HDMI_REG(27)
#define HDMI_CORE_AV_AUD_DBYTE(n)		HDMI_REG(n * 4 + 0x210)
#define HDMI_CORE_AV_AUD_DBYTE_NELEMS		HDMI_REG(10)
#define HDMI_CORE_AV_MPEG_DBYTE			HDMI_REG(0x290)
#define HDMI_CORE_AV_MPEG_DBYTE_NELEMS		HDMI_REG(27)
#define HDMI_CORE_AV_GEN_DBYTE			HDMI_REG(0x300)
#define HDMI_CORE_AV_GEN_DBYTE_NELEMS		HDMI_REG(31)
#define HDMI_CORE_AV_GEN2_DBYTE			HDMI_REG(0x380)
#define HDMI_CORE_AV_GEN2_DBYTE_NELEMS		HDMI_REG(31)
#define HDMI_CORE_AV_ACR_CTRL			HDMI_REG(0x4)
#define HDMI_CORE_AV_FREQ_SVAL			HDMI_REG(0x8)
#define HDMI_CORE_AV_N_SVAL1			HDMI_REG(0xC)
#define HDMI_CORE_AV_N_SVAL2			HDMI_REG(0x10)
#define HDMI_CORE_AV_N_SVAL3			HDMI_REG(0x14)
#define HDMI_CORE_AV_CTS_SVAL1			HDMI_REG(0x18)
#define HDMI_CORE_AV_CTS_SVAL2			HDMI_REG(0x1C)
#define HDMI_CORE_AV_CTS_SVAL3			HDMI_REG(0x20)
#define HDMI_CORE_AV_CTS_HVAL1			HDMI_REG(0x24)
#define HDMI_CORE_AV_CTS_HVAL2			HDMI_REG(0x28)
#define HDMI_CORE_AV_CTS_HVAL3			HDMI_REG(0x2C)
#define HDMI_CORE_AV_AUD_MODE			HDMI_REG(0x50)
#define HDMI_CORE_AV_SPDIF_CTRL			HDMI_REG(0x54)
#define HDMI_CORE_AV_HW_SPDIF_FS		HDMI_REG(0x60)
#define HDMI_CORE_AV_SWAP_I2S			HDMI_REG(0x64)
#define HDMI_CORE_AV_SPDIF_ERTH			HDMI_REG(0x6C)
#define HDMI_CORE_AV_I2S_IN_MAP			HDMI_REG(0x70)
#define HDMI_CORE_AV_I2S_IN_CTRL		HDMI_REG(0x74)
#define HDMI_CORE_AV_I2S_CHST0			HDMI_REG(0x78)
#define HDMI_CORE_AV_I2S_CHST1			HDMI_REG(0x7C)
#define HDMI_CORE_AV_I2S_CHST2			HDMI_REG(0x80)
#define HDMI_CORE_AV_I2S_CHST4			HDMI_REG(0x84)
#define HDMI_CORE_AV_I2S_CHST5			HDMI_REG(0x88)
#define HDMI_CORE_AV_ASRC			HDMI_REG(0x8C)
#define HDMI_CORE_AV_I2S_IN_LEN			HDMI_REG(0x90)
#define HDMI_CORE_AV_HDMI_CTRL			HDMI_REG(0xBC)
#define HDMI_CORE_AV_AUDO_TXSTAT		HDMI_REG(0xC0)
#define HDMI_CORE_AV_AUD_PAR_BUSCLK_1		HDMI_REG(0xCC)
#define HDMI_CORE_AV_AUD_PAR_BUSCLK_2		HDMI_REG(0xD0)
#define HDMI_CORE_AV_AUD_PAR_BUSCLK_3		HDMI_REG(0xD4)
#define HDMI_CORE_AV_TEST_TXCTRL		HDMI_REG(0xF0)
#define HDMI_CORE_AV_DPD			HDMI_REG(0xF4)
#define HDMI_CORE_AV_PB_CTRL1			HDMI_REG(0xF8)
#define HDMI_CORE_AV_PB_CTRL2			HDMI_REG(0xFC)
#define HDMI_CORE_AV_AVI_TYPE			HDMI_REG(0x100)
#define HDMI_CORE_AV_AVI_VERS			HDMI_REG(0x104)
#define HDMI_CORE_AV_AVI_LEN			HDMI_REG(0x108)
#define HDMI_CORE_AV_AVI_CHSUM			HDMI_REG(0x10C)
#define HDMI_CORE_AV_SPD_TYPE			HDMI_REG(0x180)
#define HDMI_CORE_AV_SPD_VERS			HDMI_REG(0x184)
#define HDMI_CORE_AV_SPD_LEN			HDMI_REG(0x188)
#define HDMI_CORE_AV_SPD_CHSUM			HDMI_REG(0x18C)
#define HDMI_CORE_AV_AUDIO_TYPE			HDMI_REG(0x200)
#define HDMI_CORE_AV_AUDIO_VERS			HDMI_REG(0x204)
#define HDMI_CORE_AV_AUDIO_LEN			HDMI_REG(0x208)
#define HDMI_CORE_AV_AUDIO_CHSUM		HDMI_REG(0x20C)
#define HDMI_CORE_AV_MPEG_TYPE			HDMI_REG(0x280)
#define HDMI_CORE_AV_MPEG_VERS			HDMI_REG(0x284)
#define HDMI_CORE_AV_MPEG_LEN			HDMI_REG(0x288)
#define HDMI_CORE_AV_MPEG_CHSUM			HDMI_REG(0x28C)
#define HDMI_CORE_AV_CP_BYTE1			HDMI_REG(0x37C)
#define HDMI_CORE_AV_CEC_ADDR_ID		HDMI_REG(0x3FC)
#define HDMI_CORE_AV_SPD_DBYTE_ELSIZE		0x4
#define HDMI_CORE_AV_GEN2_DBYTE_ELSIZE		0x4
#define HDMI_CORE_AV_MPEG_DBYTE_ELSIZE		0x4
#define HDMI_CORE_AV_GEN_DBYTE_ELSIZE		0x4

/* PLL */

#define PLLCTRL_PLL_CONTROL			HDMI_REG(0x0)
#define PLLCTRL_PLL_STATUS			HDMI_REG(0x4)
#define PLLCTRL_PLL_GO				HDMI_REG(0x8)
#define PLLCTRL_CFG1				HDMI_REG(0xC)
#define PLLCTRL_CFG2				HDMI_REG(0x10)
#define PLLCTRL_CFG3				HDMI_REG(0x14)
#define PLLCTRL_CFG4				HDMI_REG(0x20)

/* HDMI PHY */

#define HDMI_TXPHY_TX_CTRL			HDMI_REG(0x0)
#define HDMI_TXPHY_DIGITAL_CTRL			HDMI_REG(0x4)
#define HDMI_TXPHY_POWER_CTRL			HDMI_REG(0x8)
#define HDMI_TXPHY_PAD_CFG_CTRL			HDMI_REG(0xC)

/* HDMI EDID Length  */
#define HDMI_EDID_MAX_LENGTH			256
#define EDID_TIMING_DESCRIPTOR_SIZE		0x12
#define EDID_DESCRIPTOR_BLOCK0_ADDRESS		0x36
#define EDID_DESCRIPTOR_BLOCK1_ADDRESS		0x80
#define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR	4
#define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR	4

#define OMAP_HDMI_TIMINGS_NB			34

#define REG_FLD_MOD(base, idx, val, start, end) \
	hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
							val, start, end))
#define REG_GET(base, idx, start, end) \
	FLD_GET(hdmi_read_reg(base, idx), start, end)

enum hdmi_phy_pwr {
	HDMI_PHYPWRCMD_OFF = 0,
	HDMI_PHYPWRCMD_LDOON = 1,
	HDMI_PHYPWRCMD_TXON = 2
};

enum hdmi_core_inputbus_width {
	HDMI_INPUT_8BIT = 0,
	HDMI_INPUT_10BIT = 1,
	HDMI_INPUT_12BIT = 2
};

enum hdmi_core_dither_trunc {
	HDMI_OUTPUTTRUNCATION_8BIT = 0,
	HDMI_OUTPUTTRUNCATION_10BIT = 1,
	HDMI_OUTPUTTRUNCATION_12BIT = 2,
	HDMI_OUTPUTDITHER_8BIT = 3,
	HDMI_OUTPUTDITHER_10BIT = 4,
	HDMI_OUTPUTDITHER_12BIT = 5
};

enum hdmi_core_deepcolor_ed {
	HDMI_DEEPCOLORPACKECTDISABLE = 0,
	HDMI_DEEPCOLORPACKECTENABLE = 1
};

enum hdmi_core_packet_mode {
	HDMI_PACKETMODERESERVEDVALUE = 0,
	HDMI_PACKETMODE24BITPERPIXEL = 4,
	HDMI_PACKETMODE30BITPERPIXEL = 5,
	HDMI_PACKETMODE36BITPERPIXEL = 6,
	HDMI_PACKETMODE48BITPERPIXEL = 7
};

enum hdmi_core_tclkselclkmult {
	HDMI_FPLL05IDCK = 0,
	HDMI_FPLL10IDCK = 1,
	HDMI_FPLL20IDCK = 2,
	HDMI_FPLL40IDCK = 3
};

enum hdmi_core_packet_ctrl {
	HDMI_PACKETENABLE = 1,
	HDMI_PACKETDISABLE = 0,
	HDMI_PACKETREPEATON = 1,
	HDMI_PACKETREPEATOFF = 0
};

/* INFOFRAME_AVI_ and INFOFRAME_AUDIO_ definitions */
enum hdmi_core_infoframe {
	HDMI_INFOFRAME_AVI_DB1Y_RGB = 0,
	HDMI_INFOFRAME_AVI_DB1Y_YUV422 = 1,
	HDMI_INFOFRAME_AVI_DB1Y_YUV444 = 2,
	HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF = 0,
	HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_ON =  1,
	HDMI_INFOFRAME_AVI_DB1B_NO = 0,
	HDMI_INFOFRAME_AVI_DB1B_VERT = 1,
	HDMI_INFOFRAME_AVI_DB1B_HORI = 2,
	HDMI_INFOFRAME_AVI_DB1B_VERTHORI = 3,
	HDMI_INFOFRAME_AVI_DB1S_0 = 0,
	HDMI_INFOFRAME_AVI_DB1S_1 = 1,
	HDMI_INFOFRAME_AVI_DB1S_2 = 2,
	HDMI_INFOFRAME_AVI_DB2C_NO = 0,
	HDMI_INFOFRAME_AVI_DB2C_ITU601 = 1,
	HDMI_INFOFRAME_AVI_DB2C_ITU709 = 2,
	HDMI_INFOFRAME_AVI_DB2C_EC_EXTENDED = 3,
	HDMI_INFOFRAME_AVI_DB2M_NO = 0,
	HDMI_INFOFRAME_AVI_DB2M_43 = 1,
	HDMI_INFOFRAME_AVI_DB2M_169 = 2,
	HDMI_INFOFRAME_AVI_DB2R_SAME = 8,
	HDMI_INFOFRAME_AVI_DB2R_43 = 9,
	HDMI_INFOFRAME_AVI_DB2R_169 = 10,
	HDMI_INFOFRAME_AVI_DB2R_149 = 11,
	HDMI_INFOFRAME_AVI_DB3ITC_NO = 0,
	HDMI_INFOFRAME_AVI_DB3ITC_YES = 1,
	HDMI_INFOFRAME_AVI_DB3EC_XVYUV601 = 0,
	HDMI_INFOFRAME_AVI_DB3EC_XVYUV709 = 1,
	HDMI_INFOFRAME_AVI_DB3Q_DEFAULT = 0,
	HDMI_INFOFRAME_AVI_DB3Q_LR = 1,
	HDMI_INFOFRAME_AVI_DB3Q_FR = 2,
	HDMI_INFOFRAME_AVI_DB3SC_NO = 0,
	HDMI_INFOFRAME_AVI_DB3SC_HORI = 1,
	HDMI_INFOFRAME_AVI_DB3SC_VERT = 2,
	HDMI_INFOFRAME_AVI_DB3SC_HORIVERT = 3,
	HDMI_INFOFRAME_AVI_DB5PR_NO = 0,
	HDMI_INFOFRAME_AVI_DB5PR_2 = 1,
	HDMI_INFOFRAME_AVI_DB5PR_3 = 2,
	HDMI_INFOFRAME_AVI_DB5PR_4 = 3,
	HDMI_INFOFRAME_AVI_DB5PR_5 = 4,
	HDMI_INFOFRAME_AVI_DB5PR_6 = 5,
	HDMI_INFOFRAME_AVI_DB5PR_7 = 6,
	HDMI_INFOFRAME_AVI_DB5PR_8 = 7,
	HDMI_INFOFRAME_AVI_DB5PR_9 = 8,
	HDMI_INFOFRAME_AVI_DB5PR_10 = 9,
	HDMI_INFOFRAME_AUDIO_DB1CT_FROM_STREAM = 0,
	HDMI_INFOFRAME_AUDIO_DB1CT_IEC60958 = 1,
	HDMI_INFOFRAME_AUDIO_DB1CT_AC3 = 2,
	HDMI_INFOFRAME_AUDIO_DB1CT_MPEG1 = 3,
	HDMI_INFOFRAME_AUDIO_DB1CT_MP3 = 4,
	HDMI_INFOFRAME_AUDIO_DB1CT_MPEG2_MULTICH = 5,
	HDMI_INFOFRAME_AUDIO_DB1CT_AAC = 6,
	HDMI_INFOFRAME_AUDIO_DB1CT_DTS = 7,
	HDMI_INFOFRAME_AUDIO_DB1CT_ATRAC = 8,
	HDMI_INFOFRAME_AUDIO_DB1CT_ONEBIT = 9,
	HDMI_INFOFRAME_AUDIO_DB1CT_DOLBY_DIGITAL_PLUS = 10,
	HDMI_INFOFRAME_AUDIO_DB1CT_DTS_HD = 11,
	HDMI_INFOFRAME_AUDIO_DB1CT_MAT = 12,
	HDMI_INFOFRAME_AUDIO_DB1CT_DST = 13,
	HDMI_INFOFRAME_AUDIO_DB1CT_WMA_PRO = 14,
	HDMI_INFOFRAME_AUDIO_DB2SF_FROM_STREAM = 0,
	HDMI_INFOFRAME_AUDIO_DB2SF_32000 = 1,
	HDMI_INFOFRAME_AUDIO_DB2SF_44100 = 2,
	HDMI_INFOFRAME_AUDIO_DB2SF_48000 = 3,
	HDMI_INFOFRAME_AUDIO_DB2SF_88200 = 4,
	HDMI_INFOFRAME_AUDIO_DB2SF_96000 = 5,
	HDMI_INFOFRAME_AUDIO_DB2SF_176400 = 6,
	HDMI_INFOFRAME_AUDIO_DB2SF_192000 = 7,
	HDMI_INFOFRAME_AUDIO_DB2SS_FROM_STREAM = 0,
	HDMI_INFOFRAME_AUDIO_DB2SS_16BIT = 1,
	HDMI_INFOFRAME_AUDIO_DB2SS_20BIT = 2,
	HDMI_INFOFRAME_AUDIO_DB2SS_24BIT = 3,
	HDMI_INFOFRAME_AUDIO_DB5_DM_INH_PERMITTED = 0,
	HDMI_INFOFRAME_AUDIO_DB5_DM_INH_PROHIBITED = 1
};

enum hdmi_packing_mode {
	HDMI_PACK_10b_RGB_YUV444 = 0,
	HDMI_PACK_24b_RGB_YUV444_YUV422 = 1,
	HDMI_PACK_20b_YUV422 = 2,
	HDMI_PACK_ALREADYPACKED = 7
};

enum hdmi_core_audio_sample_freq {
	HDMI_AUDIO_FS_32000 = 0x3,
	HDMI_AUDIO_FS_44100 = 0x0,
	HDMI_AUDIO_FS_48000 = 0x2,
	HDMI_AUDIO_FS_88200 = 0x8,
	HDMI_AUDIO_FS_96000 = 0xA,
	HDMI_AUDIO_FS_176400 = 0xC,
	HDMI_AUDIO_FS_192000 = 0xE,
	HDMI_AUDIO_FS_NOT_INDICATED = 0x1
};

enum hdmi_core_audio_layout {
	HDMI_AUDIO_LAYOUT_2CH = 0,
	HDMI_AUDIO_LAYOUT_8CH = 1
};

enum hdmi_core_cts_mode {
	HDMI_AUDIO_CTS_MODE_HW = 0,
	HDMI_AUDIO_CTS_MODE_SW = 1
};

enum hdmi_stereo_channels {
	HDMI_AUDIO_STEREO_NOCHANNELS = 0,
	HDMI_AUDIO_STEREO_ONECHANNEL = 1,
	HDMI_AUDIO_STEREO_TWOCHANNELS = 2,
	HDMI_AUDIO_STEREO_THREECHANNELS = 3,
	HDMI_AUDIO_STEREO_FOURCHANNELS = 4
};

enum hdmi_audio_type {
	HDMI_AUDIO_TYPE_LPCM = 0,
	HDMI_AUDIO_TYPE_IEC = 1
};

enum hdmi_audio_justify {
	HDMI_AUDIO_JUSTIFY_LEFT = 0,
	HDMI_AUDIO_JUSTIFY_RIGHT = 1
};

enum hdmi_audio_sample_order {
	HDMI_AUDIO_SAMPLE_RIGHT_FIRST = 0,
	HDMI_AUDIO_SAMPLE_LEFT_FIRST = 1
};

enum hdmi_audio_samples_perword {
	HDMI_AUDIO_ONEWORD_ONESAMPLE = 0,
	HDMI_AUDIO_ONEWORD_TWOSAMPLES = 1
};

enum hdmi_audio_sample_size {
	HDMI_AUDIO_SAMPLE_16BITS = 0,
	HDMI_AUDIO_SAMPLE_24BITS = 1
};

enum hdmi_audio_transf_mode {
	HDMI_AUDIO_TRANSF_DMA = 0,
	HDMI_AUDIO_TRANSF_IRQ = 1
};

enum hdmi_audio_blk_strt_end_sig {
	HDMI_AUDIO_BLOCK_SIG_STARTEND_ON = 0,
	HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1
};

enum hdmi_audio_i2s_config {
	HDMI_AUDIO_I2S_WS_POLARITY_LOW_IS_LEFT = 0,
	HDMI_AUDIO_I2S_WS_POLARIT_YLOW_IS_RIGHT = 1,
	HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST = 0,
	HDMI_AUDIO_I2S_LSB_SHIFTED_FIRST = 1,
	HDMI_AUDIO_I2S_MAX_WORD_20BITS = 0,
	HDMI_AUDIO_I2S_MAX_WORD_24BITS = 1,
	HDMI_AUDIO_I2S_CHST_WORD_NOT_SPECIFIED = 0,
	HDMI_AUDIO_I2S_CHST_WORD_16_BITS = 1,
	HDMI_AUDIO_I2S_CHST_WORD_17_BITS = 6,
	HDMI_AUDIO_I2S_CHST_WORD_18_BITS = 2,
	HDMI_AUDIO_I2S_CHST_WORD_19_BITS = 4,
	HDMI_AUDIO_I2S_CHST_WORD_20_BITS_20MAX = 5,
	HDMI_AUDIO_I2S_CHST_WORD_20_BITS_24MAX = 1,
	HDMI_AUDIO_I2S_CHST_WORD_21_BITS = 6,
	HDMI_AUDIO_I2S_CHST_WORD_22_BITS = 2,
	HDMI_AUDIO_I2S_CHST_WORD_23_BITS = 4,
	HDMI_AUDIO_I2S_CHST_WORD_24_BITS = 5,
	HDMI_AUDIO_I2S_SCK_EDGE_FALLING = 0,
	HDMI_AUDIO_I2S_SCK_EDGE_RISING = 1,
	HDMI_AUDIO_I2S_VBIT_FOR_PCM = 0,
	HDMI_AUDIO_I2S_VBIT_FOR_COMPRESSED = 1,
	HDMI_AUDIO_I2S_INPUT_LENGTH_NA = 0,
	HDMI_AUDIO_I2S_INPUT_LENGTH_16 = 2,
	HDMI_AUDIO_I2S_INPUT_LENGTH_17 = 12,
	HDMI_AUDIO_I2S_INPUT_LENGTH_18 = 4,
	HDMI_AUDIO_I2S_INPUT_LENGTH_19 = 8,
	HDMI_AUDIO_I2S_INPUT_LENGTH_20 = 10,
	HDMI_AUDIO_I2S_INPUT_LENGTH_21 = 13,
	HDMI_AUDIO_I2S_INPUT_LENGTH_22 = 5,
	HDMI_AUDIO_I2S_INPUT_LENGTH_23 = 9,
	HDMI_AUDIO_I2S_INPUT_LENGTH_24 = 11,
	HDMI_AUDIO_I2S_FIRST_BIT_SHIFT = 0,
	HDMI_AUDIO_I2S_FIRST_BIT_NO_SHIFT = 1,
	HDMI_AUDIO_I2S_SD0_EN = 1,
	HDMI_AUDIO_I2S_SD1_EN = 1 << 1,
	HDMI_AUDIO_I2S_SD2_EN = 1 << 2,
	HDMI_AUDIO_I2S_SD3_EN = 1 << 3,
};

enum hdmi_audio_mclk_mode {
	HDMI_AUDIO_MCLK_128FS = 0,
	HDMI_AUDIO_MCLK_256FS = 1,
	HDMI_AUDIO_MCLK_384FS = 2,
	HDMI_AUDIO_MCLK_512FS = 3,
	HDMI_AUDIO_MCLK_768FS = 4,
	HDMI_AUDIO_MCLK_1024FS = 5,
	HDMI_AUDIO_MCLK_1152FS = 6,
	HDMI_AUDIO_MCLK_192FS = 7
};

struct hdmi_core_video_config {
	enum hdmi_core_inputbus_width	ip_bus_width;
	enum hdmi_core_dither_trunc	op_dither_truc;
	enum hdmi_core_deepcolor_ed	deep_color_pkt;
	enum hdmi_core_packet_mode	pkt_mode;
	enum hdmi_core_hdmi_dvi		hdmi_dvi;
	enum hdmi_core_tclkselclkmult	tclk_sel_clkmult;
};

/*
 * Refer to section 8.2 in HDMI 1.3 specification for
 * details about infoframe databytes
 */
struct hdmi_core_infoframe_avi {
	u8	db1_format;
		/* Y0, Y1 rgb,yCbCr */
	u8	db1_active_info;
		/* A0  Active information Present */
	u8	db1_bar_info_dv;
		/* B0, B1 Bar info data valid */
	u8	db1_scan_info;
		/* S0, S1 scan information */
	u8	db2_colorimetry;
		/* C0, C1 colorimetry */
	u8	db2_aspect_ratio;
		/* M0, M1 Aspect ratio (4:3, 16:9) */
	u8	db2_active_fmt_ar;
		/* R0...R3 Active format aspect ratio */
	u8	db3_itc;
		/* ITC IT content. */
	u8	db3_ec;
		/* EC0, EC1, EC2 Extended colorimetry */
	u8	db3_q_range;
		/* Q1, Q0 Quantization range */
	u8	db3_nup_scaling;
		/* SC1, SC0 Non-uniform picture scaling */
	u8	db4_videocode;
		/* VIC0..6 Video format identification */
	u8	db5_pixel_repeat;
		/* PR0..PR3 Pixel repetition factor */
	u16	db6_7_line_eoftop;
		/* Line number end of top bar */
	u16	db8_9_line_sofbottom;
		/* Line number start of bottom bar */
	u16	db10_11_pixel_eofleft;
		/* Pixel number end of left bar */
	u16	db12_13_pixel_sofright;
		/* Pixel number start of right bar */
};
/*
 * Refer to section 8.2 in HDMI 1.3 specification for
 * details about infoframe databytes
 */
struct hdmi_core_infoframe_audio {
	u8 db1_coding_type;
	u8 db1_channel_count;
	u8 db2_sample_freq;
	u8 db2_sample_size;
	u8 db4_channel_alloc;
	bool db5_downmix_inh;
	u8 db5_lsv;	/* Level shift values for downmix */
};

struct hdmi_core_packet_enable_repeat {
	u32	audio_pkt;
	u32	audio_pkt_repeat;
	u32	avi_infoframe;
	u32	avi_infoframe_repeat;
	u32	gen_cntrl_pkt;
	u32	gen_cntrl_pkt_repeat;
	u32	generic_pkt;
	u32	generic_pkt_repeat;
};

struct hdmi_video_format {
	enum hdmi_packing_mode	packing_mode;
	u32			y_res;	/* Line per panel */
	u32			x_res;	/* pixel per line */
};

struct hdmi_video_interface {
	int	vsp;	/* Vsync polarity */
	int	hsp;	/* Hsync polarity */
	int	interlacing;
	int	tm;	/* Timing mode */
};

struct hdmi_audio_format {
	enum hdmi_stereo_channels		stereo_channels;
	u8					active_chnnls_msk;
	enum hdmi_audio_type			type;
	enum hdmi_audio_justify			justification;
	enum hdmi_audio_sample_order		sample_order;
	enum hdmi_audio_samples_perword		samples_per_word;
	enum hdmi_audio_sample_size		sample_size;
	enum hdmi_audio_blk_strt_end_sig	en_sig_blk_strt_end;
};

struct hdmi_audio_dma {
	u8				transfer_size;
	u8				block_size;
	enum hdmi_audio_transf_mode	mode;
	u16				fifo_threshold;
};

struct hdmi_core_audio_i2s_config {
	u8 word_max_length;
	u8 word_length;
	u8 in_length_bits;
	u8 justification;
	u8 en_high_bitrate_aud;
	u8 sck_edge_mode;
	u8 cbit_order;
	u8 vbit;
	u8 ws_polarity;
	u8 direction;
	u8 shift;
	u8 active_sds;
};

struct hdmi_core_audio_config {
	struct hdmi_core_audio_i2s_config	i2s_cfg;
	enum hdmi_core_audio_sample_freq	freq_sample;
	bool					fs_override;
	u32					n;
	u32					cts;
	u32					aud_par_busclk;
	enum hdmi_core_audio_layout		layout;
	enum hdmi_core_cts_mode			cts_mode;
	bool					use_mclk;
	enum hdmi_audio_mclk_mode		mclk_mode;
	bool					en_acr_pkt;
	bool					en_dsd_audio;
	bool					en_parallel_aud_input;
	bool					en_spdif;
};
#endif
Commit	Line	Data
26adeece M	1	/*
	2	* hdmi.h
	3	*
	4	* HDMI driver definition for TI OMAP4 processors.
	5	*
	6	* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License version 2 as published by
	10	* the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	15	* more details.
	16	*
	17	* You should have received a copy of the GNU General Public License along with
	18	* this program. If not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
	21	#ifndef _OMAP4_DSS_HDMI_H_
	22	#define _OMAP4_DSS_HDMI_H_
	23
	24	#include <linux/string.h>
a0b38cc4	25	#include <video/omapdss.h>
26adeece	26
26adeece M	27	struct hdmi_reg { u16 idx; };
	28
	29	#define HDMI_REG(idx) ((const struct hdmi_reg) { idx })
	30
	31	/* HDMI Wrapper */
95a8aeb6 M	32
	33	#define HDMI_WP_REVISION HDMI_REG(0x0)
	34	#define HDMI_WP_SYSCONFIG HDMI_REG(0x10)
	35	#define HDMI_WP_IRQSTATUS_RAW HDMI_REG(0x24)
	36	#define HDMI_WP_IRQSTATUS HDMI_REG(0x28)
	37	#define HDMI_WP_PWR_CTRL HDMI_REG(0x40)
	38	#define HDMI_WP_IRQENABLE_SET HDMI_REG(0x2C)
	39	#define HDMI_WP_VIDEO_CFG HDMI_REG(0x50)
	40	#define HDMI_WP_VIDEO_SIZE HDMI_REG(0x60)
	41	#define HDMI_WP_VIDEO_TIMING_H HDMI_REG(0x68)
	42	#define HDMI_WP_VIDEO_TIMING_V HDMI_REG(0x6C)
	43	#define HDMI_WP_WP_CLK HDMI_REG(0x70)
	44	#define HDMI_WP_AUDIO_CFG HDMI_REG(0x80)
	45	#define HDMI_WP_AUDIO_CFG2 HDMI_REG(0x84)
	46	#define HDMI_WP_AUDIO_CTRL HDMI_REG(0x88)
	47	#define HDMI_WP_AUDIO_DATA HDMI_REG(0x8C)
26adeece M	48
26adeece M	49	/* HDMI IP Core System */
95a8aeb6 M	50
	51	#define HDMI_CORE_SYS_VND_IDL HDMI_REG(0x0)
	52	#define HDMI_CORE_SYS_DEV_IDL HDMI_REG(0x8)
	53	#define HDMI_CORE_SYS_DEV_IDH HDMI_REG(0xC)
	54	#define HDMI_CORE_SYS_DEV_REV HDMI_REG(0x10)
	55	#define HDMI_CORE_SYS_SRST HDMI_REG(0x14)
	56	#define HDMI_CORE_CTRL1 HDMI_REG(0x20)
	57	#define HDMI_CORE_SYS_SYS_STAT HDMI_REG(0x24)
	58	#define HDMI_CORE_SYS_VID_ACEN HDMI_REG(0x124)
	59	#define HDMI_CORE_SYS_VID_MODE HDMI_REG(0x128)
	60	#define HDMI_CORE_SYS_INTR_STATE HDMI_REG(0x1C0)
	61	#define HDMI_CORE_SYS_INTR1 HDMI_REG(0x1C4)
	62	#define HDMI_CORE_SYS_INTR2 HDMI_REG(0x1C8)
	63	#define HDMI_CORE_SYS_INTR3 HDMI_REG(0x1CC)
	64	#define HDMI_CORE_SYS_INTR4 HDMI_REG(0x1D0)
	65	#define HDMI_CORE_SYS_UMASK1 HDMI_REG(0x1D4)
	66	#define HDMI_CORE_SYS_TMDS_CTRL HDMI_REG(0x208)
	67	#define HDMI_CORE_SYS_DE_DLY HDMI_REG(0xC8)
	68	#define HDMI_CORE_SYS_DE_CTRL HDMI_REG(0xCC)
	69	#define HDMI_CORE_SYS_DE_TOP HDMI_REG(0xD0)
	70	#define HDMI_CORE_SYS_DE_CNTL HDMI_REG(0xD8)
	71	#define HDMI_CORE_SYS_DE_CNTH HDMI_REG(0xDC)
	72	#define HDMI_CORE_SYS_DE_LINL HDMI_REG(0xE0)
	73	#define HDMI_CORE_SYS_DE_LINH_1 HDMI_REG(0xE4)
26adeece M	74	#define HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC 0x1
	75	#define HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC 0x1
	76	#define HDMI_CORE_CTRL1_BSEL_24BITBUS 0x1
	77	#define HDMI_CORE_CTRL1_EDGE_RISINGEDGE 0x1
	78
	79	/* HDMI DDC E-DID */
95a8aeb6 M	80	#define HDMI_CORE_DDC_CMD HDMI_REG(0x3CC)
	81	#define HDMI_CORE_DDC_STATUS HDMI_REG(0x3C8)
	82	#define HDMI_CORE_DDC_ADDR HDMI_REG(0x3B4)
	83	#define HDMI_CORE_DDC_OFFSET HDMI_REG(0x3BC)
	84	#define HDMI_CORE_DDC_COUNT1 HDMI_REG(0x3C0)
	85	#define HDMI_CORE_DDC_COUNT2 HDMI_REG(0x3C4)
	86	#define HDMI_CORE_DDC_DATA HDMI_REG(0x3D0)
	87	#define HDMI_CORE_DDC_SEGM HDMI_REG(0x3B8)
26adeece M	88
26adeece M	89	/* HDMI IP Core Audio Video */
95a8aeb6 M	90
	91	#define HDMI_CORE_AV_HDMI_CTRL HDMI_REG(0xBC)
	92	#define HDMI_CORE_AV_DPD HDMI_REG(0xF4)
	93	#define HDMI_CORE_AV_PB_CTRL1 HDMI_REG(0xF8)
	94	#define HDMI_CORE_AV_PB_CTRL2 HDMI_REG(0xFC)
	95	#define HDMI_CORE_AV_AVI_TYPE HDMI_REG(0x100)
	96	#define HDMI_CORE_AV_AVI_VERS HDMI_REG(0x104)
	97	#define HDMI_CORE_AV_AVI_LEN HDMI_REG(0x108)
	98	#define HDMI_CORE_AV_AVI_CHSUM HDMI_REG(0x10C)
	99	#define HDMI_CORE_AV_AVI_DBYTE(n) HDMI_REG(n * 4 + 0x110)
	100	#define HDMI_CORE_AV_AVI_DBYTE_NELEMS HDMI_REG(15)
	101	#define HDMI_CORE_AV_SPD_DBYTE HDMI_REG(0x190)
	102	#define HDMI_CORE_AV_SPD_DBYTE_NELEMS HDMI_REG(27)
	103	#define HDMI_CORE_AV_AUD_DBYTE(n) HDMI_REG(n * 4 + 0x210)
	104	#define HDMI_CORE_AV_AUD_DBYTE_NELEMS HDMI_REG(10)
	105	#define HDMI_CORE_AV_MPEG_DBYTE HDMI_REG(0x290)
	106	#define HDMI_CORE_AV_MPEG_DBYTE_NELEMS HDMI_REG(27)
	107	#define HDMI_CORE_AV_GEN_DBYTE HDMI_REG(0x300)
	108	#define HDMI_CORE_AV_GEN_DBYTE_NELEMS HDMI_REG(31)
	109	#define HDMI_CORE_AV_GEN2_DBYTE HDMI_REG(0x380)
	110	#define HDMI_CORE_AV_GEN2_DBYTE_NELEMS HDMI_REG(31)
	111	#define HDMI_CORE_AV_ACR_CTRL HDMI_REG(0x4)
	112	#define HDMI_CORE_AV_FREQ_SVAL HDMI_REG(0x8)
	113	#define HDMI_CORE_AV_N_SVAL1 HDMI_REG(0xC)
	114	#define HDMI_CORE_AV_N_SVAL2 HDMI_REG(0x10)
	115	#define HDMI_CORE_AV_N_SVAL3 HDMI_REG(0x14)
	116	#define HDMI_CORE_AV_CTS_SVAL1 HDMI_REG(0x18)
	117	#define HDMI_CORE_AV_CTS_SVAL2 HDMI_REG(0x1C)
	118	#define HDMI_CORE_AV_CTS_SVAL3 HDMI_REG(0x20)
	119	#define HDMI_CORE_AV_CTS_HVAL1 HDMI_REG(0x24)
	120	#define HDMI_CORE_AV_CTS_HVAL2 HDMI_REG(0x28)
	121	#define HDMI_CORE_AV_CTS_HVAL3 HDMI_REG(0x2C)
	122	#define HDMI_CORE_AV_AUD_MODE HDMI_REG(0x50)
	123	#define HDMI_CORE_AV_SPDIF_CTRL HDMI_REG(0x54)
	124	#define HDMI_CORE_AV_HW_SPDIF_FS HDMI_REG(0x60)
	125	#define HDMI_CORE_AV_SWAP_I2S HDMI_REG(0x64)
	126	#define HDMI_CORE_AV_SPDIF_ERTH HDMI_REG(0x6C)
	127	#define HDMI_CORE_AV_I2S_IN_MAP HDMI_REG(0x70)
	128	#define HDMI_CORE_AV_I2S_IN_CTRL HDMI_REG(0x74)
	129	#define HDMI_CORE_AV_I2S_CHST0 HDMI_REG(0x78)
	130	#define HDMI_CORE_AV_I2S_CHST1 HDMI_REG(0x7C)
	131	#define HDMI_CORE_AV_I2S_CHST2 HDMI_REG(0x80)
	132	#define HDMI_CORE_AV_I2S_CHST4 HDMI_REG(0x84)
	133	#define HDMI_CORE_AV_I2S_CHST5 HDMI_REG(0x88)
	134	#define HDMI_CORE_AV_ASRC HDMI_REG(0x8C)
	135	#define HDMI_CORE_AV_I2S_IN_LEN HDMI_REG(0x90)
	136	#define HDMI_CORE_AV_HDMI_CTRL HDMI_REG(0xBC)
	137	#define HDMI_CORE_AV_AUDO_TXSTAT HDMI_REG(0xC0)
	138	#define HDMI_CORE_AV_AUD_PAR_BUSCLK_1 HDMI_REG(0xCC)
	139	#define HDMI_CORE_AV_AUD_PAR_BUSCLK_2 HDMI_REG(0xD0)
	140	#define HDMI_CORE_AV_AUD_PAR_BUSCLK_3 HDMI_REG(0xD4)
	141	#define HDMI_CORE_AV_TEST_TXCTRL HDMI_REG(0xF0)
	142	#define HDMI_CORE_AV_DPD HDMI_REG(0xF4)
	143	#define HDMI_CORE_AV_PB_CTRL1 HDMI_REG(0xF8)
	144	#define HDMI_CORE_AV_PB_CTRL2 HDMI_REG(0xFC)
	145	#define HDMI_CORE_AV_AVI_TYPE HDMI_REG(0x100)
	146	#define HDMI_CORE_AV_AVI_VERS HDMI_REG(0x104)
	147	#define HDMI_CORE_AV_AVI_LEN HDMI_REG(0x108)
	148	#define HDMI_CORE_AV_AVI_CHSUM HDMI_REG(0x10C)
	149	#define HDMI_CORE_AV_SPD_TYPE HDMI_REG(0x180)
	150	#define HDMI_CORE_AV_SPD_VERS HDMI_REG(0x184)
	151	#define HDMI_CORE_AV_SPD_LEN HDMI_REG(0x188)
	152	#define HDMI_CORE_AV_SPD_CHSUM HDMI_REG(0x18C)
	153	#define HDMI_CORE_AV_AUDIO_TYPE HDMI_REG(0x200)
154	#define HDMI_CORE_AV_AUDIO_VERS HDMI_REG(0x204)
155	#define HDMI_CORE_AV_AUDIO_LEN HDMI_REG(0x208)
156	#define HDMI_CORE_AV_AUDIO_CHSUM HDMI_REG(0x20C)
157	#define HDMI_CORE_AV_MPEG_TYPE HDMI_REG(0x280)
158	#define HDMI_CORE_AV_MPEG_VERS HDMI_REG(0x284)
159	#define HDMI_CORE_AV_MPEG_LEN HDMI_REG(0x288)
160	#define HDMI_CORE_AV_MPEG_CHSUM HDMI_REG(0x28C)
161	#define HDMI_CORE_AV_CP_BYTE1 HDMI_REG(0x37C)
162	#define HDMI_CORE_AV_CEC_ADDR_ID HDMI_REG(0x3FC)
26adeece M	163	#define HDMI_CORE_AV_SPD_DBYTE_ELSIZE 0x4
	164	#define HDMI_CORE_AV_GEN2_DBYTE_ELSIZE 0x4
	165	#define HDMI_CORE_AV_MPEG_DBYTE_ELSIZE 0x4
	166	#define HDMI_CORE_AV_GEN_DBYTE_ELSIZE 0x4
	167
	168	/* PLL */
26adeece	169
95a8aeb6 M	170	#define PLLCTRL_PLL_CONTROL HDMI_REG(0x0)
	171	#define PLLCTRL_PLL_STATUS HDMI_REG(0x4)
	172	#define PLLCTRL_PLL_GO HDMI_REG(0x8)
	173	#define PLLCTRL_CFG1 HDMI_REG(0xC)
	174	#define PLLCTRL_CFG2 HDMI_REG(0x10)
	175	#define PLLCTRL_CFG3 HDMI_REG(0x14)
	176	#define PLLCTRL_CFG4 HDMI_REG(0x20)
26adeece M	177
26adeece M	178	/* HDMI PHY */
26adeece	179
95a8aeb6 M	180	#define HDMI_TXPHY_TX_CTRL HDMI_REG(0x0)
	181	#define HDMI_TXPHY_DIGITAL_CTRL HDMI_REG(0x4)
	182	#define HDMI_TXPHY_POWER_CTRL HDMI_REG(0x8)
	183	#define HDMI_TXPHY_PAD_CFG_CTRL HDMI_REG(0xC)
26adeece M	184
	185	/* HDMI EDID Length */
	186	#define HDMI_EDID_MAX_LENGTH 256
	187	#define EDID_TIMING_DESCRIPTOR_SIZE 0x12
	188	#define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36
	189	#define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80
	190	#define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4
	191	#define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4
	192
	193	#define OMAP_HDMI_TIMINGS_NB 34
	194
95a8aeb6 M	195	#define REG_FLD_MOD(base, idx, val, start, end) \
	196	hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
	197	val, start, end))
	198	#define REG_GET(base, idx, start, end) \
	199	FLD_GET(hdmi_read_reg(base, idx), start, end)
26adeece	200
26adeece M	201	enum hdmi_phy_pwr {
	202	HDMI_PHYPWRCMD_OFF = 0,
	203	HDMI_PHYPWRCMD_LDOON = 1,
	204	HDMI_PHYPWRCMD_TXON = 2
	205	};
	206
26adeece M	207	enum hdmi_core_inputbus_width {
	208	HDMI_INPUT_8BIT = 0,
	209	HDMI_INPUT_10BIT = 1,
	210	HDMI_INPUT_12BIT = 2
	211	};
	212
	213	enum hdmi_core_dither_trunc {
	214	HDMI_OUTPUTTRUNCATION_8BIT = 0,
	215	HDMI_OUTPUTTRUNCATION_10BIT = 1,
	216	HDMI_OUTPUTTRUNCATION_12BIT = 2,
	217	HDMI_OUTPUTDITHER_8BIT = 3,
	218	HDMI_OUTPUTDITHER_10BIT = 4,
	219	HDMI_OUTPUTDITHER_12BIT = 5
	220	};
	221
	222	enum hdmi_core_deepcolor_ed {
	223	HDMI_DEEPCOLORPACKECTDISABLE = 0,
	224	HDMI_DEEPCOLORPACKECTENABLE = 1
	225	};
	226
	227	enum hdmi_core_packet_mode {
	228	HDMI_PACKETMODERESERVEDVALUE = 0,
	229	HDMI_PACKETMODE24BITPERPIXEL = 4,
	230	HDMI_PACKETMODE30BITPERPIXEL = 5,
	231	HDMI_PACKETMODE36BITPERPIXEL = 6,
	232	HDMI_PACKETMODE48BITPERPIXEL = 7
	233	};
	234
26adeece M	235	enum hdmi_core_tclkselclkmult {
	236	HDMI_FPLL05IDCK = 0,
	237	HDMI_FPLL10IDCK = 1,
	238	HDMI_FPLL20IDCK = 2,
	239	HDMI_FPLL40IDCK = 3
	240	};
	241
	242	enum hdmi_core_packet_ctrl {
	243	HDMI_PACKETENABLE = 1,
	244	HDMI_PACKETDISABLE = 0,
	245	HDMI_PACKETREPEATON = 1,
	246	HDMI_PACKETREPEATOFF = 0
	247	};
	248
5d8dbe4a	249	/* INFOFRAME_AVI_ and INFOFRAME_AUDIO_ definitions */
26adeece M	250	enum hdmi_core_infoframe {
	251	HDMI_INFOFRAME_AVI_DB1Y_RGB = 0,
	252	HDMI_INFOFRAME_AVI_DB1Y_YUV422 = 1,
	253	HDMI_INFOFRAME_AVI_DB1Y_YUV444 = 2,
	254	HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF = 0,
	255	HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_ON = 1,
	256	HDMI_INFOFRAME_AVI_DB1B_NO = 0,
	257	HDMI_INFOFRAME_AVI_DB1B_VERT = 1,
	258	HDMI_INFOFRAME_AVI_DB1B_HORI = 2,
	259	HDMI_INFOFRAME_AVI_DB1B_VERTHORI = 3,
	260	HDMI_INFOFRAME_AVI_DB1S_0 = 0,
	261	HDMI_INFOFRAME_AVI_DB1S_1 = 1,
	262	HDMI_INFOFRAME_AVI_DB1S_2 = 2,
	263	HDMI_INFOFRAME_AVI_DB2C_NO = 0,
	264	HDMI_INFOFRAME_AVI_DB2C_ITU601 = 1,
	265	HDMI_INFOFRAME_AVI_DB2C_ITU709 = 2,
	266	HDMI_INFOFRAME_AVI_DB2C_EC_EXTENDED = 3,
	267	HDMI_INFOFRAME_AVI_DB2M_NO = 0,
	268	HDMI_INFOFRAME_AVI_DB2M_43 = 1,
	269	HDMI_INFOFRAME_AVI_DB2M_169 = 2,
	270	HDMI_INFOFRAME_AVI_DB2R_SAME = 8,
	271	HDMI_INFOFRAME_AVI_DB2R_43 = 9,
	272	HDMI_INFOFRAME_AVI_DB2R_169 = 10,
	273	HDMI_INFOFRAME_AVI_DB2R_149 = 11,
	274	HDMI_INFOFRAME_AVI_DB3ITC_NO = 0,
	275	HDMI_INFOFRAME_AVI_DB3ITC_YES = 1,
	276	HDMI_INFOFRAME_AVI_DB3EC_XVYUV601 = 0,
	277	HDMI_INFOFRAME_AVI_DB3EC_XVYUV709 = 1,
	278	HDMI_INFOFRAME_AVI_DB3Q_DEFAULT = 0,
	279	HDMI_INFOFRAME_AVI_DB3Q_LR = 1,
	280	HDMI_INFOFRAME_AVI_DB3Q_FR = 2,
	281	HDMI_INFOFRAME_AVI_DB3SC_NO = 0,
	282	HDMI_INFOFRAME_AVI_DB3SC_HORI = 1,
	283	HDMI_INFOFRAME_AVI_DB3SC_VERT = 2,
	284	HDMI_INFOFRAME_AVI_DB3SC_HORIVERT = 3,
	285	HDMI_INFOFRAME_AVI_DB5PR_NO = 0,
	286	HDMI_INFOFRAME_AVI_DB5PR_2 = 1,
	287	HDMI_INFOFRAME_AVI_DB5PR_3 = 2,
	288	HDMI_INFOFRAME_AVI_DB5PR_4 = 3,
	289	HDMI_INFOFRAME_AVI_DB5PR_5 = 4,
	290	HDMI_INFOFRAME_AVI_DB5PR_6 = 5,
	291	HDMI_INFOFRAME_AVI_DB5PR_7 = 6,
	292	HDMI_INFOFRAME_AVI_DB5PR_8 = 7,
	293	HDMI_INFOFRAME_AVI_DB5PR_9 = 8,
5d8dbe4a RN	294	HDMI_INFOFRAME_AVI_DB5PR_10 = 9,
	295	HDMI_INFOFRAME_AUDIO_DB1CT_FROM_STREAM = 0,
	296	HDMI_INFOFRAME_AUDIO_DB1CT_IEC60958 = 1,
	297	HDMI_INFOFRAME_AUDIO_DB1CT_AC3 = 2,
	298	HDMI_INFOFRAME_AUDIO_DB1CT_MPEG1 = 3,
	299	HDMI_INFOFRAME_AUDIO_DB1CT_MP3 = 4,
	300	HDMI_INFOFRAME_AUDIO_DB1CT_MPEG2_MULTICH = 5,
	301	HDMI_INFOFRAME_AUDIO_DB1CT_AAC = 6,
	302	HDMI_INFOFRAME_AUDIO_DB1CT_DTS = 7,
	303	HDMI_INFOFRAME_AUDIO_DB1CT_ATRAC = 8,
	304	HDMI_INFOFRAME_AUDIO_DB1CT_ONEBIT = 9,
	305	HDMI_INFOFRAME_AUDIO_DB1CT_DOLBY_DIGITAL_PLUS = 10,
	306	HDMI_INFOFRAME_AUDIO_DB1CT_DTS_HD = 11,
	307	HDMI_INFOFRAME_AUDIO_DB1CT_MAT = 12,
	308	HDMI_INFOFRAME_AUDIO_DB1CT_DST = 13,
	309	HDMI_INFOFRAME_AUDIO_DB1CT_WMA_PRO = 14,
	310	HDMI_INFOFRAME_AUDIO_DB2SF_FROM_STREAM = 0,
	311	HDMI_INFOFRAME_AUDIO_DB2SF_32000 = 1,
	312	HDMI_INFOFRAME_AUDIO_DB2SF_44100 = 2,
	313	HDMI_INFOFRAME_AUDIO_DB2SF_48000 = 3,
	314	HDMI_INFOFRAME_AUDIO_DB2SF_88200 = 4,
	315	HDMI_INFOFRAME_AUDIO_DB2SF_96000 = 5,
	316	HDMI_INFOFRAME_AUDIO_DB2SF_176400 = 6,
	317	HDMI_INFOFRAME_AUDIO_DB2SF_192000 = 7,
	318	HDMI_INFOFRAME_AUDIO_DB2SS_FROM_STREAM = 0,
	319	HDMI_INFOFRAME_AUDIO_DB2SS_16BIT = 1,
	320	HDMI_INFOFRAME_AUDIO_DB2SS_20BIT = 2,
	321	HDMI_INFOFRAME_AUDIO_DB2SS_24BIT = 3,
	322	HDMI_INFOFRAME_AUDIO_DB5_DM_INH_PERMITTED = 0,
	323	HDMI_INFOFRAME_AUDIO_DB5_DM_INH_PROHIBITED = 1
26adeece M	324	};
	325
	326	enum hdmi_packing_mode {
	327	HDMI_PACK_10b_RGB_YUV444 = 0,
	328	HDMI_PACK_24b_RGB_YUV444_YUV422 = 1,
	329	HDMI_PACK_20b_YUV422 = 2,
	330	HDMI_PACK_ALREADYPACKED = 7
	331	};
	332
5d8dbe4a RN	333	enum hdmi_core_audio_sample_freq {
	334	HDMI_AUDIO_FS_32000 = 0x3,
	335	HDMI_AUDIO_FS_44100 = 0x0,
	336	HDMI_AUDIO_FS_48000 = 0x2,
	337	HDMI_AUDIO_FS_88200 = 0x8,
	338	HDMI_AUDIO_FS_96000 = 0xA,
	339	HDMI_AUDIO_FS_176400 = 0xC,
	340	HDMI_AUDIO_FS_192000 = 0xE,
	341	HDMI_AUDIO_FS_NOT_INDICATED = 0x1
	342	};
	343
	344	enum hdmi_core_audio_layout {
	345	HDMI_AUDIO_LAYOUT_2CH = 0,
	346	HDMI_AUDIO_LAYOUT_8CH = 1
	347	};
	348
	349	enum hdmi_core_cts_mode {
	350	HDMI_AUDIO_CTS_MODE_HW = 0,
	351	HDMI_AUDIO_CTS_MODE_SW = 1
	352	};
	353
	354	enum hdmi_stereo_channels {
	355	HDMI_AUDIO_STEREO_NOCHANNELS = 0,
	356	HDMI_AUDIO_STEREO_ONECHANNEL = 1,
	357	HDMI_AUDIO_STEREO_TWOCHANNELS = 2,
	358	HDMI_AUDIO_STEREO_THREECHANNELS = 3,
	359	HDMI_AUDIO_STEREO_FOURCHANNELS = 4
	360	};
	361
	362	enum hdmi_audio_type {
	363	HDMI_AUDIO_TYPE_LPCM = 0,
	364	HDMI_AUDIO_TYPE_IEC = 1
	365	};
	366
	367	enum hdmi_audio_justify {
	368	HDMI_AUDIO_JUSTIFY_LEFT = 0,
	369	HDMI_AUDIO_JUSTIFY_RIGHT = 1
	370	};
	371
	372	enum hdmi_audio_sample_order {
	373	HDMI_AUDIO_SAMPLE_RIGHT_FIRST = 0,
	374	HDMI_AUDIO_SAMPLE_LEFT_FIRST = 1
	375	};
	376
	377	enum hdmi_audio_samples_perword {
	378	HDMI_AUDIO_ONEWORD_ONESAMPLE = 0,
	379	HDMI_AUDIO_ONEWORD_TWOSAMPLES = 1
	380	};
	381
	382	enum hdmi_audio_sample_size {
	383	HDMI_AUDIO_SAMPLE_16BITS = 0,
	384	HDMI_AUDIO_SAMPLE_24BITS = 1
	385	};
	386
	387	enum hdmi_audio_transf_mode {
	388	HDMI_AUDIO_TRANSF_DMA = 0,
	389	HDMI_AUDIO_TRANSF_IRQ = 1
	390	};
	391
	392	enum hdmi_audio_blk_strt_end_sig {
	393	HDMI_AUDIO_BLOCK_SIG_STARTEND_ON = 0,
	394	HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1
	395	};
	396
397	enum hdmi_audio_i2s_config {
398	HDMI_AUDIO_I2S_WS_POLARITY_LOW_IS_LEFT = 0,
399	HDMI_AUDIO_I2S_WS_POLARIT_YLOW_IS_RIGHT = 1,
400	HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST = 0,
401	HDMI_AUDIO_I2S_LSB_SHIFTED_FIRST = 1,
402	HDMI_AUDIO_I2S_MAX_WORD_20BITS = 0,
403	HDMI_AUDIO_I2S_MAX_WORD_24BITS = 1,
404	HDMI_AUDIO_I2S_CHST_WORD_NOT_SPECIFIED = 0,
405	HDMI_AUDIO_I2S_CHST_WORD_16_BITS = 1,
406	HDMI_AUDIO_I2S_CHST_WORD_17_BITS = 6,
407	HDMI_AUDIO_I2S_CHST_WORD_18_BITS = 2,
408	HDMI_AUDIO_I2S_CHST_WORD_19_BITS = 4,
409	HDMI_AUDIO_I2S_CHST_WORD_20_BITS_20MAX = 5,
410	HDMI_AUDIO_I2S_CHST_WORD_20_BITS_24MAX = 1,
411	HDMI_AUDIO_I2S_CHST_WORD_21_BITS = 6,
412	HDMI_AUDIO_I2S_CHST_WORD_22_BITS = 2,
413	HDMI_AUDIO_I2S_CHST_WORD_23_BITS = 4,
414	HDMI_AUDIO_I2S_CHST_WORD_24_BITS = 5,
415	HDMI_AUDIO_I2S_SCK_EDGE_FALLING = 0,
416	HDMI_AUDIO_I2S_SCK_EDGE_RISING = 1,
417	HDMI_AUDIO_I2S_VBIT_FOR_PCM = 0,
418	HDMI_AUDIO_I2S_VBIT_FOR_COMPRESSED = 1,
419	HDMI_AUDIO_I2S_INPUT_LENGTH_NA = 0,
420	HDMI_AUDIO_I2S_INPUT_LENGTH_16 = 2,
421	HDMI_AUDIO_I2S_INPUT_LENGTH_17 = 12,
422	HDMI_AUDIO_I2S_INPUT_LENGTH_18 = 4,
423	HDMI_AUDIO_I2S_INPUT_LENGTH_19 = 8,
424	HDMI_AUDIO_I2S_INPUT_LENGTH_20 = 10,
425	HDMI_AUDIO_I2S_INPUT_LENGTH_21 = 13,
426	HDMI_AUDIO_I2S_INPUT_LENGTH_22 = 5,
427	HDMI_AUDIO_I2S_INPUT_LENGTH_23 = 9,
428	HDMI_AUDIO_I2S_INPUT_LENGTH_24 = 11,
429	HDMI_AUDIO_I2S_FIRST_BIT_SHIFT = 0,
430	HDMI_AUDIO_I2S_FIRST_BIT_NO_SHIFT = 1,
431	HDMI_AUDIO_I2S_SD0_EN = 1,
432	HDMI_AUDIO_I2S_SD1_EN = 1 << 1,
433	HDMI_AUDIO_I2S_SD2_EN = 1 << 2,
434	HDMI_AUDIO_I2S_SD3_EN = 1 << 3,
435	};
436
437	enum hdmi_audio_mclk_mode {
438	HDMI_AUDIO_MCLK_128FS = 0,
439	HDMI_AUDIO_MCLK_256FS = 1,
440	HDMI_AUDIO_MCLK_384FS = 2,
441	HDMI_AUDIO_MCLK_512FS = 3,
442	HDMI_AUDIO_MCLK_768FS = 4,
443	HDMI_AUDIO_MCLK_1024FS = 5,
444	HDMI_AUDIO_MCLK_1152FS = 6,
445	HDMI_AUDIO_MCLK_192FS = 7
446	};
447
26adeece M	448	struct hdmi_core_video_config {
	449	enum hdmi_core_inputbus_width ip_bus_width;
	450	enum hdmi_core_dither_trunc op_dither_truc;
	451	enum hdmi_core_deepcolor_ed deep_color_pkt;
	452	enum hdmi_core_packet_mode pkt_mode;
	453	enum hdmi_core_hdmi_dvi hdmi_dvi;
	454	enum hdmi_core_tclkselclkmult tclk_sel_clkmult;
	455	};
	456
	457	/*
	458	* Refer to section 8.2 in HDMI 1.3 specification for
	459	* details about infoframe databytes
	460	*/
	461	struct hdmi_core_infoframe_avi {
	462	u8 db1_format;
	463	/* Y0, Y1 rgb,yCbCr */
	464	u8 db1_active_info;
	465	/* A0 Active information Present */
	466	u8 db1_bar_info_dv;
	467	/* B0, B1 Bar info data valid */
	468	u8 db1_scan_info;
	469	/* S0, S1 scan information */
	470	u8 db2_colorimetry;
	471	/* C0, C1 colorimetry */
	472	u8 db2_aspect_ratio;
	473	/* M0, M1 Aspect ratio (4:3, 16:9) */
	474	u8 db2_active_fmt_ar;
	475	/* R0...R3 Active format aspect ratio */
	476	u8 db3_itc;
	477	/* ITC IT content. */
	478	u8 db3_ec;
	479	/* EC0, EC1, EC2 Extended colorimetry */
	480	u8 db3_q_range;
	481	/* Q1, Q0 Quantization range */
	482	u8 db3_nup_scaling;
	483	/* SC1, SC0 Non-uniform picture scaling */
	484	u8 db4_videocode;
	485	/* VIC0..6 Video format identification */
	486	u8 db5_pixel_repeat;
	487	/* PR0..PR3 Pixel repetition factor */
	488	u16 db6_7_line_eoftop;
	489	/* Line number end of top bar */
	490	u16 db8_9_line_sofbottom;
	491	/* Line number start of bottom bar */
	492	u16 db10_11_pixel_eofleft;
	493	/* Pixel number end of left bar */
	494	u16 db12_13_pixel_sofright;
	495	/* Pixel number start of right bar */
	496	};
5d8dbe4a RN	497	/*
	498	* Refer to section 8.2 in HDMI 1.3 specification for
	499	* details about infoframe databytes
	500	*/
	501	struct hdmi_core_infoframe_audio {
	502	u8 db1_coding_type;
	503	u8 db1_channel_count;
	504	u8 db2_sample_freq;
	505	u8 db2_sample_size;
	506	u8 db4_channel_alloc;
	507	bool db5_downmix_inh;
	508	u8 db5_lsv; /* Level shift values for downmix */
	509	};
26adeece M	510
	511	struct hdmi_core_packet_enable_repeat {
	512	u32 audio_pkt;
	513	u32 audio_pkt_repeat;
	514	u32 avi_infoframe;
	515	u32 avi_infoframe_repeat;
	516	u32 gen_cntrl_pkt;
	517	u32 gen_cntrl_pkt_repeat;
	518	u32 generic_pkt;
	519	u32 generic_pkt_repeat;
	520	};
	521
	522	struct hdmi_video_format {
	523	enum hdmi_packing_mode packing_mode;
	524	u32 y_res; /* Line per panel */
	525	u32 x_res; /* pixel per line */
	526	};
	527
	528	struct hdmi_video_interface {
	529	int vsp; /* Vsync polarity */
	530	int hsp; /* Hsync polarity */
	531	int interlacing;
	532	int tm; /* Timing mode */
	533	};
	534
5d8dbe4a RN	535	struct hdmi_audio_format {
	536	enum hdmi_stereo_channels stereo_channels;
	537	u8 active_chnnls_msk;
	538	enum hdmi_audio_type type;
	539	enum hdmi_audio_justify justification;
	540	enum hdmi_audio_sample_order sample_order;
	541	enum hdmi_audio_samples_perword samples_per_word;
	542	enum hdmi_audio_sample_size sample_size;
	543	enum hdmi_audio_blk_strt_end_sig en_sig_blk_strt_end;
	544	};
	545
	546	struct hdmi_audio_dma {
	547	u8 transfer_size;
	548	u8 block_size;
	549	enum hdmi_audio_transf_mode mode;
	550	u16 fifo_threshold;
	551	};
	552
	553	struct hdmi_core_audio_i2s_config {
	554	u8 word_max_length;
	555	u8 word_length;
	556	u8 in_length_bits;
	557	u8 justification;
	558	u8 en_high_bitrate_aud;
	559	u8 sck_edge_mode;
	560	u8 cbit_order;
	561	u8 vbit;
	562	u8 ws_polarity;
	563	u8 direction;
	564	u8 shift;
	565	u8 active_sds;
	566	};
	567
	568	struct hdmi_core_audio_config {
	569	struct hdmi_core_audio_i2s_config i2s_cfg;
	570	enum hdmi_core_audio_sample_freq freq_sample;
	571	bool fs_override;
	572	u32 n;
	573	u32 cts;
	574	u32 aud_par_busclk;
	575	enum hdmi_core_audio_layout layout;
	576	enum hdmi_core_cts_mode cts_mode;
	577	bool use_mclk;
	578	enum hdmi_audio_mclk_mode mclk_mode;
	579	bool en_acr_pkt;
	580	bool en_dsd_audio;
	581	bool en_parallel_aud_input;
	582	bool en_spdif;
	583	};
26adeece	584	#endif