Commit | Line | Data |
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7d983f39 M |
1 | /* |
2 | * ti_hdmi_4xxx_ip.c | |
3 | * | |
4 | * HDMI TI81xx, TI38xx, TI OMAP4 etc IP driver Library | |
5 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ | |
6 | * Authors: Yong Zhi | |
7 | * Mythri pk <mythripk@ti.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License version 2 as published by | |
11 | * the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along with | |
19 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
ac9f2421 TV |
22 | #define DSS_SUBSYS_NAME "HDMICORE" |
23 | ||
7d983f39 M |
24 | #include <linux/kernel.h> |
25 | #include <linux/module.h> | |
26 | #include <linux/err.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/mutex.h> | |
30 | #include <linux/delay.h> | |
425f02fd | 31 | #include <linux/platform_device.h> |
7d983f39 | 32 | #include <linux/string.h> |
162874d5 | 33 | #include <linux/seq_file.h> |
7e151f7f | 34 | #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) |
199e7fd6 | 35 | #include <sound/asound.h> |
6ec355d6 | 36 | #include <sound/asoundef.h> |
199e7fd6 | 37 | #endif |
7d983f39 | 38 | |
ef26958a | 39 | #include "hdmi4_core.h" |
6ec355d6 | 40 | #include "dss_features.h" |
7d983f39 | 41 | |
425f02fd AT |
42 | #define HDMI_CORE_AV 0x500 |
43 | ||
425f02fd | 44 | static inline void __iomem *hdmi_av_base(struct hdmi_core_data *core) |
7d983f39 | 45 | { |
425f02fd | 46 | return core->base + HDMI_CORE_AV; |
7d983f39 M |
47 | } |
48 | ||
425f02fd | 49 | static int hdmi_core_ddc_init(struct hdmi_core_data *core) |
7d983f39 | 50 | { |
425f02fd | 51 | void __iomem *base = core->base; |
7d983f39 M |
52 | |
53 | /* Turn on CLK for DDC */ | |
032b8ea5 TV |
54 | REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0); |
55 | ||
56 | /* IN_PROG */ | |
57 | if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) { | |
58 | /* Abort transaction */ | |
59 | REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xf, 3, 0); | |
60 | /* IN_PROG */ | |
61 | if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, | |
62 | 4, 4, 0) != 0) { | |
63 | DSSERR("Timeout aborting DDC transaction\n"); | |
64 | return -ETIMEDOUT; | |
65 | } | |
66 | } | |
7d983f39 | 67 | |
032b8ea5 TV |
68 | /* Clk SCL Devices */ |
69 | REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xA, 3, 0); | |
7d983f39 | 70 | |
032b8ea5 TV |
71 | /* HDMI_CORE_DDC_STATUS_IN_PROG */ |
72 | if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, | |
73 | 4, 4, 0) != 0) { | |
74 | DSSERR("Timeout starting SCL clock\n"); | |
75 | return -ETIMEDOUT; | |
76 | } | |
7d983f39 | 77 | |
032b8ea5 TV |
78 | /* Clear FIFO */ |
79 | REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x9, 3, 0); | |
7d983f39 | 80 | |
032b8ea5 TV |
81 | /* HDMI_CORE_DDC_STATUS_IN_PROG */ |
82 | if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, | |
83 | 4, 4, 0) != 0) { | |
84 | DSSERR("Timeout clearing DDC fifo\n"); | |
85 | return -ETIMEDOUT; | |
86 | } | |
7d983f39 | 87 | |
032b8ea5 TV |
88 | return 0; |
89 | } | |
7d983f39 | 90 | |
425f02fd | 91 | static int hdmi_core_ddc_edid(struct hdmi_core_data *core, |
032b8ea5 TV |
92 | u8 *pedid, int ext) |
93 | { | |
425f02fd | 94 | void __iomem *base = core->base; |
937fce13 TV |
95 | u32 i; |
96 | char checksum; | |
032b8ea5 TV |
97 | u32 offset = 0; |
98 | ||
99 | /* HDMI_CORE_DDC_STATUS_IN_PROG */ | |
100 | if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, | |
101 | 4, 4, 0) != 0) { | |
102 | DSSERR("Timeout waiting DDC to be ready\n"); | |
103 | return -ETIMEDOUT; | |
7d983f39 M |
104 | } |
105 | ||
032b8ea5 TV |
106 | if (ext % 2 != 0) |
107 | offset = 0x80; | |
108 | ||
7d983f39 | 109 | /* Load Segment Address Register */ |
032b8ea5 | 110 | REG_FLD_MOD(base, HDMI_CORE_DDC_SEGM, ext / 2, 7, 0); |
7d983f39 M |
111 | |
112 | /* Load Slave Address Register */ | |
032b8ea5 | 113 | REG_FLD_MOD(base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1); |
7d983f39 M |
114 | |
115 | /* Load Offset Address Register */ | |
032b8ea5 | 116 | REG_FLD_MOD(base, HDMI_CORE_DDC_OFFSET, offset, 7, 0); |
7d983f39 M |
117 | |
118 | /* Load Byte Count */ | |
032b8ea5 TV |
119 | REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0); |
120 | REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0); | |
7d983f39 M |
121 | |
122 | /* Set DDC_CMD */ | |
123 | if (ext) | |
032b8ea5 | 124 | REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x4, 3, 0); |
7d983f39 | 125 | else |
032b8ea5 | 126 | REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x2, 3, 0); |
7d983f39 M |
127 | |
128 | /* HDMI_CORE_DDC_STATUS_BUS_LOW */ | |
032b8ea5 | 129 | if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) { |
ac9f2421 | 130 | DSSERR("I2C Bus Low?\n"); |
7d983f39 M |
131 | return -EIO; |
132 | } | |
133 | /* HDMI_CORE_DDC_STATUS_NO_ACK */ | |
032b8ea5 | 134 | if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) { |
ac9f2421 | 135 | DSSERR("I2C No Ack\n"); |
7d983f39 M |
136 | return -EIO; |
137 | } | |
138 | ||
937fce13 TV |
139 | for (i = 0; i < 0x80; ++i) { |
140 | int t; | |
7d983f39 | 141 | |
937fce13 TV |
142 | /* IN_PROG */ |
143 | if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) { | |
144 | DSSERR("operation stopped when reading edid\n"); | |
145 | return -EIO; | |
146 | } | |
147 | ||
148 | t = 0; | |
149 | /* FIFO_EMPTY */ | |
150 | while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) { | |
151 | if (t++ > 10000) { | |
152 | DSSERR("timeout reading edid\n"); | |
153 | return -ETIMEDOUT; | |
154 | } | |
155 | udelay(1); | |
7d983f39 | 156 | } |
937fce13 TV |
157 | |
158 | pedid[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0); | |
7d983f39 M |
159 | } |
160 | ||
937fce13 TV |
161 | checksum = 0; |
162 | for (i = 0; i < 0x80; ++i) | |
163 | checksum += pedid[i]; | |
7d983f39 M |
164 | |
165 | if (checksum != 0) { | |
ac9f2421 | 166 | DSSERR("E-EDID checksum failed!!\n"); |
7d983f39 M |
167 | return -EIO; |
168 | } | |
169 | ||
170 | return 0; | |
171 | } | |
172 | ||
425f02fd | 173 | int hdmi4_read_edid(struct hdmi_core_data *core, u8 *edid, int len) |
7d983f39 | 174 | { |
937fce13 TV |
175 | int r, l; |
176 | ||
177 | if (len < 128) | |
178 | return -EINVAL; | |
7d983f39 | 179 | |
425f02fd | 180 | r = hdmi_core_ddc_init(core); |
032b8ea5 TV |
181 | if (r) |
182 | return r; | |
183 | ||
425f02fd | 184 | r = hdmi_core_ddc_edid(core, edid, 0); |
47024565 | 185 | if (r) |
7d983f39 | 186 | return r; |
47024565 | 187 | |
937fce13 | 188 | l = 128; |
47024565 | 189 | |
937fce13 | 190 | if (len >= 128 * 2 && edid[0x7e] > 0) { |
425f02fd | 191 | r = hdmi_core_ddc_edid(core, edid + 0x80, 1); |
47024565 TV |
192 | if (r) |
193 | return r; | |
937fce13 | 194 | l += 128; |
7d983f39 | 195 | } |
47024565 | 196 | |
937fce13 | 197 | return l; |
7d983f39 M |
198 | } |
199 | ||
200 | static void hdmi_core_init(struct hdmi_core_video_config *video_cfg, | |
201 | struct hdmi_core_infoframe_avi *avi_cfg, | |
202 | struct hdmi_core_packet_enable_repeat *repeat_cfg) | |
203 | { | |
ac9f2421 | 204 | DSSDBG("Enter hdmi_core_init\n"); |
7d983f39 M |
205 | |
206 | /* video core */ | |
207 | video_cfg->ip_bus_width = HDMI_INPUT_8BIT; | |
208 | video_cfg->op_dither_truc = HDMI_OUTPUTTRUNCATION_8BIT; | |
209 | video_cfg->deep_color_pkt = HDMI_DEEPCOLORPACKECTDISABLE; | |
210 | video_cfg->pkt_mode = HDMI_PACKETMODERESERVEDVALUE; | |
211 | video_cfg->hdmi_dvi = HDMI_DVI; | |
212 | video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK; | |
213 | ||
214 | /* info frame */ | |
215 | avi_cfg->db1_format = 0; | |
216 | avi_cfg->db1_active_info = 0; | |
217 | avi_cfg->db1_bar_info_dv = 0; | |
218 | avi_cfg->db1_scan_info = 0; | |
219 | avi_cfg->db2_colorimetry = 0; | |
220 | avi_cfg->db2_aspect_ratio = 0; | |
221 | avi_cfg->db2_active_fmt_ar = 0; | |
222 | avi_cfg->db3_itc = 0; | |
223 | avi_cfg->db3_ec = 0; | |
224 | avi_cfg->db3_q_range = 0; | |
225 | avi_cfg->db3_nup_scaling = 0; | |
226 | avi_cfg->db4_videocode = 0; | |
227 | avi_cfg->db5_pixel_repeat = 0; | |
ef26958a | 228 | avi_cfg->db6_7_line_eoftop = 0; |
7d983f39 M |
229 | avi_cfg->db8_9_line_sofbottom = 0; |
230 | avi_cfg->db10_11_pixel_eofleft = 0; | |
231 | avi_cfg->db12_13_pixel_sofright = 0; | |
232 | ||
233 | /* packet enable and repeat */ | |
234 | repeat_cfg->audio_pkt = 0; | |
235 | repeat_cfg->audio_pkt_repeat = 0; | |
236 | repeat_cfg->avi_infoframe = 0; | |
237 | repeat_cfg->avi_infoframe_repeat = 0; | |
238 | repeat_cfg->gen_cntrl_pkt = 0; | |
239 | repeat_cfg->gen_cntrl_pkt_repeat = 0; | |
240 | repeat_cfg->generic_pkt = 0; | |
241 | repeat_cfg->generic_pkt_repeat = 0; | |
242 | } | |
243 | ||
425f02fd | 244 | static void hdmi_core_powerdown_disable(struct hdmi_core_data *core) |
7d983f39 | 245 | { |
ac9f2421 | 246 | DSSDBG("Enter hdmi_core_powerdown_disable\n"); |
425f02fd | 247 | REG_FLD_MOD(core->base, HDMI_CORE_SYS_SYS_CTRL1, 0x0, 0, 0); |
7d983f39 M |
248 | } |
249 | ||
425f02fd | 250 | static void hdmi_core_swreset_release(struct hdmi_core_data *core) |
7d983f39 | 251 | { |
ac9f2421 | 252 | DSSDBG("Enter hdmi_core_swreset_release\n"); |
425f02fd | 253 | REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x0, 0, 0); |
7d983f39 M |
254 | } |
255 | ||
425f02fd | 256 | static void hdmi_core_swreset_assert(struct hdmi_core_data *core) |
7d983f39 | 257 | { |
ac9f2421 | 258 | DSSDBG("Enter hdmi_core_swreset_assert\n"); |
425f02fd | 259 | REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x1, 0, 0); |
7d983f39 M |
260 | } |
261 | ||
262 | /* HDMI_CORE_VIDEO_CONFIG */ | |
425f02fd | 263 | static void hdmi_core_video_config(struct hdmi_core_data *core, |
7d983f39 M |
264 | struct hdmi_core_video_config *cfg) |
265 | { | |
266 | u32 r = 0; | |
425f02fd AT |
267 | void __iomem *core_sys_base = core->base; |
268 | void __iomem *core_av_base = hdmi_av_base(core); | |
7d983f39 M |
269 | |
270 | /* sys_ctrl1 default configuration not tunable */ | |
190d57c9 RN |
271 | r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_SYS_CTRL1); |
272 | r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_VEN_FOLLOWVSYNC, 5, 5); | |
273 | r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_HEN_FOLLOWHSYNC, 4, 4); | |
274 | r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_BSEL_24BITBUS, 2, 2); | |
275 | r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_EDGE_RISINGEDGE, 1, 1); | |
276 | hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_SYS_CTRL1, r); | |
7d983f39 M |
277 | |
278 | REG_FLD_MOD(core_sys_base, | |
279 | HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6); | |
280 | ||
281 | /* Vid_Mode */ | |
282 | r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE); | |
283 | ||
284 | /* dither truncation configuration */ | |
285 | if (cfg->op_dither_truc > HDMI_OUTPUTTRUNCATION_12BIT) { | |
286 | r = FLD_MOD(r, cfg->op_dither_truc - 3, 7, 6); | |
287 | r = FLD_MOD(r, 1, 5, 5); | |
288 | } else { | |
289 | r = FLD_MOD(r, cfg->op_dither_truc, 7, 6); | |
290 | r = FLD_MOD(r, 0, 5, 5); | |
291 | } | |
292 | hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE, r); | |
293 | ||
294 | /* HDMI_Ctrl */ | |
425f02fd | 295 | r = hdmi_read_reg(core_av_base, HDMI_CORE_AV_HDMI_CTRL); |
7d983f39 M |
296 | r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6); |
297 | r = FLD_MOD(r, cfg->pkt_mode, 5, 3); | |
298 | r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0); | |
425f02fd | 299 | hdmi_write_reg(core_av_base, HDMI_CORE_AV_HDMI_CTRL, r); |
7d983f39 M |
300 | |
301 | /* TMDS_CTRL */ | |
302 | REG_FLD_MOD(core_sys_base, | |
303 | HDMI_CORE_SYS_TMDS_CTRL, cfg->tclk_sel_clkmult, 6, 5); | |
304 | } | |
305 | ||
425f02fd | 306 | static void hdmi_core_aux_infoframe_avi_config(struct hdmi_core_data *core) |
7d983f39 M |
307 | { |
308 | u32 val; | |
309 | char sum = 0, checksum = 0; | |
425f02fd AT |
310 | void __iomem *av_base = hdmi_av_base(core); |
311 | struct hdmi_core_infoframe_avi info_avi = core->avi_cfg; | |
7d983f39 M |
312 | |
313 | sum += 0x82 + 0x002 + 0x00D; | |
314 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_TYPE, 0x082); | |
315 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_VERS, 0x002); | |
316 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_LEN, 0x00D); | |
317 | ||
318 | val = (info_avi.db1_format << 5) | | |
319 | (info_avi.db1_active_info << 4) | | |
320 | (info_avi.db1_bar_info_dv << 2) | | |
321 | (info_avi.db1_scan_info); | |
322 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(0), val); | |
323 | sum += val; | |
324 | ||
325 | val = (info_avi.db2_colorimetry << 6) | | |
326 | (info_avi.db2_aspect_ratio << 4) | | |
327 | (info_avi.db2_active_fmt_ar); | |
328 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(1), val); | |
329 | sum += val; | |
330 | ||
331 | val = (info_avi.db3_itc << 7) | | |
332 | (info_avi.db3_ec << 4) | | |
333 | (info_avi.db3_q_range << 2) | | |
334 | (info_avi.db3_nup_scaling); | |
335 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(2), val); | |
336 | sum += val; | |
337 | ||
338 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(3), | |
339 | info_avi.db4_videocode); | |
340 | sum += info_avi.db4_videocode; | |
341 | ||
342 | val = info_avi.db5_pixel_repeat; | |
343 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(4), val); | |
344 | sum += val; | |
345 | ||
346 | val = info_avi.db6_7_line_eoftop & 0x00FF; | |
347 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(5), val); | |
348 | sum += val; | |
349 | ||
350 | val = ((info_avi.db6_7_line_eoftop >> 8) & 0x00FF); | |
351 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(6), val); | |
352 | sum += val; | |
353 | ||
354 | val = info_avi.db8_9_line_sofbottom & 0x00FF; | |
355 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(7), val); | |
356 | sum += val; | |
357 | ||
358 | val = ((info_avi.db8_9_line_sofbottom >> 8) & 0x00FF); | |
359 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(8), val); | |
360 | sum += val; | |
361 | ||
362 | val = info_avi.db10_11_pixel_eofleft & 0x00FF; | |
363 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(9), val); | |
364 | sum += val; | |
365 | ||
366 | val = ((info_avi.db10_11_pixel_eofleft >> 8) & 0x00FF); | |
367 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(10), val); | |
368 | sum += val; | |
369 | ||
370 | val = info_avi.db12_13_pixel_sofright & 0x00FF; | |
371 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(11), val); | |
372 | sum += val; | |
373 | ||
374 | val = ((info_avi.db12_13_pixel_sofright >> 8) & 0x00FF); | |
375 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(12), val); | |
376 | sum += val; | |
377 | ||
378 | checksum = 0x100 - sum; | |
379 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_CHSUM, checksum); | |
380 | } | |
381 | ||
425f02fd | 382 | static void hdmi_core_av_packet_config(struct hdmi_core_data *core, |
7d983f39 M |
383 | struct hdmi_core_packet_enable_repeat repeat_cfg) |
384 | { | |
385 | /* enable/repeat the infoframe */ | |
425f02fd | 386 | hdmi_write_reg(hdmi_av_base(core), HDMI_CORE_AV_PB_CTRL1, |
7d983f39 M |
387 | (repeat_cfg.audio_pkt << 5) | |
388 | (repeat_cfg.audio_pkt_repeat << 4) | | |
389 | (repeat_cfg.avi_infoframe << 1) | | |
390 | (repeat_cfg.avi_infoframe_repeat)); | |
391 | ||
392 | /* enable/repeat the packet */ | |
425f02fd | 393 | hdmi_write_reg(hdmi_av_base(core), HDMI_CORE_AV_PB_CTRL2, |
7d983f39 M |
394 | (repeat_cfg.gen_cntrl_pkt << 3) | |
395 | (repeat_cfg.gen_cntrl_pkt_repeat << 2) | | |
396 | (repeat_cfg.generic_pkt << 1) | | |
397 | (repeat_cfg.generic_pkt_repeat)); | |
398 | } | |
399 | ||
425f02fd AT |
400 | void hdmi4_configure(struct hdmi_core_data *core, |
401 | struct hdmi_wp_data *wp, struct hdmi_config *cfg) | |
7d983f39 M |
402 | { |
403 | /* HDMI */ | |
404 | struct omap_video_timings video_timing; | |
405 | struct hdmi_video_format video_format; | |
7d983f39 | 406 | /* HDMI core */ |
425f02fd | 407 | struct hdmi_core_infoframe_avi *avi_cfg = &core->avi_cfg; |
7d983f39 M |
408 | struct hdmi_core_video_config v_core_cfg; |
409 | struct hdmi_core_packet_enable_repeat repeat_cfg; | |
7d983f39 | 410 | |
fd3cd7ee | 411 | hdmi_core_init(&v_core_cfg, avi_cfg, &repeat_cfg); |
7d983f39 | 412 | |
f382d9eb | 413 | hdmi_wp_init_vid_fmt_timings(&video_format, &video_timing, cfg); |
7d983f39 | 414 | |
425f02fd | 415 | hdmi_wp_video_config_timing(wp, &video_timing); |
7d983f39 M |
416 | |
417 | /* video config */ | |
418 | video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422; | |
419 | ||
425f02fd | 420 | hdmi_wp_video_config_format(wp, &video_format); |
7d983f39 | 421 | |
425f02fd | 422 | hdmi_wp_video_config_interface(wp, &video_timing); |
7d983f39 M |
423 | |
424 | /* | |
425 | * configure core video part | |
426 | * set software reset in the core | |
427 | */ | |
425f02fd | 428 | hdmi_core_swreset_assert(core); |
7d983f39 M |
429 | |
430 | /* power down off */ | |
425f02fd | 431 | hdmi_core_powerdown_disable(core); |
7d983f39 M |
432 | |
433 | v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL; | |
434 | v_core_cfg.hdmi_dvi = cfg->cm.mode; | |
435 | ||
425f02fd | 436 | hdmi_core_video_config(core, &v_core_cfg); |
7d983f39 M |
437 | |
438 | /* release software reset in the core */ | |
425f02fd | 439 | hdmi_core_swreset_release(core); |
7d983f39 M |
440 | |
441 | /* | |
442 | * configure packet | |
443 | * info frame video see doc CEA861-D page 65 | |
444 | */ | |
fd3cd7ee M |
445 | avi_cfg->db1_format = HDMI_INFOFRAME_AVI_DB1Y_RGB; |
446 | avi_cfg->db1_active_info = | |
447 | HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF; | |
448 | avi_cfg->db1_bar_info_dv = HDMI_INFOFRAME_AVI_DB1B_NO; | |
449 | avi_cfg->db1_scan_info = HDMI_INFOFRAME_AVI_DB1S_0; | |
450 | avi_cfg->db2_colorimetry = HDMI_INFOFRAME_AVI_DB2C_NO; | |
451 | avi_cfg->db2_aspect_ratio = HDMI_INFOFRAME_AVI_DB2M_NO; | |
452 | avi_cfg->db2_active_fmt_ar = HDMI_INFOFRAME_AVI_DB2R_SAME; | |
453 | avi_cfg->db3_itc = HDMI_INFOFRAME_AVI_DB3ITC_NO; | |
454 | avi_cfg->db3_ec = HDMI_INFOFRAME_AVI_DB3EC_XVYUV601; | |
455 | avi_cfg->db3_q_range = HDMI_INFOFRAME_AVI_DB3Q_DEFAULT; | |
456 | avi_cfg->db3_nup_scaling = HDMI_INFOFRAME_AVI_DB3SC_NO; | |
457 | avi_cfg->db4_videocode = cfg->cm.code; | |
458 | avi_cfg->db5_pixel_repeat = HDMI_INFOFRAME_AVI_DB5PR_NO; | |
459 | avi_cfg->db6_7_line_eoftop = 0; | |
460 | avi_cfg->db8_9_line_sofbottom = 0; | |
461 | avi_cfg->db10_11_pixel_eofleft = 0; | |
462 | avi_cfg->db12_13_pixel_sofright = 0; | |
7d983f39 | 463 | |
425f02fd | 464 | hdmi_core_aux_infoframe_avi_config(core); |
7d983f39 M |
465 | |
466 | /* enable/repeat the infoframe */ | |
467 | repeat_cfg.avi_infoframe = HDMI_PACKETENABLE; | |
468 | repeat_cfg.avi_infoframe_repeat = HDMI_PACKETREPEATON; | |
469 | /* wakeup */ | |
470 | repeat_cfg.audio_pkt = HDMI_PACKETENABLE; | |
471 | repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON; | |
425f02fd | 472 | hdmi_core_av_packet_config(core, repeat_cfg); |
7d983f39 | 473 | } |
7334167b | 474 | |
425f02fd | 475 | void hdmi4_core_dump(struct hdmi_core_data *core, struct seq_file *s) |
162874d5 M |
476 | { |
477 | int i; | |
478 | ||
479 | #define CORE_REG(i, name) name(i) | |
480 | #define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\ | |
425f02fd | 481 | hdmi_read_reg(core->base, r)) |
3c7de247 | 482 | #define DUMPCOREAV(r) seq_printf(s, "%-35s %08x\n", #r,\ |
425f02fd | 483 | hdmi_read_reg(hdmi_av_base(core), r)) |
3c7de247 | 484 | #define DUMPCOREAV2(i, r) seq_printf(s, "%s[%d]%*s %08x\n", #r, i, \ |
311d5ce8 | 485 | (i < 10) ? 32 - (int)strlen(#r) : 31 - (int)strlen(#r), " ", \ |
425f02fd | 486 | hdmi_read_reg(hdmi_av_base(core), CORE_REG(i, r))) |
162874d5 M |
487 | |
488 | DUMPCORE(HDMI_CORE_SYS_VND_IDL); | |
489 | DUMPCORE(HDMI_CORE_SYS_DEV_IDL); | |
490 | DUMPCORE(HDMI_CORE_SYS_DEV_IDH); | |
491 | DUMPCORE(HDMI_CORE_SYS_DEV_REV); | |
492 | DUMPCORE(HDMI_CORE_SYS_SRST); | |
190d57c9 | 493 | DUMPCORE(HDMI_CORE_SYS_SYS_CTRL1); |
162874d5 | 494 | DUMPCORE(HDMI_CORE_SYS_SYS_STAT); |
78145a95 | 495 | DUMPCORE(HDMI_CORE_SYS_SYS_CTRL3); |
9b9c457b AT |
496 | DUMPCORE(HDMI_CORE_SYS_DE_DLY); |
497 | DUMPCORE(HDMI_CORE_SYS_DE_CTRL); | |
498 | DUMPCORE(HDMI_CORE_SYS_DE_TOP); | |
499 | DUMPCORE(HDMI_CORE_SYS_DE_CNTL); | |
500 | DUMPCORE(HDMI_CORE_SYS_DE_CNTH); | |
501 | DUMPCORE(HDMI_CORE_SYS_DE_LINL); | |
502 | DUMPCORE(HDMI_CORE_SYS_DE_LINH_1); | |
78145a95 RN |
503 | DUMPCORE(HDMI_CORE_SYS_HRES_L); |
504 | DUMPCORE(HDMI_CORE_SYS_HRES_H); | |
505 | DUMPCORE(HDMI_CORE_SYS_VRES_L); | |
506 | DUMPCORE(HDMI_CORE_SYS_VRES_H); | |
507 | DUMPCORE(HDMI_CORE_SYS_IADJUST); | |
508 | DUMPCORE(HDMI_CORE_SYS_POLDETECT); | |
509 | DUMPCORE(HDMI_CORE_SYS_HWIDTH1); | |
510 | DUMPCORE(HDMI_CORE_SYS_HWIDTH2); | |
511 | DUMPCORE(HDMI_CORE_SYS_VWIDTH); | |
512 | DUMPCORE(HDMI_CORE_SYS_VID_CTRL); | |
162874d5 M |
513 | DUMPCORE(HDMI_CORE_SYS_VID_ACEN); |
514 | DUMPCORE(HDMI_CORE_SYS_VID_MODE); | |
78145a95 RN |
515 | DUMPCORE(HDMI_CORE_SYS_VID_BLANK1); |
516 | DUMPCORE(HDMI_CORE_SYS_VID_BLANK3); | |
517 | DUMPCORE(HDMI_CORE_SYS_VID_BLANK1); | |
518 | DUMPCORE(HDMI_CORE_SYS_DC_HEADER); | |
519 | DUMPCORE(HDMI_CORE_SYS_VID_DITHER); | |
520 | DUMPCORE(HDMI_CORE_SYS_RGB2XVYCC_CT); | |
521 | DUMPCORE(HDMI_CORE_SYS_R2Y_COEFF_LOW); | |
522 | DUMPCORE(HDMI_CORE_SYS_R2Y_COEFF_UP); | |
523 | DUMPCORE(HDMI_CORE_SYS_G2Y_COEFF_LOW); | |
524 | DUMPCORE(HDMI_CORE_SYS_G2Y_COEFF_UP); | |
525 | DUMPCORE(HDMI_CORE_SYS_B2Y_COEFF_LOW); | |
526 | DUMPCORE(HDMI_CORE_SYS_B2Y_COEFF_UP); | |
527 | DUMPCORE(HDMI_CORE_SYS_R2CB_COEFF_LOW); | |
528 | DUMPCORE(HDMI_CORE_SYS_R2CB_COEFF_UP); | |
529 | DUMPCORE(HDMI_CORE_SYS_G2CB_COEFF_LOW); | |
530 | DUMPCORE(HDMI_CORE_SYS_G2CB_COEFF_UP); | |
531 | DUMPCORE(HDMI_CORE_SYS_B2CB_COEFF_LOW); | |
532 | DUMPCORE(HDMI_CORE_SYS_B2CB_COEFF_UP); | |
533 | DUMPCORE(HDMI_CORE_SYS_R2CR_COEFF_LOW); | |
534 | DUMPCORE(HDMI_CORE_SYS_R2CR_COEFF_UP); | |
535 | DUMPCORE(HDMI_CORE_SYS_G2CR_COEFF_LOW); | |
536 | DUMPCORE(HDMI_CORE_SYS_G2CR_COEFF_UP); | |
537 | DUMPCORE(HDMI_CORE_SYS_B2CR_COEFF_LOW); | |
538 | DUMPCORE(HDMI_CORE_SYS_B2CR_COEFF_UP); | |
539 | DUMPCORE(HDMI_CORE_SYS_RGB_OFFSET_LOW); | |
540 | DUMPCORE(HDMI_CORE_SYS_RGB_OFFSET_UP); | |
541 | DUMPCORE(HDMI_CORE_SYS_Y_OFFSET_LOW); | |
542 | DUMPCORE(HDMI_CORE_SYS_Y_OFFSET_UP); | |
543 | DUMPCORE(HDMI_CORE_SYS_CBCR_OFFSET_LOW); | |
544 | DUMPCORE(HDMI_CORE_SYS_CBCR_OFFSET_UP); | |
162874d5 M |
545 | DUMPCORE(HDMI_CORE_SYS_INTR_STATE); |
546 | DUMPCORE(HDMI_CORE_SYS_INTR1); | |
547 | DUMPCORE(HDMI_CORE_SYS_INTR2); | |
548 | DUMPCORE(HDMI_CORE_SYS_INTR3); | |
549 | DUMPCORE(HDMI_CORE_SYS_INTR4); | |
78145a95 RN |
550 | DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK1); |
551 | DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK2); | |
552 | DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK3); | |
553 | DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK4); | |
554 | DUMPCORE(HDMI_CORE_SYS_INTR_CTRL); | |
162874d5 | 555 | DUMPCORE(HDMI_CORE_SYS_TMDS_CTRL); |
162874d5 | 556 | |
162874d5 | 557 | DUMPCORE(HDMI_CORE_DDC_ADDR); |
9b9c457b | 558 | DUMPCORE(HDMI_CORE_DDC_SEGM); |
162874d5 M |
559 | DUMPCORE(HDMI_CORE_DDC_OFFSET); |
560 | DUMPCORE(HDMI_CORE_DDC_COUNT1); | |
561 | DUMPCORE(HDMI_CORE_DDC_COUNT2); | |
9b9c457b AT |
562 | DUMPCORE(HDMI_CORE_DDC_STATUS); |
563 | DUMPCORE(HDMI_CORE_DDC_CMD); | |
162874d5 | 564 | DUMPCORE(HDMI_CORE_DDC_DATA); |
3c7de247 AT |
565 | |
566 | DUMPCOREAV(HDMI_CORE_AV_ACR_CTRL); | |
567 | DUMPCOREAV(HDMI_CORE_AV_FREQ_SVAL); | |
568 | DUMPCOREAV(HDMI_CORE_AV_N_SVAL1); | |
569 | DUMPCOREAV(HDMI_CORE_AV_N_SVAL2); | |
570 | DUMPCOREAV(HDMI_CORE_AV_N_SVAL3); | |
571 | DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL1); | |
572 | DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL2); | |
573 | DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL3); | |
574 | DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL1); | |
575 | DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL2); | |
576 | DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL3); | |
577 | DUMPCOREAV(HDMI_CORE_AV_AUD_MODE); | |
578 | DUMPCOREAV(HDMI_CORE_AV_SPDIF_CTRL); | |
579 | DUMPCOREAV(HDMI_CORE_AV_HW_SPDIF_FS); | |
580 | DUMPCOREAV(HDMI_CORE_AV_SWAP_I2S); | |
581 | DUMPCOREAV(HDMI_CORE_AV_SPDIF_ERTH); | |
582 | DUMPCOREAV(HDMI_CORE_AV_I2S_IN_MAP); | |
583 | DUMPCOREAV(HDMI_CORE_AV_I2S_IN_CTRL); | |
584 | DUMPCOREAV(HDMI_CORE_AV_I2S_CHST0); | |
585 | DUMPCOREAV(HDMI_CORE_AV_I2S_CHST1); | |
586 | DUMPCOREAV(HDMI_CORE_AV_I2S_CHST2); | |
587 | DUMPCOREAV(HDMI_CORE_AV_I2S_CHST4); | |
588 | DUMPCOREAV(HDMI_CORE_AV_I2S_CHST5); | |
589 | DUMPCOREAV(HDMI_CORE_AV_ASRC); | |
590 | DUMPCOREAV(HDMI_CORE_AV_I2S_IN_LEN); | |
591 | DUMPCOREAV(HDMI_CORE_AV_HDMI_CTRL); | |
592 | DUMPCOREAV(HDMI_CORE_AV_AUDO_TXSTAT); | |
593 | DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_1); | |
594 | DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_2); | |
595 | DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_3); | |
596 | DUMPCOREAV(HDMI_CORE_AV_TEST_TXCTRL); | |
597 | DUMPCOREAV(HDMI_CORE_AV_DPD); | |
598 | DUMPCOREAV(HDMI_CORE_AV_PB_CTRL1); | |
599 | DUMPCOREAV(HDMI_CORE_AV_PB_CTRL2); | |
600 | DUMPCOREAV(HDMI_CORE_AV_AVI_TYPE); | |
601 | DUMPCOREAV(HDMI_CORE_AV_AVI_VERS); | |
602 | DUMPCOREAV(HDMI_CORE_AV_AVI_LEN); | |
603 | DUMPCOREAV(HDMI_CORE_AV_AVI_CHSUM); | |
9b9c457b AT |
604 | |
605 | for (i = 0; i < HDMI_CORE_AV_AVI_DBYTE_NELEMS; i++) | |
606 | DUMPCOREAV2(i, HDMI_CORE_AV_AVI_DBYTE); | |
607 | ||
3c7de247 AT |
608 | DUMPCOREAV(HDMI_CORE_AV_SPD_TYPE); |
609 | DUMPCOREAV(HDMI_CORE_AV_SPD_VERS); | |
610 | DUMPCOREAV(HDMI_CORE_AV_SPD_LEN); | |
611 | DUMPCOREAV(HDMI_CORE_AV_SPD_CHSUM); | |
9b9c457b AT |
612 | |
613 | for (i = 0; i < HDMI_CORE_AV_SPD_DBYTE_NELEMS; i++) | |
614 | DUMPCOREAV2(i, HDMI_CORE_AV_SPD_DBYTE); | |
615 | ||
3c7de247 AT |
616 | DUMPCOREAV(HDMI_CORE_AV_AUDIO_TYPE); |
617 | DUMPCOREAV(HDMI_CORE_AV_AUDIO_VERS); | |
618 | DUMPCOREAV(HDMI_CORE_AV_AUDIO_LEN); | |
619 | DUMPCOREAV(HDMI_CORE_AV_AUDIO_CHSUM); | |
9b9c457b AT |
620 | |
621 | for (i = 0; i < HDMI_CORE_AV_AUD_DBYTE_NELEMS; i++) | |
622 | DUMPCOREAV2(i, HDMI_CORE_AV_AUD_DBYTE); | |
623 | ||
3c7de247 AT |
624 | DUMPCOREAV(HDMI_CORE_AV_MPEG_TYPE); |
625 | DUMPCOREAV(HDMI_CORE_AV_MPEG_VERS); | |
626 | DUMPCOREAV(HDMI_CORE_AV_MPEG_LEN); | |
627 | DUMPCOREAV(HDMI_CORE_AV_MPEG_CHSUM); | |
9b9c457b AT |
628 | |
629 | for (i = 0; i < HDMI_CORE_AV_MPEG_DBYTE_NELEMS; i++) | |
630 | DUMPCOREAV2(i, HDMI_CORE_AV_MPEG_DBYTE); | |
631 | ||
632 | for (i = 0; i < HDMI_CORE_AV_GEN_DBYTE_NELEMS; i++) | |
633 | DUMPCOREAV2(i, HDMI_CORE_AV_GEN_DBYTE); | |
634 | ||
3c7de247 | 635 | DUMPCOREAV(HDMI_CORE_AV_CP_BYTE1); |
9b9c457b AT |
636 | |
637 | for (i = 0; i < HDMI_CORE_AV_GEN2_DBYTE_NELEMS; i++) | |
638 | DUMPCOREAV2(i, HDMI_CORE_AV_GEN2_DBYTE); | |
639 | ||
3c7de247 | 640 | DUMPCOREAV(HDMI_CORE_AV_CEC_ADDR_ID); |
162874d5 M |
641 | } |
642 | ||
7e151f7f | 643 | #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) |
425f02fd | 644 | static void hdmi_core_audio_config(struct hdmi_core_data *core, |
7334167b M |
645 | struct hdmi_core_audio_config *cfg) |
646 | { | |
647 | u32 r; | |
425f02fd | 648 | void __iomem *av_base = hdmi_av_base(core); |
7334167b | 649 | |
d8989d96 RN |
650 | /* |
651 | * Parameters for generation of Audio Clock Recovery packets | |
652 | */ | |
7334167b M |
653 | REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL1, cfg->n, 7, 0); |
654 | REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL2, cfg->n >> 8, 7, 0); | |
655 | REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL3, cfg->n >> 16, 7, 0); | |
656 | ||
657 | if (cfg->cts_mode == HDMI_AUDIO_CTS_MODE_SW) { | |
658 | REG_FLD_MOD(av_base, HDMI_CORE_AV_CTS_SVAL1, cfg->cts, 7, 0); | |
659 | REG_FLD_MOD(av_base, | |
660 | HDMI_CORE_AV_CTS_SVAL2, cfg->cts >> 8, 7, 0); | |
661 | REG_FLD_MOD(av_base, | |
662 | HDMI_CORE_AV_CTS_SVAL3, cfg->cts >> 16, 7, 0); | |
663 | } else { | |
7334167b M |
664 | REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_1, |
665 | cfg->aud_par_busclk, 7, 0); | |
666 | REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_2, | |
667 | (cfg->aud_par_busclk >> 8), 7, 0); | |
668 | REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_3, | |
669 | (cfg->aud_par_busclk >> 16), 7, 0); | |
670 | } | |
671 | ||
d8989d96 RN |
672 | /* Set ACR clock divisor */ |
673 | REG_FLD_MOD(av_base, | |
674 | HDMI_CORE_AV_FREQ_SVAL, cfg->mclk_mode, 2, 0); | |
675 | ||
676 | r = hdmi_read_reg(av_base, HDMI_CORE_AV_ACR_CTRL); | |
677 | /* | |
678 | * Use TMDS clock for ACR packets. For devices that use | |
679 | * the MCLK, this is the first part of the MCLK initialization. | |
680 | */ | |
681 | r = FLD_MOD(r, 0, 2, 2); | |
682 | ||
683 | r = FLD_MOD(r, cfg->en_acr_pkt, 1, 1); | |
684 | r = FLD_MOD(r, cfg->cts_mode, 0, 0); | |
685 | hdmi_write_reg(av_base, HDMI_CORE_AV_ACR_CTRL, r); | |
686 | ||
687 | /* For devices using MCLK, this completes its initialization. */ | |
688 | if (cfg->use_mclk) | |
689 | REG_FLD_MOD(av_base, HDMI_CORE_AV_ACR_CTRL, 1, 2, 2); | |
690 | ||
7334167b M |
691 | /* Override of SPDIF sample frequency with value in I2S_CHST4 */ |
692 | REG_FLD_MOD(av_base, HDMI_CORE_AV_SPDIF_CTRL, | |
693 | cfg->fs_override, 1, 1); | |
694 | ||
c1164ed8 RN |
695 | /* |
696 | * Set IEC-60958-3 channel status word. It is passed to the IP | |
697 | * just as it is received. The user of the driver is responsible | |
698 | * for its contents. | |
699 | */ | |
700 | hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST0, | |
701 | cfg->iec60958_cfg->status[0]); | |
702 | hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST1, | |
703 | cfg->iec60958_cfg->status[1]); | |
704 | hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST2, | |
705 | cfg->iec60958_cfg->status[2]); | |
706 | /* yes, this is correct: status[3] goes to CHST4 register */ | |
707 | hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST4, | |
708 | cfg->iec60958_cfg->status[3]); | |
709 | /* yes, this is correct: status[4] goes to CHST5 register */ | |
710 | hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST5, | |
711 | cfg->iec60958_cfg->status[4]); | |
712 | ||
713 | /* set I2S parameters */ | |
7334167b | 714 | r = hdmi_read_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL); |
7334167b | 715 | r = FLD_MOD(r, cfg->i2s_cfg.sck_edge_mode, 6, 6); |
7334167b | 716 | r = FLD_MOD(r, cfg->i2s_cfg.vbit, 4, 4); |
7334167b M |
717 | r = FLD_MOD(r, cfg->i2s_cfg.justification, 2, 2); |
718 | r = FLD_MOD(r, cfg->i2s_cfg.direction, 1, 1); | |
719 | r = FLD_MOD(r, cfg->i2s_cfg.shift, 0, 0); | |
720 | hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL, r); | |
721 | ||
7334167b M |
722 | REG_FLD_MOD(av_base, HDMI_CORE_AV_I2S_IN_LEN, |
723 | cfg->i2s_cfg.in_length_bits, 3, 0); | |
724 | ||
725 | /* Audio channels and mode parameters */ | |
726 | REG_FLD_MOD(av_base, HDMI_CORE_AV_HDMI_CTRL, cfg->layout, 2, 1); | |
727 | r = hdmi_read_reg(av_base, HDMI_CORE_AV_AUD_MODE); | |
728 | r = FLD_MOD(r, cfg->i2s_cfg.active_sds, 7, 4); | |
729 | r = FLD_MOD(r, cfg->en_dsd_audio, 3, 3); | |
730 | r = FLD_MOD(r, cfg->en_parallel_aud_input, 2, 2); | |
731 | r = FLD_MOD(r, cfg->en_spdif, 1, 1); | |
732 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_MODE, r); | |
24ccfc55 RN |
733 | |
734 | /* Audio channel mappings */ | |
735 | /* TODO: Make channel mapping dynamic. For now, map channels | |
736 | * in the ALSA order: FL/FR/RL/RR/C/LFE/SL/SR. Remapping is needed as | |
737 | * HDMI speaker order is different. See CEA-861 Section 6.6.2. | |
738 | */ | |
739 | hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_MAP, 0x78); | |
740 | REG_FLD_MOD(av_base, HDMI_CORE_AV_SWAP_I2S, 1, 5, 5); | |
7334167b M |
741 | } |
742 | ||
425f02fd | 743 | static void hdmi_core_audio_infoframe_cfg(struct hdmi_core_data *core, |
199e7fd6 | 744 | struct snd_cea_861_aud_if *info_aud) |
7334167b | 745 | { |
7334167b | 746 | u8 sum = 0, checksum = 0; |
425f02fd | 747 | void __iomem *av_base = hdmi_av_base(core); |
7334167b M |
748 | |
749 | /* | |
750 | * Set audio info frame type, version and length as | |
751 | * described in HDMI 1.4a Section 8.2.2 specification. | |
752 | * Checksum calculation is defined in Section 5.3.5. | |
753 | */ | |
754 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_TYPE, 0x84); | |
755 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_VERS, 0x01); | |
756 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_LEN, 0x0a); | |
757 | sum += 0x84 + 0x001 + 0x00a; | |
758 | ||
199e7fd6 RN |
759 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(0), |
760 | info_aud->db1_ct_cc); | |
761 | sum += info_aud->db1_ct_cc; | |
7334167b | 762 | |
199e7fd6 RN |
763 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(1), |
764 | info_aud->db2_sf_ss); | |
765 | sum += info_aud->db2_sf_ss; | |
7334167b | 766 | |
199e7fd6 RN |
767 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(2), info_aud->db3); |
768 | sum += info_aud->db3; | |
7334167b | 769 | |
199e7fd6 RN |
770 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(3), info_aud->db4_ca); |
771 | sum += info_aud->db4_ca; | |
7334167b | 772 | |
199e7fd6 RN |
773 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(4), |
774 | info_aud->db5_dminh_lsv); | |
775 | sum += info_aud->db5_dminh_lsv; | |
7334167b M |
776 | |
777 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(5), 0x00); | |
778 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(6), 0x00); | |
779 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(7), 0x00); | |
780 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(8), 0x00); | |
781 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(9), 0x00); | |
782 | ||
783 | checksum = 0x100 - sum; | |
784 | hdmi_write_reg(av_base, | |
785 | HDMI_CORE_AV_AUDIO_CHSUM, checksum); | |
786 | ||
787 | /* | |
788 | * TODO: Add MPEG and SPD enable and repeat cfg when EDID parsing | |
789 | * is available. | |
790 | */ | |
791 | } | |
792 | ||
425f02fd | 793 | int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, |
08d83e4e | 794 | struct omap_dss_audio *audio, u32 pclk) |
6ec355d6 RN |
795 | { |
796 | struct hdmi_audio_format audio_format; | |
797 | struct hdmi_audio_dma audio_dma; | |
425f02fd | 798 | struct hdmi_core_audio_config acore; |
6ec355d6 RN |
799 | int err, n, cts, channel_count; |
800 | unsigned int fs_nr; | |
801 | bool word_length_16b = false; | |
802 | ||
425f02fd | 803 | if (!audio || !audio->iec || !audio->cea || !core) |
6ec355d6 RN |
804 | return -EINVAL; |
805 | ||
425f02fd | 806 | acore.iec60958_cfg = audio->iec; |
6ec355d6 RN |
807 | /* |
808 | * In the IEC-60958 status word, check if the audio sample word length | |
809 | * is 16-bit as several optimizations can be performed in such case. | |
810 | */ | |
811 | if (!(audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24)) | |
812 | if (audio->iec->status[4] & IEC958_AES4_CON_WORDLEN_20_16) | |
813 | word_length_16b = true; | |
814 | ||
815 | /* I2S configuration. See Phillips' specification */ | |
816 | if (word_length_16b) | |
425f02fd | 817 | acore.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_LEFT; |
6ec355d6 | 818 | else |
425f02fd | 819 | acore.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_RIGHT; |
6ec355d6 RN |
820 | /* |
821 | * The I2S input word length is twice the lenght given in the IEC-60958 | |
822 | * status word. If the word size is greater than | |
823 | * 20 bits, increment by one. | |
824 | */ | |
425f02fd | 825 | acore.i2s_cfg.in_length_bits = audio->iec->status[4] |
6ec355d6 RN |
826 | & IEC958_AES4_CON_WORDLEN; |
827 | if (audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24) | |
425f02fd AT |
828 | acore.i2s_cfg.in_length_bits++; |
829 | acore.i2s_cfg.sck_edge_mode = HDMI_AUDIO_I2S_SCK_EDGE_RISING; | |
830 | acore.i2s_cfg.vbit = HDMI_AUDIO_I2S_VBIT_FOR_PCM; | |
831 | acore.i2s_cfg.direction = HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST; | |
832 | acore.i2s_cfg.shift = HDMI_AUDIO_I2S_FIRST_BIT_SHIFT; | |
6ec355d6 RN |
833 | |
834 | /* convert sample frequency to a number */ | |
835 | switch (audio->iec->status[3] & IEC958_AES3_CON_FS) { | |
836 | case IEC958_AES3_CON_FS_32000: | |
837 | fs_nr = 32000; | |
838 | break; | |
839 | case IEC958_AES3_CON_FS_44100: | |
840 | fs_nr = 44100; | |
841 | break; | |
842 | case IEC958_AES3_CON_FS_48000: | |
843 | fs_nr = 48000; | |
844 | break; | |
845 | case IEC958_AES3_CON_FS_88200: | |
846 | fs_nr = 88200; | |
847 | break; | |
848 | case IEC958_AES3_CON_FS_96000: | |
849 | fs_nr = 96000; | |
850 | break; | |
851 | case IEC958_AES3_CON_FS_176400: | |
852 | fs_nr = 176400; | |
853 | break; | |
854 | case IEC958_AES3_CON_FS_192000: | |
855 | fs_nr = 192000; | |
856 | break; | |
857 | default: | |
858 | return -EINVAL; | |
859 | } | |
860 | ||
08d83e4e | 861 | err = hdmi_compute_acr(pclk, fs_nr, &n, &cts); |
6ec355d6 RN |
862 | |
863 | /* Audio clock regeneration settings */ | |
425f02fd AT |
864 | acore.n = n; |
865 | acore.cts = cts; | |
6ec355d6 | 866 | if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) { |
425f02fd AT |
867 | acore.aud_par_busclk = 0; |
868 | acore.cts_mode = HDMI_AUDIO_CTS_MODE_SW; | |
869 | acore.use_mclk = dss_has_feature(FEAT_HDMI_AUDIO_USE_MCLK); | |
6ec355d6 | 870 | } else { |
425f02fd AT |
871 | acore.aud_par_busclk = (((128 * 31) - 1) << 8); |
872 | acore.cts_mode = HDMI_AUDIO_CTS_MODE_HW; | |
873 | acore.use_mclk = true; | |
6ec355d6 RN |
874 | } |
875 | ||
425f02fd AT |
876 | if (acore.use_mclk) |
877 | acore.mclk_mode = HDMI_AUDIO_MCLK_128FS; | |
6ec355d6 RN |
878 | |
879 | /* Audio channels settings */ | |
880 | channel_count = (audio->cea->db1_ct_cc & | |
881 | CEA861_AUDIO_INFOFRAME_DB1CC) + 1; | |
882 | ||
883 | switch (channel_count) { | |
884 | case 2: | |
885 | audio_format.active_chnnls_msk = 0x03; | |
886 | break; | |
887 | case 3: | |
888 | audio_format.active_chnnls_msk = 0x07; | |
889 | break; | |
890 | case 4: | |
891 | audio_format.active_chnnls_msk = 0x0f; | |
892 | break; | |
893 | case 5: | |
894 | audio_format.active_chnnls_msk = 0x1f; | |
895 | break; | |
896 | case 6: | |
897 | audio_format.active_chnnls_msk = 0x3f; | |
898 | break; | |
899 | case 7: | |
900 | audio_format.active_chnnls_msk = 0x7f; | |
901 | break; | |
902 | case 8: | |
903 | audio_format.active_chnnls_msk = 0xff; | |
904 | break; | |
905 | default: | |
906 | return -EINVAL; | |
907 | } | |
908 | ||
909 | /* | |
910 | * the HDMI IP needs to enable four stereo channels when transmitting | |
911 | * more than 2 audio channels | |
912 | */ | |
913 | if (channel_count == 2) { | |
914 | audio_format.stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL; | |
425f02fd AT |
915 | acore.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN; |
916 | acore.layout = HDMI_AUDIO_LAYOUT_2CH; | |
6ec355d6 RN |
917 | } else { |
918 | audio_format.stereo_channels = HDMI_AUDIO_STEREO_FOURCHANNELS; | |
425f02fd | 919 | acore.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN | |
6ec355d6 RN |
920 | HDMI_AUDIO_I2S_SD1_EN | HDMI_AUDIO_I2S_SD2_EN | |
921 | HDMI_AUDIO_I2S_SD3_EN; | |
425f02fd | 922 | acore.layout = HDMI_AUDIO_LAYOUT_8CH; |
6ec355d6 RN |
923 | } |
924 | ||
425f02fd | 925 | acore.en_spdif = false; |
6ec355d6 | 926 | /* use sample frequency from channel status word */ |
425f02fd | 927 | acore.fs_override = true; |
6ec355d6 | 928 | /* enable ACR packets */ |
425f02fd | 929 | acore.en_acr_pkt = true; |
6ec355d6 | 930 | /* disable direct streaming digital audio */ |
425f02fd | 931 | acore.en_dsd_audio = false; |
6ec355d6 | 932 | /* use parallel audio interface */ |
425f02fd | 933 | acore.en_parallel_aud_input = true; |
6ec355d6 RN |
934 | |
935 | /* DMA settings */ | |
936 | if (word_length_16b) | |
937 | audio_dma.transfer_size = 0x10; | |
938 | else | |
939 | audio_dma.transfer_size = 0x20; | |
940 | audio_dma.block_size = 0xC0; | |
941 | audio_dma.mode = HDMI_AUDIO_TRANSF_DMA; | |
942 | audio_dma.fifo_threshold = 0x20; /* in number of samples */ | |
943 | ||
944 | /* audio FIFO format settings */ | |
945 | if (word_length_16b) { | |
946 | audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES; | |
947 | audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS; | |
948 | audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT; | |
949 | } else { | |
950 | audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_ONESAMPLE; | |
951 | audio_format.sample_size = HDMI_AUDIO_SAMPLE_24BITS; | |
952 | audio_format.justification = HDMI_AUDIO_JUSTIFY_RIGHT; | |
953 | } | |
954 | audio_format.type = HDMI_AUDIO_TYPE_LPCM; | |
955 | audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST; | |
956 | /* disable start/stop signals of IEC 60958 blocks */ | |
957 | audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_ON; | |
958 | ||
959 | /* configure DMA and audio FIFO format*/ | |
425f02fd AT |
960 | hdmi_wp_audio_config_dma(wp, &audio_dma); |
961 | hdmi_wp_audio_config_format(wp, &audio_format); | |
6ec355d6 RN |
962 | |
963 | /* configure the core*/ | |
425f02fd | 964 | hdmi_core_audio_config(core, &acore); |
6ec355d6 RN |
965 | |
966 | /* configure CEA 861 audio infoframe*/ | |
425f02fd | 967 | hdmi_core_audio_infoframe_cfg(core, audio->cea); |
6ec355d6 RN |
968 | |
969 | return 0; | |
970 | } | |
971 | ||
425f02fd | 972 | int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp) |
3df9fb5c | 973 | { |
425f02fd | 974 | REG_FLD_MOD(hdmi_av_base(core), |
3df9fb5c | 975 | HDMI_CORE_AV_AUD_MODE, true, 0, 0); |
f382d9eb | 976 | |
425f02fd | 977 | hdmi_wp_audio_core_req_enable(wp, true); |
f382d9eb | 978 | |
027bdc85 RN |
979 | return 0; |
980 | } | |
981 | ||
425f02fd | 982 | void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp) |
027bdc85 | 983 | { |
425f02fd | 984 | REG_FLD_MOD(hdmi_av_base(core), |
027bdc85 | 985 | HDMI_CORE_AV_AUD_MODE, false, 0, 0); |
f382d9eb | 986 | |
425f02fd | 987 | hdmi_wp_audio_core_req_enable(wp, false); |
80a48596 | 988 | } |
d7b6f443 | 989 | |
425f02fd | 990 | int hdmi4_audio_get_dma_port(u32 *offset, u32 *size) |
d7b6f443 RN |
991 | { |
992 | if (!offset || !size) | |
993 | return -EINVAL; | |
994 | *offset = HDMI_WP_AUDIO_DATA; | |
995 | *size = 4; | |
996 | return 0; | |
997 | } | |
f382d9eb | 998 | |
7334167b | 999 | #endif |
425f02fd AT |
1000 | |
1001 | #define CORE_OFFSET 0x400 | |
1002 | #define CORE_SIZE 0xc00 | |
1003 | ||
1004 | int hdmi4_core_init(struct platform_device *pdev, struct hdmi_core_data *core) | |
1005 | { | |
1006 | struct resource *res; | |
1007 | struct resource temp_res; | |
1008 | ||
77601507 | 1009 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core"); |
425f02fd AT |
1010 | if (!res) { |
1011 | DSSDBG("can't get CORE mem resource by name\n"); | |
1012 | /* | |
1013 | * if hwmod/DT doesn't have the memory resource information | |
1014 | * split into HDMI sub blocks by name, we try again by getting | |
1015 | * the platform's first resource. this code will be removed when | |
1016 | * the driver can get the mem resources by name | |
1017 | */ | |
1018 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1019 | if (!res) { | |
1020 | DSSERR("can't get CORE mem resource\n"); | |
1021 | return -EINVAL; | |
1022 | } | |
1023 | ||
1024 | temp_res.start = res->start + CORE_OFFSET; | |
1025 | temp_res.end = temp_res.start + CORE_SIZE - 1; | |
1026 | res = &temp_res; | |
1027 | } | |
1028 | ||
1029 | core->base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); | |
1030 | if (!core->base) { | |
1031 | DSSERR("can't ioremap CORE\n"); | |
1032 | return -ENOMEM; | |
1033 | } | |
1034 | ||
1035 | return 0; | |
1036 | } |