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Linux 2.6.39-rc7
[deliverable/linux.git] / drivers / video / omap2 / dss / rfbi.c
CommitLineData
5c18adb3
TV		 1/*
2 * linux/drivers/video/omap2/dss/rfbi.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "RFBI"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
28#include <linux/clk.h>
29#include <linux/io.h>
30#include <linux/delay.h>
31#include <linux/kfifo.h>
32#include <linux/ktime.h>
33#include <linux/hrtimer.h>
34#include <linux/seq_file.h>
35
36#include <plat/display.h>
37#include "dss.h"
38
5c18adb3
TV		 39struct rfbi_reg { u16 idx; };
40
41#define RFBI_REG(idx) ((const struct rfbi_reg) { idx })
42
43#define RFBI_REVISION RFBI_REG(0x0000)
44#define RFBI_SYSCONFIG RFBI_REG(0x0010)
45#define RFBI_SYSSTATUS RFBI_REG(0x0014)
46#define RFBI_CONTROL RFBI_REG(0x0040)
47#define RFBI_PIXEL_CNT RFBI_REG(0x0044)
48#define RFBI_LINE_NUMBER RFBI_REG(0x0048)
49#define RFBI_CMD RFBI_REG(0x004c)
50#define RFBI_PARAM RFBI_REG(0x0050)
51#define RFBI_DATA RFBI_REG(0x0054)
52#define RFBI_READ RFBI_REG(0x0058)
53#define RFBI_STATUS RFBI_REG(0x005c)
54
55#define RFBI_CONFIG(n) RFBI_REG(0x0060 + (n)*0x18)
56#define RFBI_ONOFF_TIME(n) RFBI_REG(0x0064 + (n)*0x18)
57#define RFBI_CYCLE_TIME(n) RFBI_REG(0x0068 + (n)*0x18)
58#define RFBI_DATA_CYCLE1(n) RFBI_REG(0x006c + (n)*0x18)
59#define RFBI_DATA_CYCLE2(n) RFBI_REG(0x0070 + (n)*0x18)
60#define RFBI_DATA_CYCLE3(n) RFBI_REG(0x0074 + (n)*0x18)
61
62#define RFBI_VSYNC_WIDTH RFBI_REG(0x0090)
63#define RFBI_HSYNC_WIDTH RFBI_REG(0x0094)
64
5c18adb3
TV		 65#define REG_FLD_MOD(idx, val, start, end) \
66 rfbi_write_reg(idx, FLD_MOD(rfbi_read_reg(idx), val, start, end))
67
68/* To work around an RFBI transfer rate limitation */
69#define OMAP_RFBI_RATE_LIMIT 1
70
71enum omap_rfbi_cycleformat {
72 OMAP_DSS_RFBI_CYCLEFORMAT_1_1 = 0,
73 OMAP_DSS_RFBI_CYCLEFORMAT_2_1 = 1,
74 OMAP_DSS_RFBI_CYCLEFORMAT_3_1 = 2,
75 OMAP_DSS_RFBI_CYCLEFORMAT_3_2 = 3,
76};
77
78enum omap_rfbi_datatype {
79 OMAP_DSS_RFBI_DATATYPE_12 = 0,
80 OMAP_DSS_RFBI_DATATYPE_16 = 1,
81 OMAP_DSS_RFBI_DATATYPE_18 = 2,
82 OMAP_DSS_RFBI_DATATYPE_24 = 3,
83};
84
85enum omap_rfbi_parallelmode {
86 OMAP_DSS_RFBI_PARALLELMODE_8 = 0,
87 OMAP_DSS_RFBI_PARALLELMODE_9 = 1,
88 OMAP_DSS_RFBI_PARALLELMODE_12 = 2,
89 OMAP_DSS_RFBI_PARALLELMODE_16 = 3,
90};
91
92enum update_cmd {
93 RFBI_CMD_UPDATE = 0,
94 RFBI_CMD_SYNC = 1,
95};
96
97static int rfbi_convert_timings(struct rfbi_timings *t);
98static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div);
5c18adb3
TV		 99
100static struct {
3448d500 101 struct platform_device *pdev;
5c18adb3
TV		 102 void __iomem *base;
103
104 unsigned long l4_khz;
105
106 enum omap_rfbi_datatype datatype;
107 enum omap_rfbi_parallelmode parallelmode;
108
109 enum omap_rfbi_te_mode te_mode;
110 int te_enabled;
111
112 void (*framedone_callback)(void *data);
113 void *framedone_callback_data;
114
115 struct omap_dss_device *dssdev[2];
116
fc248a49 117 struct kfifo cmd_fifo;
5c18adb3
TV		 118 spinlock_t cmd_lock;
119 struct completion cmd_done;
120 atomic_t cmd_fifo_full;
121 atomic_t cmd_pending;
5c18adb3
TV		 122} rfbi;
123
124struct update_region {
125 u16 x;
126 u16 y;
127 u16 w;
128 u16 h;
129};
130
5c18adb3
TV		 131static inline void rfbi_write_reg(const struct rfbi_reg idx, u32 val)
132{
133 __raw_writel(val, rfbi.base + idx.idx);
134}
135
136static inline u32 rfbi_read_reg(const struct rfbi_reg idx)
137{
138 return __raw_readl(rfbi.base + idx.idx);
139}
140
141static void rfbi_enable_clocks(bool enable)
142{
143 if (enable)
6af9cd14 144 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
5c18adb3 145 else
6af9cd14 146 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
5c18adb3
TV		 147}
148
149void omap_rfbi_write_command(const void *buf, u32 len)
150{
151 rfbi_enable_clocks(1);
152 switch (rfbi.parallelmode) {
153 case OMAP_DSS_RFBI_PARALLELMODE_8:
154 {
155 const u8 *b = buf;
156 for (; len; len--)
157 rfbi_write_reg(RFBI_CMD, *b++);
158 break;
159 }
160
161 case OMAP_DSS_RFBI_PARALLELMODE_16:
162 {
163 const u16 *w = buf;
164 BUG_ON(len & 1);
165 for (; len; len -= 2)
166 rfbi_write_reg(RFBI_CMD, *w++);
167 break;
168 }
169
170 case OMAP_DSS_RFBI_PARALLELMODE_9:
171 case OMAP_DSS_RFBI_PARALLELMODE_12:
172 default:
173 BUG();
174 }
175 rfbi_enable_clocks(0);
176}
177EXPORT_SYMBOL(omap_rfbi_write_command);
178
179void omap_rfbi_read_data(void *buf, u32 len)
180{
181 rfbi_enable_clocks(1);
182 switch (rfbi.parallelmode) {
183 case OMAP_DSS_RFBI_PARALLELMODE_8:
184 {
185 u8 *b = buf;
186 for (; len; len--) {
187 rfbi_write_reg(RFBI_READ, 0);
188 *b++ = rfbi_read_reg(RFBI_READ);
189 }
190 break;
191 }
192
193 case OMAP_DSS_RFBI_PARALLELMODE_16:
194 {
195 u16 *w = buf;
196 BUG_ON(len & ~1);
197 for (; len; len -= 2) {
198 rfbi_write_reg(RFBI_READ, 0);
199 *w++ = rfbi_read_reg(RFBI_READ);
200 }
201 break;
202 }
203
204 case OMAP_DSS_RFBI_PARALLELMODE_9:
205 case OMAP_DSS_RFBI_PARALLELMODE_12:
206 default:
207 BUG();
208 }
209 rfbi_enable_clocks(0);
210}
211EXPORT_SYMBOL(omap_rfbi_read_data);
212
213void omap_rfbi_write_data(const void *buf, u32 len)
214{
215 rfbi_enable_clocks(1);
216 switch (rfbi.parallelmode) {
217 case OMAP_DSS_RFBI_PARALLELMODE_8:
218 {
219 const u8 *b = buf;
220 for (; len; len--)
221 rfbi_write_reg(RFBI_PARAM, *b++);
222 break;
223 }
224
225 case OMAP_DSS_RFBI_PARALLELMODE_16:
226 {
227 const u16 *w = buf;
228 BUG_ON(len & 1);
229 for (; len; len -= 2)
230 rfbi_write_reg(RFBI_PARAM, *w++);
231 break;
232 }
233
234 case OMAP_DSS_RFBI_PARALLELMODE_9:
235 case OMAP_DSS_RFBI_PARALLELMODE_12:
236 default:
237 BUG();
238
239 }
240 rfbi_enable_clocks(0);
241}
242EXPORT_SYMBOL(omap_rfbi_write_data);
243
244void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
245 u16 x, u16 y,
246 u16 w, u16 h)
247{
248 int start_offset = scr_width * y + x;
249 int horiz_offset = scr_width - w;
250 int i;
251
252 rfbi_enable_clocks(1);
253
254 if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_16 &&
255 rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_8) {
256 const u16 __iomem *pd = buf;
257 pd += start_offset;
258
259 for (; h; --h) {
260 for (i = 0; i < w; ++i) {
261 const u8 __iomem *b = (const u8 __iomem *)pd;
262 rfbi_write_reg(RFBI_PARAM, __raw_readb(b+1));
263 rfbi_write_reg(RFBI_PARAM, __raw_readb(b+0));
264 ++pd;
265 }
266 pd += horiz_offset;
267 }
268 } else if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_24 &&
269 rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_8) {
270 const u32 __iomem *pd = buf;
271 pd += start_offset;
272
273 for (; h; --h) {
274 for (i = 0; i < w; ++i) {
275 const u8 __iomem *b = (const u8 __iomem *)pd;
276 rfbi_write_reg(RFBI_PARAM, __raw_readb(b+2));
277 rfbi_write_reg(RFBI_PARAM, __raw_readb(b+1));
278 rfbi_write_reg(RFBI_PARAM, __raw_readb(b+0));
279 ++pd;
280 }
281 pd += horiz_offset;
282 }
283 } else if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_16 &&
284 rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_16) {
285 const u16 __iomem *pd = buf;
286 pd += start_offset;
287
288 for (; h; --h) {
289 for (i = 0; i < w; ++i) {
290 rfbi_write_reg(RFBI_PARAM, __raw_readw(pd));
291 ++pd;
292 }
293 pd += horiz_offset;
294 }
295 } else {
296 BUG();
297 }
298
299 rfbi_enable_clocks(0);
300}
301EXPORT_SYMBOL(omap_rfbi_write_pixels);
302
64ba4f74
SS		 303void rfbi_transfer_area(struct omap_dss_device *dssdev, u16 width,
304 u16 height, void (*callback)(void *data), void *data)
5c18adb3
TV		 305{
306 u32 l;
307
308 /*BUG_ON(callback == 0);*/
309 BUG_ON(rfbi.framedone_callback != NULL);
310
311 DSSDBG("rfbi_transfer_area %dx%d\n", width, height);
312
64ba4f74 313 dispc_set_lcd_size(dssdev->manager->id, width, height);
5c18adb3 314
64ba4f74 315 dispc_enable_channel(dssdev->manager->id, true);
5c18adb3
TV		 316
317 rfbi.framedone_callback = callback;
318 rfbi.framedone_callback_data = data;
319
320 rfbi_enable_clocks(1);
321
322 rfbi_write_reg(RFBI_PIXEL_CNT, width * height);
323
324 l = rfbi_read_reg(RFBI_CONTROL);
325 l = FLD_MOD(l, 1, 0, 0); /* enable */
326 if (!rfbi.te_enabled)
327 l = FLD_MOD(l, 1, 4, 4); /* ITE */
328
5c18adb3
TV		 329 rfbi_write_reg(RFBI_CONTROL, l);
330}
331
332static void framedone_callback(void *data, u32 mask)
333{
334 void (*callback)(void *data);
335
336 DSSDBG("FRAMEDONE\n");
337
5c18adb3
TV		 338 REG_FLD_MOD(RFBI_CONTROL, 0, 0, 0);
339
340 rfbi_enable_clocks(0);
341
342 callback = rfbi.framedone_callback;
343 rfbi.framedone_callback = NULL;
344
18946f62
TV		 345 if (callback != NULL)
346 callback(rfbi.framedone_callback_data);
5c18adb3
TV		 347
348 atomic_set(&rfbi.cmd_pending, 0);
5c18adb3
TV		 349}
350
351#if 1 /* VERBOSE */
352static void rfbi_print_timings(void)
353{
354 u32 l;
355 u32 time;
356
357 l = rfbi_read_reg(RFBI_CONFIG(0));
358 time = 1000000000 / rfbi.l4_khz;
359 if (l & (1 << 4))
360 time *= 2;
361
362 DSSDBG("Tick time %u ps\n", time);
363 l = rfbi_read_reg(RFBI_ONOFF_TIME(0));
364 DSSDBG("CSONTIME %d, CSOFFTIME %d, WEONTIME %d, WEOFFTIME %d, "
365 "REONTIME %d, REOFFTIME %d\n",
366 l & 0x0f, (l >> 4) & 0x3f, (l >> 10) & 0x0f, (l >> 14) & 0x3f,
367 (l >> 20) & 0x0f, (l >> 24) & 0x3f);
368
369 l = rfbi_read_reg(RFBI_CYCLE_TIME(0));
370 DSSDBG("WECYCLETIME %d, RECYCLETIME %d, CSPULSEWIDTH %d, "
371 "ACCESSTIME %d\n",
372 (l & 0x3f), (l >> 6) & 0x3f, (l >> 12) & 0x3f,
373 (l >> 22) & 0x3f);
374}
375#else
376static void rfbi_print_timings(void) {}
377#endif
378
379
380
381
382static u32 extif_clk_period;
383
384static inline unsigned long round_to_extif_ticks(unsigned long ps, int div)
385{
386 int bus_tick = extif_clk_period * div;
387 return (ps + bus_tick - 1) / bus_tick * bus_tick;
388}
389
390static int calc_reg_timing(struct rfbi_timings *t, int div)
391{
392 t->clk_div = div;
393
394 t->cs_on_time = round_to_extif_ticks(t->cs_on_time, div);
395
396 t->we_on_time = round_to_extif_ticks(t->we_on_time, div);
397 t->we_off_time = round_to_extif_ticks(t->we_off_time, div);
398 t->we_cycle_time = round_to_extif_ticks(t->we_cycle_time, div);
399
400 t->re_on_time = round_to_extif_ticks(t->re_on_time, div);
401 t->re_off_time = round_to_extif_ticks(t->re_off_time, div);
402 t->re_cycle_time = round_to_extif_ticks(t->re_cycle_time, div);
403
404 t->access_time = round_to_extif_ticks(t->access_time, div);
405 t->cs_off_time = round_to_extif_ticks(t->cs_off_time, div);
406 t->cs_pulse_width = round_to_extif_ticks(t->cs_pulse_width, div);
407
408 DSSDBG("[reg]cson %d csoff %d reon %d reoff %d\n",
409 t->cs_on_time, t->cs_off_time, t->re_on_time, t->re_off_time);
410 DSSDBG("[reg]weon %d weoff %d recyc %d wecyc %d\n",
411 t->we_on_time, t->we_off_time, t->re_cycle_time,
412 t->we_cycle_time);
413 DSSDBG("[reg]rdaccess %d cspulse %d\n",
414 t->access_time, t->cs_pulse_width);
415
416 return rfbi_convert_timings(t);
417}
418
419static int calc_extif_timings(struct rfbi_timings *t)
420{
421 u32 max_clk_div;
422 int div;
423
424 rfbi_get_clk_info(&extif_clk_period, &max_clk_div);
425 for (div = 1; div <= max_clk_div; div++) {
426 if (calc_reg_timing(t, div) == 0)
427 break;
428 }
429
430 if (div <= max_clk_div)
431 return 0;
432
433 DSSERR("can't setup timings\n");
434 return -1;
435}
436
437
438void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t)
439{
440 int r;
441
442 if (!t->converted) {
443 r = calc_extif_timings(t);
444 if (r < 0)
445 DSSERR("Failed to calc timings\n");
446 }
447
448 BUG_ON(!t->converted);
449
450 rfbi_enable_clocks(1);
451 rfbi_write_reg(RFBI_ONOFF_TIME(rfbi_module), t->tim[0]);
452 rfbi_write_reg(RFBI_CYCLE_TIME(rfbi_module), t->tim[1]);
453
454 /* TIMEGRANULARITY */
455 REG_FLD_MOD(RFBI_CONFIG(rfbi_module),
456 (t->tim[2] ? 1 : 0), 4, 4);
457
458 rfbi_print_timings();
459 rfbi_enable_clocks(0);
460}
461
462static int ps_to_rfbi_ticks(int time, int div)
463{
464 unsigned long tick_ps;
465 int ret;
466
467 /* Calculate in picosecs to yield more exact results */
468 tick_ps = 1000000000 / (rfbi.l4_khz) * div;
469
470 ret = (time + tick_ps - 1) / tick_ps;
471
472 return ret;
473}
474
475#ifdef OMAP_RFBI_RATE_LIMIT
476unsigned long rfbi_get_max_tx_rate(void)
477{
478 unsigned long l4_rate, dss1_rate;
479 int min_l4_ticks = 0;
480 int i;
481
482 /* According to TI this can't be calculated so make the
483 * adjustments for a couple of known frequencies and warn for
484 * others.
485 */
486 static const struct {
487 unsigned long l4_clk; /* HZ */
488 unsigned long dss1_clk; /* HZ */
489 unsigned long min_l4_ticks;
490 } ftab[] = {
491 { 55, 132, 7, }, /* 7.86 MPix/s */
492 { 110, 110, 12, }, /* 9.16 MPix/s */
493 { 110, 132, 10, }, /* 11 Mpix/s */
494 { 120, 120, 10, }, /* 12 Mpix/s */
495 { 133, 133, 10, }, /* 13.3 Mpix/s */
496 };
497
498 l4_rate = rfbi.l4_khz / 1000;
6af9cd14 499 dss1_rate = dss_clk_get_rate(DSS_CLK_FCK) / 1000000;
5c18adb3
TV		 500
501 for (i = 0; i < ARRAY_SIZE(ftab); i++) {
502 /* Use a window instead of an exact match, to account
503 * for different DPLL multiplier / divider pairs.
504 */
505 if (abs(ftab[i].l4_clk - l4_rate) < 3 &&
506 abs(ftab[i].dss1_clk - dss1_rate) < 3) {
507 min_l4_ticks = ftab[i].min_l4_ticks;
508 break;
509 }
510 }
511 if (i == ARRAY_SIZE(ftab)) {
512 /* Can't be sure, return anyway the maximum not
513 * rate-limited. This might cause a problem only for the
514 * tearing synchronisation.
515 */
516 DSSERR("can't determine maximum RFBI transfer rate\n");
517 return rfbi.l4_khz * 1000;
518 }
519 return rfbi.l4_khz * 1000 / min_l4_ticks;
520}
521#else
522int rfbi_get_max_tx_rate(void)
523{
524 return rfbi.l4_khz * 1000;
525}
526#endif
527
528static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div)
529{
530 *clk_period = 1000000000 / rfbi.l4_khz;
531 *max_clk_div = 2;
532}
533
534static int rfbi_convert_timings(struct rfbi_timings *t)
535{
536 u32 l;
537 int reon, reoff, weon, weoff, cson, csoff, cs_pulse;
538 int actim, recyc, wecyc;
539 int div = t->clk_div;
540
541 if (div <= 0 || div > 2)
542 return -1;
543
544 /* Make sure that after conversion it still holds that:
545 * weoff > weon, reoff > reon, recyc >= reoff, wecyc >= weoff,
546 * csoff > cson, csoff >= max(weoff, reoff), actim > reon
547 */
548 weon = ps_to_rfbi_ticks(t->we_on_time, div);
549 weoff = ps_to_rfbi_ticks(t->we_off_time, div);
550 if (weoff <= weon)
551 weoff = weon + 1;
552 if (weon > 0x0f)
553 return -1;
554 if (weoff > 0x3f)
555 return -1;
556
557 reon = ps_to_rfbi_ticks(t->re_on_time, div);
558 reoff = ps_to_rfbi_ticks(t->re_off_time, div);
559 if (reoff <= reon)
560 reoff = reon + 1;
561 if (reon > 0x0f)
562 return -1;
563 if (reoff > 0x3f)
564 return -1;
565
566 cson = ps_to_rfbi_ticks(t->cs_on_time, div);
567 csoff = ps_to_rfbi_ticks(t->cs_off_time, div);
568 if (csoff <= cson)
569 csoff = cson + 1;
570 if (csoff < max(weoff, reoff))
571 csoff = max(weoff, reoff);
572 if (cson > 0x0f)
573 return -1;
574 if (csoff > 0x3f)
575 return -1;
576
577 l = cson;
578 l |= csoff << 4;
579 l |= weon << 10;
580 l |= weoff << 14;
581 l |= reon << 20;
582 l |= reoff << 24;
583
584 t->tim[0] = l;
585
586 actim = ps_to_rfbi_ticks(t->access_time, div);
587 if (actim <= reon)
588 actim = reon + 1;
589 if (actim > 0x3f)
590 return -1;
591
592 wecyc = ps_to_rfbi_ticks(t->we_cycle_time, div);
593 if (wecyc < weoff)
594 wecyc = weoff;
595 if (wecyc > 0x3f)
596 return -1;
597
598 recyc = ps_to_rfbi_ticks(t->re_cycle_time, div);
599 if (recyc < reoff)
600 recyc = reoff;
601 if (recyc > 0x3f)
602 return -1;
603
604 cs_pulse = ps_to_rfbi_ticks(t->cs_pulse_width, div);
605 if (cs_pulse > 0x3f)
606 return -1;
607
608 l = wecyc;
609 l |= recyc << 6;
610 l |= cs_pulse << 12;
611 l |= actim << 22;
612
613 t->tim[1] = l;
614
615 t->tim[2] = div - 1;
616
617 t->converted = 1;
618
619 return 0;
620}
621
622/* xxx FIX module selection missing */
623int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
624 unsigned hs_pulse_time, unsigned vs_pulse_time,
625 int hs_pol_inv, int vs_pol_inv, int extif_div)
626{
627 int hs, vs;
628 int min;
629 u32 l;
630
631 hs = ps_to_rfbi_ticks(hs_pulse_time, 1);
632 vs = ps_to_rfbi_ticks(vs_pulse_time, 1);
633 if (hs < 2)
634 return -EDOM;
635 if (mode == OMAP_DSS_RFBI_TE_MODE_2)
636 min = 2;
637 else /* OMAP_DSS_RFBI_TE_MODE_1 */
638 min = 4;
639 if (vs < min)
640 return -EDOM;
641 if (vs == hs)
642 return -EINVAL;
643 rfbi.te_mode = mode;
644 DSSDBG("setup_te: mode %d hs %d vs %d hs_inv %d vs_inv %d\n",
645 mode, hs, vs, hs_pol_inv, vs_pol_inv);
646
647 rfbi_enable_clocks(1);
648 rfbi_write_reg(RFBI_HSYNC_WIDTH, hs);
649 rfbi_write_reg(RFBI_VSYNC_WIDTH, vs);
650
651 l = rfbi_read_reg(RFBI_CONFIG(0));
652 if (hs_pol_inv)
653 l &= ~(1 << 21);
654 else
655 l |= 1 << 21;
656 if (vs_pol_inv)
657 l &= ~(1 << 20);
658 else
659 l |= 1 << 20;
660 rfbi_enable_clocks(0);
661
662 return 0;
663}
664EXPORT_SYMBOL(omap_rfbi_setup_te);
665
666/* xxx FIX module selection missing */
667int omap_rfbi_enable_te(bool enable, unsigned line)
668{
669 u32 l;
670
671 DSSDBG("te %d line %d mode %d\n", enable, line, rfbi.te_mode);
672 if (line > (1 << 11) - 1)
673 return -EINVAL;
674
675 rfbi_enable_clocks(1);
676 l = rfbi_read_reg(RFBI_CONFIG(0));
677 l &= ~(0x3 << 2);
678 if (enable) {
679 rfbi.te_enabled = 1;
680 l |= rfbi.te_mode << 2;
681 } else
682 rfbi.te_enabled = 0;
683 rfbi_write_reg(RFBI_CONFIG(0), l);
684 rfbi_write_reg(RFBI_LINE_NUMBER, line);
685 rfbi_enable_clocks(0);
686
687 return 0;
688}
689EXPORT_SYMBOL(omap_rfbi_enable_te);
690
691#if 0
692static void rfbi_enable_config(int enable1, int enable2)
693{
694 u32 l;
695 int cs = 0;
696
697 if (enable1)
698 cs |= 1<<0;
699 if (enable2)
700 cs |= 1<<1;
701
702 rfbi_enable_clocks(1);
703
704 l = rfbi_read_reg(RFBI_CONTROL);
705
706 l = FLD_MOD(l, cs, 3, 2);
707 l = FLD_MOD(l, 0, 1, 1);
708
709 rfbi_write_reg(RFBI_CONTROL, l);
710
711
712 l = rfbi_read_reg(RFBI_CONFIG(0));
713 l = FLD_MOD(l, 0, 3, 2); /* TRIGGERMODE: ITE */
714 /*l |= FLD_VAL(2, 8, 7); */ /* L4FORMAT, 2pix/L4 */
715 /*l |= FLD_VAL(0, 8, 7); */ /* L4FORMAT, 1pix/L4 */
716
717 l = FLD_MOD(l, 0, 16, 16); /* A0POLARITY */
718 l = FLD_MOD(l, 1, 20, 20); /* TE_VSYNC_POLARITY */
719 l = FLD_MOD(l, 1, 21, 21); /* HSYNCPOLARITY */
720
721 l = FLD_MOD(l, OMAP_DSS_RFBI_PARALLELMODE_8, 1, 0);
722 rfbi_write_reg(RFBI_CONFIG(0), l);
723
724 rfbi_enable_clocks(0);
725}
726#endif
727
728int rfbi_configure(int rfbi_module, int bpp, int lines)
729{
730 u32 l;
731 int cycle1 = 0, cycle2 = 0, cycle3 = 0;
732 enum omap_rfbi_cycleformat cycleformat;
733 enum omap_rfbi_datatype datatype;
734 enum omap_rfbi_parallelmode parallelmode;
735
736 switch (bpp) {
737 case 12:
738 datatype = OMAP_DSS_RFBI_DATATYPE_12;
739 break;
740 case 16:
741 datatype = OMAP_DSS_RFBI_DATATYPE_16;
742 break;
743 case 18:
744 datatype = OMAP_DSS_RFBI_DATATYPE_18;
745 break;
746 case 24:
747 datatype = OMAP_DSS_RFBI_DATATYPE_24;
748 break;
749 default:
750 BUG();
751 return 1;
752 }
753 rfbi.datatype = datatype;
754
755 switch (lines) {
756 case 8:
757 parallelmode = OMAP_DSS_RFBI_PARALLELMODE_8;
758 break;
759 case 9:
760 parallelmode = OMAP_DSS_RFBI_PARALLELMODE_9;
761 break;
762 case 12:
763 parallelmode = OMAP_DSS_RFBI_PARALLELMODE_12;
764 break;
765 case 16:
766 parallelmode = OMAP_DSS_RFBI_PARALLELMODE_16;
767 break;
768 default:
769 BUG();
770 return 1;
771 }
772 rfbi.parallelmode = parallelmode;
773
774 if ((bpp % lines) == 0) {
775 switch (bpp / lines) {
776 case 1:
777 cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_1_1;
778 break;
779 case 2:
780 cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_2_1;
781 break;
782 case 3:
783 cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_1;
784 break;
785 default:
786 BUG();
787 return 1;
788 }
789 } else if ((2 * bpp % lines) == 0) {
790 if ((2 * bpp / lines) == 3)
791 cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_2;
792 else {
793 BUG();
794 return 1;
795 }
796 } else {
797 BUG();
798 return 1;
799 }
800
801 switch (cycleformat) {
802 case OMAP_DSS_RFBI_CYCLEFORMAT_1_1:
803 cycle1 = lines;
804 break;
805
806 case OMAP_DSS_RFBI_CYCLEFORMAT_2_1:
807 cycle1 = lines;
808 cycle2 = lines;
809 break;
810
811 case OMAP_DSS_RFBI_CYCLEFORMAT_3_1:
812 cycle1 = lines;
813 cycle2 = lines;
814 cycle3 = lines;
815 break;
816
817 case OMAP_DSS_RFBI_CYCLEFORMAT_3_2:
818 cycle1 = lines;
819 cycle2 = (lines / 2) | ((lines / 2) << 16);
820 cycle3 = (lines << 16);
821 break;
822 }
823
824 rfbi_enable_clocks(1);
825
826 REG_FLD_MOD(RFBI_CONTROL, 0, 3, 2); /* clear CS */
827
828 l = 0;
829 l |= FLD_VAL(parallelmode, 1, 0);
830 l |= FLD_VAL(0, 3, 2); /* TRIGGERMODE: ITE */
831 l |= FLD_VAL(0, 4, 4); /* TIMEGRANULARITY */
832 l |= FLD_VAL(datatype, 6, 5);
833 /* l |= FLD_VAL(2, 8, 7); */ /* L4FORMAT, 2pix/L4 */
834 l |= FLD_VAL(0, 8, 7); /* L4FORMAT, 1pix/L4 */
835 l |= FLD_VAL(cycleformat, 10, 9);
836 l |= FLD_VAL(0, 12, 11); /* UNUSEDBITS */
837 l |= FLD_VAL(0, 16, 16); /* A0POLARITY */
838 l |= FLD_VAL(0, 17, 17); /* REPOLARITY */
839 l |= FLD_VAL(0, 18, 18); /* WEPOLARITY */
840 l |= FLD_VAL(0, 19, 19); /* CSPOLARITY */
841 l |= FLD_VAL(1, 20, 20); /* TE_VSYNC_POLARITY */
842 l |= FLD_VAL(1, 21, 21); /* HSYNCPOLARITY */
843 rfbi_write_reg(RFBI_CONFIG(rfbi_module), l);
844
845 rfbi_write_reg(RFBI_DATA_CYCLE1(rfbi_module), cycle1);
846 rfbi_write_reg(RFBI_DATA_CYCLE2(rfbi_module), cycle2);
847 rfbi_write_reg(RFBI_DATA_CYCLE3(rfbi_module), cycle3);
848
849
850 l = rfbi_read_reg(RFBI_CONTROL);
851 l = FLD_MOD(l, rfbi_module+1, 3, 2); /* Select CSx */
852 l = FLD_MOD(l, 0, 1, 1); /* clear bypass */
853 rfbi_write_reg(RFBI_CONTROL, l);
854
855
856 DSSDBG("RFBI config: bpp %d, lines %d, cycles: 0x%x 0x%x 0x%x\n",
857 bpp, lines, cycle1, cycle2, cycle3);
858
859 rfbi_enable_clocks(0);
860
861 return 0;
862}
863EXPORT_SYMBOL(rfbi_configure);
864
18946f62
TV		 865int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
866 u16 *x, u16 *y, u16 *w, u16 *h)
5c18adb3 867{
18946f62 868 u16 dw, dh;
5c18adb3 869
18946f62 870 dssdev->driver->get_resolution(dssdev, &dw, &dh);
5c18adb3 871
18946f62
TV		 872 if (*x > dw || *y > dh)
873 return -EINVAL;
5c18adb3 874
18946f62
TV		 875 if (*x + *w > dw)
876 return -EINVAL;
5c18adb3 877
18946f62
TV		 878 if (*y + *h > dh)
879 return -EINVAL;
5c18adb3 880
18946f62
TV		 881 if (*w == 1)
882 return -EINVAL;
5c18adb3 883
18946f62
TV		 884 if (*w == 0 || *h == 0)
885 return -EINVAL;
5c18adb3
TV		 886
887 if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
26a8c250 888 dss_setup_partial_planes(dssdev, x, y, w, h, true);
64ba4f74 889 dispc_set_lcd_size(dssdev->manager->id, *w, *h);
5c18adb3
TV		 890 }
891
18946f62
TV		 892 return 0;
893}
894EXPORT_SYMBOL(omap_rfbi_prepare_update);
5c18adb3 895
18946f62
TV		 896int omap_rfbi_update(struct omap_dss_device *dssdev,
897 u16 x, u16 y, u16 w, u16 h,
898 void (*callback)(void *), void *data)
899{
5c18adb3 900 if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
64ba4f74 901 rfbi_transfer_area(dssdev, w, h, callback, data);
5c18adb3
TV		 902 } else {
903 struct omap_overlay *ovl;
904 void __iomem *addr;
905 int scr_width;
906
907 ovl = dssdev->manager->overlays[0];
908 scr_width = ovl->info.screen_width;
909 addr = ovl->info.vaddr;
910
911 omap_rfbi_write_pixels(addr, scr_width, x, y, w, h);
912
18946f62 913 callback(data);
5c18adb3
TV		 914 }
915
18946f62 916 return 0;
5c18adb3 917}
18946f62 918EXPORT_SYMBOL(omap_rfbi_update);
5c18adb3
TV		 919
920void rfbi_dump_regs(struct seq_file *s)
921{
922#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, rfbi_read_reg(r))
923
6af9cd14 924 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
5c18adb3
TV		 925
926 DUMPREG(RFBI_REVISION);
927 DUMPREG(RFBI_SYSCONFIG);
928 DUMPREG(RFBI_SYSSTATUS);
929 DUMPREG(RFBI_CONTROL);
930 DUMPREG(RFBI_PIXEL_CNT);
931 DUMPREG(RFBI_LINE_NUMBER);
932 DUMPREG(RFBI_CMD);
933 DUMPREG(RFBI_PARAM);
934 DUMPREG(RFBI_DATA);
935 DUMPREG(RFBI_READ);
936 DUMPREG(RFBI_STATUS);
937
938 DUMPREG(RFBI_CONFIG(0));
939 DUMPREG(RFBI_ONOFF_TIME(0));
940 DUMPREG(RFBI_CYCLE_TIME(0));
941 DUMPREG(RFBI_DATA_CYCLE1(0));
942 DUMPREG(RFBI_DATA_CYCLE2(0));
943 DUMPREG(RFBI_DATA_CYCLE3(0));
944
945 DUMPREG(RFBI_CONFIG(1));
946 DUMPREG(RFBI_ONOFF_TIME(1));
947 DUMPREG(RFBI_CYCLE_TIME(1));
948 DUMPREG(RFBI_DATA_CYCLE1(1));
949 DUMPREG(RFBI_DATA_CYCLE2(1));
950 DUMPREG(RFBI_DATA_CYCLE3(1));
951
952 DUMPREG(RFBI_VSYNC_WIDTH);
953 DUMPREG(RFBI_HSYNC_WIDTH);
954
6af9cd14 955 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
5c18adb3
TV		 956#undef DUMPREG
957}
958
37ac60e4 959int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev)
5c18adb3
TV		 960{
961 int r;
962
963 r = omap_dss_start_device(dssdev);
964 if (r) {
965 DSSERR("failed to start device\n");
966 goto err0;
967 }
968
969 r = omap_dispc_register_isr(framedone_callback, NULL,
970 DISPC_IRQ_FRAMEDONE);
971 if (r) {
972 DSSERR("can't get FRAMEDONE irq\n");
973 goto err1;
974 }
975
64ba4f74
SS		 976 dispc_set_lcd_display_type(dssdev->manager->id,
977 OMAP_DSS_LCD_DISPLAY_TFT);
5c18adb3 978
64ba4f74
SS		 979 dispc_set_parallel_interface_mode(dssdev->manager->id,
980 OMAP_DSS_PARALLELMODE_RFBI);
5c18adb3 981
64ba4f74 982 dispc_set_tft_data_lines(dssdev->manager->id, dssdev->ctrl.pixel_size);
5c18adb3
TV		 983
984 rfbi_configure(dssdev->phy.rfbi.channel,
985 dssdev->ctrl.pixel_size,
986 dssdev->phy.rfbi.data_lines);
987
988 rfbi_set_timings(dssdev->phy.rfbi.channel,
989 &dssdev->ctrl.rfbi_timings);
990
991
5c18adb3 992 return 0;
5c18adb3
TV		 993err1:
994 omap_dss_stop_device(dssdev);
995err0:
996 return r;
997}
37ac60e4 998EXPORT_SYMBOL(omapdss_rfbi_display_enable);
5c18adb3 999
37ac60e4 1000void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev)
5c18adb3 1001{
5c18adb3
TV		 1002 omap_dispc_unregister_isr(framedone_callback, NULL,
1003 DISPC_IRQ_FRAMEDONE);
1004 omap_dss_stop_device(dssdev);
1005}
37ac60e4 1006EXPORT_SYMBOL(omapdss_rfbi_display_disable);
5c18adb3
TV		 1007
1008int rfbi_init_display(struct omap_dss_device *dssdev)
1009{
5c18adb3 1010 rfbi.dssdev[dssdev->phy.rfbi.channel] = dssdev;
5c18adb3 1011 dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE;
5c18adb3
TV		 1012 return 0;
1013}
3448d500
SG		 1014
1015/* RFBI HW IP initialisation */
1016static int omap_rfbihw_probe(struct platform_device *pdev)
1017{
1018 u32 rev;
1019 u32 l;
ea9da36a 1020 struct resource *rfbi_mem;
3448d500
SG		 1021
1022 rfbi.pdev = pdev;
1023
1024 spin_lock_init(&rfbi.cmd_lock);
1025
1026 init_completion(&rfbi.cmd_done);
1027 atomic_set(&rfbi.cmd_fifo_full, 0);
1028 atomic_set(&rfbi.cmd_pending, 0);
1029
ea9da36a
SG		 1030 rfbi_mem = platform_get_resource(rfbi.pdev, IORESOURCE_MEM, 0);
1031 if (!rfbi_mem) {
1032 DSSERR("can't get IORESOURCE_MEM RFBI\n");
1033 return -EINVAL;
1034 }
1035 rfbi.base = ioremap(rfbi_mem->start, resource_size(rfbi_mem));
3448d500
SG		 1036 if (!rfbi.base) {
1037 DSSERR("can't ioremap RFBI\n");
1038 return -ENOMEM;
1039 }
1040
1041 rfbi_enable_clocks(1);
1042
1043 msleep(10);
1044
1045 rfbi.l4_khz = dss_clk_get_rate(DSS_CLK_ICK) / 1000;
1046
1047 /* Enable autoidle and smart-idle */
1048 l = rfbi_read_reg(RFBI_SYSCONFIG);
1049 l |= (1 << 0) | (2 << 3);
1050 rfbi_write_reg(RFBI_SYSCONFIG, l);
1051
1052 rev = rfbi_read_reg(RFBI_REVISION);
a06b62f8 1053 dev_dbg(&pdev->dev, "OMAP RFBI rev %d.%d\n",
3448d500
SG		 1054 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
1055
1056 rfbi_enable_clocks(0);
1057
1058 return 0;
1059}
1060
1061static int omap_rfbihw_remove(struct platform_device *pdev)
1062{
1063 iounmap(rfbi.base);
1064 return 0;
1065}
1066
1067static struct platform_driver omap_rfbihw_driver = {
1068 .probe = omap_rfbihw_probe,
1069 .remove = omap_rfbihw_remove,
1070 .driver = {
1071 .name = "omapdss_rfbi",
1072 .owner = THIS_MODULE,
1073 },
1074};
1075
1076int rfbi_init_platform_driver(void)
1077{
1078 return platform_driver_register(&omap_rfbihw_driver);
1079}
1080
1081void rfbi_uninit_platform_driver(void)
1082{
1083 return platform_driver_unregister(&omap_rfbihw_driver);
1084}
Linux kernel - Deliverables
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