OMAPDSS: remove omap_dss_start/stop_device()
[deliverable/linux.git] / drivers / video / omap2 / dss / sdi.c
CommitLineData
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1/*
2 * linux/drivers/video/omap2/dss/sdi.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#define DSS_SUBSYS_NAME "SDI"
21
22#include <linux/kernel.h>
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23#include <linux/delay.h>
24#include <linux/err.h>
508886cf 25#include <linux/regulator/consumer.h>
a8a35931 26#include <linux/export.h>
a57dd4fe 27#include <linux/platform_device.h>
13b1ba7d 28#include <linux/string.h>
23c0a7a6 29
a0b38cc4 30#include <video/omapdss.h>
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31#include "dss.h"
32
33static struct {
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34 struct platform_device *pdev;
35
23c0a7a6 36 bool update_enabled;
508886cf 37 struct regulator *vdds_sdi_reg;
23c0a7a6 38
37a57990 39 struct dss_lcd_mgr_config mgr_config;
9b4a5716 40 struct omap_video_timings timings;
889b4fd7 41 int datapairs;
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42
43 struct omap_dss_output output;
37a57990 44} sdi;
64ba4f74 45
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46struct sdi_clk_calc_ctx {
47 unsigned long pck_min, pck_max;
48
49 struct dss_clock_info dss_cinfo;
50 struct dispc_clock_info dispc_cinfo;
51};
52
53static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
54 unsigned long pck, void *data)
55{
56 struct sdi_clk_calc_ctx *ctx = data;
57
58 ctx->dispc_cinfo.lck_div = lckd;
59 ctx->dispc_cinfo.pck_div = pckd;
60 ctx->dispc_cinfo.lck = lck;
61 ctx->dispc_cinfo.pck = pck;
62
63 return true;
64}
65
66static bool dpi_calc_dss_cb(int fckd, unsigned long fck, void *data)
67{
68 struct sdi_clk_calc_ctx *ctx = data;
69
70 ctx->dss_cinfo.fck = fck;
71 ctx->dss_cinfo.fck_div = fckd;
72
73 return dispc_div_calc(fck, ctx->pck_min, ctx->pck_max,
74 dpi_calc_dispc_cb, ctx);
75}
76
77static int sdi_calc_clock_div(unsigned long pclk,
78 struct dss_clock_info *dss_cinfo,
79 struct dispc_clock_info *dispc_cinfo)
80{
81 int i;
82 struct sdi_clk_calc_ctx ctx;
83
84 /*
85 * DSS fclk gives us very few possibilities, so finding a good pixel
86 * clock may not be possible. We try multiple times to find the clock,
87 * each time widening the pixel clock range we look for, up to
88 * +/- 1MHz.
89 */
90
91 for (i = 0; i < 10; ++i) {
92 bool ok;
93
94 memset(&ctx, 0, sizeof(ctx));
95 if (pclk > 1000 * i * i * i)
96 ctx.pck_min = max(pclk - 1000 * i * i * i, 0lu);
97 else
98 ctx.pck_min = 0;
99 ctx.pck_max = pclk + 1000 * i * i * i;
100
101 ok = dss_div_calc(ctx.pck_min, dpi_calc_dss_cb, &ctx);
102 if (ok) {
103 *dss_cinfo = ctx.dss_cinfo;
104 *dispc_cinfo = ctx.dispc_cinfo;
105 return 0;
106 }
107 }
108
109 return -EINVAL;
110}
111
37a57990 112static void sdi_config_lcd_manager(struct omap_dss_device *dssdev)
23c0a7a6 113{
7ae9a71e 114 struct omap_overlay_manager *mgr = sdi.output.manager;
7d6069e5 115
37a57990 116 sdi.mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
64ba4f74 117
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118 sdi.mgr_config.stallmode = false;
119 sdi.mgr_config.fifohandcheck = false;
120
121 sdi.mgr_config.video_port_width = 24;
122 sdi.mgr_config.lcden_sig_polarity = 1;
123
7d6069e5 124 dss_mgr_set_lcd_config(mgr, &sdi.mgr_config);
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125}
126
37ac60e4 127int omapdss_sdi_display_enable(struct omap_dss_device *dssdev)
23c0a7a6 128{
7ae9a71e 129 struct omap_dss_output *out = &sdi.output;
9b4a5716 130 struct omap_video_timings *t = &sdi.timings;
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131 struct dss_clock_info dss_cinfo;
132 struct dispc_clock_info dispc_cinfo;
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133 unsigned long pck;
134 int r;
135
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136 if (out == NULL || out->manager == NULL) {
137 DSSERR("failed to enable display: no output/manager\n");
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138 return -ENODEV;
139 }
140
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141 r = regulator_enable(sdi.vdds_sdi_reg);
142 if (r)
4fbafaf3 143 goto err_reg_enable;
508886cf 144
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145 r = dispc_runtime_get();
146 if (r)
147 goto err_get_dispc;
23c0a7a6 148
23c0a7a6 149 /* 15.5.9.1.2 */
9b4a5716
AT
150 t->data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
151 t->sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
a8d5e41c 152
36816faa 153 r = sdi_calc_clock_div(t->pixel_clock * 1000, &dss_cinfo, &dispc_cinfo);
23c0a7a6 154 if (r)
4fbafaf3 155 goto err_calc_clock_div;
23c0a7a6 156
37a57990 157 sdi.mgr_config.clock_info = dispc_cinfo;
23c0a7a6 158
37a57990 159 pck = dss_cinfo.fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div / 1000;
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160
161 if (pck != t->pixel_clock) {
162 DSSWARN("Could not find exact pixel clock. Requested %d kHz, "
163 "got %lu kHz\n",
164 t->pixel_clock, pck);
165
166 t->pixel_clock = pck;
167 }
168
169
7d6069e5 170 dss_mgr_set_timings(out->manager, t);
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171
172 r = dss_set_clock_div(&dss_cinfo);
173 if (r)
4fbafaf3 174 goto err_set_dss_clock_div;
23c0a7a6 175
37a57990 176 sdi_config_lcd_manager(dssdev);
23c0a7a6 177
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178 /*
179 * LCLK and PCLK divisors are located in shadow registers, and we
180 * normally write them to DISPC registers when enabling the output.
181 * However, SDI uses pck-free as source clock for its PLL, and pck-free
182 * is affected by the divisors. And as we need the PLL before enabling
183 * the output, we need to write the divisors early.
184 *
185 * It seems just writing to the DISPC register is enough, and we don't
186 * need to care about the shadow register mechanism for pck-free. The
187 * exact reason for this is unknown.
188 */
7d6069e5 189 dispc_mgr_set_clock_div(out->manager->id, &sdi.mgr_config.clock_info);
889b4fd7 190
66591457 191 dss_sdi_init(sdi.datapairs);
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192 r = dss_sdi_enable();
193 if (r)
4fbafaf3 194 goto err_sdi_enable;
42c9dee8 195 mdelay(2);
23c0a7a6 196
7d6069e5 197 r = dss_mgr_enable(out->manager);
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198 if (r)
199 goto err_mgr_enable;
23c0a7a6 200
23c0a7a6 201 return 0;
4fbafaf3 202
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203err_mgr_enable:
204 dss_sdi_disable();
4fbafaf3 205err_sdi_enable:
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206err_set_dss_clock_div:
207err_calc_clock_div:
208 dispc_runtime_put();
209err_get_dispc:
508886cf 210 regulator_disable(sdi.vdds_sdi_reg);
4fbafaf3 211err_reg_enable:
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212 return r;
213}
37ac60e4 214EXPORT_SYMBOL(omapdss_sdi_display_enable);
23c0a7a6 215
37ac60e4 216void omapdss_sdi_display_disable(struct omap_dss_device *dssdev)
23c0a7a6 217{
7ae9a71e 218 struct omap_overlay_manager *mgr = sdi.output.manager;
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219
220 dss_mgr_disable(mgr);
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221
222 dss_sdi_disable();
223
4fbafaf3 224 dispc_runtime_put();
23c0a7a6 225
508886cf 226 regulator_disable(sdi.vdds_sdi_reg);
23c0a7a6 227}
37ac60e4 228EXPORT_SYMBOL(omapdss_sdi_display_disable);
23c0a7a6 229
c7833f7b
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230void omapdss_sdi_set_timings(struct omap_dss_device *dssdev,
231 struct omap_video_timings *timings)
232{
9b4a5716 233 sdi.timings = *timings;
c7833f7b
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234}
235EXPORT_SYMBOL(omapdss_sdi_set_timings);
236
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237void omapdss_sdi_set_datapairs(struct omap_dss_device *dssdev, int datapairs)
238{
239 sdi.datapairs = datapairs;
240}
241EXPORT_SYMBOL(omapdss_sdi_set_datapairs);
242
d37801b3 243static int sdi_init_regulator(void)
23c0a7a6 244{
d37801b3 245 struct regulator *vdds_sdi;
23c0a7a6 246
d37801b3
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247 if (sdi.vdds_sdi_reg)
248 return 0;
5f42f2ce 249
d37801b3 250 vdds_sdi = dss_get_vdds_sdi();
5f42f2ce 251
d37801b3 252 if (IS_ERR(vdds_sdi)) {
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253 vdds_sdi = devm_regulator_get(&sdi.pdev->dev, "vdds_sdi");
254 if (IS_ERR(vdds_sdi)) {
255 DSSERR("can't get VDDS_SDI regulator\n");
256 return PTR_ERR(vdds_sdi);
257 }
5f42f2ce
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258 }
259
d37801b3
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260 sdi.vdds_sdi_reg = vdds_sdi;
261
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262 return 0;
263}
264
d23b3357 265static struct omap_dss_device *sdi_find_dssdev(struct platform_device *pdev)
23c0a7a6 266{
35deca3d 267 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
2bbcce5e 268 const char *def_disp_name = omapdss_get_default_display_name();
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269 struct omap_dss_device *def_dssdev;
270 int i;
271
272 def_dssdev = NULL;
35deca3d
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273
274 for (i = 0; i < pdata->num_devices; ++i) {
275 struct omap_dss_device *dssdev = pdata->devices[i];
276
277 if (dssdev->type != OMAP_DISPLAY_TYPE_SDI)
278 continue;
279
1521653c
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280 if (def_dssdev == NULL)
281 def_dssdev = dssdev;
282
283 if (def_disp_name != NULL &&
284 strcmp(dssdev->name, def_disp_name) == 0) {
285 def_dssdev = dssdev;
286 break;
9d8232a7 287 }
1521653c 288 }
9d8232a7 289
1521653c
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290 return def_dssdev;
291}
292
e1086278 293static int sdi_probe_pdata(struct platform_device *sdidev)
1521653c 294{
5274484b 295 struct omap_dss_device *plat_dssdev;
1521653c
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296 struct omap_dss_device *dssdev;
297 int r;
298
5274484b 299 plat_dssdev = sdi_find_dssdev(sdidev);
1521653c 300
5274484b 301 if (!plat_dssdev)
e1086278 302 return 0;
5274484b
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303
304 dssdev = dss_alloc_and_init_device(&sdidev->dev);
1521653c 305 if (!dssdev)
e1086278 306 return -ENOMEM;
1521653c 307
5274484b
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308 dss_copy_device_pdata(dssdev, plat_dssdev);
309
d37801b3 310 r = sdi_init_regulator();
1521653c
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311 if (r) {
312 DSSERR("device %s init failed: %d\n", dssdev->name, r);
5274484b 313 dss_put_device(dssdev);
e1086278 314 return r;
1521653c
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315 }
316
486c0e17
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317 r = omapdss_output_set_device(&sdi.output, dssdev);
318 if (r) {
319 DSSERR("failed to connect output to new device: %s\n",
320 dssdev->name);
321 dss_put_device(dssdev);
e1086278 322 return r;
486c0e17
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323 }
324
5274484b 325 r = dss_add_device(dssdev);
1521653c
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326 if (r) {
327 DSSERR("device %s register failed: %d\n", dssdev->name, r);
486c0e17 328 omapdss_output_unset_device(&sdi.output);
5274484b 329 dss_put_device(dssdev);
e1086278 330 return r;
35deca3d 331 }
e1086278
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332
333 return 0;
38f3daf6
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334}
335
d23b3357 336static void sdi_init_output(struct platform_device *pdev)
81b87f51
AT
337{
338 struct omap_dss_output *out = &sdi.output;
339
340 out->pdev = pdev;
341 out->id = OMAP_DSS_OUTPUT_SDI;
342 out->type = OMAP_DISPLAY_TYPE_SDI;
7286a08f 343 out->name = "sdi.0";
2eea5ae6 344 out->dispc_channel = OMAP_DSS_CHANNEL_LCD;
81b87f51
AT
345
346 dss_register_output(out);
347}
348
349static void __exit sdi_uninit_output(struct platform_device *pdev)
350{
351 struct omap_dss_output *out = &sdi.output;
352
353 dss_unregister_output(out);
354}
355
d23b3357 356static int omap_sdi_probe(struct platform_device *pdev)
38f3daf6 357{
e1086278
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358 int r;
359
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360 sdi.pdev = pdev;
361
81b87f51
AT
362 sdi_init_output(pdev);
363
c6ca5b22
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364 if (pdev->dev.platform_data) {
365 r = sdi_probe_pdata(pdev);
366 if (r)
367 goto err_probe;
e1086278 368 }
35deca3d 369
23c0a7a6 370 return 0;
c6ca5b22
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371
372err_probe:
373 sdi_uninit_output(pdev);
374 return r;
23c0a7a6
TV
375}
376
6e7e8f06 377static int __exit omap_sdi_remove(struct platform_device *pdev)
23c0a7a6 378{
5274484b 379 dss_unregister_child_devices(&pdev->dev);
35deca3d 380
81b87f51
AT
381 sdi_uninit_output(pdev);
382
a57dd4fe
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383 return 0;
384}
385
386static struct platform_driver omap_sdi_driver = {
d23b3357 387 .probe = omap_sdi_probe,
6e7e8f06 388 .remove = __exit_p(omap_sdi_remove),
a57dd4fe
TV
389 .driver = {
390 .name = "omapdss_sdi",
391 .owner = THIS_MODULE,
392 },
393};
394
6e7e8f06 395int __init sdi_init_platform_driver(void)
a57dd4fe 396{
d23b3357 397 return platform_driver_register(&omap_sdi_driver);
a57dd4fe
TV
398}
399
6e7e8f06 400void __exit sdi_uninit_platform_driver(void)
a57dd4fe
TV
401{
402 platform_driver_unregister(&omap_sdi_driver);
23c0a7a6 403}
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