projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
OMAPDSS: AnalogTV: Add ops
[deliverable/linux.git] / drivers / video / omap2 / dss / venc.c
CommitLineData
b2886273
TV		 1/*
2 * linux/drivers/video/omap2/dss/venc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * VENC settings from TI's DSS driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#define DSS_SUBSYS_NAME "VENC"
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/clk.h>
27#include <linux/err.h>
28#include <linux/io.h>
29#include <linux/mutex.h>
30#include <linux/completion.h>
31#include <linux/delay.h>
32#include <linux/string.h>
33#include <linux/seq_file.h>
34#include <linux/platform_device.h>
35#include <linux/regulator/consumer.h>
4fbafaf3 36#include <linux/pm_runtime.h>
b2886273 37
a0b38cc4 38#include <video/omapdss.h>
b2886273
TV		 39
40#include "dss.h"
525dae61 41#include "dss_features.h"
b2886273 42
b2886273
TV		 43/* Venc registers */
44#define VENC_REV_ID 0x00
45#define VENC_STATUS 0x04
46#define VENC_F_CONTROL 0x08
47#define VENC_VIDOUT_CTRL 0x10
48#define VENC_SYNC_CTRL 0x14
49#define VENC_LLEN 0x1C
50#define VENC_FLENS 0x20
51#define VENC_HFLTR_CTRL 0x24
52#define VENC_CC_CARR_WSS_CARR 0x28
53#define VENC_C_PHASE 0x2C
54#define VENC_GAIN_U 0x30
55#define VENC_GAIN_V 0x34
56#define VENC_GAIN_Y 0x38
57#define VENC_BLACK_LEVEL 0x3C
58#define VENC_BLANK_LEVEL 0x40
59#define VENC_X_COLOR 0x44
60#define VENC_M_CONTROL 0x48
61#define VENC_BSTAMP_WSS_DATA 0x4C
62#define VENC_S_CARR 0x50
63#define VENC_LINE21 0x54
64#define VENC_LN_SEL 0x58
65#define VENC_L21__WC_CTL 0x5C
66#define VENC_HTRIGGER_VTRIGGER 0x60
67#define VENC_SAVID__EAVID 0x64
68#define VENC_FLEN__FAL 0x68
69#define VENC_LAL__PHASE_RESET 0x6C
70#define VENC_HS_INT_START_STOP_X 0x70
71#define VENC_HS_EXT_START_STOP_X 0x74
72#define VENC_VS_INT_START_X 0x78
73#define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C
74#define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80
75#define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84
76#define VENC_VS_EXT_STOP_Y 0x88
77#define VENC_AVID_START_STOP_X 0x90
78#define VENC_AVID_START_STOP_Y 0x94
79#define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0
80#define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4
81#define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8
82#define VENC_TVDETGP_INT_START_STOP_X 0xB0
83#define VENC_TVDETGP_INT_START_STOP_Y 0xB4
84#define VENC_GEN_CTRL 0xB8
85#define VENC_OUTPUT_CONTROL 0xC4
86#define VENC_OUTPUT_TEST 0xC8
87#define VENC_DAC_B__DAC_C 0xC8
88
89struct venc_config {
90 u32 f_control;
91 u32 vidout_ctrl;
92 u32 sync_ctrl;
93 u32 llen;
94 u32 flens;
95 u32 hfltr_ctrl;
96 u32 cc_carr_wss_carr;
97 u32 c_phase;
98 u32 gain_u;
99 u32 gain_v;
100 u32 gain_y;
101 u32 black_level;
102 u32 blank_level;
103 u32 x_color;
104 u32 m_control;
105 u32 bstamp_wss_data;
106 u32 s_carr;
107 u32 line21;
108 u32 ln_sel;
109 u32 l21__wc_ctl;
110 u32 htrigger_vtrigger;
111 u32 savid__eavid;
112 u32 flen__fal;
113 u32 lal__phase_reset;
114 u32 hs_int_start_stop_x;
115 u32 hs_ext_start_stop_x;
116 u32 vs_int_start_x;
117 u32 vs_int_stop_x__vs_int_start_y;
118 u32 vs_int_stop_y__vs_ext_start_x;
119 u32 vs_ext_stop_x__vs_ext_start_y;
120 u32 vs_ext_stop_y;
121 u32 avid_start_stop_x;
122 u32 avid_start_stop_y;
123 u32 fid_int_start_x__fid_int_start_y;
124 u32 fid_int_offset_y__fid_ext_start_x;
125 u32 fid_ext_start_y__fid_ext_offset_y;
126 u32 tvdetgp_int_start_stop_x;
127 u32 tvdetgp_int_start_stop_y;
128 u32 gen_ctrl;
129};
130
131/* from TRM */
132static const struct venc_config venc_config_pal_trm = {
133 .f_control = 0,
134 .vidout_ctrl = 1,
135 .sync_ctrl = 0x40,
136 .llen = 0x35F, /* 863 */
137 .flens = 0x270, /* 624 */
138 .hfltr_ctrl = 0,
139 .cc_carr_wss_carr = 0x2F7225ED,
140 .c_phase = 0,
141 .gain_u = 0x111,
142 .gain_v = 0x181,
143 .gain_y = 0x140,
144 .black_level = 0x3B,
145 .blank_level = 0x3B,
146 .x_color = 0x7,
147 .m_control = 0x2,
148 .bstamp_wss_data = 0x3F,
149 .s_carr = 0x2A098ACB,
150 .line21 = 0,
151 .ln_sel = 0x01290015,
152 .l21__wc_ctl = 0x0000F603,
153 .htrigger_vtrigger = 0,
154
155 .savid__eavid = 0x06A70108,
156 .flen__fal = 0x00180270,
157 .lal__phase_reset = 0x00040135,
158 .hs_int_start_stop_x = 0x00880358,
159 .hs_ext_start_stop_x = 0x000F035F,
160 .vs_int_start_x = 0x01A70000,
161 .vs_int_stop_x__vs_int_start_y = 0x000001A7,
162 .vs_int_stop_y__vs_ext_start_x = 0x01AF0000,
163 .vs_ext_stop_x__vs_ext_start_y = 0x000101AF,
164 .vs_ext_stop_y = 0x00000025,
165 .avid_start_stop_x = 0x03530083,
166 .avid_start_stop_y = 0x026C002E,
167 .fid_int_start_x__fid_int_start_y = 0x0001008A,
168 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
169 .fid_ext_start_y__fid_ext_offset_y = 0x01380001,
170
171 .tvdetgp_int_start_stop_x = 0x00140001,
172 .tvdetgp_int_start_stop_y = 0x00010001,
173 .gen_ctrl = 0x00FF0000,
174};
175
176/* from TRM */
177static const struct venc_config venc_config_ntsc_trm = {
178 .f_control = 0,
179 .vidout_ctrl = 1,
180 .sync_ctrl = 0x8040,
181 .llen = 0x359,
182 .flens = 0x20C,
183 .hfltr_ctrl = 0,
184 .cc_carr_wss_carr = 0x043F2631,
185 .c_phase = 0,
186 .gain_u = 0x102,
187 .gain_v = 0x16C,
188 .gain_y = 0x12F,
189 .black_level = 0x43,
190 .blank_level = 0x38,
191 .x_color = 0x7,
192 .m_control = 0x1,
193 .bstamp_wss_data = 0x38,
194 .s_carr = 0x21F07C1F,
195 .line21 = 0,
196 .ln_sel = 0x01310011,
197 .l21__wc_ctl = 0x0000F003,
198 .htrigger_vtrigger = 0,
199
200 .savid__eavid = 0x069300F4,
201 .flen__fal = 0x0016020C,
202 .lal__phase_reset = 0x00060107,
203 .hs_int_start_stop_x = 0x008E0350,
204 .hs_ext_start_stop_x = 0x000F0359,
205 .vs_int_start_x = 0x01A00000,
206 .vs_int_stop_x__vs_int_start_y = 0x020701A0,
207 .vs_int_stop_y__vs_ext_start_x = 0x01AC0024,
208 .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,
209 .vs_ext_stop_y = 0x00000006,
210 .avid_start_stop_x = 0x03480078,
211 .avid_start_stop_y = 0x02060024,
212 .fid_int_start_x__fid_int_start_y = 0x0001008A,
213 .fid_int_offset_y__fid_ext_start_x = 0x01AC0106,
214 .fid_ext_start_y__fid_ext_offset_y = 0x01060006,
215
216 .tvdetgp_int_start_stop_x = 0x00140001,
217 .tvdetgp_int_start_stop_y = 0x00010001,
218 .gen_ctrl = 0x00F90000,
219};
220
221static const struct venc_config venc_config_pal_bdghi = {
222 .f_control = 0,
223 .vidout_ctrl = 0,
224 .sync_ctrl = 0,
225 .hfltr_ctrl = 0,
226 .x_color = 0,
227 .line21 = 0,
228 .ln_sel = 21,
229 .htrigger_vtrigger = 0,
230 .tvdetgp_int_start_stop_x = 0x00140001,
231 .tvdetgp_int_start_stop_y = 0x00010001,
232 .gen_ctrl = 0x00FB0000,
233
234 .llen = 864-1,
235 .flens = 625-1,
236 .cc_carr_wss_carr = 0x2F7625ED,
237 .c_phase = 0xDF,
238 .gain_u = 0x111,
239 .gain_v = 0x181,
240 .gain_y = 0x140,
241 .black_level = 0x3e,
242 .blank_level = 0x3e,
243 .m_control = 0<<2 | 1<<1,
244 .bstamp_wss_data = 0x42,
245 .s_carr = 0x2a098acb,
246 .l21__wc_ctl = 0<<13 | 0x16<<8 | 0<<0,
247 .savid__eavid = 0x06A70108,
248 .flen__fal = 23<<16 | 624<<0,
249 .lal__phase_reset = 2<<17 | 310<<0,
250 .hs_int_start_stop_x = 0x00920358,
251 .hs_ext_start_stop_x = 0x000F035F,
252 .vs_int_start_x = 0x1a7<<16,
253 .vs_int_stop_x__vs_int_start_y = 0x000601A7,
254 .vs_int_stop_y__vs_ext_start_x = 0x01AF0036,
255 .vs_ext_stop_x__vs_ext_start_y = 0x27101af,
256 .vs_ext_stop_y = 0x05,
257 .avid_start_stop_x = 0x03530082,
258 .avid_start_stop_y = 0x0270002E,
259 .fid_int_start_x__fid_int_start_y = 0x0005008A,
260 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
261 .fid_ext_start_y__fid_ext_offset_y = 0x01380005,
262};
263
264const struct omap_video_timings omap_dss_pal_timings = {
265 .x_res = 720,
266 .y_res = 574,
267 .pixel_clock = 13500,
268 .hsw = 64,
269 .hfp = 12,
270 .hbp = 68,
271 .vsw = 5,
272 .vfp = 5,
273 .vbp = 41,
23c8f88e
AT		 274
275 .interlace = true,
b2886273
TV		 276};
277EXPORT_SYMBOL(omap_dss_pal_timings);
278
279const struct omap_video_timings omap_dss_ntsc_timings = {
280 .x_res = 720,
281 .y_res = 482,
282 .pixel_clock = 13500,
283 .hsw = 64,
284 .hfp = 16,
285 .hbp = 58,
286 .vsw = 6,
287 .vfp = 6,
288 .vbp = 31,
23c8f88e
AT		 289
290 .interlace = true,
b2886273
TV		 291};
292EXPORT_SYMBOL(omap_dss_ntsc_timings);
293
294static struct {
30ea50c9 295 struct platform_device *pdev;
b2886273
TV		 296 void __iomem *base;
297 struct mutex venc_lock;
298 u32 wss_data;
299 struct regulator *vdda_dac_reg;
4fbafaf3 300
4fbafaf3 301 struct clk *tv_dac_clk;
a5abf472
AT		 302
303 struct omap_video_timings timings;
febe2905 304 enum omap_dss_venc_type type;
89e71956 305 bool invert_polarity;
81b87f51 306
1f68d9c4 307 struct omap_dss_device output;
b2886273
TV		 308} venc;
309
310static inline void venc_write_reg(int idx, u32 val)
311{
312 __raw_writel(val, venc.base + idx);
313}
314
315static inline u32 venc_read_reg(int idx)
316{
317 u32 l = __raw_readl(venc.base + idx);
318 return l;
319}
320
321static void venc_write_config(const struct venc_config *config)
322{
323 DSSDBG("write venc conf\n");
324
325 venc_write_reg(VENC_LLEN, config->llen);
326 venc_write_reg(VENC_FLENS, config->flens);
327 venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
328 venc_write_reg(VENC_C_PHASE, config->c_phase);
329 venc_write_reg(VENC_GAIN_U, config->gain_u);
330 venc_write_reg(VENC_GAIN_V, config->gain_v);
331 venc_write_reg(VENC_GAIN_Y, config->gain_y);
332 venc_write_reg(VENC_BLACK_LEVEL, config->black_level);
333 venc_write_reg(VENC_BLANK_LEVEL, config->blank_level);
334 venc_write_reg(VENC_M_CONTROL, config->m_control);
335 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
336 venc.wss_data);
337 venc_write_reg(VENC_S_CARR, config->s_carr);
338 venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl);
339 venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid);
340 venc_write_reg(VENC_FLEN__FAL, config->flen__fal);
341 venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset);
342 venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x);
343 venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x);
344 venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x);
345 venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y,
346 config->vs_int_stop_x__vs_int_start_y);
347 venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X,
348 config->vs_int_stop_y__vs_ext_start_x);
349 venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
350 config->vs_ext_stop_x__vs_ext_start_y);
351 venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
352 venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x);
353 venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
354 venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y,
355 config->fid_int_start_x__fid_int_start_y);
356 venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
357 config->fid_int_offset_y__fid_ext_start_x);
358 venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
359 config->fid_ext_start_y__fid_ext_offset_y);
360
361 venc_write_reg(VENC_DAC_B__DAC_C, venc_read_reg(VENC_DAC_B__DAC_C));
362 venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl);
363 venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl);
364 venc_write_reg(VENC_X_COLOR, config->x_color);
365 venc_write_reg(VENC_LINE21, config->line21);
366 venc_write_reg(VENC_LN_SEL, config->ln_sel);
367 venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
368 venc_write_reg(VENC_TVDETGP_INT_START_STOP_X,
369 config->tvdetgp_int_start_stop_x);
370 venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y,
371 config->tvdetgp_int_start_stop_y);
372 venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl);
373 venc_write_reg(VENC_F_CONTROL, config->f_control);
374 venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl);
375}
376
377static void venc_reset(void)
378{
379 int t = 1000;
380
381 venc_write_reg(VENC_F_CONTROL, 1<<8);
382 while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) {
383 if (--t == 0) {
384 DSSERR("Failed to reset venc\n");
385 return;
386 }
387 }
388
c6f65e1a 389#ifdef CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET
b2886273 390 /* the magical sleep that makes things work */
c6f65e1a 391 /* XXX more info? What bug this circumvents? */
b2886273 392 msleep(20);
c6f65e1a 393#endif
b2886273
TV		 394}
395
4fbafaf3 396static int venc_runtime_get(void)
b2886273 397{
4fbafaf3
TV		 398 int r;
399
400 DSSDBG("venc_runtime_get\n");
401
402 r = pm_runtime_get_sync(&venc.pdev->dev);
403 WARN_ON(r < 0);
404 return r < 0 ? r : 0;
405}
406
407static void venc_runtime_put(void)
408{
409 int r;
410
411 DSSDBG("venc_runtime_put\n");
412
0eaf9f52 413 r = pm_runtime_put_sync(&venc.pdev->dev);
5be3aebd 414 WARN_ON(r < 0 && r != -ENOSYS);
b2886273
TV		 415}
416
417static const struct venc_config *venc_timings_to_config(
418 struct omap_video_timings *timings)
419{
420 if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
421 return &venc_config_pal_trm;
422
423 if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
424 return &venc_config_ntsc_trm;
425
426 BUG();
c6eee968 427 return NULL;
b2886273
TV		 428}
429
33ca237f 430static int venc_power_on(struct omap_dss_device *dssdev)
37ac60e4 431{
7ae9a71e 432 struct omap_overlay_manager *mgr = venc.output.manager;
37ac60e4 433 u32 l;
33ca237f 434 int r;
37ac60e4 435
156fd99e
AT		 436 r = venc_runtime_get();
437 if (r)
438 goto err0;
439
37ac60e4 440 venc_reset();
a5abf472 441 venc_write_config(venc_timings_to_config(&venc.timings));
37ac60e4 442
febe2905 443 dss_set_venc_output(venc.type);
37ac60e4
TV		 444 dss_set_dac_pwrdn_bgz(1);
445
446 l = 0;
447
febe2905 448 if (venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE)
37ac60e4
TV		 449 l |= 1 << 1;
450 else /* S-Video */
451 l |= (1 << 0) | (1 << 2);
452
89e71956 453 if (venc.invert_polarity == false)
37ac60e4
TV		 454 l |= 1 << 3;
455
456 venc_write_reg(VENC_OUTPUT_CONTROL, l);
457
8f1f736c 458 dss_mgr_set_timings(mgr, &venc.timings);
37ac60e4 459
ec874107
MB		 460 r = regulator_enable(venc.vdda_dac_reg);
461 if (r)
156fd99e 462 goto err1;
37ac60e4 463
8f1f736c 464 r = dss_mgr_enable(mgr);
33ca237f 465 if (r)
156fd99e 466 goto err2;
33ca237f
TV		 467
468 return 0;
469
156fd99e
AT		 470err2:
471 regulator_disable(venc.vdda_dac_reg);
472err1:
33ca237f
TV		 473 venc_write_reg(VENC_OUTPUT_CONTROL, 0);
474 dss_set_dac_pwrdn_bgz(0);
475
156fd99e
AT		 476 venc_runtime_put();
477err0:
33ca237f 478 return r;
37ac60e4
TV		 479}
480
481static void venc_power_off(struct omap_dss_device *dssdev)
482{
7ae9a71e 483 struct omap_overlay_manager *mgr = venc.output.manager;
8f1f736c 484
37ac60e4
TV		 485 venc_write_reg(VENC_OUTPUT_CONTROL, 0);
486 dss_set_dac_pwrdn_bgz(0);
487
8f1f736c 488 dss_mgr_disable(mgr);
37ac60e4 489
37ac60e4 490 regulator_disable(venc.vdda_dac_reg);
156fd99e
AT		 491
492 venc_runtime_put();
37ac60e4
TV		 493}
494
156fd99e 495int omapdss_venc_display_enable(struct omap_dss_device *dssdev)
0aca3c63 496{
1f68d9c4 497 struct omap_dss_device *out = &venc.output;
156fd99e 498 int r;
0aca3c63 499
156fd99e 500 DSSDBG("venc_display_enable\n");
0aca3c63
GI		 501
502 mutex_lock(&venc.venc_lock);
503
8f1f736c
AT		 504 if (out == NULL || out->manager == NULL) {
505 DSSERR("Failed to enable display: no output/manager\n");
156fd99e
AT		 506 r = -ENODEV;
507 goto err0;
0aca3c63
GI		 508 }
509
33ca237f
TV		 510 r = venc_power_on(dssdev);
511 if (r)
d3923933 512 goto err0;
37ac60e4
TV		 513
514 venc.wss_data = 0;
515
14572c63 516 mutex_unlock(&venc.venc_lock);
156fd99e 517
14572c63 518 return 0;
14572c63 519err0:
37ac60e4 520 mutex_unlock(&venc.venc_lock);
b2886273
TV		 521 return r;
522}
523
156fd99e 524void omapdss_venc_display_disable(struct omap_dss_device *dssdev)
b2886273 525{
156fd99e 526 DSSDBG("venc_display_disable\n");
b2886273 527
37ac60e4
TV		 528 mutex_lock(&venc.venc_lock);
529
37ac60e4
TV		 530 venc_power_off(dssdev);
531
156fd99e 532 mutex_unlock(&venc.venc_lock);
b2886273
TV		 533}
534
156fd99e
AT		 535void omapdss_venc_set_timings(struct omap_dss_device *dssdev,
536 struct omap_video_timings *timings)
69b2048f
TV		 537{
538 DSSDBG("venc_set_timings\n");
539
156fd99e
AT		 540 mutex_lock(&venc.venc_lock);
541
69b2048f 542 /* Reset WSS data when the TV standard changes. */
a5abf472 543 if (memcmp(&venc.timings, timings, sizeof(*timings)))
69b2048f
TV		 544 venc.wss_data = 0;
545
a5abf472 546 venc.timings = *timings;
156fd99e 547
5391e87d
TV		 548 dispc_set_tv_pclk(13500000);
549
156fd99e 550 mutex_unlock(&venc.venc_lock);
69b2048f
TV		 551}
552
156fd99e
AT		 553int omapdss_venc_check_timings(struct omap_dss_device *dssdev,
554 struct omap_video_timings *timings)
69b2048f
TV		 555{
556 DSSDBG("venc_check_timings\n");
557
558 if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
559 return 0;
560
561 if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
562 return 0;
563
564 return -EINVAL;
565}
566
fb8efa49
TV		 567static void venc_get_timings(struct omap_dss_device *dssdev,
568 struct omap_video_timings *timings)
569{
570 mutex_lock(&venc.venc_lock);
571
572 *timings = venc.timings;
573
574 mutex_unlock(&venc.venc_lock);
575}
576
156fd99e 577u32 omapdss_venc_get_wss(struct omap_dss_device *dssdev)
36511312
TV		 578{
579 /* Invert due to VENC_L21_WC_CTL:INV=1 */
580 return (venc.wss_data >> 8) ^ 0xfffff;
581}
582
156fd99e 583int omapdss_venc_set_wss(struct omap_dss_device *dssdev, u32 wss)
36511312
TV		 584{
585 const struct venc_config *config;
4fbafaf3 586 int r;
36511312
TV		 587
588 DSSDBG("venc_set_wss\n");
589
590 mutex_lock(&venc.venc_lock);
591
a5abf472 592 config = venc_timings_to_config(&venc.timings);
36511312
TV		 593
594 /* Invert due to VENC_L21_WC_CTL:INV=1 */
595 venc.wss_data = (wss ^ 0xfffff) << 8;
596
4fbafaf3
TV		 597 r = venc_runtime_get();
598 if (r)
599 goto err;
36511312
TV		 600
601 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
602 venc.wss_data);
603
4fbafaf3 604 venc_runtime_put();
36511312 605
4fbafaf3 606err:
36511312
TV		 607 mutex_unlock(&venc.venc_lock);
608
4fbafaf3 609 return r;
36511312
TV		 610}
611
febe2905
AT		 612void omapdss_venc_set_type(struct omap_dss_device *dssdev,
613 enum omap_dss_venc_type type)
614{
615 mutex_lock(&venc.venc_lock);
616
617 venc.type = type;
618
619 mutex_unlock(&venc.venc_lock);
620}
621
89e71956
AT		 622void omapdss_venc_invert_vid_out_polarity(struct omap_dss_device *dssdev,
623 bool invert_polarity)
624{
625 mutex_lock(&venc.venc_lock);
626
627 venc.invert_polarity = invert_polarity;
628
629 mutex_unlock(&venc.venc_lock);
630}
631
7e436bb2 632static int venc_init_regulator(void)
b2886273 633{
7e436bb2 634 struct regulator *vdda_dac;
b2886273 635
7e436bb2
TV		 636 if (venc.vdda_dac_reg != NULL)
637 return 0;
5f42f2ce 638
7e436bb2 639 vdda_dac = devm_regulator_get(&venc.pdev->dev, "vdda_dac");
5f42f2ce 640
7e436bb2
TV		 641 if (IS_ERR(vdda_dac)) {
642 DSSERR("can't get VDDA_DAC regulator\n");
643 return PTR_ERR(vdda_dac);
5f42f2ce
TV		 644 }
645
7e436bb2
TV		 646 venc.vdda_dac_reg = vdda_dac;
647
b2886273
TV		 648 return 0;
649}
650
e40402cf 651static void venc_dump_regs(struct seq_file *s)
b2886273
TV		 652{
653#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r))
654
4fbafaf3
TV		 655 if (venc_runtime_get())
656 return;
b2886273
TV		 657
658 DUMPREG(VENC_F_CONTROL);
659 DUMPREG(VENC_VIDOUT_CTRL);
660 DUMPREG(VENC_SYNC_CTRL);
661 DUMPREG(VENC_LLEN);
662 DUMPREG(VENC_FLENS);
663 DUMPREG(VENC_HFLTR_CTRL);
664 DUMPREG(VENC_CC_CARR_WSS_CARR);
665 DUMPREG(VENC_C_PHASE);
666 DUMPREG(VENC_GAIN_U);
667 DUMPREG(VENC_GAIN_V);
668 DUMPREG(VENC_GAIN_Y);
669 DUMPREG(VENC_BLACK_LEVEL);
670 DUMPREG(VENC_BLANK_LEVEL);
671 DUMPREG(VENC_X_COLOR);
672 DUMPREG(VENC_M_CONTROL);
673 DUMPREG(VENC_BSTAMP_WSS_DATA);
674 DUMPREG(VENC_S_CARR);
675 DUMPREG(VENC_LINE21);
676 DUMPREG(VENC_LN_SEL);
677 DUMPREG(VENC_L21__WC_CTL);
678 DUMPREG(VENC_HTRIGGER_VTRIGGER);
679 DUMPREG(VENC_SAVID__EAVID);
680 DUMPREG(VENC_FLEN__FAL);
681 DUMPREG(VENC_LAL__PHASE_RESET);
682 DUMPREG(VENC_HS_INT_START_STOP_X);
683 DUMPREG(VENC_HS_EXT_START_STOP_X);
684 DUMPREG(VENC_VS_INT_START_X);
685 DUMPREG(VENC_VS_INT_STOP_X__VS_INT_START_Y);
686 DUMPREG(VENC_VS_INT_STOP_Y__VS_EXT_START_X);
687 DUMPREG(VENC_VS_EXT_STOP_X__VS_EXT_START_Y);
688 DUMPREG(VENC_VS_EXT_STOP_Y);
689 DUMPREG(VENC_AVID_START_STOP_X);
690 DUMPREG(VENC_AVID_START_STOP_Y);
691 DUMPREG(VENC_FID_INT_START_X__FID_INT_START_Y);
692 DUMPREG(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X);
693 DUMPREG(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y);
694 DUMPREG(VENC_TVDETGP_INT_START_STOP_X);
695 DUMPREG(VENC_TVDETGP_INT_START_STOP_Y);
696 DUMPREG(VENC_GEN_CTRL);
697 DUMPREG(VENC_OUTPUT_CONTROL);
698 DUMPREG(VENC_OUTPUT_TEST);
699
4fbafaf3 700 venc_runtime_put();
b2886273
TV		 701
702#undef DUMPREG
703}
30ea50c9 704
4fbafaf3
TV		 705static int venc_get_clocks(struct platform_device *pdev)
706{
707 struct clk *clk;
708
4fbafaf3 709 if (dss_has_feature(FEAT_VENC_REQUIRES_TV_DAC_CLK)) {
b2c9c8ee 710 clk = devm_clk_get(&pdev->dev, "tv_dac_clk");
4fbafaf3
TV		 711 if (IS_ERR(clk)) {
712 DSSERR("can't get tv_dac_clk\n");
4fbafaf3
TV		 713 return PTR_ERR(clk);
714 }
715 } else {
716 clk = NULL;
717 }
718
719 venc.tv_dac_clk = clk;
720
721 return 0;
722}
723
b5a99c26 724static struct omap_dss_device *venc_find_dssdev(struct platform_device *pdev)
38f3daf6
TV		 725{
726 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
2bbcce5e 727 const char *def_disp_name = omapdss_get_default_display_name();
1521653c
TV		 728 struct omap_dss_device *def_dssdev;
729 int i;
730
731 def_dssdev = NULL;
38f3daf6
TV		 732
733 for (i = 0; i < pdata->num_devices; ++i) {
734 struct omap_dss_device *dssdev = pdata->devices[i];
735
736 if (dssdev->type != OMAP_DISPLAY_TYPE_VENC)
737 continue;
738
1521653c
TV		 739 if (def_dssdev == NULL)
740 def_dssdev = dssdev;
741
742 if (def_disp_name != NULL &&
743 strcmp(dssdev->name, def_disp_name) == 0) {
744 def_dssdev = dssdev;
745 break;
38f3daf6 746 }
1521653c
TV		 747 }
748
749 return def_dssdev;
750}
751
6aa66f5c 752static int venc_probe_pdata(struct platform_device *vencdev)
1521653c 753{
5274484b 754 struct omap_dss_device *plat_dssdev;
1521653c
TV		 755 struct omap_dss_device *dssdev;
756 int r;
757
5274484b 758 plat_dssdev = venc_find_dssdev(vencdev);
1521653c 759
5274484b 760 if (!plat_dssdev)
6aa66f5c 761 return 0;
5274484b 762
7e436bb2
TV		 763 r = venc_init_regulator();
764 if (r)
765 return r;
766
5274484b 767 dssdev = dss_alloc_and_init_device(&vencdev->dev);
1521653c 768 if (!dssdev)
6aa66f5c 769 return -ENOMEM;
1521653c 770
5274484b
TV		 771 dss_copy_device_pdata(dssdev, plat_dssdev);
772
486c0e17
TV		 773 r = omapdss_output_set_device(&venc.output, dssdev);
774 if (r) {
775 DSSERR("failed to connect output to new device: %s\n",
776 dssdev->name);
777 dss_put_device(dssdev);
6aa66f5c 778 return r;
486c0e17
TV		 779 }
780
5274484b 781 r = dss_add_device(dssdev);
1521653c
TV		 782 if (r) {
783 DSSERR("device %s register failed: %d\n", dssdev->name, r);
486c0e17 784 omapdss_output_unset_device(&venc.output);
5274484b 785 dss_put_device(dssdev);
6aa66f5c 786 return r;
38f3daf6 787 }
6aa66f5c
TV		 788
789 return 0;
38f3daf6
TV		 790}
791
fb8efa49
TV		 792static int venc_connect(struct omap_dss_device *dssdev,
793 struct omap_dss_device *dst)
794{
795 struct omap_overlay_manager *mgr;
796 int r;
797
798 r = venc_init_regulator();
799 if (r)
800 return r;
801
802 mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
803 if (!mgr)
804 return -ENODEV;
805
806 r = dss_mgr_connect(mgr, dssdev);
807 if (r)
808 return r;
809
810 r = omapdss_output_set_device(dssdev, dst);
811 if (r) {
812 DSSERR("failed to connect output to new device: %s\n",
813 dst->name);
814 dss_mgr_disconnect(mgr, dssdev);
815 return r;
816 }
817
818 return 0;
819}
820
821static void venc_disconnect(struct omap_dss_device *dssdev,
822 struct omap_dss_device *dst)
823{
824 WARN_ON(dst != dssdev->device);
825
826 if (dst != dssdev->device)
827 return;
828
829 omapdss_output_unset_device(dssdev);
830
831 if (dssdev->manager)
832 dss_mgr_disconnect(dssdev->manager, dssdev);
833}
834
835static const struct omapdss_atv_ops venc_ops = {
836 .connect = venc_connect,
837 .disconnect = venc_disconnect,
838
839 .enable = omapdss_venc_display_enable,
840 .disable = omapdss_venc_display_disable,
841
842 .check_timings = omapdss_venc_check_timings,
843 .set_timings = omapdss_venc_set_timings,
844 .get_timings = venc_get_timings,
845
846 .set_type = omapdss_venc_set_type,
847 .invert_vid_out_polarity = omapdss_venc_invert_vid_out_polarity,
848
849 .set_wss = omapdss_venc_set_wss,
850 .get_wss = omapdss_venc_get_wss,
851};
852
b5a99c26 853static void venc_init_output(struct platform_device *pdev)
81b87f51 854{
1f68d9c4 855 struct omap_dss_device *out = &venc.output;
81b87f51 856
1f68d9c4 857 out->dev = &pdev->dev;
81b87f51 858 out->id = OMAP_DSS_OUTPUT_VENC;
1f68d9c4 859 out->output_type = OMAP_DISPLAY_TYPE_VENC;
7286a08f 860 out->name = "venc.0";
2eea5ae6 861 out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
fb8efa49 862 out->ops.atv = &venc_ops;
b7328e14 863 out->owner = THIS_MODULE;
81b87f51 864
5d47dbc8 865 omapdss_register_output(out);
81b87f51
AT		 866}
867
868static void __exit venc_uninit_output(struct platform_device *pdev)
869{
1f68d9c4 870 struct omap_dss_device *out = &venc.output;
81b87f51 871
5d47dbc8 872 omapdss_unregister_output(out);
81b87f51
AT		 873}
874
30ea50c9 875/* VENC HW IP initialisation */
b5a99c26 876static int omap_venchw_probe(struct platform_device *pdev)
30ea50c9
SG		 877{
878 u8 rev_id;
ea9da36a 879 struct resource *venc_mem;
38f3daf6 880 int r;
ea9da36a 881
30ea50c9
SG		 882 venc.pdev = pdev;
883
884 mutex_init(&venc.venc_lock);
885
886 venc.wss_data = 0;
887
ea9da36a
SG		 888 venc_mem = platform_get_resource(venc.pdev, IORESOURCE_MEM, 0);
889 if (!venc_mem) {
890 DSSERR("can't get IORESOURCE_MEM VENC\n");
cd3b3449 891 return -EINVAL;
ea9da36a 892 }
cd3b3449 893
6e2a14d2
JL		 894 venc.base = devm_ioremap(&pdev->dev, venc_mem->start,
895 resource_size(venc_mem));
30ea50c9
SG		 896 if (!venc.base) {
897 DSSERR("can't ioremap VENC\n");
cd3b3449 898 return -ENOMEM;
30ea50c9
SG		 899 }
900
4fbafaf3
TV		 901 r = venc_get_clocks(pdev);
902 if (r)
cd3b3449 903 return r;
4fbafaf3
TV		 904
905 pm_runtime_enable(&pdev->dev);
906
907 r = venc_runtime_get();
908 if (r)
cd3b3449 909 goto err_runtime_get;
30ea50c9
SG		 910
911 rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff);
a06b62f8 912 dev_dbg(&pdev->dev, "OMAP VENC rev %d\n", rev_id);
30ea50c9 913
4fbafaf3 914 venc_runtime_put();
30ea50c9 915
156fd99e 916 r = venc_panel_init();
cd3b3449 917 if (r)
156fd99e 918 goto err_panel_init;
cd3b3449 919
e40402cf
TV		 920 dss_debugfs_create_file("venc", venc_dump_regs);
921
81b87f51
AT		 922 venc_init_output(pdev);
923
c6ca5b22
TV		 924 if (pdev->dev.platform_data) {
925 r = venc_probe_pdata(pdev);
926 if (r)
927 goto err_probe;
6aa66f5c 928 }
35deca3d 929
cd3b3449 930 return 0;
4fbafaf3 931
c6ca5b22
TV		 932err_probe:
933 venc_panel_exit();
934 venc_uninit_output(pdev);
156fd99e 935err_panel_init:
cd3b3449 936err_runtime_get:
4fbafaf3 937 pm_runtime_disable(&pdev->dev);
4fbafaf3 938 return r;
30ea50c9
SG		 939}
940
6e7e8f06 941static int __exit omap_venchw_remove(struct platform_device *pdev)
30ea50c9 942{
5274484b 943 dss_unregister_child_devices(&pdev->dev);
35deca3d 944
156fd99e 945 venc_panel_exit();
30ea50c9 946
81b87f51
AT		 947 venc_uninit_output(pdev);
948
4fbafaf3 949 pm_runtime_disable(&pdev->dev);
4fbafaf3 950
30ea50c9
SG		 951 return 0;
952}
953
4fbafaf3
TV		 954static int venc_runtime_suspend(struct device *dev)
955{
956 if (venc.tv_dac_clk)
f11766d1 957 clk_disable_unprepare(venc.tv_dac_clk);
4fbafaf3
TV		 958
959 dispc_runtime_put();
4fbafaf3
TV		 960
961 return 0;
962}
963
964static int venc_runtime_resume(struct device *dev)
965{
966 int r;
967
4fbafaf3
TV		 968 r = dispc_runtime_get();
969 if (r < 0)
852f0838 970 return r;
4fbafaf3 971
4fbafaf3 972 if (venc.tv_dac_clk)
f11766d1 973 clk_prepare_enable(venc.tv_dac_clk);
4fbafaf3
TV		 974
975 return 0;
4fbafaf3
TV		 976}
977
978static const struct dev_pm_ops venc_pm_ops = {
979 .runtime_suspend = venc_runtime_suspend,
980 .runtime_resume = venc_runtime_resume,
981};
982
30ea50c9 983static struct platform_driver omap_venchw_driver = {
b5a99c26 984 .probe = omap_venchw_probe,
6e7e8f06 985 .remove = __exit_p(omap_venchw_remove),
30ea50c9
SG		 986 .driver = {
987 .name = "omapdss_venc",
988 .owner = THIS_MODULE,
4fbafaf3 989 .pm = &venc_pm_ops,
30ea50c9
SG		 990 },
991};
992
6e7e8f06 993int __init venc_init_platform_driver(void)
30ea50c9 994{
b5a99c26 995 return platform_driver_register(&omap_venchw_driver);
30ea50c9
SG		 996}
997
6e7e8f06 998void __exit venc_uninit_platform_driver(void)
30ea50c9 999{
04c742c3 1000 platform_driver_unregister(&omap_venchw_driver);
30ea50c9 1001}
Linux kernel - Deliverables
This page took 0.395512 seconds and 5 git commands to generate.