Commit | Line | Data |
---|---|---|
b2886273 TV |
1 | /* |
2 | * linux/drivers/video/omap2/dss/venc.c | |
3 | * | |
4 | * Copyright (C) 2009 Nokia Corporation | |
5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> | |
6 | * | |
7 | * VENC settings from TI's DSS driver | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License version 2 as published by | |
11 | * the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along with | |
19 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #define DSS_SUBSYS_NAME "VENC" | |
23 | ||
24 | #include <linux/kernel.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/clk.h> | |
27 | #include <linux/err.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/mutex.h> | |
30 | #include <linux/completion.h> | |
31 | #include <linux/delay.h> | |
32 | #include <linux/string.h> | |
33 | #include <linux/seq_file.h> | |
34 | #include <linux/platform_device.h> | |
35 | #include <linux/regulator/consumer.h> | |
36 | ||
37 | #include <plat/display.h> | |
38 | #include <plat/cpu.h> | |
39 | ||
40 | #include "dss.h" | |
41 | ||
42 | #define VENC_BASE 0x48050C00 | |
43 | ||
44 | /* Venc registers */ | |
45 | #define VENC_REV_ID 0x00 | |
46 | #define VENC_STATUS 0x04 | |
47 | #define VENC_F_CONTROL 0x08 | |
48 | #define VENC_VIDOUT_CTRL 0x10 | |
49 | #define VENC_SYNC_CTRL 0x14 | |
50 | #define VENC_LLEN 0x1C | |
51 | #define VENC_FLENS 0x20 | |
52 | #define VENC_HFLTR_CTRL 0x24 | |
53 | #define VENC_CC_CARR_WSS_CARR 0x28 | |
54 | #define VENC_C_PHASE 0x2C | |
55 | #define VENC_GAIN_U 0x30 | |
56 | #define VENC_GAIN_V 0x34 | |
57 | #define VENC_GAIN_Y 0x38 | |
58 | #define VENC_BLACK_LEVEL 0x3C | |
59 | #define VENC_BLANK_LEVEL 0x40 | |
60 | #define VENC_X_COLOR 0x44 | |
61 | #define VENC_M_CONTROL 0x48 | |
62 | #define VENC_BSTAMP_WSS_DATA 0x4C | |
63 | #define VENC_S_CARR 0x50 | |
64 | #define VENC_LINE21 0x54 | |
65 | #define VENC_LN_SEL 0x58 | |
66 | #define VENC_L21__WC_CTL 0x5C | |
67 | #define VENC_HTRIGGER_VTRIGGER 0x60 | |
68 | #define VENC_SAVID__EAVID 0x64 | |
69 | #define VENC_FLEN__FAL 0x68 | |
70 | #define VENC_LAL__PHASE_RESET 0x6C | |
71 | #define VENC_HS_INT_START_STOP_X 0x70 | |
72 | #define VENC_HS_EXT_START_STOP_X 0x74 | |
73 | #define VENC_VS_INT_START_X 0x78 | |
74 | #define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C | |
75 | #define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80 | |
76 | #define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84 | |
77 | #define VENC_VS_EXT_STOP_Y 0x88 | |
78 | #define VENC_AVID_START_STOP_X 0x90 | |
79 | #define VENC_AVID_START_STOP_Y 0x94 | |
80 | #define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0 | |
81 | #define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4 | |
82 | #define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8 | |
83 | #define VENC_TVDETGP_INT_START_STOP_X 0xB0 | |
84 | #define VENC_TVDETGP_INT_START_STOP_Y 0xB4 | |
85 | #define VENC_GEN_CTRL 0xB8 | |
86 | #define VENC_OUTPUT_CONTROL 0xC4 | |
87 | #define VENC_OUTPUT_TEST 0xC8 | |
88 | #define VENC_DAC_B__DAC_C 0xC8 | |
89 | ||
90 | struct venc_config { | |
91 | u32 f_control; | |
92 | u32 vidout_ctrl; | |
93 | u32 sync_ctrl; | |
94 | u32 llen; | |
95 | u32 flens; | |
96 | u32 hfltr_ctrl; | |
97 | u32 cc_carr_wss_carr; | |
98 | u32 c_phase; | |
99 | u32 gain_u; | |
100 | u32 gain_v; | |
101 | u32 gain_y; | |
102 | u32 black_level; | |
103 | u32 blank_level; | |
104 | u32 x_color; | |
105 | u32 m_control; | |
106 | u32 bstamp_wss_data; | |
107 | u32 s_carr; | |
108 | u32 line21; | |
109 | u32 ln_sel; | |
110 | u32 l21__wc_ctl; | |
111 | u32 htrigger_vtrigger; | |
112 | u32 savid__eavid; | |
113 | u32 flen__fal; | |
114 | u32 lal__phase_reset; | |
115 | u32 hs_int_start_stop_x; | |
116 | u32 hs_ext_start_stop_x; | |
117 | u32 vs_int_start_x; | |
118 | u32 vs_int_stop_x__vs_int_start_y; | |
119 | u32 vs_int_stop_y__vs_ext_start_x; | |
120 | u32 vs_ext_stop_x__vs_ext_start_y; | |
121 | u32 vs_ext_stop_y; | |
122 | u32 avid_start_stop_x; | |
123 | u32 avid_start_stop_y; | |
124 | u32 fid_int_start_x__fid_int_start_y; | |
125 | u32 fid_int_offset_y__fid_ext_start_x; | |
126 | u32 fid_ext_start_y__fid_ext_offset_y; | |
127 | u32 tvdetgp_int_start_stop_x; | |
128 | u32 tvdetgp_int_start_stop_y; | |
129 | u32 gen_ctrl; | |
130 | }; | |
131 | ||
132 | /* from TRM */ | |
133 | static const struct venc_config venc_config_pal_trm = { | |
134 | .f_control = 0, | |
135 | .vidout_ctrl = 1, | |
136 | .sync_ctrl = 0x40, | |
137 | .llen = 0x35F, /* 863 */ | |
138 | .flens = 0x270, /* 624 */ | |
139 | .hfltr_ctrl = 0, | |
140 | .cc_carr_wss_carr = 0x2F7225ED, | |
141 | .c_phase = 0, | |
142 | .gain_u = 0x111, | |
143 | .gain_v = 0x181, | |
144 | .gain_y = 0x140, | |
145 | .black_level = 0x3B, | |
146 | .blank_level = 0x3B, | |
147 | .x_color = 0x7, | |
148 | .m_control = 0x2, | |
149 | .bstamp_wss_data = 0x3F, | |
150 | .s_carr = 0x2A098ACB, | |
151 | .line21 = 0, | |
152 | .ln_sel = 0x01290015, | |
153 | .l21__wc_ctl = 0x0000F603, | |
154 | .htrigger_vtrigger = 0, | |
155 | ||
156 | .savid__eavid = 0x06A70108, | |
157 | .flen__fal = 0x00180270, | |
158 | .lal__phase_reset = 0x00040135, | |
159 | .hs_int_start_stop_x = 0x00880358, | |
160 | .hs_ext_start_stop_x = 0x000F035F, | |
161 | .vs_int_start_x = 0x01A70000, | |
162 | .vs_int_stop_x__vs_int_start_y = 0x000001A7, | |
163 | .vs_int_stop_y__vs_ext_start_x = 0x01AF0000, | |
164 | .vs_ext_stop_x__vs_ext_start_y = 0x000101AF, | |
165 | .vs_ext_stop_y = 0x00000025, | |
166 | .avid_start_stop_x = 0x03530083, | |
167 | .avid_start_stop_y = 0x026C002E, | |
168 | .fid_int_start_x__fid_int_start_y = 0x0001008A, | |
169 | .fid_int_offset_y__fid_ext_start_x = 0x002E0138, | |
170 | .fid_ext_start_y__fid_ext_offset_y = 0x01380001, | |
171 | ||
172 | .tvdetgp_int_start_stop_x = 0x00140001, | |
173 | .tvdetgp_int_start_stop_y = 0x00010001, | |
174 | .gen_ctrl = 0x00FF0000, | |
175 | }; | |
176 | ||
177 | /* from TRM */ | |
178 | static const struct venc_config venc_config_ntsc_trm = { | |
179 | .f_control = 0, | |
180 | .vidout_ctrl = 1, | |
181 | .sync_ctrl = 0x8040, | |
182 | .llen = 0x359, | |
183 | .flens = 0x20C, | |
184 | .hfltr_ctrl = 0, | |
185 | .cc_carr_wss_carr = 0x043F2631, | |
186 | .c_phase = 0, | |
187 | .gain_u = 0x102, | |
188 | .gain_v = 0x16C, | |
189 | .gain_y = 0x12F, | |
190 | .black_level = 0x43, | |
191 | .blank_level = 0x38, | |
192 | .x_color = 0x7, | |
193 | .m_control = 0x1, | |
194 | .bstamp_wss_data = 0x38, | |
195 | .s_carr = 0x21F07C1F, | |
196 | .line21 = 0, | |
197 | .ln_sel = 0x01310011, | |
198 | .l21__wc_ctl = 0x0000F003, | |
199 | .htrigger_vtrigger = 0, | |
200 | ||
201 | .savid__eavid = 0x069300F4, | |
202 | .flen__fal = 0x0016020C, | |
203 | .lal__phase_reset = 0x00060107, | |
204 | .hs_int_start_stop_x = 0x008E0350, | |
205 | .hs_ext_start_stop_x = 0x000F0359, | |
206 | .vs_int_start_x = 0x01A00000, | |
207 | .vs_int_stop_x__vs_int_start_y = 0x020701A0, | |
208 | .vs_int_stop_y__vs_ext_start_x = 0x01AC0024, | |
209 | .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC, | |
210 | .vs_ext_stop_y = 0x00000006, | |
211 | .avid_start_stop_x = 0x03480078, | |
212 | .avid_start_stop_y = 0x02060024, | |
213 | .fid_int_start_x__fid_int_start_y = 0x0001008A, | |
214 | .fid_int_offset_y__fid_ext_start_x = 0x01AC0106, | |
215 | .fid_ext_start_y__fid_ext_offset_y = 0x01060006, | |
216 | ||
217 | .tvdetgp_int_start_stop_x = 0x00140001, | |
218 | .tvdetgp_int_start_stop_y = 0x00010001, | |
219 | .gen_ctrl = 0x00F90000, | |
220 | }; | |
221 | ||
222 | static const struct venc_config venc_config_pal_bdghi = { | |
223 | .f_control = 0, | |
224 | .vidout_ctrl = 0, | |
225 | .sync_ctrl = 0, | |
226 | .hfltr_ctrl = 0, | |
227 | .x_color = 0, | |
228 | .line21 = 0, | |
229 | .ln_sel = 21, | |
230 | .htrigger_vtrigger = 0, | |
231 | .tvdetgp_int_start_stop_x = 0x00140001, | |
232 | .tvdetgp_int_start_stop_y = 0x00010001, | |
233 | .gen_ctrl = 0x00FB0000, | |
234 | ||
235 | .llen = 864-1, | |
236 | .flens = 625-1, | |
237 | .cc_carr_wss_carr = 0x2F7625ED, | |
238 | .c_phase = 0xDF, | |
239 | .gain_u = 0x111, | |
240 | .gain_v = 0x181, | |
241 | .gain_y = 0x140, | |
242 | .black_level = 0x3e, | |
243 | .blank_level = 0x3e, | |
244 | .m_control = 0<<2 | 1<<1, | |
245 | .bstamp_wss_data = 0x42, | |
246 | .s_carr = 0x2a098acb, | |
247 | .l21__wc_ctl = 0<<13 | 0x16<<8 | 0<<0, | |
248 | .savid__eavid = 0x06A70108, | |
249 | .flen__fal = 23<<16 | 624<<0, | |
250 | .lal__phase_reset = 2<<17 | 310<<0, | |
251 | .hs_int_start_stop_x = 0x00920358, | |
252 | .hs_ext_start_stop_x = 0x000F035F, | |
253 | .vs_int_start_x = 0x1a7<<16, | |
254 | .vs_int_stop_x__vs_int_start_y = 0x000601A7, | |
255 | .vs_int_stop_y__vs_ext_start_x = 0x01AF0036, | |
256 | .vs_ext_stop_x__vs_ext_start_y = 0x27101af, | |
257 | .vs_ext_stop_y = 0x05, | |
258 | .avid_start_stop_x = 0x03530082, | |
259 | .avid_start_stop_y = 0x0270002E, | |
260 | .fid_int_start_x__fid_int_start_y = 0x0005008A, | |
261 | .fid_int_offset_y__fid_ext_start_x = 0x002E0138, | |
262 | .fid_ext_start_y__fid_ext_offset_y = 0x01380005, | |
263 | }; | |
264 | ||
265 | const struct omap_video_timings omap_dss_pal_timings = { | |
266 | .x_res = 720, | |
267 | .y_res = 574, | |
268 | .pixel_clock = 13500, | |
269 | .hsw = 64, | |
270 | .hfp = 12, | |
271 | .hbp = 68, | |
272 | .vsw = 5, | |
273 | .vfp = 5, | |
274 | .vbp = 41, | |
275 | }; | |
276 | EXPORT_SYMBOL(omap_dss_pal_timings); | |
277 | ||
278 | const struct omap_video_timings omap_dss_ntsc_timings = { | |
279 | .x_res = 720, | |
280 | .y_res = 482, | |
281 | .pixel_clock = 13500, | |
282 | .hsw = 64, | |
283 | .hfp = 16, | |
284 | .hbp = 58, | |
285 | .vsw = 6, | |
286 | .vfp = 6, | |
287 | .vbp = 31, | |
288 | }; | |
289 | EXPORT_SYMBOL(omap_dss_ntsc_timings); | |
290 | ||
291 | static struct { | |
292 | void __iomem *base; | |
293 | struct mutex venc_lock; | |
294 | u32 wss_data; | |
295 | struct regulator *vdda_dac_reg; | |
296 | } venc; | |
297 | ||
298 | static inline void venc_write_reg(int idx, u32 val) | |
299 | { | |
300 | __raw_writel(val, venc.base + idx); | |
301 | } | |
302 | ||
303 | static inline u32 venc_read_reg(int idx) | |
304 | { | |
305 | u32 l = __raw_readl(venc.base + idx); | |
306 | return l; | |
307 | } | |
308 | ||
309 | static void venc_write_config(const struct venc_config *config) | |
310 | { | |
311 | DSSDBG("write venc conf\n"); | |
312 | ||
313 | venc_write_reg(VENC_LLEN, config->llen); | |
314 | venc_write_reg(VENC_FLENS, config->flens); | |
315 | venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr); | |
316 | venc_write_reg(VENC_C_PHASE, config->c_phase); | |
317 | venc_write_reg(VENC_GAIN_U, config->gain_u); | |
318 | venc_write_reg(VENC_GAIN_V, config->gain_v); | |
319 | venc_write_reg(VENC_GAIN_Y, config->gain_y); | |
320 | venc_write_reg(VENC_BLACK_LEVEL, config->black_level); | |
321 | venc_write_reg(VENC_BLANK_LEVEL, config->blank_level); | |
322 | venc_write_reg(VENC_M_CONTROL, config->m_control); | |
323 | venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data | | |
324 | venc.wss_data); | |
325 | venc_write_reg(VENC_S_CARR, config->s_carr); | |
326 | venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl); | |
327 | venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid); | |
328 | venc_write_reg(VENC_FLEN__FAL, config->flen__fal); | |
329 | venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset); | |
330 | venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x); | |
331 | venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x); | |
332 | venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x); | |
333 | venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y, | |
334 | config->vs_int_stop_x__vs_int_start_y); | |
335 | venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X, | |
336 | config->vs_int_stop_y__vs_ext_start_x); | |
337 | venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y, | |
338 | config->vs_ext_stop_x__vs_ext_start_y); | |
339 | venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y); | |
340 | venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x); | |
341 | venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y); | |
342 | venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y, | |
343 | config->fid_int_start_x__fid_int_start_y); | |
344 | venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X, | |
345 | config->fid_int_offset_y__fid_ext_start_x); | |
346 | venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y, | |
347 | config->fid_ext_start_y__fid_ext_offset_y); | |
348 | ||
349 | venc_write_reg(VENC_DAC_B__DAC_C, venc_read_reg(VENC_DAC_B__DAC_C)); | |
350 | venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl); | |
351 | venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl); | |
352 | venc_write_reg(VENC_X_COLOR, config->x_color); | |
353 | venc_write_reg(VENC_LINE21, config->line21); | |
354 | venc_write_reg(VENC_LN_SEL, config->ln_sel); | |
355 | venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger); | |
356 | venc_write_reg(VENC_TVDETGP_INT_START_STOP_X, | |
357 | config->tvdetgp_int_start_stop_x); | |
358 | venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y, | |
359 | config->tvdetgp_int_start_stop_y); | |
360 | venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl); | |
361 | venc_write_reg(VENC_F_CONTROL, config->f_control); | |
362 | venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl); | |
363 | } | |
364 | ||
365 | static void venc_reset(void) | |
366 | { | |
367 | int t = 1000; | |
368 | ||
369 | venc_write_reg(VENC_F_CONTROL, 1<<8); | |
370 | while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) { | |
371 | if (--t == 0) { | |
372 | DSSERR("Failed to reset venc\n"); | |
373 | return; | |
374 | } | |
375 | } | |
376 | ||
377 | /* the magical sleep that makes things work */ | |
378 | msleep(20); | |
379 | } | |
380 | ||
381 | static void venc_enable_clocks(int enable) | |
382 | { | |
383 | if (enable) | |
384 | dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_54M | | |
385 | DSS_CLK_96M); | |
386 | else | |
387 | dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_54M | | |
388 | DSS_CLK_96M); | |
389 | } | |
390 | ||
391 | static const struct venc_config *venc_timings_to_config( | |
392 | struct omap_video_timings *timings) | |
393 | { | |
394 | if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0) | |
395 | return &venc_config_pal_trm; | |
396 | ||
397 | if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0) | |
398 | return &venc_config_ntsc_trm; | |
399 | ||
400 | BUG(); | |
401 | } | |
402 | ||
403 | ||
404 | ||
405 | ||
406 | ||
407 | /* driver */ | |
408 | static int venc_panel_probe(struct omap_dss_device *dssdev) | |
409 | { | |
410 | dssdev->panel.timings = omap_dss_pal_timings; | |
411 | ||
412 | return 0; | |
413 | } | |
414 | ||
415 | static void venc_panel_remove(struct omap_dss_device *dssdev) | |
416 | { | |
417 | } | |
418 | ||
419 | static int venc_panel_enable(struct omap_dss_device *dssdev) | |
420 | { | |
421 | int r = 0; | |
422 | ||
423 | /* wait couple of vsyncs until enabling the LCD */ | |
424 | msleep(50); | |
425 | ||
426 | if (dssdev->platform_enable) | |
427 | r = dssdev->platform_enable(dssdev); | |
428 | ||
429 | return r; | |
430 | } | |
431 | ||
432 | static void venc_panel_disable(struct omap_dss_device *dssdev) | |
433 | { | |
434 | if (dssdev->platform_disable) | |
435 | dssdev->platform_disable(dssdev); | |
436 | ||
437 | /* wait at least 5 vsyncs after disabling the LCD */ | |
438 | ||
439 | msleep(100); | |
440 | } | |
441 | ||
442 | static int venc_panel_suspend(struct omap_dss_device *dssdev) | |
443 | { | |
444 | venc_panel_disable(dssdev); | |
445 | return 0; | |
446 | } | |
447 | ||
448 | static int venc_panel_resume(struct omap_dss_device *dssdev) | |
449 | { | |
450 | return venc_panel_enable(dssdev); | |
451 | } | |
452 | ||
446f7bff TV |
453 | static enum omap_dss_update_mode venc_get_update_mode( |
454 | struct omap_dss_device *dssdev) | |
455 | { | |
456 | return OMAP_DSS_UPDATE_AUTO; | |
457 | } | |
458 | ||
459 | static int venc_set_update_mode(struct omap_dss_device *dssdev, | |
460 | enum omap_dss_update_mode mode) | |
461 | { | |
462 | if (mode != OMAP_DSS_UPDATE_AUTO) | |
463 | return -EINVAL; | |
464 | return 0; | |
465 | } | |
466 | ||
b2886273 TV |
467 | static struct omap_dss_driver venc_driver = { |
468 | .probe = venc_panel_probe, | |
469 | .remove = venc_panel_remove, | |
470 | ||
471 | .enable = venc_panel_enable, | |
472 | .disable = venc_panel_disable, | |
473 | .suspend = venc_panel_suspend, | |
474 | .resume = venc_panel_resume, | |
475 | ||
96adcece | 476 | .get_resolution = omapdss_default_get_resolution, |
a2699504 | 477 | .get_recommended_bpp = omapdss_default_get_recommended_bpp, |
96adcece | 478 | |
446f7bff TV |
479 | .set_update_mode = venc_set_update_mode, |
480 | .get_update_mode = venc_get_update_mode, | |
481 | ||
b2886273 TV |
482 | .driver = { |
483 | .name = "venc", | |
484 | .owner = THIS_MODULE, | |
485 | }, | |
486 | }; | |
487 | /* driver end */ | |
488 | ||
489 | ||
490 | ||
491 | int venc_init(struct platform_device *pdev) | |
492 | { | |
493 | u8 rev_id; | |
494 | ||
495 | mutex_init(&venc.venc_lock); | |
496 | ||
497 | venc.wss_data = 0; | |
498 | ||
499 | venc.base = ioremap(VENC_BASE, SZ_1K); | |
500 | if (!venc.base) { | |
501 | DSSERR("can't ioremap VENC\n"); | |
502 | return -ENOMEM; | |
503 | } | |
504 | ||
8a2cfea8 | 505 | venc.vdda_dac_reg = dss_get_vdda_dac(); |
b2886273 TV |
506 | if (IS_ERR(venc.vdda_dac_reg)) { |
507 | iounmap(venc.base); | |
508 | DSSERR("can't get VDDA_DAC regulator\n"); | |
509 | return PTR_ERR(venc.vdda_dac_reg); | |
510 | } | |
511 | ||
512 | venc_enable_clocks(1); | |
513 | ||
514 | rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff); | |
515 | printk(KERN_INFO "OMAP VENC rev %d\n", rev_id); | |
516 | ||
517 | venc_enable_clocks(0); | |
518 | ||
519 | return omap_dss_register_driver(&venc_driver); | |
520 | } | |
521 | ||
522 | void venc_exit(void) | |
523 | { | |
524 | omap_dss_unregister_driver(&venc_driver); | |
525 | ||
b2886273 TV |
526 | iounmap(venc.base); |
527 | } | |
528 | ||
529 | static void venc_power_on(struct omap_dss_device *dssdev) | |
530 | { | |
531 | u32 l; | |
532 | ||
533 | venc_enable_clocks(1); | |
534 | ||
535 | venc_reset(); | |
536 | venc_write_config(venc_timings_to_config(&dssdev->panel.timings)); | |
537 | ||
538 | dss_set_venc_output(dssdev->phy.venc.type); | |
539 | dss_set_dac_pwrdn_bgz(1); | |
540 | ||
541 | l = 0; | |
542 | ||
543 | if (dssdev->phy.venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE) | |
544 | l |= 1 << 1; | |
545 | else /* S-Video */ | |
546 | l |= (1 << 0) | (1 << 2); | |
547 | ||
548 | if (dssdev->phy.venc.invert_polarity == false) | |
549 | l |= 1 << 3; | |
550 | ||
551 | venc_write_reg(VENC_OUTPUT_CONTROL, l); | |
552 | ||
553 | dispc_set_digit_size(dssdev->panel.timings.x_res, | |
554 | dssdev->panel.timings.y_res/2); | |
555 | ||
556 | regulator_enable(venc.vdda_dac_reg); | |
557 | ||
558 | if (dssdev->platform_enable) | |
559 | dssdev->platform_enable(dssdev); | |
560 | ||
a2faee84 | 561 | dssdev->manager->enable(dssdev->manager); |
b2886273 TV |
562 | } |
563 | ||
564 | static void venc_power_off(struct omap_dss_device *dssdev) | |
565 | { | |
566 | venc_write_reg(VENC_OUTPUT_CONTROL, 0); | |
567 | dss_set_dac_pwrdn_bgz(0); | |
568 | ||
a2faee84 | 569 | dssdev->manager->disable(dssdev->manager); |
b2886273 TV |
570 | |
571 | if (dssdev->platform_disable) | |
572 | dssdev->platform_disable(dssdev); | |
573 | ||
574 | regulator_disable(venc.vdda_dac_reg); | |
575 | ||
576 | venc_enable_clocks(0); | |
577 | } | |
578 | ||
579 | static int venc_enable_display(struct omap_dss_device *dssdev) | |
580 | { | |
581 | int r = 0; | |
582 | ||
583 | DSSDBG("venc_enable_display\n"); | |
584 | ||
585 | mutex_lock(&venc.venc_lock); | |
586 | ||
587 | if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) { | |
588 | r = -EINVAL; | |
589 | goto err; | |
590 | } | |
591 | ||
592 | venc_power_on(dssdev); | |
593 | ||
594 | venc.wss_data = 0; | |
595 | ||
596 | dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; | |
597 | err: | |
598 | mutex_unlock(&venc.venc_lock); | |
599 | ||
600 | return r; | |
601 | } | |
602 | ||
603 | static void venc_disable_display(struct omap_dss_device *dssdev) | |
604 | { | |
605 | DSSDBG("venc_disable_display\n"); | |
606 | ||
607 | mutex_lock(&venc.venc_lock); | |
608 | ||
609 | if (dssdev->state == OMAP_DSS_DISPLAY_DISABLED) | |
610 | goto end; | |
611 | ||
612 | if (dssdev->state == OMAP_DSS_DISPLAY_SUSPENDED) { | |
613 | /* suspended is the same as disabled with venc */ | |
614 | dssdev->state = OMAP_DSS_DISPLAY_DISABLED; | |
615 | goto end; | |
616 | } | |
617 | ||
618 | venc_power_off(dssdev); | |
619 | ||
620 | dssdev->state = OMAP_DSS_DISPLAY_DISABLED; | |
621 | end: | |
622 | mutex_unlock(&venc.venc_lock); | |
623 | } | |
624 | ||
625 | static int venc_display_suspend(struct omap_dss_device *dssdev) | |
626 | { | |
627 | int r = 0; | |
628 | ||
629 | DSSDBG("venc_display_suspend\n"); | |
630 | ||
631 | mutex_lock(&venc.venc_lock); | |
632 | ||
633 | if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) { | |
634 | r = -EINVAL; | |
635 | goto err; | |
636 | } | |
637 | ||
638 | venc_power_off(dssdev); | |
639 | ||
640 | dssdev->state = OMAP_DSS_DISPLAY_SUSPENDED; | |
641 | err: | |
642 | mutex_unlock(&venc.venc_lock); | |
643 | ||
644 | return r; | |
645 | } | |
646 | ||
647 | static int venc_display_resume(struct omap_dss_device *dssdev) | |
648 | { | |
649 | int r = 0; | |
650 | ||
651 | DSSDBG("venc_display_resume\n"); | |
652 | ||
653 | mutex_lock(&venc.venc_lock); | |
654 | ||
655 | if (dssdev->state != OMAP_DSS_DISPLAY_SUSPENDED) { | |
656 | r = -EINVAL; | |
657 | goto err; | |
658 | } | |
659 | ||
660 | venc_power_on(dssdev); | |
661 | ||
662 | dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; | |
663 | err: | |
664 | mutex_unlock(&venc.venc_lock); | |
665 | ||
666 | return r; | |
667 | } | |
668 | ||
669 | static void venc_get_timings(struct omap_dss_device *dssdev, | |
670 | struct omap_video_timings *timings) | |
671 | { | |
672 | *timings = dssdev->panel.timings; | |
673 | } | |
674 | ||
675 | static void venc_set_timings(struct omap_dss_device *dssdev, | |
676 | struct omap_video_timings *timings) | |
677 | { | |
678 | DSSDBG("venc_set_timings\n"); | |
679 | ||
680 | /* Reset WSS data when the TV standard changes. */ | |
681 | if (memcmp(&dssdev->panel.timings, timings, sizeof(*timings))) | |
682 | venc.wss_data = 0; | |
683 | ||
684 | dssdev->panel.timings = *timings; | |
685 | if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) { | |
686 | /* turn the venc off and on to get new timings to use */ | |
687 | venc_disable_display(dssdev); | |
688 | venc_enable_display(dssdev); | |
689 | } | |
690 | } | |
691 | ||
692 | static int venc_check_timings(struct omap_dss_device *dssdev, | |
693 | struct omap_video_timings *timings) | |
694 | { | |
695 | DSSDBG("venc_check_timings\n"); | |
696 | ||
697 | if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0) | |
698 | return 0; | |
699 | ||
700 | if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0) | |
701 | return 0; | |
702 | ||
703 | return -EINVAL; | |
704 | } | |
705 | ||
706 | static u32 venc_get_wss(struct omap_dss_device *dssdev) | |
707 | { | |
708 | /* Invert due to VENC_L21_WC_CTL:INV=1 */ | |
709 | return (venc.wss_data >> 8) ^ 0xfffff; | |
710 | } | |
711 | ||
712 | static int venc_set_wss(struct omap_dss_device *dssdev, u32 wss) | |
713 | { | |
714 | const struct venc_config *config; | |
715 | ||
716 | DSSDBG("venc_set_wss\n"); | |
717 | ||
718 | mutex_lock(&venc.venc_lock); | |
719 | ||
720 | config = venc_timings_to_config(&dssdev->panel.timings); | |
721 | ||
722 | /* Invert due to VENC_L21_WC_CTL:INV=1 */ | |
723 | venc.wss_data = (wss ^ 0xfffff) << 8; | |
724 | ||
725 | venc_enable_clocks(1); | |
726 | ||
727 | venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data | | |
728 | venc.wss_data); | |
729 | ||
730 | venc_enable_clocks(0); | |
731 | ||
732 | mutex_unlock(&venc.venc_lock); | |
733 | ||
734 | return 0; | |
735 | } | |
736 | ||
b2886273 TV |
737 | int venc_init_display(struct omap_dss_device *dssdev) |
738 | { | |
739 | DSSDBG("init_display\n"); | |
740 | ||
741 | dssdev->enable = venc_enable_display; | |
742 | dssdev->disable = venc_disable_display; | |
743 | dssdev->suspend = venc_display_suspend; | |
744 | dssdev->resume = venc_display_resume; | |
745 | dssdev->get_timings = venc_get_timings; | |
746 | dssdev->set_timings = venc_set_timings; | |
747 | dssdev->check_timings = venc_check_timings; | |
748 | dssdev->get_wss = venc_get_wss; | |
749 | dssdev->set_wss = venc_set_wss; | |
b2886273 TV |
750 | |
751 | return 0; | |
752 | } | |
753 | ||
754 | void venc_dump_regs(struct seq_file *s) | |
755 | { | |
756 | #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r)) | |
757 | ||
758 | venc_enable_clocks(1); | |
759 | ||
760 | DUMPREG(VENC_F_CONTROL); | |
761 | DUMPREG(VENC_VIDOUT_CTRL); | |
762 | DUMPREG(VENC_SYNC_CTRL); | |
763 | DUMPREG(VENC_LLEN); | |
764 | DUMPREG(VENC_FLENS); | |
765 | DUMPREG(VENC_HFLTR_CTRL); | |
766 | DUMPREG(VENC_CC_CARR_WSS_CARR); | |
767 | DUMPREG(VENC_C_PHASE); | |
768 | DUMPREG(VENC_GAIN_U); | |
769 | DUMPREG(VENC_GAIN_V); | |
770 | DUMPREG(VENC_GAIN_Y); | |
771 | DUMPREG(VENC_BLACK_LEVEL); | |
772 | DUMPREG(VENC_BLANK_LEVEL); | |
773 | DUMPREG(VENC_X_COLOR); | |
774 | DUMPREG(VENC_M_CONTROL); | |
775 | DUMPREG(VENC_BSTAMP_WSS_DATA); | |
776 | DUMPREG(VENC_S_CARR); | |
777 | DUMPREG(VENC_LINE21); | |
778 | DUMPREG(VENC_LN_SEL); | |
779 | DUMPREG(VENC_L21__WC_CTL); | |
780 | DUMPREG(VENC_HTRIGGER_VTRIGGER); | |
781 | DUMPREG(VENC_SAVID__EAVID); | |
782 | DUMPREG(VENC_FLEN__FAL); | |
783 | DUMPREG(VENC_LAL__PHASE_RESET); | |
784 | DUMPREG(VENC_HS_INT_START_STOP_X); | |
785 | DUMPREG(VENC_HS_EXT_START_STOP_X); | |
786 | DUMPREG(VENC_VS_INT_START_X); | |
787 | DUMPREG(VENC_VS_INT_STOP_X__VS_INT_START_Y); | |
788 | DUMPREG(VENC_VS_INT_STOP_Y__VS_EXT_START_X); | |
789 | DUMPREG(VENC_VS_EXT_STOP_X__VS_EXT_START_Y); | |
790 | DUMPREG(VENC_VS_EXT_STOP_Y); | |
791 | DUMPREG(VENC_AVID_START_STOP_X); | |
792 | DUMPREG(VENC_AVID_START_STOP_Y); | |
793 | DUMPREG(VENC_FID_INT_START_X__FID_INT_START_Y); | |
794 | DUMPREG(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X); | |
795 | DUMPREG(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y); | |
796 | DUMPREG(VENC_TVDETGP_INT_START_STOP_X); | |
797 | DUMPREG(VENC_TVDETGP_INT_START_STOP_Y); | |
798 | DUMPREG(VENC_GEN_CTRL); | |
799 | DUMPREG(VENC_OUTPUT_CONTROL); | |
800 | DUMPREG(VENC_OUTPUT_TEST); | |
801 | ||
802 | venc_enable_clocks(0); | |
803 | ||
804 | #undef DUMPREG | |
805 | } |