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Merge branch 'x86-debug-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / drivers / video / omap2 / dss / venc.c
CommitLineData
b2886273
TV		 1/*
2 * linux/drivers/video/omap2/dss/venc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * VENC settings from TI's DSS driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#define DSS_SUBSYS_NAME "VENC"
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/clk.h>
27#include <linux/err.h>
28#include <linux/io.h>
29#include <linux/mutex.h>
30#include <linux/completion.h>
31#include <linux/delay.h>
32#include <linux/string.h>
33#include <linux/seq_file.h>
34#include <linux/platform_device.h>
35#include <linux/regulator/consumer.h>
4fbafaf3 36#include <linux/pm_runtime.h>
b2886273 37
a0b38cc4 38#include <video/omapdss.h>
b2886273
TV		 39#include <plat/cpu.h>
40
41#include "dss.h"
525dae61 42#include "dss_features.h"
b2886273 43
b2886273
TV		 44/* Venc registers */
45#define VENC_REV_ID 0x00
46#define VENC_STATUS 0x04
47#define VENC_F_CONTROL 0x08
48#define VENC_VIDOUT_CTRL 0x10
49#define VENC_SYNC_CTRL 0x14
50#define VENC_LLEN 0x1C
51#define VENC_FLENS 0x20
52#define VENC_HFLTR_CTRL 0x24
53#define VENC_CC_CARR_WSS_CARR 0x28
54#define VENC_C_PHASE 0x2C
55#define VENC_GAIN_U 0x30
56#define VENC_GAIN_V 0x34
57#define VENC_GAIN_Y 0x38
58#define VENC_BLACK_LEVEL 0x3C
59#define VENC_BLANK_LEVEL 0x40
60#define VENC_X_COLOR 0x44
61#define VENC_M_CONTROL 0x48
62#define VENC_BSTAMP_WSS_DATA 0x4C
63#define VENC_S_CARR 0x50
64#define VENC_LINE21 0x54
65#define VENC_LN_SEL 0x58
66#define VENC_L21__WC_CTL 0x5C
67#define VENC_HTRIGGER_VTRIGGER 0x60
68#define VENC_SAVID__EAVID 0x64
69#define VENC_FLEN__FAL 0x68
70#define VENC_LAL__PHASE_RESET 0x6C
71#define VENC_HS_INT_START_STOP_X 0x70
72#define VENC_HS_EXT_START_STOP_X 0x74
73#define VENC_VS_INT_START_X 0x78
74#define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C
75#define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80
76#define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84
77#define VENC_VS_EXT_STOP_Y 0x88
78#define VENC_AVID_START_STOP_X 0x90
79#define VENC_AVID_START_STOP_Y 0x94
80#define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0
81#define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4
82#define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8
83#define VENC_TVDETGP_INT_START_STOP_X 0xB0
84#define VENC_TVDETGP_INT_START_STOP_Y 0xB4
85#define VENC_GEN_CTRL 0xB8
86#define VENC_OUTPUT_CONTROL 0xC4
87#define VENC_OUTPUT_TEST 0xC8
88#define VENC_DAC_B__DAC_C 0xC8
89
90struct venc_config {
91 u32 f_control;
92 u32 vidout_ctrl;
93 u32 sync_ctrl;
94 u32 llen;
95 u32 flens;
96 u32 hfltr_ctrl;
97 u32 cc_carr_wss_carr;
98 u32 c_phase;
99 u32 gain_u;
100 u32 gain_v;
101 u32 gain_y;
102 u32 black_level;
103 u32 blank_level;
104 u32 x_color;
105 u32 m_control;
106 u32 bstamp_wss_data;
107 u32 s_carr;
108 u32 line21;
109 u32 ln_sel;
110 u32 l21__wc_ctl;
111 u32 htrigger_vtrigger;
112 u32 savid__eavid;
113 u32 flen__fal;
114 u32 lal__phase_reset;
115 u32 hs_int_start_stop_x;
116 u32 hs_ext_start_stop_x;
117 u32 vs_int_start_x;
118 u32 vs_int_stop_x__vs_int_start_y;
119 u32 vs_int_stop_y__vs_ext_start_x;
120 u32 vs_ext_stop_x__vs_ext_start_y;
121 u32 vs_ext_stop_y;
122 u32 avid_start_stop_x;
123 u32 avid_start_stop_y;
124 u32 fid_int_start_x__fid_int_start_y;
125 u32 fid_int_offset_y__fid_ext_start_x;
126 u32 fid_ext_start_y__fid_ext_offset_y;
127 u32 tvdetgp_int_start_stop_x;
128 u32 tvdetgp_int_start_stop_y;
129 u32 gen_ctrl;
130};
131
132/* from TRM */
133static const struct venc_config venc_config_pal_trm = {
134 .f_control = 0,
135 .vidout_ctrl = 1,
136 .sync_ctrl = 0x40,
137 .llen = 0x35F, /* 863 */
138 .flens = 0x270, /* 624 */
139 .hfltr_ctrl = 0,
140 .cc_carr_wss_carr = 0x2F7225ED,
141 .c_phase = 0,
142 .gain_u = 0x111,
143 .gain_v = 0x181,
144 .gain_y = 0x140,
145 .black_level = 0x3B,
146 .blank_level = 0x3B,
147 .x_color = 0x7,
148 .m_control = 0x2,
149 .bstamp_wss_data = 0x3F,
150 .s_carr = 0x2A098ACB,
151 .line21 = 0,
152 .ln_sel = 0x01290015,
153 .l21__wc_ctl = 0x0000F603,
154 .htrigger_vtrigger = 0,
155
156 .savid__eavid = 0x06A70108,
157 .flen__fal = 0x00180270,
158 .lal__phase_reset = 0x00040135,
159 .hs_int_start_stop_x = 0x00880358,
160 .hs_ext_start_stop_x = 0x000F035F,
161 .vs_int_start_x = 0x01A70000,
162 .vs_int_stop_x__vs_int_start_y = 0x000001A7,
163 .vs_int_stop_y__vs_ext_start_x = 0x01AF0000,
164 .vs_ext_stop_x__vs_ext_start_y = 0x000101AF,
165 .vs_ext_stop_y = 0x00000025,
166 .avid_start_stop_x = 0x03530083,
167 .avid_start_stop_y = 0x026C002E,
168 .fid_int_start_x__fid_int_start_y = 0x0001008A,
169 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
170 .fid_ext_start_y__fid_ext_offset_y = 0x01380001,
171
172 .tvdetgp_int_start_stop_x = 0x00140001,
173 .tvdetgp_int_start_stop_y = 0x00010001,
174 .gen_ctrl = 0x00FF0000,
175};
176
177/* from TRM */
178static const struct venc_config venc_config_ntsc_trm = {
179 .f_control = 0,
180 .vidout_ctrl = 1,
181 .sync_ctrl = 0x8040,
182 .llen = 0x359,
183 .flens = 0x20C,
184 .hfltr_ctrl = 0,
185 .cc_carr_wss_carr = 0x043F2631,
186 .c_phase = 0,
187 .gain_u = 0x102,
188 .gain_v = 0x16C,
189 .gain_y = 0x12F,
190 .black_level = 0x43,
191 .blank_level = 0x38,
192 .x_color = 0x7,
193 .m_control = 0x1,
194 .bstamp_wss_data = 0x38,
195 .s_carr = 0x21F07C1F,
196 .line21 = 0,
197 .ln_sel = 0x01310011,
198 .l21__wc_ctl = 0x0000F003,
199 .htrigger_vtrigger = 0,
200
201 .savid__eavid = 0x069300F4,
202 .flen__fal = 0x0016020C,
203 .lal__phase_reset = 0x00060107,
204 .hs_int_start_stop_x = 0x008E0350,
205 .hs_ext_start_stop_x = 0x000F0359,
206 .vs_int_start_x = 0x01A00000,
207 .vs_int_stop_x__vs_int_start_y = 0x020701A0,
208 .vs_int_stop_y__vs_ext_start_x = 0x01AC0024,
209 .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,
210 .vs_ext_stop_y = 0x00000006,
211 .avid_start_stop_x = 0x03480078,
212 .avid_start_stop_y = 0x02060024,
213 .fid_int_start_x__fid_int_start_y = 0x0001008A,
214 .fid_int_offset_y__fid_ext_start_x = 0x01AC0106,
215 .fid_ext_start_y__fid_ext_offset_y = 0x01060006,
216
217 .tvdetgp_int_start_stop_x = 0x00140001,
218 .tvdetgp_int_start_stop_y = 0x00010001,
219 .gen_ctrl = 0x00F90000,
220};
221
222static const struct venc_config venc_config_pal_bdghi = {
223 .f_control = 0,
224 .vidout_ctrl = 0,
225 .sync_ctrl = 0,
226 .hfltr_ctrl = 0,
227 .x_color = 0,
228 .line21 = 0,
229 .ln_sel = 21,
230 .htrigger_vtrigger = 0,
231 .tvdetgp_int_start_stop_x = 0x00140001,
232 .tvdetgp_int_start_stop_y = 0x00010001,
233 .gen_ctrl = 0x00FB0000,
234
235 .llen = 864-1,
236 .flens = 625-1,
237 .cc_carr_wss_carr = 0x2F7625ED,
238 .c_phase = 0xDF,
239 .gain_u = 0x111,
240 .gain_v = 0x181,
241 .gain_y = 0x140,
242 .black_level = 0x3e,
243 .blank_level = 0x3e,
244 .m_control = 0<<2 | 1<<1,
245 .bstamp_wss_data = 0x42,
246 .s_carr = 0x2a098acb,
247 .l21__wc_ctl = 0<<13 | 0x16<<8 | 0<<0,
248 .savid__eavid = 0x06A70108,
249 .flen__fal = 23<<16 | 624<<0,
250 .lal__phase_reset = 2<<17 | 310<<0,
251 .hs_int_start_stop_x = 0x00920358,
252 .hs_ext_start_stop_x = 0x000F035F,
253 .vs_int_start_x = 0x1a7<<16,
254 .vs_int_stop_x__vs_int_start_y = 0x000601A7,
255 .vs_int_stop_y__vs_ext_start_x = 0x01AF0036,
256 .vs_ext_stop_x__vs_ext_start_y = 0x27101af,
257 .vs_ext_stop_y = 0x05,
258 .avid_start_stop_x = 0x03530082,
259 .avid_start_stop_y = 0x0270002E,
260 .fid_int_start_x__fid_int_start_y = 0x0005008A,
261 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
262 .fid_ext_start_y__fid_ext_offset_y = 0x01380005,
263};
264
265const struct omap_video_timings omap_dss_pal_timings = {
266 .x_res = 720,
267 .y_res = 574,
268 .pixel_clock = 13500,
269 .hsw = 64,
270 .hfp = 12,
271 .hbp = 68,
272 .vsw = 5,
273 .vfp = 5,
274 .vbp = 41,
275};
276EXPORT_SYMBOL(omap_dss_pal_timings);
277
278const struct omap_video_timings omap_dss_ntsc_timings = {
279 .x_res = 720,
280 .y_res = 482,
281 .pixel_clock = 13500,
282 .hsw = 64,
283 .hfp = 16,
284 .hbp = 58,
285 .vsw = 6,
286 .vfp = 6,
287 .vbp = 31,
288};
289EXPORT_SYMBOL(omap_dss_ntsc_timings);
290
291static struct {
30ea50c9 292 struct platform_device *pdev;
b2886273
TV		 293 void __iomem *base;
294 struct mutex venc_lock;
295 u32 wss_data;
296 struct regulator *vdda_dac_reg;
4fbafaf3 297
4fbafaf3 298 struct clk *tv_dac_clk;
b2886273
TV		 299} venc;
300
301static inline void venc_write_reg(int idx, u32 val)
302{
303 __raw_writel(val, venc.base + idx);
304}
305
306static inline u32 venc_read_reg(int idx)
307{
308 u32 l = __raw_readl(venc.base + idx);
309 return l;
310}
311
312static void venc_write_config(const struct venc_config *config)
313{
314 DSSDBG("write venc conf\n");
315
316 venc_write_reg(VENC_LLEN, config->llen);
317 venc_write_reg(VENC_FLENS, config->flens);
318 venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
319 venc_write_reg(VENC_C_PHASE, config->c_phase);
320 venc_write_reg(VENC_GAIN_U, config->gain_u);
321 venc_write_reg(VENC_GAIN_V, config->gain_v);
322 venc_write_reg(VENC_GAIN_Y, config->gain_y);
323 venc_write_reg(VENC_BLACK_LEVEL, config->black_level);
324 venc_write_reg(VENC_BLANK_LEVEL, config->blank_level);
325 venc_write_reg(VENC_M_CONTROL, config->m_control);
326 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
327 venc.wss_data);
328 venc_write_reg(VENC_S_CARR, config->s_carr);
329 venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl);
330 venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid);
331 venc_write_reg(VENC_FLEN__FAL, config->flen__fal);
332 venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset);
333 venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x);
334 venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x);
335 venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x);
336 venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y,
337 config->vs_int_stop_x__vs_int_start_y);
338 venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X,
339 config->vs_int_stop_y__vs_ext_start_x);
340 venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
341 config->vs_ext_stop_x__vs_ext_start_y);
342 venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
343 venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x);
344 venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
345 venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y,
346 config->fid_int_start_x__fid_int_start_y);
347 venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
348 config->fid_int_offset_y__fid_ext_start_x);
349 venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
350 config->fid_ext_start_y__fid_ext_offset_y);
351
352 venc_write_reg(VENC_DAC_B__DAC_C, venc_read_reg(VENC_DAC_B__DAC_C));
353 venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl);
354 venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl);
355 venc_write_reg(VENC_X_COLOR, config->x_color);
356 venc_write_reg(VENC_LINE21, config->line21);
357 venc_write_reg(VENC_LN_SEL, config->ln_sel);
358 venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
359 venc_write_reg(VENC_TVDETGP_INT_START_STOP_X,
360 config->tvdetgp_int_start_stop_x);
361 venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y,
362 config->tvdetgp_int_start_stop_y);
363 venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl);
364 venc_write_reg(VENC_F_CONTROL, config->f_control);
365 venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl);
366}
367
368static void venc_reset(void)
369{
370 int t = 1000;
371
372 venc_write_reg(VENC_F_CONTROL, 1<<8);
373 while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) {
374 if (--t == 0) {
375 DSSERR("Failed to reset venc\n");
376 return;
377 }
378 }
379
c6f65e1a 380#ifdef CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET
b2886273 381 /* the magical sleep that makes things work */
c6f65e1a 382 /* XXX more info? What bug this circumvents? */
b2886273 383 msleep(20);
c6f65e1a 384#endif
b2886273
TV		 385}
386
4fbafaf3 387static int venc_runtime_get(void)
b2886273 388{
4fbafaf3
TV		 389 int r;
390
391 DSSDBG("venc_runtime_get\n");
392
393 r = pm_runtime_get_sync(&venc.pdev->dev);
394 WARN_ON(r < 0);
395 return r < 0 ? r : 0;
396}
397
398static void venc_runtime_put(void)
399{
400 int r;
401
402 DSSDBG("venc_runtime_put\n");
403
0eaf9f52 404 r = pm_runtime_put_sync(&venc.pdev->dev);
373b4365 405 WARN_ON(r < 0 && r != -ENOSYS);
b2886273
TV		 406}
407
408static const struct venc_config *venc_timings_to_config(
409 struct omap_video_timings *timings)
410{
411 if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
412 return &venc_config_pal_trm;
413
414 if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
415 return &venc_config_ntsc_trm;
416
417 BUG();
c6eee968 418 return NULL;
b2886273
TV		 419}
420
33ca237f 421static int venc_power_on(struct omap_dss_device *dssdev)
37ac60e4
TV		 422{
423 u32 l;
33ca237f 424 int r;
37ac60e4 425
37ac60e4
TV		 426 venc_reset();
427 venc_write_config(venc_timings_to_config(&dssdev->panel.timings));
428
429 dss_set_venc_output(dssdev->phy.venc.type);
430 dss_set_dac_pwrdn_bgz(1);
431
432 l = 0;
433
434 if (dssdev->phy.venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE)
435 l |= 1 << 1;
436 else /* S-Video */
437 l |= (1 << 0) | (1 << 2);
438
439 if (dssdev->phy.venc.invert_polarity == false)
440 l |= 1 << 3;
441
442 venc_write_reg(VENC_OUTPUT_CONTROL, l);
443
2aefad49 444 dss_mgr_set_timings(dssdev->manager, &dssdev->panel.timings);
37ac60e4 445
ec874107
MB		 446 r = regulator_enable(venc.vdda_dac_reg);
447 if (r)
448 goto err;
37ac60e4
TV		 449
450 if (dssdev->platform_enable)
451 dssdev->platform_enable(dssdev);
452
33ca237f
TV		 453 r = dss_mgr_enable(dssdev->manager);
454 if (r)
455 goto err;
456
457 return 0;
458
459err:
460 venc_write_reg(VENC_OUTPUT_CONTROL, 0);
461 dss_set_dac_pwrdn_bgz(0);
462
463 if (dssdev->platform_disable)
464 dssdev->platform_disable(dssdev);
465
466 regulator_disable(venc.vdda_dac_reg);
467
468 return r;
37ac60e4
TV		 469}
470
471static void venc_power_off(struct omap_dss_device *dssdev)
472{
473 venc_write_reg(VENC_OUTPUT_CONTROL, 0);
474 dss_set_dac_pwrdn_bgz(0);
475
7797c6da 476 dss_mgr_disable(dssdev->manager);
37ac60e4
TV		 477
478 if (dssdev->platform_disable)
479 dssdev->platform_disable(dssdev);
480
481 regulator_disable(venc.vdda_dac_reg);
37ac60e4
TV		 482}
483
c3dc6a7a
AT		 484unsigned long venc_get_pixel_clock(void)
485{
486 /* VENC Pixel Clock in Mhz */
487 return 13500000;
488}
b2886273 489
0aca3c63
GI		 490static ssize_t display_output_type_show(struct device *dev,
491 struct device_attribute *attr, char *buf)
492{
493 struct omap_dss_device *dssdev = to_dss_device(dev);
494 const char *ret;
495
496 switch (dssdev->phy.venc.type) {
497 case OMAP_DSS_VENC_TYPE_COMPOSITE:
498 ret = "composite";
499 break;
500 case OMAP_DSS_VENC_TYPE_SVIDEO:
501 ret = "svideo";
502 break;
503 default:
504 return -EINVAL;
505 }
506
507 return snprintf(buf, PAGE_SIZE, "%s\n", ret);
508}
509
510static ssize_t display_output_type_store(struct device *dev,
511 struct device_attribute *attr, const char *buf, size_t size)
512{
513 struct omap_dss_device *dssdev = to_dss_device(dev);
514 enum omap_dss_venc_type new_type;
515
516 if (sysfs_streq("composite", buf))
517 new_type = OMAP_DSS_VENC_TYPE_COMPOSITE;
518 else if (sysfs_streq("svideo", buf))
519 new_type = OMAP_DSS_VENC_TYPE_SVIDEO;
520 else
521 return -EINVAL;
522
523 mutex_lock(&venc.venc_lock);
524
525 if (dssdev->phy.venc.type != new_type) {
526 dssdev->phy.venc.type = new_type;
527 if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
528 venc_power_off(dssdev);
529 venc_power_on(dssdev);
530 }
531 }
532
533 mutex_unlock(&venc.venc_lock);
534
535 return size;
536}
537
538static DEVICE_ATTR(output_type, S_IRUGO | S_IWUSR,
539 display_output_type_show, display_output_type_store);
540
b2886273
TV		 541/* driver */
542static int venc_panel_probe(struct omap_dss_device *dssdev)
543{
544 dssdev->panel.timings = omap_dss_pal_timings;
545
0aca3c63 546 return device_create_file(&dssdev->dev, &dev_attr_output_type);
b2886273
TV		 547}
548
549static void venc_panel_remove(struct omap_dss_device *dssdev)
550{
0aca3c63 551 device_remove_file(&dssdev->dev, &dev_attr_output_type);
b2886273
TV		 552}
553
554static int venc_panel_enable(struct omap_dss_device *dssdev)
555{
556 int r = 0;
557
37ac60e4
TV		 558 DSSDBG("venc_enable_display\n");
559
560 mutex_lock(&venc.venc_lock);
561
14572c63
TV		 562 r = omap_dss_start_device(dssdev);
563 if (r) {
564 DSSERR("failed to start device\n");
565 goto err0;
566 }
567
37ac60e4
TV		 568 if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) {
569 r = -EINVAL;
570 goto err1;
571 }
572
4fbafaf3
TV		 573 r = venc_runtime_get();
574 if (r)
575 goto err1;
576
33ca237f
TV		 577 r = venc_power_on(dssdev);
578 if (r)
579 goto err2;
37ac60e4
TV		 580
581 venc.wss_data = 0;
582
583 dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
584
14572c63
TV		 585 mutex_unlock(&venc.venc_lock);
586 return 0;
33ca237f
TV		 587err2:
588 venc_runtime_put();
37ac60e4 589err1:
14572c63
TV		 590 omap_dss_stop_device(dssdev);
591err0:
37ac60e4 592 mutex_unlock(&venc.venc_lock);
35bc42c5 593
b2886273
TV		 594 return r;
595}
596
597static void venc_panel_disable(struct omap_dss_device *dssdev)
598{
37ac60e4 599 DSSDBG("venc_disable_display\n");
b2886273 600
37ac60e4
TV		 601 mutex_lock(&venc.venc_lock);
602
603 if (dssdev->state == OMAP_DSS_DISPLAY_DISABLED)
604 goto end;
b2886273 605
37ac60e4
TV		 606 if (dssdev->state == OMAP_DSS_DISPLAY_SUSPENDED) {
607 /* suspended is the same as disabled with venc */
608 dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
609 goto end;
610 }
611
612 venc_power_off(dssdev);
613
4fbafaf3
TV		 614 venc_runtime_put();
615
37ac60e4 616 dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
14572c63
TV		 617
618 omap_dss_stop_device(dssdev);
37ac60e4
TV		 619end:
620 mutex_unlock(&venc.venc_lock);
b2886273
TV		 621}
622
623static int venc_panel_suspend(struct omap_dss_device *dssdev)
624{
625 venc_panel_disable(dssdev);
626 return 0;
627}
628
629static int venc_panel_resume(struct omap_dss_device *dssdev)
630{
631 return venc_panel_enable(dssdev);
632}
633
69b2048f
TV		 634static void venc_set_timings(struct omap_dss_device *dssdev,
635 struct omap_video_timings *timings)
636{
637 DSSDBG("venc_set_timings\n");
638
639 /* Reset WSS data when the TV standard changes. */
640 if (memcmp(&dssdev->panel.timings, timings, sizeof(*timings)))
641 venc.wss_data = 0;
642
643 dssdev->panel.timings = *timings;
644 if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
645 /* turn the venc off and on to get new timings to use */
646 venc_panel_disable(dssdev);
647 venc_panel_enable(dssdev);
c808ab9c
AT		 648 } else {
649 dss_mgr_set_timings(dssdev->manager, timings);
69b2048f
TV		 650 }
651}
652
653static int venc_check_timings(struct omap_dss_device *dssdev,
654 struct omap_video_timings *timings)
655{
656 DSSDBG("venc_check_timings\n");
657
658 if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
659 return 0;
660
661 if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
662 return 0;
663
664 return -EINVAL;
665}
666
36511312
TV		 667static u32 venc_get_wss(struct omap_dss_device *dssdev)
668{
669 /* Invert due to VENC_L21_WC_CTL:INV=1 */
670 return (venc.wss_data >> 8) ^ 0xfffff;
671}
672
673static int venc_set_wss(struct omap_dss_device *dssdev, u32 wss)
674{
675 const struct venc_config *config;
4fbafaf3 676 int r;
36511312
TV		 677
678 DSSDBG("venc_set_wss\n");
679
680 mutex_lock(&venc.venc_lock);
681
682 config = venc_timings_to_config(&dssdev->panel.timings);
683
684 /* Invert due to VENC_L21_WC_CTL:INV=1 */
685 venc.wss_data = (wss ^ 0xfffff) << 8;
686
4fbafaf3
TV		 687 r = venc_runtime_get();
688 if (r)
689 goto err;
36511312
TV		 690
691 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
692 venc.wss_data);
693
4fbafaf3 694 venc_runtime_put();
36511312 695
4fbafaf3 696err:
36511312
TV		 697 mutex_unlock(&venc.venc_lock);
698
4fbafaf3 699 return r;
36511312
TV		 700}
701
b2886273
TV		 702static struct omap_dss_driver venc_driver = {
703 .probe = venc_panel_probe,
704 .remove = venc_panel_remove,
705
706 .enable = venc_panel_enable,
707 .disable = venc_panel_disable,
708 .suspend = venc_panel_suspend,
709 .resume = venc_panel_resume,
710
96adcece 711 .get_resolution = omapdss_default_get_resolution,
a2699504 712 .get_recommended_bpp = omapdss_default_get_recommended_bpp,
96adcece 713
69b2048f
TV		 714 .set_timings = venc_set_timings,
715 .check_timings = venc_check_timings,
716
36511312
TV		 717 .get_wss = venc_get_wss,
718 .set_wss = venc_set_wss,
719
b2886273
TV		 720 .driver = {
721 .name = "venc",
722 .owner = THIS_MODULE,
723 },
724};
725/* driver end */
726
9d8232a7 727static int __init venc_init_display(struct omap_dss_device *dssdev)
b2886273
TV		 728{
729 DSSDBG("init_display\n");
730
5f42f2ce
TV		 731 if (venc.vdda_dac_reg == NULL) {
732 struct regulator *vdda_dac;
733
734 vdda_dac = regulator_get(&venc.pdev->dev, "vdda_dac");
735
736 if (IS_ERR(vdda_dac)) {
737 DSSERR("can't get VDDA_DAC regulator\n");
738 return PTR_ERR(vdda_dac);
739 }
740
741 venc.vdda_dac_reg = vdda_dac;
742 }
743
b2886273
TV		 744 return 0;
745}
746
e40402cf 747static void venc_dump_regs(struct seq_file *s)
b2886273
TV		 748{
749#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r))
750
cc1d3e03
DK		 751 if (cpu_is_omap44xx()) {
752 seq_printf(s, "VENC currently disabled on OMAP44xx\n");
753 return;
754 }
755
4fbafaf3
TV		 756 if (venc_runtime_get())
757 return;
b2886273
TV		 758
759 DUMPREG(VENC_F_CONTROL);
760 DUMPREG(VENC_VIDOUT_CTRL);
761 DUMPREG(VENC_SYNC_CTRL);
762 DUMPREG(VENC_LLEN);
763 DUMPREG(VENC_FLENS);
764 DUMPREG(VENC_HFLTR_CTRL);
765 DUMPREG(VENC_CC_CARR_WSS_CARR);
766 DUMPREG(VENC_C_PHASE);
767 DUMPREG(VENC_GAIN_U);
768 DUMPREG(VENC_GAIN_V);
769 DUMPREG(VENC_GAIN_Y);
770 DUMPREG(VENC_BLACK_LEVEL);
771 DUMPREG(VENC_BLANK_LEVEL);
772 DUMPREG(VENC_X_COLOR);
773 DUMPREG(VENC_M_CONTROL);
774 DUMPREG(VENC_BSTAMP_WSS_DATA);
775 DUMPREG(VENC_S_CARR);
776 DUMPREG(VENC_LINE21);
777 DUMPREG(VENC_LN_SEL);
778 DUMPREG(VENC_L21__WC_CTL);
779 DUMPREG(VENC_HTRIGGER_VTRIGGER);
780 DUMPREG(VENC_SAVID__EAVID);
781 DUMPREG(VENC_FLEN__FAL);
782 DUMPREG(VENC_LAL__PHASE_RESET);
783 DUMPREG(VENC_HS_INT_START_STOP_X);
784 DUMPREG(VENC_HS_EXT_START_STOP_X);
785 DUMPREG(VENC_VS_INT_START_X);
786 DUMPREG(VENC_VS_INT_STOP_X__VS_INT_START_Y);
787 DUMPREG(VENC_VS_INT_STOP_Y__VS_EXT_START_X);
788 DUMPREG(VENC_VS_EXT_STOP_X__VS_EXT_START_Y);
789 DUMPREG(VENC_VS_EXT_STOP_Y);
790 DUMPREG(VENC_AVID_START_STOP_X);
791 DUMPREG(VENC_AVID_START_STOP_Y);
792 DUMPREG(VENC_FID_INT_START_X__FID_INT_START_Y);
793 DUMPREG(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X);
794 DUMPREG(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y);
795 DUMPREG(VENC_TVDETGP_INT_START_STOP_X);
796 DUMPREG(VENC_TVDETGP_INT_START_STOP_Y);
797 DUMPREG(VENC_GEN_CTRL);
798 DUMPREG(VENC_OUTPUT_CONTROL);
799 DUMPREG(VENC_OUTPUT_TEST);
800
4fbafaf3 801 venc_runtime_put();
b2886273
TV		 802
803#undef DUMPREG
804}
30ea50c9 805
4fbafaf3
TV		 806static int venc_get_clocks(struct platform_device *pdev)
807{
808 struct clk *clk;
809
4fbafaf3 810 if (dss_has_feature(FEAT_VENC_REQUIRES_TV_DAC_CLK)) {
bfe4f8d3 811 clk = clk_get(&pdev->dev, "tv_dac_clk");
4fbafaf3
TV		 812 if (IS_ERR(clk)) {
813 DSSERR("can't get tv_dac_clk\n");
4fbafaf3
TV		 814 return PTR_ERR(clk);
815 }
816 } else {
817 clk = NULL;
818 }
819
820 venc.tv_dac_clk = clk;
821
822 return 0;
823}
824
825static void venc_put_clocks(void)
826{
4fbafaf3
TV		 827 if (venc.tv_dac_clk)
828 clk_put(venc.tv_dac_clk);
829}
830
38f3daf6
TV		 831static void __init venc_probe_pdata(struct platform_device *pdev)
832{
833 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
834 int r, i;
835
836 for (i = 0; i < pdata->num_devices; ++i) {
837 struct omap_dss_device *dssdev = pdata->devices[i];
838
839 if (dssdev->type != OMAP_DISPLAY_TYPE_VENC)
840 continue;
841
842 r = venc_init_display(dssdev);
843 if (r) {
844 DSSERR("device %s init failed: %d\n", dssdev->name, r);
845 continue;
846 }
847
848 r = omap_dss_register_device(dssdev, &pdev->dev, i);
849 if (r)
850 DSSERR("device %s register failed: %d\n",
851 dssdev->name, r);
852 }
853}
854
30ea50c9 855/* VENC HW IP initialisation */
6e7e8f06 856static int __init omap_venchw_probe(struct platform_device *pdev)
30ea50c9
SG		 857{
858 u8 rev_id;
ea9da36a 859 struct resource *venc_mem;
38f3daf6 860 int r;
ea9da36a 861
30ea50c9
SG		 862 venc.pdev = pdev;
863
864 mutex_init(&venc.venc_lock);
865
866 venc.wss_data = 0;
867
ea9da36a
SG		 868 venc_mem = platform_get_resource(venc.pdev, IORESOURCE_MEM, 0);
869 if (!venc_mem) {
870 DSSERR("can't get IORESOURCE_MEM VENC\n");
cd3b3449 871 return -EINVAL;
ea9da36a 872 }
cd3b3449 873
6e2a14d2
JL		 874 venc.base = devm_ioremap(&pdev->dev, venc_mem->start,
875 resource_size(venc_mem));
30ea50c9
SG		 876 if (!venc.base) {
877 DSSERR("can't ioremap VENC\n");
cd3b3449 878 return -ENOMEM;
30ea50c9
SG		 879 }
880
4fbafaf3
TV		 881 r = venc_get_clocks(pdev);
882 if (r)
cd3b3449 883 return r;
4fbafaf3
TV		 884
885 pm_runtime_enable(&pdev->dev);
886
887 r = venc_runtime_get();
888 if (r)
cd3b3449 889 goto err_runtime_get;
30ea50c9
SG		 890
891 rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff);
a06b62f8 892 dev_dbg(&pdev->dev, "OMAP VENC rev %d\n", rev_id);
30ea50c9 893
4fbafaf3 894 venc_runtime_put();
30ea50c9 895
cd3b3449
TV		 896 r = omap_dss_register_driver(&venc_driver);
897 if (r)
898 goto err_reg_panel_driver;
899
e40402cf
TV		 900 dss_debugfs_create_file("venc", venc_dump_regs);
901
38f3daf6 902 venc_probe_pdata(pdev);
35deca3d 903
cd3b3449 904 return 0;
4fbafaf3 905
cd3b3449
TV		 906err_reg_panel_driver:
907err_runtime_get:
4fbafaf3
TV		 908 pm_runtime_disable(&pdev->dev);
909 venc_put_clocks();
4fbafaf3 910 return r;
30ea50c9
SG		 911}
912
6e7e8f06 913static int __exit omap_venchw_remove(struct platform_device *pdev)
30ea50c9 914{
35deca3d
TV		 915 omap_dss_unregister_child_devices(&pdev->dev);
916
30ea50c9
SG		 917 if (venc.vdda_dac_reg != NULL) {
918 regulator_put(venc.vdda_dac_reg);
919 venc.vdda_dac_reg = NULL;
920 }
35deca3d 921
30ea50c9
SG		 922 omap_dss_unregister_driver(&venc_driver);
923
4fbafaf3
TV		 924 pm_runtime_disable(&pdev->dev);
925 venc_put_clocks();
926
30ea50c9
SG		 927 return 0;
928}
929
4fbafaf3
TV		 930static int venc_runtime_suspend(struct device *dev)
931{
932 if (venc.tv_dac_clk)
933 clk_disable(venc.tv_dac_clk);
4fbafaf3
TV		 934
935 dispc_runtime_put();
4fbafaf3
TV		 936
937 return 0;
938}
939
940static int venc_runtime_resume(struct device *dev)
941{
942 int r;
943
4fbafaf3
TV		 944 r = dispc_runtime_get();
945 if (r < 0)
852f0838 946 return r;
4fbafaf3 947
4fbafaf3
TV		 948 if (venc.tv_dac_clk)
949 clk_enable(venc.tv_dac_clk);
950
951 return 0;
4fbafaf3
TV		 952}
953
954static const struct dev_pm_ops venc_pm_ops = {
955 .runtime_suspend = venc_runtime_suspend,
956 .runtime_resume = venc_runtime_resume,
957};
958
30ea50c9 959static struct platform_driver omap_venchw_driver = {
6e7e8f06 960 .remove = __exit_p(omap_venchw_remove),
30ea50c9
SG		 961 .driver = {
962 .name = "omapdss_venc",
963 .owner = THIS_MODULE,
4fbafaf3 964 .pm = &venc_pm_ops,
30ea50c9
SG		 965 },
966};
967
6e7e8f06 968int __init venc_init_platform_driver(void)
30ea50c9 969{
ba02fa37
TV		 970 if (cpu_is_omap44xx())
971 return 0;
972
61055d4b 973 return platform_driver_probe(&omap_venchw_driver, omap_venchw_probe);
30ea50c9
SG		 974}
975
6e7e8f06 976void __exit venc_uninit_platform_driver(void)
30ea50c9 977{
ba02fa37
TV		 978 if (cpu_is_omap44xx())
979 return;
980
04c742c3 981 platform_driver_unregister(&omap_venchw_driver);
30ea50c9 982}
Linux kernel - Deliverables
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