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b2886273 TV |
1 | /* |
2 | * linux/drivers/video/omap2/dss/venc.c | |
3 | * | |
4 | * Copyright (C) 2009 Nokia Corporation | |
5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> | |
6 | * | |
7 | * VENC settings from TI's DSS driver | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License version 2 as published by | |
11 | * the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along with | |
19 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #define DSS_SUBSYS_NAME "VENC" | |
23 | ||
24 | #include <linux/kernel.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/clk.h> | |
27 | #include <linux/err.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/mutex.h> | |
30 | #include <linux/completion.h> | |
31 | #include <linux/delay.h> | |
32 | #include <linux/string.h> | |
33 | #include <linux/seq_file.h> | |
34 | #include <linux/platform_device.h> | |
35 | #include <linux/regulator/consumer.h> | |
4fbafaf3 | 36 | #include <linux/pm_runtime.h> |
b2886273 | 37 | |
a0b38cc4 | 38 | #include <video/omapdss.h> |
b2886273 TV |
39 | #include <plat/cpu.h> |
40 | ||
41 | #include "dss.h" | |
525dae61 | 42 | #include "dss_features.h" |
b2886273 | 43 | |
b2886273 TV |
44 | /* Venc registers */ |
45 | #define VENC_REV_ID 0x00 | |
46 | #define VENC_STATUS 0x04 | |
47 | #define VENC_F_CONTROL 0x08 | |
48 | #define VENC_VIDOUT_CTRL 0x10 | |
49 | #define VENC_SYNC_CTRL 0x14 | |
50 | #define VENC_LLEN 0x1C | |
51 | #define VENC_FLENS 0x20 | |
52 | #define VENC_HFLTR_CTRL 0x24 | |
53 | #define VENC_CC_CARR_WSS_CARR 0x28 | |
54 | #define VENC_C_PHASE 0x2C | |
55 | #define VENC_GAIN_U 0x30 | |
56 | #define VENC_GAIN_V 0x34 | |
57 | #define VENC_GAIN_Y 0x38 | |
58 | #define VENC_BLACK_LEVEL 0x3C | |
59 | #define VENC_BLANK_LEVEL 0x40 | |
60 | #define VENC_X_COLOR 0x44 | |
61 | #define VENC_M_CONTROL 0x48 | |
62 | #define VENC_BSTAMP_WSS_DATA 0x4C | |
63 | #define VENC_S_CARR 0x50 | |
64 | #define VENC_LINE21 0x54 | |
65 | #define VENC_LN_SEL 0x58 | |
66 | #define VENC_L21__WC_CTL 0x5C | |
67 | #define VENC_HTRIGGER_VTRIGGER 0x60 | |
68 | #define VENC_SAVID__EAVID 0x64 | |
69 | #define VENC_FLEN__FAL 0x68 | |
70 | #define VENC_LAL__PHASE_RESET 0x6C | |
71 | #define VENC_HS_INT_START_STOP_X 0x70 | |
72 | #define VENC_HS_EXT_START_STOP_X 0x74 | |
73 | #define VENC_VS_INT_START_X 0x78 | |
74 | #define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C | |
75 | #define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80 | |
76 | #define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84 | |
77 | #define VENC_VS_EXT_STOP_Y 0x88 | |
78 | #define VENC_AVID_START_STOP_X 0x90 | |
79 | #define VENC_AVID_START_STOP_Y 0x94 | |
80 | #define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0 | |
81 | #define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4 | |
82 | #define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8 | |
83 | #define VENC_TVDETGP_INT_START_STOP_X 0xB0 | |
84 | #define VENC_TVDETGP_INT_START_STOP_Y 0xB4 | |
85 | #define VENC_GEN_CTRL 0xB8 | |
86 | #define VENC_OUTPUT_CONTROL 0xC4 | |
87 | #define VENC_OUTPUT_TEST 0xC8 | |
88 | #define VENC_DAC_B__DAC_C 0xC8 | |
89 | ||
90 | struct venc_config { | |
91 | u32 f_control; | |
92 | u32 vidout_ctrl; | |
93 | u32 sync_ctrl; | |
94 | u32 llen; | |
95 | u32 flens; | |
96 | u32 hfltr_ctrl; | |
97 | u32 cc_carr_wss_carr; | |
98 | u32 c_phase; | |
99 | u32 gain_u; | |
100 | u32 gain_v; | |
101 | u32 gain_y; | |
102 | u32 black_level; | |
103 | u32 blank_level; | |
104 | u32 x_color; | |
105 | u32 m_control; | |
106 | u32 bstamp_wss_data; | |
107 | u32 s_carr; | |
108 | u32 line21; | |
109 | u32 ln_sel; | |
110 | u32 l21__wc_ctl; | |
111 | u32 htrigger_vtrigger; | |
112 | u32 savid__eavid; | |
113 | u32 flen__fal; | |
114 | u32 lal__phase_reset; | |
115 | u32 hs_int_start_stop_x; | |
116 | u32 hs_ext_start_stop_x; | |
117 | u32 vs_int_start_x; | |
118 | u32 vs_int_stop_x__vs_int_start_y; | |
119 | u32 vs_int_stop_y__vs_ext_start_x; | |
120 | u32 vs_ext_stop_x__vs_ext_start_y; | |
121 | u32 vs_ext_stop_y; | |
122 | u32 avid_start_stop_x; | |
123 | u32 avid_start_stop_y; | |
124 | u32 fid_int_start_x__fid_int_start_y; | |
125 | u32 fid_int_offset_y__fid_ext_start_x; | |
126 | u32 fid_ext_start_y__fid_ext_offset_y; | |
127 | u32 tvdetgp_int_start_stop_x; | |
128 | u32 tvdetgp_int_start_stop_y; | |
129 | u32 gen_ctrl; | |
130 | }; | |
131 | ||
132 | /* from TRM */ | |
133 | static const struct venc_config venc_config_pal_trm = { | |
134 | .f_control = 0, | |
135 | .vidout_ctrl = 1, | |
136 | .sync_ctrl = 0x40, | |
137 | .llen = 0x35F, /* 863 */ | |
138 | .flens = 0x270, /* 624 */ | |
139 | .hfltr_ctrl = 0, | |
140 | .cc_carr_wss_carr = 0x2F7225ED, | |
141 | .c_phase = 0, | |
142 | .gain_u = 0x111, | |
143 | .gain_v = 0x181, | |
144 | .gain_y = 0x140, | |
145 | .black_level = 0x3B, | |
146 | .blank_level = 0x3B, | |
147 | .x_color = 0x7, | |
148 | .m_control = 0x2, | |
149 | .bstamp_wss_data = 0x3F, | |
150 | .s_carr = 0x2A098ACB, | |
151 | .line21 = 0, | |
152 | .ln_sel = 0x01290015, | |
153 | .l21__wc_ctl = 0x0000F603, | |
154 | .htrigger_vtrigger = 0, | |
155 | ||
156 | .savid__eavid = 0x06A70108, | |
157 | .flen__fal = 0x00180270, | |
158 | .lal__phase_reset = 0x00040135, | |
159 | .hs_int_start_stop_x = 0x00880358, | |
160 | .hs_ext_start_stop_x = 0x000F035F, | |
161 | .vs_int_start_x = 0x01A70000, | |
162 | .vs_int_stop_x__vs_int_start_y = 0x000001A7, | |
163 | .vs_int_stop_y__vs_ext_start_x = 0x01AF0000, | |
164 | .vs_ext_stop_x__vs_ext_start_y = 0x000101AF, | |
165 | .vs_ext_stop_y = 0x00000025, | |
166 | .avid_start_stop_x = 0x03530083, | |
167 | .avid_start_stop_y = 0x026C002E, | |
168 | .fid_int_start_x__fid_int_start_y = 0x0001008A, | |
169 | .fid_int_offset_y__fid_ext_start_x = 0x002E0138, | |
170 | .fid_ext_start_y__fid_ext_offset_y = 0x01380001, | |
171 | ||
172 | .tvdetgp_int_start_stop_x = 0x00140001, | |
173 | .tvdetgp_int_start_stop_y = 0x00010001, | |
174 | .gen_ctrl = 0x00FF0000, | |
175 | }; | |
176 | ||
177 | /* from TRM */ | |
178 | static const struct venc_config venc_config_ntsc_trm = { | |
179 | .f_control = 0, | |
180 | .vidout_ctrl = 1, | |
181 | .sync_ctrl = 0x8040, | |
182 | .llen = 0x359, | |
183 | .flens = 0x20C, | |
184 | .hfltr_ctrl = 0, | |
185 | .cc_carr_wss_carr = 0x043F2631, | |
186 | .c_phase = 0, | |
187 | .gain_u = 0x102, | |
188 | .gain_v = 0x16C, | |
189 | .gain_y = 0x12F, | |
190 | .black_level = 0x43, | |
191 | .blank_level = 0x38, | |
192 | .x_color = 0x7, | |
193 | .m_control = 0x1, | |
194 | .bstamp_wss_data = 0x38, | |
195 | .s_carr = 0x21F07C1F, | |
196 | .line21 = 0, | |
197 | .ln_sel = 0x01310011, | |
198 | .l21__wc_ctl = 0x0000F003, | |
199 | .htrigger_vtrigger = 0, | |
200 | ||
201 | .savid__eavid = 0x069300F4, | |
202 | .flen__fal = 0x0016020C, | |
203 | .lal__phase_reset = 0x00060107, | |
204 | .hs_int_start_stop_x = 0x008E0350, | |
205 | .hs_ext_start_stop_x = 0x000F0359, | |
206 | .vs_int_start_x = 0x01A00000, | |
207 | .vs_int_stop_x__vs_int_start_y = 0x020701A0, | |
208 | .vs_int_stop_y__vs_ext_start_x = 0x01AC0024, | |
209 | .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC, | |
210 | .vs_ext_stop_y = 0x00000006, | |
211 | .avid_start_stop_x = 0x03480078, | |
212 | .avid_start_stop_y = 0x02060024, | |
213 | .fid_int_start_x__fid_int_start_y = 0x0001008A, | |
214 | .fid_int_offset_y__fid_ext_start_x = 0x01AC0106, | |
215 | .fid_ext_start_y__fid_ext_offset_y = 0x01060006, | |
216 | ||
217 | .tvdetgp_int_start_stop_x = 0x00140001, | |
218 | .tvdetgp_int_start_stop_y = 0x00010001, | |
219 | .gen_ctrl = 0x00F90000, | |
220 | }; | |
221 | ||
222 | static const struct venc_config venc_config_pal_bdghi = { | |
223 | .f_control = 0, | |
224 | .vidout_ctrl = 0, | |
225 | .sync_ctrl = 0, | |
226 | .hfltr_ctrl = 0, | |
227 | .x_color = 0, | |
228 | .line21 = 0, | |
229 | .ln_sel = 21, | |
230 | .htrigger_vtrigger = 0, | |
231 | .tvdetgp_int_start_stop_x = 0x00140001, | |
232 | .tvdetgp_int_start_stop_y = 0x00010001, | |
233 | .gen_ctrl = 0x00FB0000, | |
234 | ||
235 | .llen = 864-1, | |
236 | .flens = 625-1, | |
237 | .cc_carr_wss_carr = 0x2F7625ED, | |
238 | .c_phase = 0xDF, | |
239 | .gain_u = 0x111, | |
240 | .gain_v = 0x181, | |
241 | .gain_y = 0x140, | |
242 | .black_level = 0x3e, | |
243 | .blank_level = 0x3e, | |
244 | .m_control = 0<<2 | 1<<1, | |
245 | .bstamp_wss_data = 0x42, | |
246 | .s_carr = 0x2a098acb, | |
247 | .l21__wc_ctl = 0<<13 | 0x16<<8 | 0<<0, | |
248 | .savid__eavid = 0x06A70108, | |
249 | .flen__fal = 23<<16 | 624<<0, | |
250 | .lal__phase_reset = 2<<17 | 310<<0, | |
251 | .hs_int_start_stop_x = 0x00920358, | |
252 | .hs_ext_start_stop_x = 0x000F035F, | |
253 | .vs_int_start_x = 0x1a7<<16, | |
254 | .vs_int_stop_x__vs_int_start_y = 0x000601A7, | |
255 | .vs_int_stop_y__vs_ext_start_x = 0x01AF0036, | |
256 | .vs_ext_stop_x__vs_ext_start_y = 0x27101af, | |
257 | .vs_ext_stop_y = 0x05, | |
258 | .avid_start_stop_x = 0x03530082, | |
259 | .avid_start_stop_y = 0x0270002E, | |
260 | .fid_int_start_x__fid_int_start_y = 0x0005008A, | |
261 | .fid_int_offset_y__fid_ext_start_x = 0x002E0138, | |
262 | .fid_ext_start_y__fid_ext_offset_y = 0x01380005, | |
263 | }; | |
264 | ||
265 | const struct omap_video_timings omap_dss_pal_timings = { | |
266 | .x_res = 720, | |
267 | .y_res = 574, | |
268 | .pixel_clock = 13500, | |
269 | .hsw = 64, | |
270 | .hfp = 12, | |
271 | .hbp = 68, | |
272 | .vsw = 5, | |
273 | .vfp = 5, | |
274 | .vbp = 41, | |
275 | }; | |
276 | EXPORT_SYMBOL(omap_dss_pal_timings); | |
277 | ||
278 | const struct omap_video_timings omap_dss_ntsc_timings = { | |
279 | .x_res = 720, | |
280 | .y_res = 482, | |
281 | .pixel_clock = 13500, | |
282 | .hsw = 64, | |
283 | .hfp = 16, | |
284 | .hbp = 58, | |
285 | .vsw = 6, | |
286 | .vfp = 6, | |
287 | .vbp = 31, | |
288 | }; | |
289 | EXPORT_SYMBOL(omap_dss_ntsc_timings); | |
290 | ||
291 | static struct { | |
30ea50c9 | 292 | struct platform_device *pdev; |
b2886273 TV |
293 | void __iomem *base; |
294 | struct mutex venc_lock; | |
295 | u32 wss_data; | |
296 | struct regulator *vdda_dac_reg; | |
4fbafaf3 | 297 | |
4fbafaf3 | 298 | struct clk *tv_dac_clk; |
b2886273 TV |
299 | } venc; |
300 | ||
301 | static inline void venc_write_reg(int idx, u32 val) | |
302 | { | |
303 | __raw_writel(val, venc.base + idx); | |
304 | } | |
305 | ||
306 | static inline u32 venc_read_reg(int idx) | |
307 | { | |
308 | u32 l = __raw_readl(venc.base + idx); | |
309 | return l; | |
310 | } | |
311 | ||
312 | static void venc_write_config(const struct venc_config *config) | |
313 | { | |
314 | DSSDBG("write venc conf\n"); | |
315 | ||
316 | venc_write_reg(VENC_LLEN, config->llen); | |
317 | venc_write_reg(VENC_FLENS, config->flens); | |
318 | venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr); | |
319 | venc_write_reg(VENC_C_PHASE, config->c_phase); | |
320 | venc_write_reg(VENC_GAIN_U, config->gain_u); | |
321 | venc_write_reg(VENC_GAIN_V, config->gain_v); | |
322 | venc_write_reg(VENC_GAIN_Y, config->gain_y); | |
323 | venc_write_reg(VENC_BLACK_LEVEL, config->black_level); | |
324 | venc_write_reg(VENC_BLANK_LEVEL, config->blank_level); | |
325 | venc_write_reg(VENC_M_CONTROL, config->m_control); | |
326 | venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data | | |
327 | venc.wss_data); | |
328 | venc_write_reg(VENC_S_CARR, config->s_carr); | |
329 | venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl); | |
330 | venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid); | |
331 | venc_write_reg(VENC_FLEN__FAL, config->flen__fal); | |
332 | venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset); | |
333 | venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x); | |
334 | venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x); | |
335 | venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x); | |
336 | venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y, | |
337 | config->vs_int_stop_x__vs_int_start_y); | |
338 | venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X, | |
339 | config->vs_int_stop_y__vs_ext_start_x); | |
340 | venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y, | |
341 | config->vs_ext_stop_x__vs_ext_start_y); | |
342 | venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y); | |
343 | venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x); | |
344 | venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y); | |
345 | venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y, | |
346 | config->fid_int_start_x__fid_int_start_y); | |
347 | venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X, | |
348 | config->fid_int_offset_y__fid_ext_start_x); | |
349 | venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y, | |
350 | config->fid_ext_start_y__fid_ext_offset_y); | |
351 | ||
352 | venc_write_reg(VENC_DAC_B__DAC_C, venc_read_reg(VENC_DAC_B__DAC_C)); | |
353 | venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl); | |
354 | venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl); | |
355 | venc_write_reg(VENC_X_COLOR, config->x_color); | |
356 | venc_write_reg(VENC_LINE21, config->line21); | |
357 | venc_write_reg(VENC_LN_SEL, config->ln_sel); | |
358 | venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger); | |
359 | venc_write_reg(VENC_TVDETGP_INT_START_STOP_X, | |
360 | config->tvdetgp_int_start_stop_x); | |
361 | venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y, | |
362 | config->tvdetgp_int_start_stop_y); | |
363 | venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl); | |
364 | venc_write_reg(VENC_F_CONTROL, config->f_control); | |
365 | venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl); | |
366 | } | |
367 | ||
368 | static void venc_reset(void) | |
369 | { | |
370 | int t = 1000; | |
371 | ||
372 | venc_write_reg(VENC_F_CONTROL, 1<<8); | |
373 | while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) { | |
374 | if (--t == 0) { | |
375 | DSSERR("Failed to reset venc\n"); | |
376 | return; | |
377 | } | |
378 | } | |
379 | ||
c6f65e1a | 380 | #ifdef CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET |
b2886273 | 381 | /* the magical sleep that makes things work */ |
c6f65e1a | 382 | /* XXX more info? What bug this circumvents? */ |
b2886273 | 383 | msleep(20); |
c6f65e1a | 384 | #endif |
b2886273 TV |
385 | } |
386 | ||
4fbafaf3 | 387 | static int venc_runtime_get(void) |
b2886273 | 388 | { |
4fbafaf3 TV |
389 | int r; |
390 | ||
391 | DSSDBG("venc_runtime_get\n"); | |
392 | ||
393 | r = pm_runtime_get_sync(&venc.pdev->dev); | |
394 | WARN_ON(r < 0); | |
395 | return r < 0 ? r : 0; | |
396 | } | |
397 | ||
398 | static void venc_runtime_put(void) | |
399 | { | |
400 | int r; | |
401 | ||
402 | DSSDBG("venc_runtime_put\n"); | |
403 | ||
0eaf9f52 | 404 | r = pm_runtime_put_sync(&venc.pdev->dev); |
4fbafaf3 | 405 | WARN_ON(r < 0); |
b2886273 TV |
406 | } |
407 | ||
408 | static const struct venc_config *venc_timings_to_config( | |
409 | struct omap_video_timings *timings) | |
410 | { | |
411 | if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0) | |
412 | return &venc_config_pal_trm; | |
413 | ||
414 | if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0) | |
415 | return &venc_config_ntsc_trm; | |
416 | ||
417 | BUG(); | |
418 | } | |
419 | ||
33ca237f | 420 | static int venc_power_on(struct omap_dss_device *dssdev) |
37ac60e4 TV |
421 | { |
422 | u32 l; | |
33ca237f | 423 | int r; |
c51d921a | 424 | struct omap_video_timings timings; |
37ac60e4 | 425 | |
37ac60e4 TV |
426 | venc_reset(); |
427 | venc_write_config(venc_timings_to_config(&dssdev->panel.timings)); | |
428 | ||
429 | dss_set_venc_output(dssdev->phy.venc.type); | |
430 | dss_set_dac_pwrdn_bgz(1); | |
431 | ||
432 | l = 0; | |
433 | ||
434 | if (dssdev->phy.venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE) | |
435 | l |= 1 << 1; | |
436 | else /* S-Video */ | |
437 | l |= (1 << 0) | (1 << 2); | |
438 | ||
439 | if (dssdev->phy.venc.invert_polarity == false) | |
440 | l |= 1 << 3; | |
441 | ||
442 | venc_write_reg(VENC_OUTPUT_CONTROL, l); | |
443 | ||
c51d921a AT |
444 | timings = dssdev->panel.timings; |
445 | timings.y_res /= 2; | |
446 | ||
41721163 | 447 | dss_mgr_set_timings(dssdev->manager, &timings); |
37ac60e4 | 448 | |
ec874107 MB |
449 | r = regulator_enable(venc.vdda_dac_reg); |
450 | if (r) | |
451 | goto err; | |
37ac60e4 TV |
452 | |
453 | if (dssdev->platform_enable) | |
454 | dssdev->platform_enable(dssdev); | |
455 | ||
33ca237f TV |
456 | r = dss_mgr_enable(dssdev->manager); |
457 | if (r) | |
458 | goto err; | |
459 | ||
460 | return 0; | |
461 | ||
462 | err: | |
463 | venc_write_reg(VENC_OUTPUT_CONTROL, 0); | |
464 | dss_set_dac_pwrdn_bgz(0); | |
465 | ||
466 | if (dssdev->platform_disable) | |
467 | dssdev->platform_disable(dssdev); | |
468 | ||
469 | regulator_disable(venc.vdda_dac_reg); | |
470 | ||
471 | return r; | |
37ac60e4 TV |
472 | } |
473 | ||
474 | static void venc_power_off(struct omap_dss_device *dssdev) | |
475 | { | |
476 | venc_write_reg(VENC_OUTPUT_CONTROL, 0); | |
477 | dss_set_dac_pwrdn_bgz(0); | |
478 | ||
7797c6da | 479 | dss_mgr_disable(dssdev->manager); |
37ac60e4 TV |
480 | |
481 | if (dssdev->platform_disable) | |
482 | dssdev->platform_disable(dssdev); | |
483 | ||
484 | regulator_disable(venc.vdda_dac_reg); | |
37ac60e4 TV |
485 | } |
486 | ||
c3dc6a7a AT |
487 | unsigned long venc_get_pixel_clock(void) |
488 | { | |
489 | /* VENC Pixel Clock in Mhz */ | |
490 | return 13500000; | |
491 | } | |
b2886273 | 492 | |
0aca3c63 GI |
493 | static ssize_t display_output_type_show(struct device *dev, |
494 | struct device_attribute *attr, char *buf) | |
495 | { | |
496 | struct omap_dss_device *dssdev = to_dss_device(dev); | |
497 | const char *ret; | |
498 | ||
499 | switch (dssdev->phy.venc.type) { | |
500 | case OMAP_DSS_VENC_TYPE_COMPOSITE: | |
501 | ret = "composite"; | |
502 | break; | |
503 | case OMAP_DSS_VENC_TYPE_SVIDEO: | |
504 | ret = "svideo"; | |
505 | break; | |
506 | default: | |
507 | return -EINVAL; | |
508 | } | |
509 | ||
510 | return snprintf(buf, PAGE_SIZE, "%s\n", ret); | |
511 | } | |
512 | ||
513 | static ssize_t display_output_type_store(struct device *dev, | |
514 | struct device_attribute *attr, const char *buf, size_t size) | |
515 | { | |
516 | struct omap_dss_device *dssdev = to_dss_device(dev); | |
517 | enum omap_dss_venc_type new_type; | |
518 | ||
519 | if (sysfs_streq("composite", buf)) | |
520 | new_type = OMAP_DSS_VENC_TYPE_COMPOSITE; | |
521 | else if (sysfs_streq("svideo", buf)) | |
522 | new_type = OMAP_DSS_VENC_TYPE_SVIDEO; | |
523 | else | |
524 | return -EINVAL; | |
525 | ||
526 | mutex_lock(&venc.venc_lock); | |
527 | ||
528 | if (dssdev->phy.venc.type != new_type) { | |
529 | dssdev->phy.venc.type = new_type; | |
530 | if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) { | |
531 | venc_power_off(dssdev); | |
532 | venc_power_on(dssdev); | |
533 | } | |
534 | } | |
535 | ||
536 | mutex_unlock(&venc.venc_lock); | |
537 | ||
538 | return size; | |
539 | } | |
540 | ||
541 | static DEVICE_ATTR(output_type, S_IRUGO | S_IWUSR, | |
542 | display_output_type_show, display_output_type_store); | |
543 | ||
b2886273 TV |
544 | /* driver */ |
545 | static int venc_panel_probe(struct omap_dss_device *dssdev) | |
546 | { | |
547 | dssdev->panel.timings = omap_dss_pal_timings; | |
548 | ||
0aca3c63 | 549 | return device_create_file(&dssdev->dev, &dev_attr_output_type); |
b2886273 TV |
550 | } |
551 | ||
552 | static void venc_panel_remove(struct omap_dss_device *dssdev) | |
553 | { | |
0aca3c63 | 554 | device_remove_file(&dssdev->dev, &dev_attr_output_type); |
b2886273 TV |
555 | } |
556 | ||
557 | static int venc_panel_enable(struct omap_dss_device *dssdev) | |
558 | { | |
559 | int r = 0; | |
560 | ||
37ac60e4 TV |
561 | DSSDBG("venc_enable_display\n"); |
562 | ||
563 | mutex_lock(&venc.venc_lock); | |
564 | ||
14572c63 TV |
565 | r = omap_dss_start_device(dssdev); |
566 | if (r) { | |
567 | DSSERR("failed to start device\n"); | |
568 | goto err0; | |
569 | } | |
570 | ||
37ac60e4 TV |
571 | if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) { |
572 | r = -EINVAL; | |
573 | goto err1; | |
574 | } | |
575 | ||
4fbafaf3 TV |
576 | r = venc_runtime_get(); |
577 | if (r) | |
578 | goto err1; | |
579 | ||
33ca237f TV |
580 | r = venc_power_on(dssdev); |
581 | if (r) | |
582 | goto err2; | |
37ac60e4 TV |
583 | |
584 | venc.wss_data = 0; | |
585 | ||
586 | dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; | |
587 | ||
14572c63 TV |
588 | mutex_unlock(&venc.venc_lock); |
589 | return 0; | |
33ca237f TV |
590 | err2: |
591 | venc_runtime_put(); | |
37ac60e4 | 592 | err1: |
14572c63 TV |
593 | omap_dss_stop_device(dssdev); |
594 | err0: | |
37ac60e4 | 595 | mutex_unlock(&venc.venc_lock); |
35bc42c5 | 596 | |
b2886273 TV |
597 | return r; |
598 | } | |
599 | ||
600 | static void venc_panel_disable(struct omap_dss_device *dssdev) | |
601 | { | |
37ac60e4 | 602 | DSSDBG("venc_disable_display\n"); |
b2886273 | 603 | |
37ac60e4 TV |
604 | mutex_lock(&venc.venc_lock); |
605 | ||
606 | if (dssdev->state == OMAP_DSS_DISPLAY_DISABLED) | |
607 | goto end; | |
b2886273 | 608 | |
37ac60e4 TV |
609 | if (dssdev->state == OMAP_DSS_DISPLAY_SUSPENDED) { |
610 | /* suspended is the same as disabled with venc */ | |
611 | dssdev->state = OMAP_DSS_DISPLAY_DISABLED; | |
612 | goto end; | |
613 | } | |
614 | ||
615 | venc_power_off(dssdev); | |
616 | ||
4fbafaf3 TV |
617 | venc_runtime_put(); |
618 | ||
37ac60e4 | 619 | dssdev->state = OMAP_DSS_DISPLAY_DISABLED; |
14572c63 TV |
620 | |
621 | omap_dss_stop_device(dssdev); | |
37ac60e4 TV |
622 | end: |
623 | mutex_unlock(&venc.venc_lock); | |
b2886273 TV |
624 | } |
625 | ||
626 | static int venc_panel_suspend(struct omap_dss_device *dssdev) | |
627 | { | |
628 | venc_panel_disable(dssdev); | |
629 | return 0; | |
630 | } | |
631 | ||
632 | static int venc_panel_resume(struct omap_dss_device *dssdev) | |
633 | { | |
634 | return venc_panel_enable(dssdev); | |
635 | } | |
636 | ||
69b2048f TV |
637 | static void venc_set_timings(struct omap_dss_device *dssdev, |
638 | struct omap_video_timings *timings) | |
639 | { | |
640 | DSSDBG("venc_set_timings\n"); | |
641 | ||
642 | /* Reset WSS data when the TV standard changes. */ | |
643 | if (memcmp(&dssdev->panel.timings, timings, sizeof(*timings))) | |
644 | venc.wss_data = 0; | |
645 | ||
646 | dssdev->panel.timings = *timings; | |
647 | if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) { | |
648 | /* turn the venc off and on to get new timings to use */ | |
649 | venc_panel_disable(dssdev); | |
650 | venc_panel_enable(dssdev); | |
651 | } | |
652 | } | |
653 | ||
654 | static int venc_check_timings(struct omap_dss_device *dssdev, | |
655 | struct omap_video_timings *timings) | |
656 | { | |
657 | DSSDBG("venc_check_timings\n"); | |
658 | ||
659 | if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0) | |
660 | return 0; | |
661 | ||
662 | if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0) | |
663 | return 0; | |
664 | ||
665 | return -EINVAL; | |
666 | } | |
667 | ||
36511312 TV |
668 | static u32 venc_get_wss(struct omap_dss_device *dssdev) |
669 | { | |
670 | /* Invert due to VENC_L21_WC_CTL:INV=1 */ | |
671 | return (venc.wss_data >> 8) ^ 0xfffff; | |
672 | } | |
673 | ||
674 | static int venc_set_wss(struct omap_dss_device *dssdev, u32 wss) | |
675 | { | |
676 | const struct venc_config *config; | |
4fbafaf3 | 677 | int r; |
36511312 TV |
678 | |
679 | DSSDBG("venc_set_wss\n"); | |
680 | ||
681 | mutex_lock(&venc.venc_lock); | |
682 | ||
683 | config = venc_timings_to_config(&dssdev->panel.timings); | |
684 | ||
685 | /* Invert due to VENC_L21_WC_CTL:INV=1 */ | |
686 | venc.wss_data = (wss ^ 0xfffff) << 8; | |
687 | ||
4fbafaf3 TV |
688 | r = venc_runtime_get(); |
689 | if (r) | |
690 | goto err; | |
36511312 TV |
691 | |
692 | venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data | | |
693 | venc.wss_data); | |
694 | ||
4fbafaf3 | 695 | venc_runtime_put(); |
36511312 | 696 | |
4fbafaf3 | 697 | err: |
36511312 TV |
698 | mutex_unlock(&venc.venc_lock); |
699 | ||
4fbafaf3 | 700 | return r; |
36511312 TV |
701 | } |
702 | ||
b2886273 TV |
703 | static struct omap_dss_driver venc_driver = { |
704 | .probe = venc_panel_probe, | |
705 | .remove = venc_panel_remove, | |
706 | ||
707 | .enable = venc_panel_enable, | |
708 | .disable = venc_panel_disable, | |
709 | .suspend = venc_panel_suspend, | |
710 | .resume = venc_panel_resume, | |
711 | ||
96adcece | 712 | .get_resolution = omapdss_default_get_resolution, |
a2699504 | 713 | .get_recommended_bpp = omapdss_default_get_recommended_bpp, |
96adcece | 714 | |
69b2048f TV |
715 | .set_timings = venc_set_timings, |
716 | .check_timings = venc_check_timings, | |
717 | ||
36511312 TV |
718 | .get_wss = venc_get_wss, |
719 | .set_wss = venc_set_wss, | |
720 | ||
b2886273 TV |
721 | .driver = { |
722 | .name = "venc", | |
723 | .owner = THIS_MODULE, | |
724 | }, | |
725 | }; | |
726 | /* driver end */ | |
727 | ||
b2886273 TV |
728 | int venc_init_display(struct omap_dss_device *dssdev) |
729 | { | |
730 | DSSDBG("init_display\n"); | |
731 | ||
5f42f2ce TV |
732 | if (venc.vdda_dac_reg == NULL) { |
733 | struct regulator *vdda_dac; | |
734 | ||
735 | vdda_dac = regulator_get(&venc.pdev->dev, "vdda_dac"); | |
736 | ||
737 | if (IS_ERR(vdda_dac)) { | |
738 | DSSERR("can't get VDDA_DAC regulator\n"); | |
739 | return PTR_ERR(vdda_dac); | |
740 | } | |
741 | ||
742 | venc.vdda_dac_reg = vdda_dac; | |
743 | } | |
744 | ||
b2886273 TV |
745 | return 0; |
746 | } | |
747 | ||
e40402cf | 748 | static void venc_dump_regs(struct seq_file *s) |
b2886273 TV |
749 | { |
750 | #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r)) | |
751 | ||
cc1d3e03 DK |
752 | if (cpu_is_omap44xx()) { |
753 | seq_printf(s, "VENC currently disabled on OMAP44xx\n"); | |
754 | return; | |
755 | } | |
756 | ||
4fbafaf3 TV |
757 | if (venc_runtime_get()) |
758 | return; | |
b2886273 TV |
759 | |
760 | DUMPREG(VENC_F_CONTROL); | |
761 | DUMPREG(VENC_VIDOUT_CTRL); | |
762 | DUMPREG(VENC_SYNC_CTRL); | |
763 | DUMPREG(VENC_LLEN); | |
764 | DUMPREG(VENC_FLENS); | |
765 | DUMPREG(VENC_HFLTR_CTRL); | |
766 | DUMPREG(VENC_CC_CARR_WSS_CARR); | |
767 | DUMPREG(VENC_C_PHASE); | |
768 | DUMPREG(VENC_GAIN_U); | |
769 | DUMPREG(VENC_GAIN_V); | |
770 | DUMPREG(VENC_GAIN_Y); | |
771 | DUMPREG(VENC_BLACK_LEVEL); | |
772 | DUMPREG(VENC_BLANK_LEVEL); | |
773 | DUMPREG(VENC_X_COLOR); | |
774 | DUMPREG(VENC_M_CONTROL); | |
775 | DUMPREG(VENC_BSTAMP_WSS_DATA); | |
776 | DUMPREG(VENC_S_CARR); | |
777 | DUMPREG(VENC_LINE21); | |
778 | DUMPREG(VENC_LN_SEL); | |
779 | DUMPREG(VENC_L21__WC_CTL); | |
780 | DUMPREG(VENC_HTRIGGER_VTRIGGER); | |
781 | DUMPREG(VENC_SAVID__EAVID); | |
782 | DUMPREG(VENC_FLEN__FAL); | |
783 | DUMPREG(VENC_LAL__PHASE_RESET); | |
784 | DUMPREG(VENC_HS_INT_START_STOP_X); | |
785 | DUMPREG(VENC_HS_EXT_START_STOP_X); | |
786 | DUMPREG(VENC_VS_INT_START_X); | |
787 | DUMPREG(VENC_VS_INT_STOP_X__VS_INT_START_Y); | |
788 | DUMPREG(VENC_VS_INT_STOP_Y__VS_EXT_START_X); | |
789 | DUMPREG(VENC_VS_EXT_STOP_X__VS_EXT_START_Y); | |
790 | DUMPREG(VENC_VS_EXT_STOP_Y); | |
791 | DUMPREG(VENC_AVID_START_STOP_X); | |
792 | DUMPREG(VENC_AVID_START_STOP_Y); | |
793 | DUMPREG(VENC_FID_INT_START_X__FID_INT_START_Y); | |
794 | DUMPREG(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X); | |
795 | DUMPREG(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y); | |
796 | DUMPREG(VENC_TVDETGP_INT_START_STOP_X); | |
797 | DUMPREG(VENC_TVDETGP_INT_START_STOP_Y); | |
798 | DUMPREG(VENC_GEN_CTRL); | |
799 | DUMPREG(VENC_OUTPUT_CONTROL); | |
800 | DUMPREG(VENC_OUTPUT_TEST); | |
801 | ||
4fbafaf3 | 802 | venc_runtime_put(); |
b2886273 TV |
803 | |
804 | #undef DUMPREG | |
805 | } | |
30ea50c9 | 806 | |
4fbafaf3 TV |
807 | static int venc_get_clocks(struct platform_device *pdev) |
808 | { | |
809 | struct clk *clk; | |
810 | ||
4fbafaf3 | 811 | if (dss_has_feature(FEAT_VENC_REQUIRES_TV_DAC_CLK)) { |
bfe4f8d3 | 812 | clk = clk_get(&pdev->dev, "tv_dac_clk"); |
4fbafaf3 TV |
813 | if (IS_ERR(clk)) { |
814 | DSSERR("can't get tv_dac_clk\n"); | |
4fbafaf3 TV |
815 | return PTR_ERR(clk); |
816 | } | |
817 | } else { | |
818 | clk = NULL; | |
819 | } | |
820 | ||
821 | venc.tv_dac_clk = clk; | |
822 | ||
823 | return 0; | |
824 | } | |
825 | ||
826 | static void venc_put_clocks(void) | |
827 | { | |
4fbafaf3 TV |
828 | if (venc.tv_dac_clk) |
829 | clk_put(venc.tv_dac_clk); | |
830 | } | |
831 | ||
30ea50c9 SG |
832 | /* VENC HW IP initialisation */ |
833 | static int omap_venchw_probe(struct platform_device *pdev) | |
834 | { | |
835 | u8 rev_id; | |
ea9da36a | 836 | struct resource *venc_mem; |
4fbafaf3 | 837 | int r; |
ea9da36a | 838 | |
30ea50c9 SG |
839 | venc.pdev = pdev; |
840 | ||
841 | mutex_init(&venc.venc_lock); | |
842 | ||
843 | venc.wss_data = 0; | |
844 | ||
ea9da36a SG |
845 | venc_mem = platform_get_resource(venc.pdev, IORESOURCE_MEM, 0); |
846 | if (!venc_mem) { | |
847 | DSSERR("can't get IORESOURCE_MEM VENC\n"); | |
cd3b3449 | 848 | return -EINVAL; |
ea9da36a | 849 | } |
cd3b3449 | 850 | |
6e2a14d2 JL |
851 | venc.base = devm_ioremap(&pdev->dev, venc_mem->start, |
852 | resource_size(venc_mem)); | |
30ea50c9 SG |
853 | if (!venc.base) { |
854 | DSSERR("can't ioremap VENC\n"); | |
cd3b3449 | 855 | return -ENOMEM; |
30ea50c9 SG |
856 | } |
857 | ||
4fbafaf3 TV |
858 | r = venc_get_clocks(pdev); |
859 | if (r) | |
cd3b3449 | 860 | return r; |
4fbafaf3 TV |
861 | |
862 | pm_runtime_enable(&pdev->dev); | |
863 | ||
864 | r = venc_runtime_get(); | |
865 | if (r) | |
cd3b3449 | 866 | goto err_runtime_get; |
30ea50c9 SG |
867 | |
868 | rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff); | |
a06b62f8 | 869 | dev_dbg(&pdev->dev, "OMAP VENC rev %d\n", rev_id); |
30ea50c9 | 870 | |
4fbafaf3 | 871 | venc_runtime_put(); |
30ea50c9 | 872 | |
cd3b3449 TV |
873 | r = omap_dss_register_driver(&venc_driver); |
874 | if (r) | |
875 | goto err_reg_panel_driver; | |
876 | ||
e40402cf TV |
877 | dss_debugfs_create_file("venc", venc_dump_regs); |
878 | ||
cd3b3449 | 879 | return 0; |
4fbafaf3 | 880 | |
cd3b3449 TV |
881 | err_reg_panel_driver: |
882 | err_runtime_get: | |
4fbafaf3 TV |
883 | pm_runtime_disable(&pdev->dev); |
884 | venc_put_clocks(); | |
4fbafaf3 | 885 | return r; |
30ea50c9 SG |
886 | } |
887 | ||
888 | static int omap_venchw_remove(struct platform_device *pdev) | |
889 | { | |
890 | if (venc.vdda_dac_reg != NULL) { | |
891 | regulator_put(venc.vdda_dac_reg); | |
892 | venc.vdda_dac_reg = NULL; | |
893 | } | |
894 | omap_dss_unregister_driver(&venc_driver); | |
895 | ||
4fbafaf3 TV |
896 | pm_runtime_disable(&pdev->dev); |
897 | venc_put_clocks(); | |
898 | ||
30ea50c9 SG |
899 | return 0; |
900 | } | |
901 | ||
4fbafaf3 TV |
902 | static int venc_runtime_suspend(struct device *dev) |
903 | { | |
904 | if (venc.tv_dac_clk) | |
905 | clk_disable(venc.tv_dac_clk); | |
4fbafaf3 TV |
906 | |
907 | dispc_runtime_put(); | |
4fbafaf3 TV |
908 | |
909 | return 0; | |
910 | } | |
911 | ||
912 | static int venc_runtime_resume(struct device *dev) | |
913 | { | |
914 | int r; | |
915 | ||
4fbafaf3 TV |
916 | r = dispc_runtime_get(); |
917 | if (r < 0) | |
852f0838 | 918 | return r; |
4fbafaf3 | 919 | |
4fbafaf3 TV |
920 | if (venc.tv_dac_clk) |
921 | clk_enable(venc.tv_dac_clk); | |
922 | ||
923 | return 0; | |
4fbafaf3 TV |
924 | } |
925 | ||
926 | static const struct dev_pm_ops venc_pm_ops = { | |
927 | .runtime_suspend = venc_runtime_suspend, | |
928 | .runtime_resume = venc_runtime_resume, | |
929 | }; | |
930 | ||
30ea50c9 | 931 | static struct platform_driver omap_venchw_driver = { |
30ea50c9 SG |
932 | .remove = omap_venchw_remove, |
933 | .driver = { | |
934 | .name = "omapdss_venc", | |
935 | .owner = THIS_MODULE, | |
4fbafaf3 | 936 | .pm = &venc_pm_ops, |
30ea50c9 SG |
937 | }, |
938 | }; | |
939 | ||
940 | int venc_init_platform_driver(void) | |
941 | { | |
ba02fa37 TV |
942 | if (cpu_is_omap44xx()) |
943 | return 0; | |
944 | ||
61055d4b | 945 | return platform_driver_probe(&omap_venchw_driver, omap_venchw_probe); |
30ea50c9 SG |
946 | } |
947 | ||
948 | void venc_uninit_platform_driver(void) | |
949 | { | |
ba02fa37 TV |
950 | if (cpu_is_omap44xx()) |
951 | return; | |
952 | ||
04c742c3 | 953 | platform_driver_unregister(&omap_venchw_driver); |
30ea50c9 | 954 | } |