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OMAP: DSS2: Use a macro to declare size of the fifo_size array in dispc.c
[deliverable/linux.git] / drivers / video / omap2 / dss / venc.c
CommitLineData
b2886273
TV		 1/*
2 * linux/drivers/video/omap2/dss/venc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * VENC settings from TI's DSS driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#define DSS_SUBSYS_NAME "VENC"
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/clk.h>
27#include <linux/err.h>
28#include <linux/io.h>
29#include <linux/mutex.h>
30#include <linux/completion.h>
31#include <linux/delay.h>
32#include <linux/string.h>
33#include <linux/seq_file.h>
34#include <linux/platform_device.h>
35#include <linux/regulator/consumer.h>
4fbafaf3 36#include <linux/pm_runtime.h>
b2886273 37
a0b38cc4 38#include <video/omapdss.h>
b2886273
TV		 39#include <plat/cpu.h>
40
41#include "dss.h"
525dae61 42#include "dss_features.h"
b2886273 43
b2886273
TV		 44/* Venc registers */
45#define VENC_REV_ID 0x00
46#define VENC_STATUS 0x04
47#define VENC_F_CONTROL 0x08
48#define VENC_VIDOUT_CTRL 0x10
49#define VENC_SYNC_CTRL 0x14
50#define VENC_LLEN 0x1C
51#define VENC_FLENS 0x20
52#define VENC_HFLTR_CTRL 0x24
53#define VENC_CC_CARR_WSS_CARR 0x28
54#define VENC_C_PHASE 0x2C
55#define VENC_GAIN_U 0x30
56#define VENC_GAIN_V 0x34
57#define VENC_GAIN_Y 0x38
58#define VENC_BLACK_LEVEL 0x3C
59#define VENC_BLANK_LEVEL 0x40
60#define VENC_X_COLOR 0x44
61#define VENC_M_CONTROL 0x48
62#define VENC_BSTAMP_WSS_DATA 0x4C
63#define VENC_S_CARR 0x50
64#define VENC_LINE21 0x54
65#define VENC_LN_SEL 0x58
66#define VENC_L21__WC_CTL 0x5C
67#define VENC_HTRIGGER_VTRIGGER 0x60
68#define VENC_SAVID__EAVID 0x64
69#define VENC_FLEN__FAL 0x68
70#define VENC_LAL__PHASE_RESET 0x6C
71#define VENC_HS_INT_START_STOP_X 0x70
72#define VENC_HS_EXT_START_STOP_X 0x74
73#define VENC_VS_INT_START_X 0x78
74#define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C
75#define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80
76#define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84
77#define VENC_VS_EXT_STOP_Y 0x88
78#define VENC_AVID_START_STOP_X 0x90
79#define VENC_AVID_START_STOP_Y 0x94
80#define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0
81#define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4
82#define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8
83#define VENC_TVDETGP_INT_START_STOP_X 0xB0
84#define VENC_TVDETGP_INT_START_STOP_Y 0xB4
85#define VENC_GEN_CTRL 0xB8
86#define VENC_OUTPUT_CONTROL 0xC4
87#define VENC_OUTPUT_TEST 0xC8
88#define VENC_DAC_B__DAC_C 0xC8
89
90struct venc_config {
91 u32 f_control;
92 u32 vidout_ctrl;
93 u32 sync_ctrl;
94 u32 llen;
95 u32 flens;
96 u32 hfltr_ctrl;
97 u32 cc_carr_wss_carr;
98 u32 c_phase;
99 u32 gain_u;
100 u32 gain_v;
101 u32 gain_y;
102 u32 black_level;
103 u32 blank_level;
104 u32 x_color;
105 u32 m_control;
106 u32 bstamp_wss_data;
107 u32 s_carr;
108 u32 line21;
109 u32 ln_sel;
110 u32 l21__wc_ctl;
111 u32 htrigger_vtrigger;
112 u32 savid__eavid;
113 u32 flen__fal;
114 u32 lal__phase_reset;
115 u32 hs_int_start_stop_x;
116 u32 hs_ext_start_stop_x;
117 u32 vs_int_start_x;
118 u32 vs_int_stop_x__vs_int_start_y;
119 u32 vs_int_stop_y__vs_ext_start_x;
120 u32 vs_ext_stop_x__vs_ext_start_y;
121 u32 vs_ext_stop_y;
122 u32 avid_start_stop_x;
123 u32 avid_start_stop_y;
124 u32 fid_int_start_x__fid_int_start_y;
125 u32 fid_int_offset_y__fid_ext_start_x;
126 u32 fid_ext_start_y__fid_ext_offset_y;
127 u32 tvdetgp_int_start_stop_x;
128 u32 tvdetgp_int_start_stop_y;
129 u32 gen_ctrl;
130};
131
132/* from TRM */
133static const struct venc_config venc_config_pal_trm = {
134 .f_control = 0,
135 .vidout_ctrl = 1,
136 .sync_ctrl = 0x40,
137 .llen = 0x35F, /* 863 */
138 .flens = 0x270, /* 624 */
139 .hfltr_ctrl = 0,
140 .cc_carr_wss_carr = 0x2F7225ED,
141 .c_phase = 0,
142 .gain_u = 0x111,
143 .gain_v = 0x181,
144 .gain_y = 0x140,
145 .black_level = 0x3B,
146 .blank_level = 0x3B,
147 .x_color = 0x7,
148 .m_control = 0x2,
149 .bstamp_wss_data = 0x3F,
150 .s_carr = 0x2A098ACB,
151 .line21 = 0,
152 .ln_sel = 0x01290015,
153 .l21__wc_ctl = 0x0000F603,
154 .htrigger_vtrigger = 0,
155
156 .savid__eavid = 0x06A70108,
157 .flen__fal = 0x00180270,
158 .lal__phase_reset = 0x00040135,
159 .hs_int_start_stop_x = 0x00880358,
160 .hs_ext_start_stop_x = 0x000F035F,
161 .vs_int_start_x = 0x01A70000,
162 .vs_int_stop_x__vs_int_start_y = 0x000001A7,
163 .vs_int_stop_y__vs_ext_start_x = 0x01AF0000,
164 .vs_ext_stop_x__vs_ext_start_y = 0x000101AF,
165 .vs_ext_stop_y = 0x00000025,
166 .avid_start_stop_x = 0x03530083,
167 .avid_start_stop_y = 0x026C002E,
168 .fid_int_start_x__fid_int_start_y = 0x0001008A,
169 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
170 .fid_ext_start_y__fid_ext_offset_y = 0x01380001,
171
172 .tvdetgp_int_start_stop_x = 0x00140001,
173 .tvdetgp_int_start_stop_y = 0x00010001,
174 .gen_ctrl = 0x00FF0000,
175};
176
177/* from TRM */
178static const struct venc_config venc_config_ntsc_trm = {
179 .f_control = 0,
180 .vidout_ctrl = 1,
181 .sync_ctrl = 0x8040,
182 .llen = 0x359,
183 .flens = 0x20C,
184 .hfltr_ctrl = 0,
185 .cc_carr_wss_carr = 0x043F2631,
186 .c_phase = 0,
187 .gain_u = 0x102,
188 .gain_v = 0x16C,
189 .gain_y = 0x12F,
190 .black_level = 0x43,
191 .blank_level = 0x38,
192 .x_color = 0x7,
193 .m_control = 0x1,
194 .bstamp_wss_data = 0x38,
195 .s_carr = 0x21F07C1F,
196 .line21 = 0,
197 .ln_sel = 0x01310011,
198 .l21__wc_ctl = 0x0000F003,
199 .htrigger_vtrigger = 0,
200
201 .savid__eavid = 0x069300F4,
202 .flen__fal = 0x0016020C,
203 .lal__phase_reset = 0x00060107,
204 .hs_int_start_stop_x = 0x008E0350,
205 .hs_ext_start_stop_x = 0x000F0359,
206 .vs_int_start_x = 0x01A00000,
207 .vs_int_stop_x__vs_int_start_y = 0x020701A0,
208 .vs_int_stop_y__vs_ext_start_x = 0x01AC0024,
209 .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,
210 .vs_ext_stop_y = 0x00000006,
211 .avid_start_stop_x = 0x03480078,
212 .avid_start_stop_y = 0x02060024,
213 .fid_int_start_x__fid_int_start_y = 0x0001008A,
214 .fid_int_offset_y__fid_ext_start_x = 0x01AC0106,
215 .fid_ext_start_y__fid_ext_offset_y = 0x01060006,
216
217 .tvdetgp_int_start_stop_x = 0x00140001,
218 .tvdetgp_int_start_stop_y = 0x00010001,
219 .gen_ctrl = 0x00F90000,
220};
221
222static const struct venc_config venc_config_pal_bdghi = {
223 .f_control = 0,
224 .vidout_ctrl = 0,
225 .sync_ctrl = 0,
226 .hfltr_ctrl = 0,
227 .x_color = 0,
228 .line21 = 0,
229 .ln_sel = 21,
230 .htrigger_vtrigger = 0,
231 .tvdetgp_int_start_stop_x = 0x00140001,
232 .tvdetgp_int_start_stop_y = 0x00010001,
233 .gen_ctrl = 0x00FB0000,
234
235 .llen = 864-1,
236 .flens = 625-1,
237 .cc_carr_wss_carr = 0x2F7625ED,
238 .c_phase = 0xDF,
239 .gain_u = 0x111,
240 .gain_v = 0x181,
241 .gain_y = 0x140,
242 .black_level = 0x3e,
243 .blank_level = 0x3e,
244 .m_control = 0<<2 | 1<<1,
245 .bstamp_wss_data = 0x42,
246 .s_carr = 0x2a098acb,
247 .l21__wc_ctl = 0<<13 | 0x16<<8 | 0<<0,
248 .savid__eavid = 0x06A70108,
249 .flen__fal = 23<<16 | 624<<0,
250 .lal__phase_reset = 2<<17 | 310<<0,
251 .hs_int_start_stop_x = 0x00920358,
252 .hs_ext_start_stop_x = 0x000F035F,
253 .vs_int_start_x = 0x1a7<<16,
254 .vs_int_stop_x__vs_int_start_y = 0x000601A7,
255 .vs_int_stop_y__vs_ext_start_x = 0x01AF0036,
256 .vs_ext_stop_x__vs_ext_start_y = 0x27101af,
257 .vs_ext_stop_y = 0x05,
258 .avid_start_stop_x = 0x03530082,
259 .avid_start_stop_y = 0x0270002E,
260 .fid_int_start_x__fid_int_start_y = 0x0005008A,
261 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
262 .fid_ext_start_y__fid_ext_offset_y = 0x01380005,
263};
264
265const struct omap_video_timings omap_dss_pal_timings = {
266 .x_res = 720,
267 .y_res = 574,
268 .pixel_clock = 13500,
269 .hsw = 64,
270 .hfp = 12,
271 .hbp = 68,
272 .vsw = 5,
273 .vfp = 5,
274 .vbp = 41,
275};
276EXPORT_SYMBOL(omap_dss_pal_timings);
277
278const struct omap_video_timings omap_dss_ntsc_timings = {
279 .x_res = 720,
280 .y_res = 482,
281 .pixel_clock = 13500,
282 .hsw = 64,
283 .hfp = 16,
284 .hbp = 58,
285 .vsw = 6,
286 .vfp = 6,
287 .vbp = 31,
288};
289EXPORT_SYMBOL(omap_dss_ntsc_timings);
290
291static struct {
30ea50c9 292 struct platform_device *pdev;
b2886273
TV		 293 void __iomem *base;
294 struct mutex venc_lock;
295 u32 wss_data;
296 struct regulator *vdda_dac_reg;
4fbafaf3
TV		 297
298 struct clk *tv_clk;
299 struct clk *tv_dac_clk;
b2886273
TV		 300} venc;
301
302static inline void venc_write_reg(int idx, u32 val)
303{
304 __raw_writel(val, venc.base + idx);
305}
306
307static inline u32 venc_read_reg(int idx)
308{
309 u32 l = __raw_readl(venc.base + idx);
310 return l;
311}
312
313static void venc_write_config(const struct venc_config *config)
314{
315 DSSDBG("write venc conf\n");
316
317 venc_write_reg(VENC_LLEN, config->llen);
318 venc_write_reg(VENC_FLENS, config->flens);
319 venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
320 venc_write_reg(VENC_C_PHASE, config->c_phase);
321 venc_write_reg(VENC_GAIN_U, config->gain_u);
322 venc_write_reg(VENC_GAIN_V, config->gain_v);
323 venc_write_reg(VENC_GAIN_Y, config->gain_y);
324 venc_write_reg(VENC_BLACK_LEVEL, config->black_level);
325 venc_write_reg(VENC_BLANK_LEVEL, config->blank_level);
326 venc_write_reg(VENC_M_CONTROL, config->m_control);
327 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
328 venc.wss_data);
329 venc_write_reg(VENC_S_CARR, config->s_carr);
330 venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl);
331 venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid);
332 venc_write_reg(VENC_FLEN__FAL, config->flen__fal);
333 venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset);
334 venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x);
335 venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x);
336 venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x);
337 venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y,
338 config->vs_int_stop_x__vs_int_start_y);
339 venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X,
340 config->vs_int_stop_y__vs_ext_start_x);
341 venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
342 config->vs_ext_stop_x__vs_ext_start_y);
343 venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
344 venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x);
345 venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
346 venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y,
347 config->fid_int_start_x__fid_int_start_y);
348 venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
349 config->fid_int_offset_y__fid_ext_start_x);
350 venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
351 config->fid_ext_start_y__fid_ext_offset_y);
352
353 venc_write_reg(VENC_DAC_B__DAC_C, venc_read_reg(VENC_DAC_B__DAC_C));
354 venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl);
355 venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl);
356 venc_write_reg(VENC_X_COLOR, config->x_color);
357 venc_write_reg(VENC_LINE21, config->line21);
358 venc_write_reg(VENC_LN_SEL, config->ln_sel);
359 venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
360 venc_write_reg(VENC_TVDETGP_INT_START_STOP_X,
361 config->tvdetgp_int_start_stop_x);
362 venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y,
363 config->tvdetgp_int_start_stop_y);
364 venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl);
365 venc_write_reg(VENC_F_CONTROL, config->f_control);
366 venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl);
367}
368
369static void venc_reset(void)
370{
371 int t = 1000;
372
373 venc_write_reg(VENC_F_CONTROL, 1<<8);
374 while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) {
375 if (--t == 0) {
376 DSSERR("Failed to reset venc\n");
377 return;
378 }
379 }
380
c6f65e1a 381#ifdef CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET
b2886273 382 /* the magical sleep that makes things work */
c6f65e1a 383 /* XXX more info? What bug this circumvents? */
b2886273 384 msleep(20);
c6f65e1a 385#endif
b2886273
TV		 386}
387
4fbafaf3 388static int venc_runtime_get(void)
b2886273 389{
4fbafaf3
TV		 390 int r;
391
392 DSSDBG("venc_runtime_get\n");
393
394 r = pm_runtime_get_sync(&venc.pdev->dev);
395 WARN_ON(r < 0);
396 return r < 0 ? r : 0;
397}
398
399static void venc_runtime_put(void)
400{
401 int r;
402
403 DSSDBG("venc_runtime_put\n");
404
405 r = pm_runtime_put(&venc.pdev->dev);
406 WARN_ON(r < 0);
b2886273
TV		 407}
408
409static const struct venc_config *venc_timings_to_config(
410 struct omap_video_timings *timings)
411{
412 if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
413 return &venc_config_pal_trm;
414
415 if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
416 return &venc_config_ntsc_trm;
417
418 BUG();
419}
420
37ac60e4
TV		 421static void venc_power_on(struct omap_dss_device *dssdev)
422{
423 u32 l;
424
37ac60e4
TV		 425 venc_reset();
426 venc_write_config(venc_timings_to_config(&dssdev->panel.timings));
427
428 dss_set_venc_output(dssdev->phy.venc.type);
429 dss_set_dac_pwrdn_bgz(1);
430
431 l = 0;
432
433 if (dssdev->phy.venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE)
434 l |= 1 << 1;
435 else /* S-Video */
436 l |= (1 << 0) | (1 << 2);
437
438 if (dssdev->phy.venc.invert_polarity == false)
439 l |= 1 << 3;
440
441 venc_write_reg(VENC_OUTPUT_CONTROL, l);
442
443 dispc_set_digit_size(dssdev->panel.timings.x_res,
444 dssdev->panel.timings.y_res/2);
445
446 regulator_enable(venc.vdda_dac_reg);
447
448 if (dssdev->platform_enable)
449 dssdev->platform_enable(dssdev);
450
451 dssdev->manager->enable(dssdev->manager);
452}
453
454static void venc_power_off(struct omap_dss_device *dssdev)
455{
456 venc_write_reg(VENC_OUTPUT_CONTROL, 0);
457 dss_set_dac_pwrdn_bgz(0);
458
459 dssdev->manager->disable(dssdev->manager);
460
461 if (dssdev->platform_disable)
462 dssdev->platform_disable(dssdev);
463
464 regulator_disable(venc.vdda_dac_reg);
37ac60e4
TV		 465}
466
b2886273
TV		 467
468
469
470
471/* driver */
472static int venc_panel_probe(struct omap_dss_device *dssdev)
473{
474 dssdev->panel.timings = omap_dss_pal_timings;
475
476 return 0;
477}
478
479static void venc_panel_remove(struct omap_dss_device *dssdev)
480{
481}
482
483static int venc_panel_enable(struct omap_dss_device *dssdev)
484{
485 int r = 0;
486
37ac60e4
TV		 487 DSSDBG("venc_enable_display\n");
488
489 mutex_lock(&venc.venc_lock);
490
14572c63
TV		 491 r = omap_dss_start_device(dssdev);
492 if (r) {
493 DSSERR("failed to start device\n");
494 goto err0;
495 }
496
37ac60e4
TV		 497 if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) {
498 r = -EINVAL;
499 goto err1;
500 }
501
4fbafaf3
TV		 502 r = venc_runtime_get();
503 if (r)
504 goto err1;
505
37ac60e4
TV		 506 venc_power_on(dssdev);
507
508 venc.wss_data = 0;
509
510 dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
511
14572c63
TV		 512 mutex_unlock(&venc.venc_lock);
513 return 0;
37ac60e4 514err1:
14572c63
TV		 515 omap_dss_stop_device(dssdev);
516err0:
37ac60e4 517 mutex_unlock(&venc.venc_lock);
35bc42c5 518
b2886273
TV		 519 return r;
520}
521
522static void venc_panel_disable(struct omap_dss_device *dssdev)
523{
37ac60e4 524 DSSDBG("venc_disable_display\n");
b2886273 525
37ac60e4
TV		 526 mutex_lock(&venc.venc_lock);
527
528 if (dssdev->state == OMAP_DSS_DISPLAY_DISABLED)
529 goto end;
b2886273 530
37ac60e4
TV		 531 if (dssdev->state == OMAP_DSS_DISPLAY_SUSPENDED) {
532 /* suspended is the same as disabled with venc */
533 dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
534 goto end;
535 }
536
537 venc_power_off(dssdev);
538
4fbafaf3
TV		 539 venc_runtime_put();
540
37ac60e4 541 dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
14572c63
TV		 542
543 omap_dss_stop_device(dssdev);
37ac60e4
TV		 544end:
545 mutex_unlock(&venc.venc_lock);
b2886273
TV		 546}
547
548static int venc_panel_suspend(struct omap_dss_device *dssdev)
549{
550 venc_panel_disable(dssdev);
551 return 0;
552}
553
554static int venc_panel_resume(struct omap_dss_device *dssdev)
555{
556 return venc_panel_enable(dssdev);
557}
558
69b2048f
TV		 559static void venc_get_timings(struct omap_dss_device *dssdev,
560 struct omap_video_timings *timings)
561{
562 *timings = dssdev->panel.timings;
563}
564
565static void venc_set_timings(struct omap_dss_device *dssdev,
566 struct omap_video_timings *timings)
567{
568 DSSDBG("venc_set_timings\n");
569
570 /* Reset WSS data when the TV standard changes. */
571 if (memcmp(&dssdev->panel.timings, timings, sizeof(*timings)))
572 venc.wss_data = 0;
573
574 dssdev->panel.timings = *timings;
575 if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
576 /* turn the venc off and on to get new timings to use */
577 venc_panel_disable(dssdev);
578 venc_panel_enable(dssdev);
579 }
580}
581
582static int venc_check_timings(struct omap_dss_device *dssdev,
583 struct omap_video_timings *timings)
584{
585 DSSDBG("venc_check_timings\n");
586
587 if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
588 return 0;
589
590 if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
591 return 0;
592
593 return -EINVAL;
594}
595
36511312
TV		 596static u32 venc_get_wss(struct omap_dss_device *dssdev)
597{
598 /* Invert due to VENC_L21_WC_CTL:INV=1 */
599 return (venc.wss_data >> 8) ^ 0xfffff;
600}
601
602static int venc_set_wss(struct omap_dss_device *dssdev, u32 wss)
603{
604 const struct venc_config *config;
4fbafaf3 605 int r;
36511312
TV		 606
607 DSSDBG("venc_set_wss\n");
608
609 mutex_lock(&venc.venc_lock);
610
611 config = venc_timings_to_config(&dssdev->panel.timings);
612
613 /* Invert due to VENC_L21_WC_CTL:INV=1 */
614 venc.wss_data = (wss ^ 0xfffff) << 8;
615
4fbafaf3
TV		 616 r = venc_runtime_get();
617 if (r)
618 goto err;
36511312
TV		 619
620 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
621 venc.wss_data);
622
4fbafaf3 623 venc_runtime_put();
36511312 624
4fbafaf3 625err:
36511312
TV		 626 mutex_unlock(&venc.venc_lock);
627
4fbafaf3 628 return r;
36511312
TV		 629}
630
b2886273
TV		 631static struct omap_dss_driver venc_driver = {
632 .probe = venc_panel_probe,
633 .remove = venc_panel_remove,
634
635 .enable = venc_panel_enable,
636 .disable = venc_panel_disable,
637 .suspend = venc_panel_suspend,
638 .resume = venc_panel_resume,
639
96adcece 640 .get_resolution = omapdss_default_get_resolution,
a2699504 641 .get_recommended_bpp = omapdss_default_get_recommended_bpp,
96adcece 642
69b2048f
TV		 643 .get_timings = venc_get_timings,
644 .set_timings = venc_set_timings,
645 .check_timings = venc_check_timings,
646
36511312
TV		 647 .get_wss = venc_get_wss,
648 .set_wss = venc_set_wss,
649
b2886273
TV		 650 .driver = {
651 .name = "venc",
652 .owner = THIS_MODULE,
653 },
654};
655/* driver end */
656
b2886273
TV		 657int venc_init_display(struct omap_dss_device *dssdev)
658{
659 DSSDBG("init_display\n");
660
5f42f2ce
TV		 661 if (venc.vdda_dac_reg == NULL) {
662 struct regulator *vdda_dac;
663
664 vdda_dac = regulator_get(&venc.pdev->dev, "vdda_dac");
665
666 if (IS_ERR(vdda_dac)) {
667 DSSERR("can't get VDDA_DAC regulator\n");
668 return PTR_ERR(vdda_dac);
669 }
670
671 venc.vdda_dac_reg = vdda_dac;
672 }
673
b2886273
TV		 674 return 0;
675}
676
677void venc_dump_regs(struct seq_file *s)
678{
679#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r))
680
4fbafaf3
TV		 681 if (venc_runtime_get())
682 return;
b2886273
TV		 683
684 DUMPREG(VENC_F_CONTROL);
685 DUMPREG(VENC_VIDOUT_CTRL);
686 DUMPREG(VENC_SYNC_CTRL);
687 DUMPREG(VENC_LLEN);
688 DUMPREG(VENC_FLENS);
689 DUMPREG(VENC_HFLTR_CTRL);
690 DUMPREG(VENC_CC_CARR_WSS_CARR);
691 DUMPREG(VENC_C_PHASE);
692 DUMPREG(VENC_GAIN_U);
693 DUMPREG(VENC_GAIN_V);
694 DUMPREG(VENC_GAIN_Y);
695 DUMPREG(VENC_BLACK_LEVEL);
696 DUMPREG(VENC_BLANK_LEVEL);
697 DUMPREG(VENC_X_COLOR);
698 DUMPREG(VENC_M_CONTROL);
699 DUMPREG(VENC_BSTAMP_WSS_DATA);
700 DUMPREG(VENC_S_CARR);
701 DUMPREG(VENC_LINE21);
702 DUMPREG(VENC_LN_SEL);
703 DUMPREG(VENC_L21__WC_CTL);
704 DUMPREG(VENC_HTRIGGER_VTRIGGER);
705 DUMPREG(VENC_SAVID__EAVID);
706 DUMPREG(VENC_FLEN__FAL);
707 DUMPREG(VENC_LAL__PHASE_RESET);
708 DUMPREG(VENC_HS_INT_START_STOP_X);
709 DUMPREG(VENC_HS_EXT_START_STOP_X);
710 DUMPREG(VENC_VS_INT_START_X);
711 DUMPREG(VENC_VS_INT_STOP_X__VS_INT_START_Y);
712 DUMPREG(VENC_VS_INT_STOP_Y__VS_EXT_START_X);
713 DUMPREG(VENC_VS_EXT_STOP_X__VS_EXT_START_Y);
714 DUMPREG(VENC_VS_EXT_STOP_Y);
715 DUMPREG(VENC_AVID_START_STOP_X);
716 DUMPREG(VENC_AVID_START_STOP_Y);
717 DUMPREG(VENC_FID_INT_START_X__FID_INT_START_Y);
718 DUMPREG(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X);
719 DUMPREG(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y);
720 DUMPREG(VENC_TVDETGP_INT_START_STOP_X);
721 DUMPREG(VENC_TVDETGP_INT_START_STOP_Y);
722 DUMPREG(VENC_GEN_CTRL);
723 DUMPREG(VENC_OUTPUT_CONTROL);
724 DUMPREG(VENC_OUTPUT_TEST);
725
4fbafaf3 726 venc_runtime_put();
b2886273
TV		 727
728#undef DUMPREG
729}
30ea50c9 730
4fbafaf3
TV		 731static int venc_get_clocks(struct platform_device *pdev)
732{
733 struct clk *clk;
734
735 clk = clk_get(&pdev->dev, "fck");
736 if (IS_ERR(clk)) {
737 DSSERR("can't get fck\n");
738 return PTR_ERR(clk);
739 }
740
741 venc.tv_clk = clk;
742
743 if (dss_has_feature(FEAT_VENC_REQUIRES_TV_DAC_CLK)) {
9ede365a
TV		 744 if (cpu_is_omap34xx() || cpu_is_omap3630())
745 clk = clk_get(&pdev->dev, "dss_96m_fck");
746 else
747 clk = clk_get(&pdev->dev, "tv_dac_clk");
4fbafaf3
TV		 748 if (IS_ERR(clk)) {
749 DSSERR("can't get tv_dac_clk\n");
750 clk_put(venc.tv_clk);
751 return PTR_ERR(clk);
752 }
753 } else {
754 clk = NULL;
755 }
756
757 venc.tv_dac_clk = clk;
758
759 return 0;
760}
761
762static void venc_put_clocks(void)
763{
764 if (venc.tv_clk)
765 clk_put(venc.tv_clk);
766 if (venc.tv_dac_clk)
767 clk_put(venc.tv_dac_clk);
768}
769
30ea50c9
SG		 770/* VENC HW IP initialisation */
771static int omap_venchw_probe(struct platform_device *pdev)
772{
773 u8 rev_id;
ea9da36a 774 struct resource *venc_mem;
4fbafaf3 775 int r;
ea9da36a 776
30ea50c9
SG		 777 venc.pdev = pdev;
778
779 mutex_init(&venc.venc_lock);
780
781 venc.wss_data = 0;
782
ea9da36a
SG		 783 venc_mem = platform_get_resource(venc.pdev, IORESOURCE_MEM, 0);
784 if (!venc_mem) {
785 DSSERR("can't get IORESOURCE_MEM VENC\n");
4fbafaf3
TV		 786 r = -EINVAL;
787 goto err_ioremap;
ea9da36a
SG		 788 }
789 venc.base = ioremap(venc_mem->start, resource_size(venc_mem));
30ea50c9
SG		 790 if (!venc.base) {
791 DSSERR("can't ioremap VENC\n");
4fbafaf3
TV		 792 r = -ENOMEM;
793 goto err_ioremap;
30ea50c9
SG		 794 }
795
4fbafaf3
TV		 796 r = venc_get_clocks(pdev);
797 if (r)
798 goto err_get_clk;
799
800 pm_runtime_enable(&pdev->dev);
801
802 r = venc_runtime_get();
803 if (r)
804 goto err_get_venc;
30ea50c9
SG		 805
806 rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff);
a06b62f8 807 dev_dbg(&pdev->dev, "OMAP VENC rev %d\n", rev_id);
30ea50c9 808
4fbafaf3 809 venc_runtime_put();
30ea50c9
SG		 810
811 return omap_dss_register_driver(&venc_driver);
4fbafaf3
TV		 812
813err_get_venc:
814 pm_runtime_disable(&pdev->dev);
815 venc_put_clocks();
816err_get_clk:
817 iounmap(venc.base);
818err_ioremap:
819 return r;
30ea50c9
SG		 820}
821
822static int omap_venchw_remove(struct platform_device *pdev)
823{
824 if (venc.vdda_dac_reg != NULL) {
825 regulator_put(venc.vdda_dac_reg);
826 venc.vdda_dac_reg = NULL;
827 }
828 omap_dss_unregister_driver(&venc_driver);
829
4fbafaf3
TV		 830 pm_runtime_disable(&pdev->dev);
831 venc_put_clocks();
832
30ea50c9
SG		 833 iounmap(venc.base);
834 return 0;
835}
836
4fbafaf3
TV		 837static int venc_runtime_suspend(struct device *dev)
838{
839 if (venc.tv_dac_clk)
840 clk_disable(venc.tv_dac_clk);
841 clk_disable(venc.tv_clk);
842
843 dispc_runtime_put();
844 dss_runtime_put();
845
846 return 0;
847}
848
849static int venc_runtime_resume(struct device *dev)
850{
851 int r;
852
853 r = dss_runtime_get();
854 if (r < 0)
855 goto err_get_dss;
856
857 r = dispc_runtime_get();
858 if (r < 0)
859 goto err_get_dispc;
860
861 clk_enable(venc.tv_clk);
862 if (venc.tv_dac_clk)
863 clk_enable(venc.tv_dac_clk);
864
865 return 0;
866
867err_get_dispc:
868 dss_runtime_put();
869err_get_dss:
870 return r;
871}
872
873static const struct dev_pm_ops venc_pm_ops = {
874 .runtime_suspend = venc_runtime_suspend,
875 .runtime_resume = venc_runtime_resume,
876};
877
30ea50c9
SG		 878static struct platform_driver omap_venchw_driver = {
879 .probe = omap_venchw_probe,
880 .remove = omap_venchw_remove,
881 .driver = {
882 .name = "omapdss_venc",
883 .owner = THIS_MODULE,
4fbafaf3 884 .pm = &venc_pm_ops,
30ea50c9
SG		 885 },
886};
887
888int venc_init_platform_driver(void)
889{
ba02fa37
TV		 890 if (cpu_is_omap44xx())
891 return 0;
892
30ea50c9
SG		 893 return platform_driver_register(&omap_venchw_driver);
894}
895
896void venc_uninit_platform_driver(void)
897{
ba02fa37
TV		 898 if (cpu_is_omap44xx())
899 return;
900
30ea50c9
SG		 901 return platform_driver_unregister(&omap_venchw_driver);
902}
Linux kernel - Deliverables
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