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pvr2fb: Fix oops when pseudo_palette is written
[deliverable/linux.git] / drivers / video / pvr2fb.c
CommitLineData
1da177e4
LT		 1/* drivers/video/pvr2fb.c
2 *
3 * Frame buffer and fbcon support for the NEC PowerVR2 found within the Sega
4 * Dreamcast.
5 *
6 * Copyright (c) 2001 M. R. Brown <mrbrown@0xd6.org>
7 * Copyright (c) 2001, 2002, 2003, 2004, 2005 Paul Mundt <lethal@linux-sh.org>
8 *
9 * This file is part of the LinuxDC project (linuxdc.sourceforge.net).
10 *
11 */
12
13/*
14 * This driver is mostly based on the excellent amifb and vfb sources. It uses
15 * an odd scheme for converting hardware values to/from framebuffer values,
16 * here are some hacked-up formulas:
17 *
18 * The Dreamcast has screen offsets from each side of its four borders and
19 * the start offsets of the display window. I used these values to calculate
20 * 'pseudo' values (think of them as placeholders) for the fb video mode, so
21 * that when it came time to convert these values back into their hardware
22 * values, I could just add mode- specific offsets to get the correct mode
23 * settings:
24 *
25 * left_margin = diwstart_h - borderstart_h;
26 * right_margin = borderstop_h - (diwstart_h + xres);
27 * upper_margin = diwstart_v - borderstart_v;
28 * lower_margin = borderstop_v - (diwstart_h + yres);
29 *
30 * hsync_len = borderstart_h + (hsync_total - borderstop_h);
31 * vsync_len = borderstart_v + (vsync_total - borderstop_v);
32 *
33 * Then, when it's time to convert back to hardware settings, the only
34 * constants are the borderstart_* offsets, all other values are derived from
35 * the fb video mode:
36 *
37 * // PAL
38 * borderstart_h = 116;
39 * borderstart_v = 44;
40 * ...
41 * borderstop_h = borderstart_h + hsync_total - hsync_len;
42 * ...
43 * diwstart_v = borderstart_v - upper_margin;
44 *
45 * However, in the current implementation, the borderstart values haven't had
46 * the benefit of being fully researched, so some modes may be broken.
47 */
48
49#undef DEBUG
50
51#include <linux/module.h>
52#include <linux/kernel.h>
53#include <linux/errno.h>
54#include <linux/string.h>
55#include <linux/mm.h>
1da177e4
LT		 56#include <linux/slab.h>
57#include <linux/delay.h>
1da177e4
LT		 58#include <linux/interrupt.h>
59#include <linux/fb.h>
60#include <linux/init.h>
61#include <linux/pci.h>
62
63#ifdef CONFIG_SH_DREAMCAST
64#include <asm/machvec.h>
65#include <asm/mach/sysasic.h>
66#endif
67
68#ifdef CONFIG_SH_DMA
69#include <linux/pagemap.h>
70#include <asm/mach/dma.h>
71#include <asm/dma.h>
72#endif
73
74#ifdef CONFIG_SH_STORE_QUEUES
75#include <asm/uaccess.h>
76#include <asm/cpu/sq.h>
77#endif
78
79#ifndef PCI_DEVICE_ID_NEC_NEON250
80# define PCI_DEVICE_ID_NEC_NEON250 0x0067
81#endif
82
83/* 2D video registers */
84#define DISP_BASE par->mmio_base
85#define DISP_BRDRCOLR (DISP_BASE + 0x40)
86#define DISP_DIWMODE (DISP_BASE + 0x44)
87#define DISP_DIWADDRL (DISP_BASE + 0x50)
88#define DISP_DIWADDRS (DISP_BASE + 0x54)
89#define DISP_DIWSIZE (DISP_BASE + 0x5c)
90#define DISP_SYNCCONF (DISP_BASE + 0xd0)
91#define DISP_BRDRHORZ (DISP_BASE + 0xd4)
92#define DISP_SYNCSIZE (DISP_BASE + 0xd8)
93#define DISP_BRDRVERT (DISP_BASE + 0xdc)
94#define DISP_DIWCONF (DISP_BASE + 0xe8)
95#define DISP_DIWHSTRT (DISP_BASE + 0xec)
96#define DISP_DIWVSTRT (DISP_BASE + 0xf0)
97
98/* Pixel clocks, one for TV output, doubled for VGA output */
99#define TV_CLK 74239
100#define VGA_CLK 37119
101
102/* This is for 60Hz - the VTOTAL is doubled for interlaced modes */
103#define PAL_HTOTAL 863
104#define PAL_VTOTAL 312
105#define NTSC_HTOTAL 857
106#define NTSC_VTOTAL 262
107
108/* Supported cable types */
109enum { CT_VGA, CT_NONE, CT_RGB, CT_COMPOSITE };
110
111/* Supported video output types */
112enum { VO_PAL, VO_NTSC, VO_VGA };
113
114/* Supported palette types */
115enum { PAL_ARGB1555, PAL_RGB565, PAL_ARGB4444, PAL_ARGB8888 };
116
117struct pvr2_params { unsigned int val; char *name; };
7e7ec0d4 118static struct pvr2_params cables[] __devinitdata = {
1da177e4
LT		 119 { CT_VGA, "VGA" }, { CT_RGB, "RGB" }, { CT_COMPOSITE, "COMPOSITE" },
120};
121
7e7ec0d4 122static struct pvr2_params outputs[] __devinitdata = {
1da177e4
LT		 123 { VO_PAL, "PAL" }, { VO_NTSC, "NTSC" }, { VO_VGA, "VGA" },
124};
125
126/*
127 * This describes the current video mode
128 */
129
130static struct pvr2fb_par {
131 unsigned int hsync_total; /* Clocks/line */
132 unsigned int vsync_total; /* Lines/field */
133 unsigned int borderstart_h;
134 unsigned int borderstop_h;
135 unsigned int borderstart_v;
136 unsigned int borderstop_v;
137 unsigned int diwstart_h; /* Horizontal offset of the display field */
138 unsigned int diwstart_v; /* Vertical offset of the display field, for
139 interlaced modes, this is the long field */
140 unsigned long disp_start; /* Address of image within VRAM */
141 unsigned char is_interlaced; /* Is the display interlaced? */
142 unsigned char is_doublescan; /* Are scanlines output twice? (doublescan) */
143 unsigned char is_lowres; /* Is horizontal pixel-doubling enabled? */
144
145 unsigned long mmio_base; /* MMIO base */
9cd1c674 146 u32 palette[16];
1da177e4
LT		 147} *currentpar;
148
149static struct fb_info *fb_info;
150
e9705a77 151static struct fb_fix_screeninfo pvr2_fix __devinitdata = {
1da177e4 152 .id = "NEC PowerVR2",
e9705a77
PM		 153 .type = FB_TYPE_PACKED_PIXELS,
154 .visual = FB_VISUAL_TRUECOLOR,
1da177e4
LT		 155 .ypanstep = 1,
156 .ywrapstep = 1,
e9705a77 157 .accel = FB_ACCEL_NONE,
1da177e4
LT		 158};
159
e9705a77 160static struct fb_var_screeninfo pvr2_var __devinitdata = {
1da177e4
LT		 161 .xres = 640,
162 .yres = 480,
163 .xres_virtual = 640,
164 .yres_virtual = 480,
165 .bits_per_pixel =16,
166 .red = { 11, 5, 0 },
167 .green = { 5, 6, 0 },
168 .blue = { 0, 5, 0 },
169 .activate = FB_ACTIVATE_NOW,
170 .height = -1,
171 .width = -1,
172 .vmode = FB_VMODE_NONINTERLACED,
173};
174
175static int cable_type = CT_VGA;
176static int video_output = VO_VGA;
177
178static int nopan = 0;
179static int nowrap = 1;
180
181/*
182 * We do all updating, blanking, etc. during the vertical retrace period
183 */
184static unsigned int do_vmode_full = 0; /* Change the video mode */
185static unsigned int do_vmode_pan = 0; /* Update the video mode */
186static short do_blank = 0; /* (Un)Blank the screen */
187
188static unsigned int is_blanked = 0; /* Is the screen blanked? */
189
190#ifdef CONFIG_SH_STORE_QUEUES
d2b06a8b 191static unsigned long pvr2fb_map;
1da177e4
LT		 192#endif
193
194#ifdef CONFIG_SH_DMA
195static unsigned int shdma = PVR2_CASCADE_CHAN;
196static unsigned int pvr2dma = ONCHIP_NR_DMA_CHANNELS;
197#endif
198
1da177e4
LT		 199static int pvr2fb_setcolreg(unsigned int regno, unsigned int red, unsigned int green, unsigned int blue,
200 unsigned int transp, struct fb_info *info);
201static int pvr2fb_blank(int blank, struct fb_info *info);
202static unsigned long get_line_length(int xres_virtual, int bpp);
203static void set_color_bitfields(struct fb_var_screeninfo *var);
204static int pvr2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info);
205static int pvr2fb_set_par(struct fb_info *info);
206static void pvr2_update_display(struct fb_info *info);
207static void pvr2_init_display(struct fb_info *info);
208static void pvr2_do_blank(void);
7d12e780 209static irqreturn_t pvr2fb_interrupt(int irq, void *dev_id);
1da177e4
LT		 210static int pvr2_init_cable(void);
211static int pvr2_get_param(const struct pvr2_params *p, const char *s,
212 int val, int size);
d2b06a8b 213#ifdef CONFIG_SH_DMA
3f9b0880 214static ssize_t pvr2fb_write(struct fb_info *info, const char *buf,
1da177e4 215 size_t count, loff_t *ppos);
d2b06a8b 216#endif
1da177e4
LT		 217
218static struct fb_ops pvr2fb_ops = {
d2b06a8b
PM		 219 .owner = THIS_MODULE,
220 .fb_setcolreg = pvr2fb_setcolreg,
221 .fb_blank = pvr2fb_blank,
222 .fb_check_var = pvr2fb_check_var,
223 .fb_set_par = pvr2fb_set_par,
1da177e4
LT		 224#ifdef CONFIG_SH_DMA
225 .fb_write = pvr2fb_write,
226#endif
e9705a77 227 .fb_fillrect = cfb_fillrect,
1da177e4
LT		 228 .fb_copyarea = cfb_copyarea,
229 .fb_imageblit = cfb_imageblit,
1da177e4
LT		 230};
231
7e7ec0d4 232static struct fb_videomode pvr2_modedb[] __devinitdata = {
1da177e4
LT		 233 /*
234 * Broadcast video modes (PAL and NTSC). I'm unfamiliar with
235 * PAL-M and PAL-N, but from what I've read both modes parallel PAL and
236 * NTSC, so it shouldn't be a problem (I hope).
237 */
238
239 {
240 /* 640x480 @ 60Hz interlaced (NTSC) */
241 "ntsc_640x480i", 60, 640, 480, TV_CLK, 38, 33, 0, 18, 146, 26,
242 FB_SYNC_BROADCAST, FB_VMODE_INTERLACED | FB_VMODE_YWRAP
243 }, {
244 /* 640x240 @ 60Hz (NTSC) */
245 /* XXX: Broken! Don't use... */
246 "ntsc_640x240", 60, 640, 240, TV_CLK, 38, 33, 0, 0, 146, 22,
247 FB_SYNC_BROADCAST, FB_VMODE_YWRAP
248 }, {
249 /* 640x480 @ 60hz (VGA) */
250 "vga_640x480", 60, 640, 480, VGA_CLK, 38, 33, 0, 18, 146, 26,
251 0, FB_VMODE_YWRAP
e9705a77 252 },
1da177e4
LT		 253};
254
255#define NUM_TOTAL_MODES ARRAY_SIZE(pvr2_modedb)
256
257#define DEFMODE_NTSC 0
258#define DEFMODE_PAL 0
259#define DEFMODE_VGA 2
260
261static int defmode = DEFMODE_NTSC;
7e7ec0d4 262static char *mode_option __devinitdata = NULL;
1da177e4
LT		 263
264static inline void pvr2fb_set_pal_type(unsigned int type)
265{
266 struct pvr2fb_par *par = (struct pvr2fb_par *)fb_info->par;
267
268 fb_writel(type, par->mmio_base + 0x108);
269}
270
271static inline void pvr2fb_set_pal_entry(struct pvr2fb_par *par,
272 unsigned int regno,
273 unsigned int val)
274{
275 fb_writel(val, par->mmio_base + 0x1000 + (4 * regno));
276}
277
278static int pvr2fb_blank(int blank, struct fb_info *info)
279{
280 do_blank = blank ? blank : -1;
281 return 0;
282}
283
284static inline unsigned long get_line_length(int xres_virtual, int bpp)
285{
286 return (unsigned long)((((xres_virtual*bpp)+31)&~31) >> 3);
287}
288
289static void set_color_bitfields(struct fb_var_screeninfo *var)
290{
291 switch (var->bits_per_pixel) {
292 case 16: /* RGB 565 */
e9705a77 293 pvr2fb_set_pal_type(PAL_RGB565);
1da177e4
LT		 294 var->red.offset = 11; var->red.length = 5;
295 var->green.offset = 5; var->green.length = 6;
296 var->blue.offset = 0; var->blue.length = 5;
297 var->transp.offset = 0; var->transp.length = 0;
298 break;
299 case 24: /* RGB 888 */
300 var->red.offset = 16; var->red.length = 8;
301 var->green.offset = 8; var->green.length = 8;
302 var->blue.offset = 0; var->blue.length = 8;
303 var->transp.offset = 0; var->transp.length = 0;
304 break;
305 case 32: /* ARGB 8888 */
e9705a77 306 pvr2fb_set_pal_type(PAL_ARGB8888);
1da177e4
LT		 307 var->red.offset = 16; var->red.length = 8;
308 var->green.offset = 8; var->green.length = 8;
309 var->blue.offset = 0; var->blue.length = 8;
310 var->transp.offset = 24; var->transp.length = 8;
311 break;
312 }
313}
314
315static int pvr2fb_setcolreg(unsigned int regno, unsigned int red,
316 unsigned int green, unsigned int blue,
317 unsigned int transp, struct fb_info *info)
318{
319 struct pvr2fb_par *par = (struct pvr2fb_par *)info->par;
320 unsigned int tmp;
321
322 if (regno > info->cmap.len)
323 return 1;
324
325 /*
326 * We only support the hardware palette for 16 and 32bpp. It's also
327 * expected that the palette format has been set by the time we get
328 * here, so we don't waste time setting it again.
329 */
330 switch (info->var.bits_per_pixel) {
331 case 16: /* RGB 565 */
332 tmp = (red & 0xf800) |
333 ((green & 0xfc00) >> 5) |
334 ((blue & 0xf800) >> 11);
335
336 pvr2fb_set_pal_entry(par, regno, tmp);
1da177e4
LT		 337 break;
338 case 24: /* RGB 888 */
339 red >>= 8; green >>= 8; blue >>= 8;
a66ad56e 340 tmp = (red << 16) | (green << 8) | blue;
1da177e4
LT		 341 break;
342 case 32: /* ARGB 8888 */
343 red >>= 8; green >>= 8; blue >>= 8;
344 tmp = (transp << 24) | (red << 16) | (green << 8) | blue;
345
346 pvr2fb_set_pal_entry(par, regno, tmp);
1da177e4
LT		 347 break;
348 default:
349 pr_debug("Invalid bit depth %d?!?\n", info->var.bits_per_pixel);
350 return 1;
351 }
352
a66ad56e
AD		 353 if (regno < 16)
354 ((u32*)(info->pseudo_palette))[regno] = tmp;
355
1da177e4
LT		 356 return 0;
357}
358
359static int pvr2fb_set_par(struct fb_info *info)
360{
361 struct pvr2fb_par *par = (struct pvr2fb_par *)info->par;
362 struct fb_var_screeninfo *var = &info->var;
363 unsigned long line_length;
364 unsigned int vtotal;
365
366 /*
367 * XXX: It's possible that a user could use a VGA box, change the cable
368 * type in hardware (i.e. switch from VGA<->composite), then change
369 * modes (i.e. switching to another VT). If that happens we should
370 * automagically change the output format to cope, but currently I
371 * don't have a VGA box to make sure this works properly.
372 */
373 cable_type = pvr2_init_cable();
374 if (cable_type == CT_VGA && video_output != VO_VGA)
375 video_output = VO_VGA;
376
377 var->vmode &= FB_VMODE_MASK;
378 if (var->vmode & FB_VMODE_INTERLACED && video_output != VO_VGA)
379 par->is_interlaced = 1;
e9705a77 380 /*
1da177e4
LT		 381 * XXX: Need to be more creative with this (i.e. allow doublecan for
382 * PAL/NTSC output).
383 */
384 if (var->vmode & FB_VMODE_DOUBLE && video_output == VO_VGA)
385 par->is_doublescan = 1;
e9705a77 386
1da177e4
LT		 387 par->hsync_total = var->left_margin + var->xres + var->right_margin +
388 var->hsync_len;
389 par->vsync_total = var->upper_margin + var->yres + var->lower_margin +
390 var->vsync_len;
391
392 if (var->sync & FB_SYNC_BROADCAST) {
393 vtotal = par->vsync_total;
394 if (par->is_interlaced)
395 vtotal /= 2;
396 if (vtotal > (PAL_VTOTAL + NTSC_VTOTAL)/2) {
397 /* XXX: Check for start values here... */
398 /* XXX: Check hardware for PAL-compatibility */
399 par->borderstart_h = 116;
400 par->borderstart_v = 44;
401 } else {
402 /* NTSC video output */
403 par->borderstart_h = 126;
404 par->borderstart_v = 18;
405 }
406 } else {
407 /* VGA mode */
408 /* XXX: What else needs to be checked? */
e9705a77 409 /*
1da177e4
LT		 410 * XXX: We have a little freedom in VGA modes, what ranges
411 * should be here (i.e. hsync/vsync totals, etc.)?
412 */
413 par->borderstart_h = 126;
414 par->borderstart_v = 40;
415 }
416
417 /* Calculate the remainding offsets */
418 par->diwstart_h = par->borderstart_h + var->left_margin;
419 par->diwstart_v = par->borderstart_v + var->upper_margin;
e9705a77
PM		 420 par->borderstop_h = par->diwstart_h + var->xres +
421 var->right_margin;
1da177e4
LT		 422 par->borderstop_v = par->diwstart_v + var->yres +
423 var->lower_margin;
424
425 if (!par->is_interlaced)
426 par->borderstop_v /= 2;
427 if (info->var.xres < 640)
428 par->is_lowres = 1;
429
430 line_length = get_line_length(var->xres_virtual, var->bits_per_pixel);
431 par->disp_start = info->fix.smem_start + (line_length * var->yoffset) * line_length;
432 info->fix.line_length = line_length;
433 return 0;
434}
435
436static int pvr2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
437{
438 struct pvr2fb_par *par = (struct pvr2fb_par *)info->par;
439 unsigned int vtotal, hsync_total;
440 unsigned long line_length;
441
442 if (var->pixclock != TV_CLK && var->pixclock != VGA_CLK) {
443 pr_debug("Invalid pixclock value %d\n", var->pixclock);
444 return -EINVAL;
445 }
446
447 if (var->xres < 320)
448 var->xres = 320;
449 if (var->yres < 240)
450 var->yres = 240;
451 if (var->xres_virtual < var->xres)
452 var->xres_virtual = var->xres;
453 if (var->yres_virtual < var->yres)
454 var->yres_virtual = var->yres;
455
456 if (var->bits_per_pixel <= 16)
457 var->bits_per_pixel = 16;
458 else if (var->bits_per_pixel <= 24)
459 var->bits_per_pixel = 24;
460 else if (var->bits_per_pixel <= 32)
461 var->bits_per_pixel = 32;
462
463 set_color_bitfields(var);
464
465 if (var->vmode & FB_VMODE_YWRAP) {
e9705a77 466 if (var->xoffset || var->yoffset < 0 ||
1da177e4
LT		 467 var->yoffset >= var->yres_virtual) {
468 var->xoffset = var->yoffset = 0;
469 } else {
470 if (var->xoffset > var->xres_virtual - var->xres ||
e9705a77 471 var->yoffset > var->yres_virtual - var->yres ||
1da177e4
LT		 472 var->xoffset < 0 || var->yoffset < 0)
473 var->xoffset = var->yoffset = 0;
474 }
475 } else {
476 var->xoffset = var->yoffset = 0;
477 }
478
e9705a77 479 /*
1da177e4
LT		 480 * XXX: Need to be more creative with this (i.e. allow doublecan for
481 * PAL/NTSC output).
482 */
483 if (var->yres < 480 && video_output == VO_VGA)
484 var->vmode |= FB_VMODE_DOUBLE;
485
486 if (video_output != VO_VGA) {
487 var->sync |= FB_SYNC_BROADCAST;
488 var->vmode |= FB_VMODE_INTERLACED;
489 } else {
490 var->sync &= ~FB_SYNC_BROADCAST;
491 var->vmode &= ~FB_VMODE_INTERLACED;
492 var->vmode |= pvr2_var.vmode;
493 }
494
495 if ((var->activate & FB_ACTIVATE_MASK) != FB_ACTIVATE_TEST) {
496 var->right_margin = par->borderstop_h -
497 (par->diwstart_h + var->xres);
498 var->left_margin = par->diwstart_h - par->borderstart_h;
499 var->hsync_len = par->borderstart_h +
500 (par->hsync_total - par->borderstop_h);
501
502 var->upper_margin = par->diwstart_v - par->borderstart_v;
503 var->lower_margin = par->borderstop_v -
504 (par->diwstart_v + var->yres);
505 var->vsync_len = par->borderstop_v +
506 (par->vsync_total - par->borderstop_v);
507 }
e9705a77 508
1da177e4
LT		 509 hsync_total = var->left_margin + var->xres + var->right_margin +
510 var->hsync_len;
511 vtotal = var->upper_margin + var->yres + var->lower_margin +
512 var->vsync_len;
513
514 if (var->sync & FB_SYNC_BROADCAST) {
515 if (var->vmode & FB_VMODE_INTERLACED)
516 vtotal /= 2;
517 if (vtotal > (PAL_VTOTAL + NTSC_VTOTAL)/2) {
518 /* PAL video output */
519 /* XXX: Should be using a range here ... ? */
520 if (hsync_total != PAL_HTOTAL) {
521 pr_debug("invalid hsync total for PAL\n");
522 return -EINVAL;
523 }
524 } else {
525 /* NTSC video output */
526 if (hsync_total != NTSC_HTOTAL) {
527 pr_debug("invalid hsync total for NTSC\n");
528 return -EINVAL;
529 }
530 }
531 }
e9705a77 532
1da177e4
LT		 533 /* Check memory sizes */
534 line_length = get_line_length(var->xres_virtual, var->bits_per_pixel);
535 if (line_length * var->yres_virtual > info->fix.smem_len)
536 return -ENOMEM;
537
538 return 0;
539}
540
541static void pvr2_update_display(struct fb_info *info)
542{
543 struct pvr2fb_par *par = (struct pvr2fb_par *) info->par;
544 struct fb_var_screeninfo *var = &info->var;
545
546 /* Update the start address of the display image */
547 fb_writel(par->disp_start, DISP_DIWADDRL);
548 fb_writel(par->disp_start +
549 get_line_length(var->xoffset+var->xres, var->bits_per_pixel),
550 DISP_DIWADDRS);
551}
552
e9705a77 553/*
1da177e4
LT		 554 * Initialize the video mode. Currently, the 16bpp and 24bpp modes aren't
555 * very stable. It's probably due to the fact that a lot of the 2D video
556 * registers are still undocumented.
557 */
558
559static void pvr2_init_display(struct fb_info *info)
560{
561 struct pvr2fb_par *par = (struct pvr2fb_par *) info->par;
562 struct fb_var_screeninfo *var = &info->var;
563 unsigned int diw_height, diw_width, diw_modulo = 1;
564 unsigned int bytesperpixel = var->bits_per_pixel >> 3;
565
566 /* hsync and vsync totals */
567 fb_writel((par->vsync_total << 16) | par->hsync_total, DISP_SYNCSIZE);
568
569 /* column height, modulo, row width */
570 /* since we're "panning" within vram, we need to offset things based
571 * on the offset from the virtual x start to our real gfx. */
572 if (video_output != VO_VGA && par->is_interlaced)
573 diw_modulo += info->fix.line_length / 4;
574 diw_height = (par->is_interlaced ? var->yres / 2 : var->yres);
575 diw_width = get_line_length(var->xres, var->bits_per_pixel) / 4;
576 fb_writel((diw_modulo << 20) | (--diw_height << 10) | --diw_width,
577 DISP_DIWSIZE);
578
579 /* display address, long and short fields */
580 fb_writel(par->disp_start, DISP_DIWADDRL);
581 fb_writel(par->disp_start +
582 get_line_length(var->xoffset+var->xres, var->bits_per_pixel),
583 DISP_DIWADDRS);
584
585 /* border horizontal, border vertical, border color */
586 fb_writel((par->borderstart_h << 16) | par->borderstop_h, DISP_BRDRHORZ);
587 fb_writel((par->borderstart_v << 16) | par->borderstop_v, DISP_BRDRVERT);
588 fb_writel(0, DISP_BRDRCOLR);
589
590 /* display window start position */
591 fb_writel(par->diwstart_h, DISP_DIWHSTRT);
592 fb_writel((par->diwstart_v << 16) | par->diwstart_v, DISP_DIWVSTRT);
e9705a77 593
1da177e4
LT		 594 /* misc. settings */
595 fb_writel((0x16 << 16) | par->is_lowres, DISP_DIWCONF);
596
597 /* clock doubler (for VGA), scan doubler, display enable */
e9705a77 598 fb_writel(((video_output == VO_VGA) << 23) |
1da177e4
LT		 599 (par->is_doublescan << 1) | 1, DISP_DIWMODE);
600
601 /* bits per pixel */
602 fb_writel(fb_readl(DISP_DIWMODE) | (--bytesperpixel << 2), DISP_DIWMODE);
603
e9705a77 604 /* video enable, color sync, interlace,
1da177e4
LT		 605 * hsync and vsync polarity (currently unused) */
606 fb_writel(0x100 | ((par->is_interlaced /*|4*/) << 4), DISP_SYNCCONF);
607}
608
609/* Simulate blanking by making the border cover the entire screen */
610
611#define BLANK_BIT (1<<3)
612
613static void pvr2_do_blank(void)
614{
615 struct pvr2fb_par *par = currentpar;
616 unsigned long diwconf;
617
618 diwconf = fb_readl(DISP_DIWCONF);
619 if (do_blank > 0)
620 fb_writel(diwconf | BLANK_BIT, DISP_DIWCONF);
621 else
622 fb_writel(diwconf & ~BLANK_BIT, DISP_DIWCONF);
623
624 is_blanked = do_blank > 0 ? do_blank : 0;
625}
626
7d12e780 627static irqreturn_t pvr2fb_interrupt(int irq, void *dev_id)
1da177e4
LT		 628{
629 struct fb_info *info = dev_id;
630
631 if (do_vmode_pan || do_vmode_full)
632 pvr2_update_display(info);
633 if (do_vmode_full)
634 pvr2_init_display(info);
635 if (do_vmode_pan)
636 do_vmode_pan = 0;
637 if (do_vmode_full)
638 do_vmode_full = 0;
639 if (do_blank) {
640 pvr2_do_blank();
641 do_blank = 0;
642 }
643 return IRQ_HANDLED;
644}
645
646/*
647 * Determine the cable type and initialize the cable output format. Don't do
648 * anything if the cable type has been overidden (via "cable:XX").
649 */
650
651#define PCTRA 0xff80002c
652#define PDTRA 0xff800030
653#define VOUTC 0xa0702c00
654
655static int pvr2_init_cable(void)
656{
657 if (cable_type < 0) {
e9705a77 658 fb_writel((fb_readl(PCTRA) & 0xfff0ffff) | 0x000a0000,
1da177e4
LT		 659 PCTRA);
660 cable_type = (fb_readw(PDTRA) >> 8) & 3;
661 }
662
663 /* Now select the output format (either composite or other) */
664 /* XXX: Save the previous val first, as this reg is also AICA
665 related */
666 if (cable_type == CT_COMPOSITE)
667 fb_writel(3 << 8, VOUTC);
668 else
669 fb_writel(0, VOUTC);
670
671 return cable_type;
672}
673
674#ifdef CONFIG_SH_DMA
3f9b0880 675static ssize_t pvr2fb_write(struct fb_info *info, const char *buf,
1da177e4
LT		 676 size_t count, loff_t *ppos)
677{
678 unsigned long dst, start, end, len;
679 unsigned int nr_pages;
680 struct page **pages;
681 int ret, i;
682
683 nr_pages = (count + PAGE_SIZE - 1) >> PAGE_SHIFT;
684
685 pages = kmalloc(nr_pages * sizeof(struct page *), GFP_KERNEL);
686 if (!pages)
687 return -ENOMEM;
e9705a77 688
1da177e4
LT		 689 down_read(&current->mm->mmap_sem);
690 ret = get_user_pages(current, current->mm, (unsigned long)buf,
691 nr_pages, WRITE, 0, pages, NULL);
692 up_read(&current->mm->mmap_sem);
693
694 if (ret < nr_pages) {
695 nr_pages = ret;
696 ret = -EINVAL;
697 goto out_unmap;
698 }
699
700 dma_configure_channel(shdma, 0x12c1);
e9705a77 701
1da177e4
LT		 702 dst = (unsigned long)fb_info->screen_base + *ppos;
703 start = (unsigned long)page_address(pages[0]);
704 end = (unsigned long)page_address(pages[nr_pages]);
705 len = nr_pages << PAGE_SHIFT;
706
707 /* Half-assed contig check */
708 if (start + len == end) {
709 /* As we do this in one shot, it's either all or nothing.. */
710 if ((*ppos + len) > fb_info->fix.smem_len) {
711 ret = -ENOSPC;
712 goto out_unmap;
713 }
714
715 dma_write(shdma, start, 0, len);
716 dma_write(pvr2dma, 0, dst, len);
717 dma_wait_for_completion(pvr2dma);
718
719 goto out;
720 }
721
722 /* Not contiguous, writeout per-page instead.. */
723 for (i = 0; i < nr_pages; i++, dst += PAGE_SIZE) {
724 if ((*ppos + (i << PAGE_SHIFT)) > fb_info->fix.smem_len) {
725 ret = -ENOSPC;
726 goto out_unmap;
727 }
728
729 dma_write_page(shdma, (unsigned long)page_address(pages[i]), 0);
730 dma_write_page(pvr2dma, 0, dst);
731 dma_wait_for_completion(pvr2dma);
732 }
733
734out:
735 *ppos += count;
736 ret = count;
737
738out_unmap:
739 for (i = 0; i < nr_pages; i++)
740 page_cache_release(pages[i]);
741
742 kfree(pages);
743
744 return ret;
e9705a77 745}
1da177e4
LT		 746#endif /* CONFIG_SH_DMA */
747
748/**
749 * pvr2fb_common_init
750 *
751 * Common init code for the PVR2 chips.
752 *
753 * This mostly takes care of the common aspects of the fb setup and
754 * registration. It's expected that the board-specific init code has
755 * already setup pvr2_fix with something meaningful at this point.
756 *
757 * Device info reporting is also done here, as well as picking a sane
758 * default from the modedb. For board-specific modelines, simply define
759 * a per-board modedb.
760 *
761 * Also worth noting is that the cable and video output types are likely
762 * always going to be VGA for the PCI-based PVR2 boards, but we leave this
763 * in for flexibility anyways. Who knows, maybe someone has tv-out on a
764 * PCI-based version of these things ;-)
765 */
7e7ec0d4 766static int __devinit pvr2fb_common_init(void)
1da177e4
LT		 767{
768 struct pvr2fb_par *par = currentpar;
769 unsigned long modememused, rev;
770
771 fb_info->screen_base = ioremap_nocache(pvr2_fix.smem_start,
772 pvr2_fix.smem_len);
e9705a77 773
1da177e4
LT		 774 if (!fb_info->screen_base) {
775 printk(KERN_ERR "pvr2fb: Failed to remap smem space\n");
776 goto out_err;
777 }
778
779 par->mmio_base = (unsigned long)ioremap_nocache(pvr2_fix.mmio_start,
e9705a77 780 pvr2_fix.mmio_len);
1da177e4
LT		 781 if (!par->mmio_base) {
782 printk(KERN_ERR "pvr2fb: Failed to remap mmio space\n");
783 goto out_err;
784 }
785
d2b06a8b 786 fb_memset(fb_info->screen_base, 0, pvr2_fix.smem_len);
1da177e4
LT		 787
788 pvr2_fix.ypanstep = nopan ? 0 : 1;
789 pvr2_fix.ywrapstep = nowrap ? 0 : 1;
790
791 fb_info->fbops = &pvr2fb_ops;
792 fb_info->fix = pvr2_fix;
793 fb_info->par = currentpar;
9cd1c674 794 fb_info->pseudo_palette = currentpar->palette;
1da177e4
LT		 795 fb_info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
796
797 if (video_output == VO_VGA)
798 defmode = DEFMODE_VGA;
799
800 if (!mode_option)
801 mode_option = "640x480@60";
802
803 if (!fb_find_mode(&fb_info->var, fb_info, mode_option, pvr2_modedb,
804 NUM_TOTAL_MODES, &pvr2_modedb[defmode], 16))
805 fb_info->var = pvr2_var;
806
807 fb_alloc_cmap(&fb_info->cmap, 256, 0);
808
809 if (register_framebuffer(fb_info) < 0)
810 goto out_err;
811
812 modememused = get_line_length(fb_info->var.xres_virtual,
813 fb_info->var.bits_per_pixel);
814 modememused *= fb_info->var.yres_virtual;
815
816 rev = fb_readl(par->mmio_base + 0x04);
817
818 printk("fb%d: %s (rev %ld.%ld) frame buffer device, using %ldk/%ldk of video memory\n",
819 fb_info->node, fb_info->fix.id, (rev >> 4) & 0x0f, rev & 0x0f,
820 modememused >> 10, (unsigned long)(fb_info->fix.smem_len >> 10));
e9705a77 821 printk("fb%d: Mode %dx%d-%d pitch = %ld cable: %s video output: %s\n",
1da177e4 822 fb_info->node, fb_info->var.xres, fb_info->var.yres,
d2b06a8b 823 fb_info->var.bits_per_pixel,
1da177e4
LT		 824 get_line_length(fb_info->var.xres, fb_info->var.bits_per_pixel),
825 (char *)pvr2_get_param(cables, NULL, cable_type, 3),
826 (char *)pvr2_get_param(outputs, NULL, video_output, 3));
827
828#ifdef CONFIG_SH_STORE_QUEUES
829 printk(KERN_NOTICE "fb%d: registering with SQ API\n", fb_info->node);
830
831 pvr2fb_map = sq_remap(fb_info->fix.smem_start, fb_info->fix.smem_len,
d2b06a8b 832 fb_info->fix.id, pgprot_val(PAGE_SHARED));
1da177e4
LT		 833
834 printk(KERN_NOTICE "fb%d: Mapped video memory to SQ addr 0x%lx\n",
d2b06a8b 835 fb_info->node, pvr2fb_map);
1da177e4
LT		 836#endif
837
838 return 0;
839
840out_err:
841 if (fb_info->screen_base)
842 iounmap(fb_info->screen_base);
843 if (par->mmio_base)
844 iounmap((void *)par->mmio_base);
845
846 return -ENXIO;
847}
848
849#ifdef CONFIG_SH_DREAMCAST
850static int __init pvr2fb_dc_init(void)
851{
852 if (!mach_is_dreamcast())
853 return -ENXIO;
854
855 /* Make a guess at the monitor based on the attached cable */
856 if (pvr2_init_cable() == CT_VGA) {
857 fb_info->monspecs.hfmin = 30000;
858 fb_info->monspecs.hfmax = 70000;
859 fb_info->monspecs.vfmin = 60;
860 fb_info->monspecs.vfmax = 60;
861 } else {
862 /* Not VGA, using a TV (taken from acornfb) */
863 fb_info->monspecs.hfmin = 15469;
864 fb_info->monspecs.hfmax = 15781;
865 fb_info->monspecs.vfmin = 49;
866 fb_info->monspecs.vfmax = 51;
867 }
868
869 /*
870 * XXX: This needs to pull default video output via BIOS or other means
871 */
872 if (video_output < 0) {
873 if (cable_type == CT_VGA) {
874 video_output = VO_VGA;
875 } else {
876 video_output = VO_NTSC;
877 }
878 }
e9705a77
PM		 879
880 /*
1da177e4
LT		 881 * Nothing exciting about the DC PVR2 .. only a measly 8MiB.
882 */
883 pvr2_fix.smem_start = 0xa5000000; /* RAM starts here */
884 pvr2_fix.smem_len = 8 << 20;
885
886 pvr2_fix.mmio_start = 0xa05f8000; /* registers start here */
887 pvr2_fix.mmio_len = 0x2000;
888
889 if (request_irq(HW_EVENT_VSYNC, pvr2fb_interrupt, 0,
890 "pvr2 VBL handler", fb_info)) {
891 return -EBUSY;
892 }
893
894#ifdef CONFIG_SH_DMA
895 if (request_dma(pvr2dma, "pvr2") != 0) {
896 free_irq(HW_EVENT_VSYNC, 0);
897 return -EBUSY;
898 }
899#endif
900
901 return pvr2fb_common_init();
902}
903
e9705a77 904static void __exit pvr2fb_dc_exit(void)
1da177e4 905{
295a1b47
AL		 906 if (fb_info->screen_base) {
907 iounmap(fb_info->screen_base);
908 fb_info->screen_base = NULL;
909 }
910 if (currentpar->mmio_base) {
911 iounmap((void *)currentpar->mmio_base);
912 currentpar->mmio_base = 0;
913 }
914
1da177e4
LT		 915 free_irq(HW_EVENT_VSYNC, 0);
916#ifdef CONFIG_SH_DMA
917 free_dma(pvr2dma);
918#endif
919}
920#endif /* CONFIG_SH_DREAMCAST */
921
922#ifdef CONFIG_PCI
923static int __devinit pvr2fb_pci_probe(struct pci_dev *pdev,
924 const struct pci_device_id *ent)
925{
926 int ret;
927
928 ret = pci_enable_device(pdev);
929 if (ret) {
930 printk(KERN_ERR "pvr2fb: PCI enable failed\n");
931 return ret;
932 }
933
934 ret = pci_request_regions(pdev, "pvr2fb");
935 if (ret) {
936 printk(KERN_ERR "pvr2fb: PCI request regions failed\n");
937 return ret;
938 }
939
940 /*
941 * Slightly more exciting than the DC PVR2 .. 16MiB!
942 */
943 pvr2_fix.smem_start = pci_resource_start(pdev, 0);
944 pvr2_fix.smem_len = pci_resource_len(pdev, 0);
945
946 pvr2_fix.mmio_start = pci_resource_start(pdev, 1);
947 pvr2_fix.mmio_len = pci_resource_len(pdev, 1);
948
949 fb_info->device = &pdev->dev;
950
951 return pvr2fb_common_init();
952}
953
954static void __devexit pvr2fb_pci_remove(struct pci_dev *pdev)
955{
295a1b47
AL		 956 if (fb_info->screen_base) {
957 iounmap(fb_info->screen_base);
958 fb_info->screen_base = NULL;
959 }
960 if (currentpar->mmio_base) {
961 iounmap((void *)currentpar->mmio_base);
962 currentpar->mmio_base = 0;
963 }
964
1da177e4
LT		 965 pci_release_regions(pdev);
966}
967
968static struct pci_device_id pvr2fb_pci_tbl[] __devinitdata = {
969 { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NEON250,
970 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
971 { 0, },
972};
973
974MODULE_DEVICE_TABLE(pci, pvr2fb_pci_tbl);
975
976static struct pci_driver pvr2fb_pci_driver = {
977 .name = "pvr2fb",
978 .id_table = pvr2fb_pci_tbl,
979 .probe = pvr2fb_pci_probe,
980 .remove = __devexit_p(pvr2fb_pci_remove),
981};
982
983static int __init pvr2fb_pci_init(void)
984{
985 return pci_register_driver(&pvr2fb_pci_driver);
986}
987
e9705a77 988static void __exit pvr2fb_pci_exit(void)
1da177e4
LT		 989{
990 pci_unregister_driver(&pvr2fb_pci_driver);
991}
992#endif /* CONFIG_PCI */
993
7e7ec0d4 994static int __devinit pvr2_get_param(const struct pvr2_params *p, const char *s,
1da177e4
LT		 995 int val, int size)
996{
997 int i;
998
999 for (i = 0 ; i < size ; i++ ) {
1000 if (s != NULL) {
1001 if (!strnicmp(p[i].name, s, strlen(s)))
1002 return p[i].val;
1003 } else {
1004 if (p[i].val == val)
1005 return (int)p[i].name;
1006 }
1007 }
1008 return -1;
1009}
1010
1011/*
1012 * Parse command arguments. Supported arguments are:
1013 * inverse Use inverse color maps
1014 * cable:composite|rgb|vga Override the video cable type
1015 * output:NTSC|PAL|VGA Override the video output format
1016 *
1017 * <xres>x<yres>[-<bpp>][@<refresh>] or,
1018 * <name>[-<bpp>][@<refresh>] Startup using this video mode
1019 */
1020
1021#ifndef MODULE
e9705a77 1022static int __init pvr2fb_setup(char *options)
1da177e4
LT		 1023{
1024 char *this_opt;
1025 char cable_arg[80];
1026 char output_arg[80];
1027
1028 if (!options || !*options)
1029 return 0;
1030
1031 while ((this_opt = strsep(&options, ","))) {
1032 if (!*this_opt)
1033 continue;
1034 if (!strcmp(this_opt, "inverse")) {
1035 fb_invert_cmaps();
1036 } else if (!strncmp(this_opt, "cable:", 6)) {
1037 strcpy(cable_arg, this_opt + 6);
1038 } else if (!strncmp(this_opt, "output:", 7)) {
1039 strcpy(output_arg, this_opt + 7);
1040 } else if (!strncmp(this_opt, "nopan", 5)) {
1041 nopan = 1;
1042 } else if (!strncmp(this_opt, "nowrap", 6)) {
1043 nowrap = 1;
1044 } else {
1045 mode_option = this_opt;
1046 }
1047 }
1048
1049 if (*cable_arg)
1050 cable_type = pvr2_get_param(cables, cable_arg, 0, 3);
1051 if (*output_arg)
1052 video_output = pvr2_get_param(outputs, output_arg, 0, 3);
1053
1054 return 0;
1055}
1056#endif
1057
1058static struct pvr2_board {
1059 int (*init)(void);
1060 void (*exit)(void);
1061 char name[16];
e9705a77 1062} board_driver[] = {
1da177e4
LT		 1063#ifdef CONFIG_SH_DREAMCAST
1064 { pvr2fb_dc_init, pvr2fb_dc_exit, "Sega DC PVR2" },
1065#endif
1066#ifdef CONFIG_PCI
1067 { pvr2fb_pci_init, pvr2fb_pci_exit, "PCI PVR2" },
1068#endif
1069 { 0, },
1070};
1071
e9705a77 1072static int __init pvr2fb_init(void)
1da177e4
LT		 1073{
1074 int i, ret = -ENODEV;
1075 int size;
1076
1077#ifndef MODULE
1078 char *option = NULL;
1079
1080 if (fb_get_options("pvr2fb", &option))
1081 return -ENODEV;
1082 pvr2fb_setup(option);
1083#endif
1084 size = sizeof(struct fb_info) + sizeof(struct pvr2fb_par) + 16 * sizeof(u32);
1085
9cd1c674
AD		 1086 fb_info = framebuffer_alloc(sizeof(struct pvr2fb_par), NULL);
1087
1da177e4
LT		 1088 if (!fb_info) {
1089 printk(KERN_ERR "Failed to allocate memory for fb_info\n");
1090 return -ENOMEM;
1091 }
1092
1da177e4 1093
9cd1c674 1094 currentpar = fb_info->par;
1da177e4 1095
e9705a77
PM		 1096 for (i = 0; i < ARRAY_SIZE(board_driver); i++) {
1097 struct pvr2_board *pvr_board = board_driver + i;
1da177e4
LT		 1098
1099 if (!pvr_board->init)
1100 continue;
1101
1102 ret = pvr_board->init();
1103
1104 if (ret != 0) {
1105 printk(KERN_ERR "pvr2fb: Failed init of %s device\n",
1106 pvr_board->name);
9cd1c674 1107 framebuffer_release(fb_info);
1da177e4
LT		 1108 break;
1109 }
1110 }
1111
1112 return ret;
1113}
1114
1115static void __exit pvr2fb_exit(void)
1116{
1117 int i;
1118
e9705a77
PM		 1119 for (i = 0; i < ARRAY_SIZE(board_driver); i++) {
1120 struct pvr2_board *pvr_board = board_driver + i;
1da177e4
LT		 1121
1122 if (pvr_board->exit)
1123 pvr_board->exit();
1124 }
e9705a77 1125
1da177e4
LT		 1126#ifdef CONFIG_SH_STORE_QUEUES
1127 sq_unmap(pvr2fb_map);
1128#endif
1129
1130 unregister_framebuffer(fb_info);
9cd1c674 1131 framebuffer_release(fb_info);
1da177e4
LT		 1132}
1133
1134module_init(pvr2fb_init);
1135module_exit(pvr2fb_exit);
1136
1137MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>, M. R. Brown <mrbrown@0xd6.org>");
1138MODULE_DESCRIPTION("Framebuffer driver for NEC PowerVR 2 based graphics boards");
1139MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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