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video: s3c-fb: Make runtime PM functional again
[deliverable/linux.git] / drivers / video / pxafb.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/video/pxafb.c
3 *
4 * Copyright (C) 1999 Eric A. Thomas.
5 * Copyright (C) 2004 Jean-Frederic Clere.
6 * Copyright (C) 2004 Ian Campbell.
7 * Copyright (C) 2004 Jeff Lackey.
8 * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
9 * which in turn is
10 * Based on acornfb.c Copyright (C) Russell King.
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file COPYING in the main directory of this archive for
14 * more details.
15 *
16 * Intel PXA250/210 LCD Controller Frame Buffer Driver
17 *
18 * Please direct your questions and comments on this driver to the following
19 * email address:
20 *
21 * linux-arm-kernel@lists.arm.linux.org.uk
22 *
198fc108
EM		 23 * Add support for overlay1 and overlay2 based on pxafb_overlay.c:
24 *
25 * Copyright (C) 2004, Intel Corporation
26 *
27 * 2003/08/27: <yu.tang@intel.com>
28 * 2004/03/10: <stanley.cai@intel.com>
29 * 2004/10/28: <yan.yin@intel.com>
30 *
31 * Copyright (C) 2006-2008 Marvell International Ltd.
32 * All Rights Reserved
1da177e4
LT		 33 */
34
1da177e4
LT		 35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/kernel.h>
38#include <linux/sched.h>
39#include <linux/errno.h>
40#include <linux/string.h>
41#include <linux/interrupt.h>
42#include <linux/slab.h>
27ac792c 43#include <linux/mm.h>
1da177e4
LT		 44#include <linux/fb.h>
45#include <linux/delay.h>
46#include <linux/init.h>
47#include <linux/ioport.h>
48#include <linux/cpufreq.h>
d052d1be 49#include <linux/platform_device.h>
1da177e4 50#include <linux/dma-mapping.h>
72e3524c
RK		 51#include <linux/clk.h>
52#include <linux/err.h>
2ba162b9 53#include <linux/completion.h>
b91dbce5 54#include <linux/mutex.h>
3c42a449
EM		 55#include <linux/kthread.h>
56#include <linux/freezer.h>
1da177e4 57
a09e64fb 58#include <mach/hardware.h>
1da177e4
LT		 59#include <asm/io.h>
60#include <asm/irq.h>
bf1b8ab6 61#include <asm/div64.h>
a09e64fb
RK		 62#include <mach/bitfield.h>
63#include <mach/pxafb.h>
1da177e4
LT		 64
65/*
66 * Complain if VAR is out of range.
67 */
68#define DEBUG_VAR 1
69
70#include "pxafb.h"
71
72/* Bits which should not be set in machine configuration structures */
b0086efb 73#define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\
74 LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\
75 LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
76
77#define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\
878f5783 78 LCCR3_PCD | LCCR3_BPP(0xf))
1da177e4 79
b0086efb 80static int pxafb_activate_var(struct fb_var_screeninfo *var,
81 struct pxafb_info *);
1da177e4 82static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
448ac479
SN		 83static void setup_base_frame(struct pxafb_info *fbi,
84 struct fb_var_screeninfo *var, int branch);
198fc108
EM		 85static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
86 unsigned long offset, size_t size);
1da177e4 87
77e19675 88static unsigned long video_mem_size = 0;
1da177e4 89
a7535ba7
EM		 90static inline unsigned long
91lcd_readl(struct pxafb_info *fbi, unsigned int off)
92{
93 return __raw_readl(fbi->mmio_base + off);
94}
95
96static inline void
97lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val)
98{
99 __raw_writel(val, fbi->mmio_base + off);
100}
101
1da177e4
LT		 102static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
103{
104 unsigned long flags;
105
106 local_irq_save(flags);
107 /*
108 * We need to handle two requests being made at the same time.
109 * There are two important cases:
b0086efb 110 * 1. When we are changing VT (C_REENABLE) while unblanking
111 * (C_ENABLE) We must perform the unblanking, which will
112 * do our REENABLE for us.
113 * 2. When we are blanking, but immediately unblank before
114 * we have blanked. We do the "REENABLE" thing here as
115 * well, just to be sure.
1da177e4
LT		 116 */
117 if (fbi->task_state == C_ENABLE && state == C_REENABLE)
118 state = (u_int) -1;
119 if (fbi->task_state == C_DISABLE && state == C_ENABLE)
120 state = C_REENABLE;
121
122 if (state != (u_int)-1) {
123 fbi->task_state = state;
124 schedule_work(&fbi->task);
125 }
126 local_irq_restore(flags);
127}
128
129static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
130{
131 chan &= 0xffff;
132 chan >>= 16 - bf->length;
133 return chan << bf->offset;
134}
135
136static int
137pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
138 u_int trans, struct fb_info *info)
139{
140 struct pxafb_info *fbi = (struct pxafb_info *)info;
9ffa7396
HK		 141 u_int val;
142
143 if (regno >= fbi->palette_size)
144 return 1;
145
146 if (fbi->fb.var.grayscale) {
147 fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff);
148 return 0;
149 }
150
151 switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) {
152 case LCCR4_PAL_FOR_0:
153 val = ((red >> 0) & 0xf800);
154 val |= ((green >> 5) & 0x07e0);
155 val |= ((blue >> 11) & 0x001f);
1da177e4 156 fbi->palette_cpu[regno] = val;
9ffa7396
HK		 157 break;
158 case LCCR4_PAL_FOR_1:
159 val = ((red << 8) & 0x00f80000);
160 val |= ((green >> 0) & 0x0000fc00);
161 val |= ((blue >> 8) & 0x000000f8);
b0086efb 162 ((u32 *)(fbi->palette_cpu))[regno] = val;
9ffa7396
HK		 163 break;
164 case LCCR4_PAL_FOR_2:
165 val = ((red << 8) & 0x00fc0000);
166 val |= ((green >> 0) & 0x0000fc00);
167 val |= ((blue >> 8) & 0x000000fc);
b0086efb 168 ((u32 *)(fbi->palette_cpu))[regno] = val;
9ffa7396 169 break;
a0427509
EM		 170 case LCCR4_PAL_FOR_3:
171 val = ((red << 8) & 0x00ff0000);
172 val |= ((green >> 0) & 0x0000ff00);
173 val |= ((blue >> 8) & 0x000000ff);
174 ((u32 *)(fbi->palette_cpu))[regno] = val;
175 break;
1da177e4 176 }
9ffa7396
HK		 177
178 return 0;
1da177e4
LT		 179}
180
181static int
182pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
183 u_int trans, struct fb_info *info)
184{
185 struct pxafb_info *fbi = (struct pxafb_info *)info;
186 unsigned int val;
187 int ret = 1;
188
189 /*
190 * If inverse mode was selected, invert all the colours
191 * rather than the register number. The register number
192 * is what you poke into the framebuffer to produce the
193 * colour you requested.
194 */
195 if (fbi->cmap_inverse) {
196 red = 0xffff - red;
197 green = 0xffff - green;
198 blue = 0xffff - blue;
199 }
200
201 /*
202 * If greyscale is true, then we convert the RGB value
203 * to greyscale no matter what visual we are using.
204 */
205 if (fbi->fb.var.grayscale)
206 red = green = blue = (19595 * red + 38470 * green +
207 7471 * blue) >> 16;
208
209 switch (fbi->fb.fix.visual) {
210 case FB_VISUAL_TRUECOLOR:
211 /*
212 * 16-bit True Colour. We encode the RGB value
213 * according to the RGB bitfield information.
214 */
215 if (regno < 16) {
216 u32 *pal = fbi->fb.pseudo_palette;
217
218 val = chan_to_field(red, &fbi->fb.var.red);
219 val |= chan_to_field(green, &fbi->fb.var.green);
220 val |= chan_to_field(blue, &fbi->fb.var.blue);
221
222 pal[regno] = val;
223 ret = 0;
224 }
225 break;
226
227 case FB_VISUAL_STATIC_PSEUDOCOLOR:
228 case FB_VISUAL_PSEUDOCOLOR:
229 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
230 break;
231 }
232
233 return ret;
234}
235
878f5783
EM		 236/* calculate pixel depth, transparency bit included, >=16bpp formats _only_ */
237static inline int var_to_depth(struct fb_var_screeninfo *var)
1da177e4 238{
878f5783
EM		 239 return var->red.length + var->green.length +
240 var->blue.length + var->transp.length;
241}
242
243/* calculate 4-bit BPP value for LCCR3 and OVLxC1 */
244static int pxafb_var_to_bpp(struct fb_var_screeninfo *var)
245{
246 int bpp = -EINVAL;
247
b0086efb 248 switch (var->bits_per_pixel) {
878f5783
EM		 249 case 1: bpp = 0; break;
250 case 2: bpp = 1; break;
251 case 4: bpp = 2; break;
252 case 8: bpp = 3; break;
253 case 16: bpp = 4; break;
c1450f15 254 case 24:
878f5783
EM		 255 switch (var_to_depth(var)) {
256 case 18: bpp = 6; break; /* 18-bits/pixel packed */
257 case 19: bpp = 8; break; /* 19-bits/pixel packed */
258 case 24: bpp = 9; break;
c1450f15
SS		 259 }
260 break;
261 case 32:
878f5783
EM		 262 switch (var_to_depth(var)) {
263 case 18: bpp = 5; break; /* 18-bits/pixel unpacked */
264 case 19: bpp = 7; break; /* 19-bits/pixel unpacked */
265 case 25: bpp = 10; break;
c1450f15
SS		 266 }
267 break;
b0086efb 268 }
878f5783
EM		 269 return bpp;
270}
271
272/*
273 * pxafb_var_to_lccr3():
274 * Convert a bits per pixel value to the correct bit pattern for LCCR3
275 *
276 * NOTE: for PXA27x with overlays support, the LCCR3_PDFOR_x bits have an
277 * implication of the acutal use of transparency bit, which we handle it
278 * here separatedly. See PXA27x Developer's Manual, Section <<7.4.6 Pixel
279 * Formats>> for the valid combination of PDFOR, PAL_FOR for various BPP.
280 *
281 * Transparency for palette pixel formats is not supported at the moment.
282 */
283static uint32_t pxafb_var_to_lccr3(struct fb_var_screeninfo *var)
284{
285 int bpp = pxafb_var_to_bpp(var);
286 uint32_t lccr3;
287
288 if (bpp < 0)
289 return 0;
290
291 lccr3 = LCCR3_BPP(bpp);
292
293 switch (var_to_depth(var)) {
294 case 16: lccr3 |= var->transp.length ? LCCR3_PDFOR_3 : 0; break;
295 case 18: lccr3 |= LCCR3_PDFOR_3; break;
296 case 24: lccr3 |= var->transp.length ? LCCR3_PDFOR_2 : LCCR3_PDFOR_3;
297 break;
298 case 19:
299 case 25: lccr3 |= LCCR3_PDFOR_0; break;
300 }
301 return lccr3;
302}
303
304#define SET_PIXFMT(v, r, g, b, t) \
305({ \
306 (v)->transp.offset = (t) ? (r) + (g) + (b) : 0; \
307 (v)->transp.length = (t) ? (t) : 0; \
308 (v)->blue.length = (b); (v)->blue.offset = 0; \
309 (v)->green.length = (g); (v)->green.offset = (b); \
310 (v)->red.length = (r); (v)->red.offset = (b) + (g); \
311})
312
313/* set the RGBT bitfields of fb_var_screeninf according to
314 * var->bits_per_pixel and given depth
315 */
316static void pxafb_set_pixfmt(struct fb_var_screeninfo *var, int depth)
317{
318 if (depth == 0)
319 depth = var->bits_per_pixel;
320
321 if (var->bits_per_pixel < 16) {
322 /* indexed pixel formats */
323 var->red.offset = 0; var->red.length = 8;
324 var->green.offset = 0; var->green.length = 8;
325 var->blue.offset = 0; var->blue.length = 8;
326 var->transp.offset = 0; var->transp.length = 8;
327 }
328
329 switch (depth) {
330 case 16: var->transp.length ?
331 SET_PIXFMT(var, 5, 5, 5, 1) : /* RGBT555 */
332 SET_PIXFMT(var, 5, 6, 5, 0); break; /* RGB565 */
333 case 18: SET_PIXFMT(var, 6, 6, 6, 0); break; /* RGB666 */
334 case 19: SET_PIXFMT(var, 6, 6, 6, 1); break; /* RGBT666 */
335 case 24: var->transp.length ?
336 SET_PIXFMT(var, 8, 8, 7, 1) : /* RGBT887 */
337 SET_PIXFMT(var, 8, 8, 8, 0); break; /* RGB888 */
338 case 25: SET_PIXFMT(var, 8, 8, 8, 1); break; /* RGBT888 */
339 }
1da177e4
LT		 340}
341
342#ifdef CONFIG_CPU_FREQ
343/*
344 * pxafb_display_dma_period()
345 * Calculate the minimum period (in picoseconds) between two DMA
346 * requests for the LCD controller. If we hit this, it means we're
347 * doing nothing but LCD DMA.
348 */
349static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
350{
b0086efb 351 /*
352 * Period = pixclock * bits_per_byte * bytes_per_transfer
353 * / memory_bits_per_pixel;
354 */
355 return var->pixclock * 8 * 16 / var->bits_per_pixel;
1da177e4 356}
1da177e4
LT		 357#endif
358
d14b272b
RP		 359/*
360 * Select the smallest mode that allows the desired resolution to be
361 * displayed. If desired parameters can be rounded up.
362 */
b0086efb 363static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach,
364 struct fb_var_screeninfo *var)
d14b272b
RP		 365{
366 struct pxafb_mode_info *mode = NULL;
367 struct pxafb_mode_info *modelist = mach->modes;
368 unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
369 unsigned int i;
370
b0086efb 371 for (i = 0; i < mach->num_modes; i++) {
372 if (modelist[i].xres >= var->xres &&
373 modelist[i].yres >= var->yres &&
374 modelist[i].xres < best_x &&
375 modelist[i].yres < best_y &&
376 modelist[i].bpp >= var->bits_per_pixel) {
d14b272b
RP		 377 best_x = modelist[i].xres;
378 best_y = modelist[i].yres;
379 mode = &modelist[i];
380 }
381 }
382
383 return mode;
384}
385
b0086efb 386static void pxafb_setmode(struct fb_var_screeninfo *var,
387 struct pxafb_mode_info *mode)
d14b272b
RP		 388{
389 var->xres = mode->xres;
390 var->yres = mode->yres;
391 var->bits_per_pixel = mode->bpp;
392 var->pixclock = mode->pixclock;
393 var->hsync_len = mode->hsync_len;
394 var->left_margin = mode->left_margin;
395 var->right_margin = mode->right_margin;
396 var->vsync_len = mode->vsync_len;
397 var->upper_margin = mode->upper_margin;
398 var->lower_margin = mode->lower_margin;
399 var->sync = mode->sync;
400 var->grayscale = mode->cmap_greyscale;
049ad833 401 var->transp.length = mode->transparency;
878f5783
EM		 402
403 /* set the initial RGBA bitfields */
404 pxafb_set_pixfmt(var, mode->depth);
d14b272b
RP		 405}
406
3f16ff60
EM		 407static int pxafb_adjust_timing(struct pxafb_info *fbi,
408 struct fb_var_screeninfo *var)
409{
410 int line_length;
411
412 var->xres = max_t(int, var->xres, MIN_XRES);
413 var->yres = max_t(int, var->yres, MIN_YRES);
414
415 if (!(fbi->lccr0 & LCCR0_LCDT)) {
416 clamp_val(var->hsync_len, 1, 64);
417 clamp_val(var->vsync_len, 1, 64);
418 clamp_val(var->left_margin, 1, 255);
419 clamp_val(var->right_margin, 1, 255);
420 clamp_val(var->upper_margin, 1, 255);
421 clamp_val(var->lower_margin, 1, 255);
422 }
423
424 /* make sure each line is aligned on word boundary */
425 line_length = var->xres * var->bits_per_pixel / 8;
426 line_length = ALIGN(line_length, 4);
427 var->xres = line_length * 8 / var->bits_per_pixel;
428
429 /* we don't support xpan, force xres_virtual to be equal to xres */
430 var->xres_virtual = var->xres;
431
432 if (var->accel_flags & FB_ACCELF_TEXT)
433 var->yres_virtual = fbi->fb.fix.smem_len / line_length;
434 else
435 var->yres_virtual = max(var->yres_virtual, var->yres);
436
437 /* check for limits */
438 if (var->xres > MAX_XRES || var->yres > MAX_YRES)
439 return -EINVAL;
440
441 if (var->yres > var->yres_virtual)
442 return -EINVAL;
443
444 return 0;
d14b272b
RP		 445}
446
1da177e4
LT		 447/*
448 * pxafb_check_var():
449 * Get the video params out of 'var'. If a value doesn't fit, round it up,
450 * if it's too big, return -EINVAL.
451 *
452 * Round up in the following order: bits_per_pixel, xres,
453 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
454 * bitfields, horizontal timing, vertical timing.
455 */
456static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
457{
458 struct pxafb_info *fbi = (struct pxafb_info *)info;
d14b272b 459 struct pxafb_mach_info *inf = fbi->dev->platform_data;
878f5783 460 int err;
d14b272b
RP		 461
462 if (inf->fixed_modes) {
463 struct pxafb_mode_info *mode;
464
465 mode = pxafb_getmode(inf, var);
466 if (!mode)
467 return -EINVAL;
468 pxafb_setmode(var, mode);
d14b272b
RP		 469 }
470
878f5783
EM		 471 /* do a test conversion to BPP fields to check the color formats */
472 err = pxafb_var_to_bpp(var);
473 if (err < 0)
474 return err;
1da177e4 475
878f5783 476 pxafb_set_pixfmt(var, var_to_depth(var));
c1450f15 477
3f16ff60
EM		 478 err = pxafb_adjust_timing(fbi, var);
479 if (err)
480 return err;
1da177e4
LT		 481
482#ifdef CONFIG_CPU_FREQ
78d3cfd3
RK		 483 pr_debug("pxafb: dma period = %d ps\n",
484 pxafb_display_dma_period(var));
1da177e4
LT		 485#endif
486
487 return 0;
488}
489
1da177e4
LT		 490/*
491 * pxafb_set_par():
492 * Set the user defined part of the display for the specified console
493 */
494static int pxafb_set_par(struct fb_info *info)
495{
496 struct pxafb_info *fbi = (struct pxafb_info *)info;
497 struct fb_var_screeninfo *var = &info->var;
1da177e4 498
c1450f15 499 if (var->bits_per_pixel >= 16)
1da177e4
LT		 500 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
501 else if (!fbi->cmap_static)
502 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
503 else {
504 /*
505 * Some people have weird ideas about wanting static
506 * pseudocolor maps. I suspect their user space
507 * applications are broken.
508 */
509 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
510 }
511
512 fbi->fb.fix.line_length = var->xres_virtual *
513 var->bits_per_pixel / 8;
c1450f15 514 if (var->bits_per_pixel >= 16)
1da177e4
LT		 515 fbi->palette_size = 0;
516 else
b0086efb 517 fbi->palette_size = var->bits_per_pixel == 1 ?
518 4 : 1 << var->bits_per_pixel;
1da177e4 519
2c42dd8e 520 fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
1da177e4 521
c1450f15 522 if (fbi->fb.var.bits_per_pixel >= 16)
1da177e4
LT		 523 fb_dealloc_cmap(&fbi->fb.cmap);
524 else
525 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
526
527 pxafb_activate_var(var, fbi);
528
529 return 0;
530}
531
6e354846
EM		 532static int pxafb_pan_display(struct fb_var_screeninfo *var,
533 struct fb_info *info)
534{
535 struct pxafb_info *fbi = (struct pxafb_info *)info;
448ac479 536 struct fb_var_screeninfo newvar;
6e354846
EM		 537 int dma = DMA_MAX + DMA_BASE;
538
539 if (fbi->state != C_ENABLE)
540 return 0;
541
448ac479
SN		 542 /* Only take .xoffset, .yoffset and .vmode & FB_VMODE_YWRAP from what
543 * was passed in and copy the rest from the old screeninfo.
544 */
545 memcpy(&newvar, &fbi->fb.var, sizeof(newvar));
546 newvar.xoffset = var->xoffset;
547 newvar.yoffset = var->yoffset;
548 newvar.vmode &= ~FB_VMODE_YWRAP;
549 newvar.vmode |= var->vmode & FB_VMODE_YWRAP;
550
551 setup_base_frame(fbi, &newvar, 1);
6e354846
EM		 552
553 if (fbi->lccr0 & LCCR0_SDS)
554 lcd_writel(fbi, FBR1, fbi->fdadr[dma + 1] | 0x1);
555
556 lcd_writel(fbi, FBR0, fbi->fdadr[dma] | 0x1);
557 return 0;
558}
559
1da177e4
LT		 560/*
561 * pxafb_blank():
562 * Blank the display by setting all palette values to zero. Note, the
563 * 16 bpp mode does not really use the palette, so this will not
564 * blank the display in all modes.
565 */
566static int pxafb_blank(int blank, struct fb_info *info)
567{
568 struct pxafb_info *fbi = (struct pxafb_info *)info;
569 int i;
570
1da177e4
LT		 571 switch (blank) {
572 case FB_BLANK_POWERDOWN:
573 case FB_BLANK_VSYNC_SUSPEND:
574 case FB_BLANK_HSYNC_SUSPEND:
575 case FB_BLANK_NORMAL:
576 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
577 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
578 for (i = 0; i < fbi->palette_size; i++)
579 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
580
581 pxafb_schedule_work(fbi, C_DISABLE);
b0086efb 582 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
1da177e4
LT		 583 break;
584
585 case FB_BLANK_UNBLANK:
b0086efb 586 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
1da177e4
LT		 587 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
588 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
589 fb_set_cmap(&fbi->fb.cmap, info);
590 pxafb_schedule_work(fbi, C_ENABLE);
591 }
592 return 0;
593}
594
1da177e4
LT		 595static struct fb_ops pxafb_ops = {
596 .owner = THIS_MODULE,
597 .fb_check_var = pxafb_check_var,
598 .fb_set_par = pxafb_set_par,
6e354846 599 .fb_pan_display = pxafb_pan_display,
1da177e4
LT		 600 .fb_setcolreg = pxafb_setcolreg,
601 .fb_fillrect = cfb_fillrect,
602 .fb_copyarea = cfb_copyarea,
603 .fb_imageblit = cfb_imageblit,
604 .fb_blank = pxafb_blank,
1da177e4
LT		 605};
606
198fc108
EM		 607#ifdef CONFIG_FB_PXA_OVERLAY
608static void overlay1fb_setup(struct pxafb_layer *ofb)
609{
610 int size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual;
611 unsigned long start = ofb->video_mem_phys;
612 setup_frame_dma(ofb->fbi, DMA_OV1, PAL_NONE, start, size);
613}
614
615/* Depending on the enable status of overlay1/2, the DMA should be
616 * updated from FDADRx (when disabled) or FBRx (when enabled).
617 */
618static void overlay1fb_enable(struct pxafb_layer *ofb)
619{
620 int enabled = lcd_readl(ofb->fbi, OVL1C1) & OVLxC1_OEN;
621 uint32_t fdadr1 = ofb->fbi->fdadr[DMA_OV1] | (enabled ? 0x1 : 0);
622
623 lcd_writel(ofb->fbi, enabled ? FBR1 : FDADR1, fdadr1);
624 lcd_writel(ofb->fbi, OVL1C2, ofb->control[1]);
625 lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] | OVLxC1_OEN);
626}
627
628static void overlay1fb_disable(struct pxafb_layer *ofb)
629{
1b98d7c4
VK		 630 uint32_t lccr5;
631
632 if (!(lcd_readl(ofb->fbi, OVL1C1) & OVLxC1_OEN))
633 return;
634
635 lccr5 = lcd_readl(ofb->fbi, LCCR5);
198fc108
EM		 636
637 lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] & ~OVLxC1_OEN);
638
639 lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(1));
640 lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(1));
641 lcd_writel(ofb->fbi, FBR1, ofb->fbi->fdadr[DMA_OV1] | 0x3);
642
643 if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0)
644 pr_warning("%s: timeout disabling overlay1\n", __func__);
645
646 lcd_writel(ofb->fbi, LCCR5, lccr5);
647}
648
649static void overlay2fb_setup(struct pxafb_layer *ofb)
650{
651 int size, div = 1, pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd);
652 unsigned long start[3] = { ofb->video_mem_phys, 0, 0 };
653
654 if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED) {
655 size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual;
656 setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size);
657 } else {
658 size = ofb->fb.var.xres_virtual * ofb->fb.var.yres_virtual;
659 switch (pfor) {
660 case OVERLAY_FORMAT_YUV444_PLANAR: div = 1; break;
661 case OVERLAY_FORMAT_YUV422_PLANAR: div = 2; break;
662 case OVERLAY_FORMAT_YUV420_PLANAR: div = 4; break;
663 }
664 start[1] = start[0] + size;
665 start[2] = start[1] + size / div;
666 setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size);
667 setup_frame_dma(ofb->fbi, DMA_OV2_Cb, -1, start[1], size / div);
668 setup_frame_dma(ofb->fbi, DMA_OV2_Cr, -1, start[2], size / div);
669 }
670}
671
672static void overlay2fb_enable(struct pxafb_layer *ofb)
673{
674 int pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd);
675 int enabled = lcd_readl(ofb->fbi, OVL2C1) & OVLxC1_OEN;
676 uint32_t fdadr2 = ofb->fbi->fdadr[DMA_OV2_Y] | (enabled ? 0x1 : 0);
677 uint32_t fdadr3 = ofb->fbi->fdadr[DMA_OV2_Cb] | (enabled ? 0x1 : 0);
678 uint32_t fdadr4 = ofb->fbi->fdadr[DMA_OV2_Cr] | (enabled ? 0x1 : 0);
679
680 if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED)
681 lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2);
682 else {
683 lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2);
684 lcd_writel(ofb->fbi, enabled ? FBR3 : FDADR3, fdadr3);
685 lcd_writel(ofb->fbi, enabled ? FBR4 : FDADR4, fdadr4);
686 }
687 lcd_writel(ofb->fbi, OVL2C2, ofb->control[1]);
688 lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] | OVLxC1_OEN);
689}
690
691static void overlay2fb_disable(struct pxafb_layer *ofb)
692{
1b98d7c4
VK		 693 uint32_t lccr5;
694
695 if (!(lcd_readl(ofb->fbi, OVL2C1) & OVLxC1_OEN))
696 return;
697
698 lccr5 = lcd_readl(ofb->fbi, LCCR5);
198fc108
EM		 699
700 lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] & ~OVLxC1_OEN);
701
702 lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(2));
703 lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(2));
704 lcd_writel(ofb->fbi, FBR2, ofb->fbi->fdadr[DMA_OV2_Y] | 0x3);
705 lcd_writel(ofb->fbi, FBR3, ofb->fbi->fdadr[DMA_OV2_Cb] | 0x3);
706 lcd_writel(ofb->fbi, FBR4, ofb->fbi->fdadr[DMA_OV2_Cr] | 0x3);
707
708 if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0)
709 pr_warning("%s: timeout disabling overlay2\n", __func__);
710}
711
712static struct pxafb_layer_ops ofb_ops[] = {
713 [0] = {
714 .enable = overlay1fb_enable,
715 .disable = overlay1fb_disable,
716 .setup = overlay1fb_setup,
717 },
718 [1] = {
719 .enable = overlay2fb_enable,
720 .disable = overlay2fb_disable,
721 .setup = overlay2fb_setup,
722 },
723};
724
725static int overlayfb_open(struct fb_info *info, int user)
726{
727 struct pxafb_layer *ofb = (struct pxafb_layer *)info;
728
729 /* no support for framebuffer console on overlay */
730 if (user == 0)
731 return -ENODEV;
732
1b98d7c4
VK		 733 if (ofb->usage++ == 0)
734 /* unblank the base framebuffer */
735 fb_blank(&ofb->fbi->fb, FB_BLANK_UNBLANK);
198fc108 736
198fc108
EM		 737 return 0;
738}
739
740static int overlayfb_release(struct fb_info *info, int user)
741{
742 struct pxafb_layer *ofb = (struct pxafb_layer*) info;
743
1b98d7c4
VK		 744 if (ofb->usage == 1) {
745 ofb->ops->disable(ofb);
746 ofb->fb.var.height = -1;
747 ofb->fb.var.width = -1;
748 ofb->fb.var.xres = ofb->fb.var.xres_virtual = 0;
749 ofb->fb.var.yres = ofb->fb.var.yres_virtual = 0;
198fc108 750
1b98d7c4
VK		 751 ofb->usage--;
752 }
198fc108
EM		 753 return 0;
754}
755
756static int overlayfb_check_var(struct fb_var_screeninfo *var,
757 struct fb_info *info)
758{
759 struct pxafb_layer *ofb = (struct pxafb_layer *)info;
760 struct fb_var_screeninfo *base_var = &ofb->fbi->fb.var;
761 int xpos, ypos, pfor, bpp;
762
763 xpos = NONSTD_TO_XPOS(var->nonstd);
dcf8eee9 764 ypos = NONSTD_TO_YPOS(var->nonstd);
198fc108
EM		 765 pfor = NONSTD_TO_PFOR(var->nonstd);
766
767 bpp = pxafb_var_to_bpp(var);
768 if (bpp < 0)
769 return -EINVAL;
770
771 /* no support for YUV format on overlay1 */
772 if (ofb->id == OVERLAY1 && pfor != 0)
773 return -EINVAL;
774
775 /* for YUV packed formats, bpp = 'minimum bpp of YUV components' */
776 switch (pfor) {
777 case OVERLAY_FORMAT_RGB:
778 bpp = pxafb_var_to_bpp(var);
779 if (bpp < 0)
780 return -EINVAL;
781
782 pxafb_set_pixfmt(var, var_to_depth(var));
783 break;
784 case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break;
785 case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 8; break;
786 case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 4; break;
787 case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 2; break;
788 default:
789 return -EINVAL;
790 }
791
792 /* each line must start at a 32-bit word boundary */
793 if ((xpos * bpp) % 32)
794 return -EINVAL;
795
796 /* xres must align on 32-bit word boundary */
797 var->xres = roundup(var->xres * bpp, 32) / bpp;
798
799 if ((xpos + var->xres > base_var->xres) ||
800 (ypos + var->yres > base_var->yres))
801 return -EINVAL;
802
803 var->xres_virtual = var->xres;
804 var->yres_virtual = max(var->yres, var->yres_virtual);
805 return 0;
806}
807
1b98d7c4 808static int overlayfb_check_video_memory(struct pxafb_layer *ofb)
198fc108
EM		 809{
810 struct fb_var_screeninfo *var = &ofb->fb.var;
811 int pfor = NONSTD_TO_PFOR(var->nonstd);
812 int size, bpp = 0;
813
814 switch (pfor) {
815 case OVERLAY_FORMAT_RGB: bpp = var->bits_per_pixel; break;
816 case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break;
817 case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 24; break;
818 case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 16; break;
819 case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 12; break;
820 }
821
822 ofb->fb.fix.line_length = var->xres_virtual * bpp / 8;
823
824 size = PAGE_ALIGN(ofb->fb.fix.line_length * var->yres_virtual);
825
198fc108
EM		 826 if (ofb->video_mem) {
827 if (ofb->video_mem_size >= size)
828 return 0;
198fc108 829 }
1b98d7c4 830 return -EINVAL;
198fc108
EM		 831}
832
833static int overlayfb_set_par(struct fb_info *info)
834{
835 struct pxafb_layer *ofb = (struct pxafb_layer *)info;
836 struct fb_var_screeninfo *var = &info->var;
837 int xpos, ypos, pfor, bpp, ret;
838
1b98d7c4 839 ret = overlayfb_check_video_memory(ofb);
198fc108
EM		 840 if (ret)
841 return ret;
842
843 bpp = pxafb_var_to_bpp(var);
844 xpos = NONSTD_TO_XPOS(var->nonstd);
dcf8eee9 845 ypos = NONSTD_TO_YPOS(var->nonstd);
198fc108
EM		 846 pfor = NONSTD_TO_PFOR(var->nonstd);
847
848 ofb->control[0] = OVLxC1_PPL(var->xres) | OVLxC1_LPO(var->yres) |
849 OVLxC1_BPP(bpp);
850 ofb->control[1] = OVLxC2_XPOS(xpos) | OVLxC2_YPOS(ypos);
851
852 if (ofb->id == OVERLAY2)
853 ofb->control[1] |= OVL2C2_PFOR(pfor);
854
855 ofb->ops->setup(ofb);
856 ofb->ops->enable(ofb);
857 return 0;
858}
859
860static struct fb_ops overlay_fb_ops = {
861 .owner = THIS_MODULE,
862 .fb_open = overlayfb_open,
863 .fb_release = overlayfb_release,
864 .fb_check_var = overlayfb_check_var,
865 .fb_set_par = overlayfb_set_par,
866};
867
868static void __devinit init_pxafb_overlay(struct pxafb_info *fbi,
869 struct pxafb_layer *ofb, int id)
870{
871 sprintf(ofb->fb.fix.id, "overlay%d", id + 1);
872
873 ofb->fb.fix.type = FB_TYPE_PACKED_PIXELS;
874 ofb->fb.fix.xpanstep = 0;
875 ofb->fb.fix.ypanstep = 1;
876
877 ofb->fb.var.activate = FB_ACTIVATE_NOW;
878 ofb->fb.var.height = -1;
879 ofb->fb.var.width = -1;
880 ofb->fb.var.vmode = FB_VMODE_NONINTERLACED;
881
882 ofb->fb.fbops = &overlay_fb_ops;
883 ofb->fb.flags = FBINFO_FLAG_DEFAULT;
884 ofb->fb.node = -1;
885 ofb->fb.pseudo_palette = NULL;
886
887 ofb->id = id;
888 ofb->ops = &ofb_ops[id];
1b98d7c4 889 ofb->usage = 0;
198fc108
EM		 890 ofb->fbi = fbi;
891 init_completion(&ofb->branch_done);
892}
893
782385ae
EM		 894static inline int pxafb_overlay_supported(void)
895{
896 if (cpu_is_pxa27x() || cpu_is_pxa3xx())
897 return 1;
898
899 return 0;
900}
901
1b98d7c4
VK		 902static int __devinit pxafb_overlay_map_video_memory(struct pxafb_info *pxafb,
903 struct pxafb_layer *ofb)
904{
905 /* We assume that user will use at most video_mem_size for overlay fb,
906 * anyway, it's useless to use 16bpp main plane and 24bpp overlay
907 */
908 ofb->video_mem = alloc_pages_exact(PAGE_ALIGN(pxafb->video_mem_size),
909 GFP_KERNEL | __GFP_ZERO);
910 if (ofb->video_mem == NULL)
911 return -ENOMEM;
912
913 ofb->video_mem_phys = virt_to_phys(ofb->video_mem);
914 ofb->video_mem_size = PAGE_ALIGN(pxafb->video_mem_size);
915
916 mutex_lock(&ofb->fb.mm_lock);
917 ofb->fb.fix.smem_start = ofb->video_mem_phys;
918 ofb->fb.fix.smem_len = pxafb->video_mem_size;
919 mutex_unlock(&ofb->fb.mm_lock);
920
921 ofb->fb.screen_base = ofb->video_mem;
922
923 return 0;
924}
925
926static void __devinit pxafb_overlay_init(struct pxafb_info *fbi)
198fc108
EM		 927{
928 int i, ret;
929
782385ae 930 if (!pxafb_overlay_supported())
1b98d7c4 931 return;
782385ae 932
198fc108 933 for (i = 0; i < 2; i++) {
1b98d7c4
VK		 934 struct pxafb_layer *ofb = &fbi->overlay[i];
935 init_pxafb_overlay(fbi, ofb, i);
936 ret = register_framebuffer(&ofb->fb);
198fc108
EM		 937 if (ret) {
938 dev_err(fbi->dev, "failed to register overlay %d\n", i);
1b98d7c4
VK		 939 continue;
940 }
941 ret = pxafb_overlay_map_video_memory(fbi, ofb);
942 if (ret) {
943 dev_err(fbi->dev,
944 "failed to map video memory for overlay %d\n",
945 i);
946 unregister_framebuffer(&ofb->fb);
947 continue;
198fc108 948 }
1b98d7c4 949 ofb->registered = 1;
198fc108
EM		 950 }
951
952 /* mask all IU/BS/EOF/SOF interrupts */
953 lcd_writel(fbi, LCCR5, ~0);
954
198fc108 955 pr_info("PXA Overlay driver loaded successfully!\n");
198fc108
EM		 956}
957
958static void __devexit pxafb_overlay_exit(struct pxafb_info *fbi)
959{
960 int i;
961
782385ae
EM		 962 if (!pxafb_overlay_supported())
963 return;
964
1b98d7c4
VK		 965 for (i = 0; i < 2; i++) {
966 struct pxafb_layer *ofb = &fbi->overlay[i];
967 if (ofb->registered) {
968 if (ofb->video_mem)
969 free_pages_exact(ofb->video_mem,
970 ofb->video_mem_size);
971 unregister_framebuffer(&ofb->fb);
972 }
973 }
198fc108
EM		 974}
975#else
976static inline void pxafb_overlay_init(struct pxafb_info *fbi) {}
977static inline void pxafb_overlay_exit(struct pxafb_info *fbi) {}
978#endif /* CONFIG_FB_PXA_OVERLAY */
979
1da177e4
LT		 980/*
981 * Calculate the PCD value from the clock rate (in picoseconds).
982 * We take account of the PPCR clock setting.
983 * From PXA Developer's Manual:
984 *
985 * PixelClock = LCLK
986 * -------------
987 * 2 ( PCD + 1 )
988 *
989 * PCD = LCLK
990 * ------------- - 1
991 * 2(PixelClock)
992 *
993 * Where:
994 * LCLK = LCD/Memory Clock
995 * PCD = LCCR3[7:0]
996 *
997 * PixelClock here is in Hz while the pixclock argument given is the
998 * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
999 *
1000 * The function get_lclk_frequency_10khz returns LCLK in units of
1001 * 10khz. Calling the result of this function lclk gives us the
1002 * following
1003 *
1004 * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
1005 * -------------------------------------- - 1
1006 * 2
1007 *
1008 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
1009 */
b0086efb 1010static inline unsigned int get_pcd(struct pxafb_info *fbi,
1011 unsigned int pixclock)
1da177e4
LT		 1012{
1013 unsigned long long pcd;
1014
1015 /* FIXME: Need to take into account Double Pixel Clock mode
72e3524c
RK		 1016 * (DPC) bit? or perhaps set it based on the various clock
1017 * speeds */
1018 pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000);
1019 pcd *= pixclock;
bf1b8ab6 1020 do_div(pcd, 100000000 * 2);
1da177e4
LT		 1021 /* no need for this, since we should subtract 1 anyway. they cancel */
1022 /* pcd += 1; */ /* make up for integer math truncations */
1023 return (unsigned int)pcd;
1024}
1025
ba44cd2d
RP		 1026/*
1027 * Some touchscreens need hsync information from the video driver to
72e3524c
RK		 1028 * function correctly. We export it here. Note that 'hsync_time' and
1029 * the value returned from pxafb_get_hsync_time() is the *reciprocal*
1030 * of the hsync period in seconds.
ba44cd2d
RP		 1031 */
1032static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
1033{
72e3524c 1034 unsigned long htime;
ba44cd2d
RP		 1035
1036 if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
b0086efb 1037 fbi->hsync_time = 0;
ba44cd2d
RP		 1038 return;
1039 }
1040
72e3524c
RK		 1041 htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len);
1042
ba44cd2d
RP		 1043 fbi->hsync_time = htime;
1044}
1045
1046unsigned long pxafb_get_hsync_time(struct device *dev)
1047{
1048 struct pxafb_info *fbi = dev_get_drvdata(dev);
1049
1050 /* If display is blanked/suspended, hsync isn't active */
1051 if (!fbi || (fbi->state != C_ENABLE))
1052 return 0;
1053
1054 return fbi->hsync_time;
1055}
1056EXPORT_SYMBOL(pxafb_get_hsync_time);
1057
2c42dd8e 1058static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
198fc108 1059 unsigned long start, size_t size)
2c42dd8e 1060{
1061 struct pxafb_dma_descriptor *dma_desc, *pal_desc;
1062 unsigned int dma_desc_off, pal_desc_off;
1063
6e354846 1064 if (dma < 0 || dma >= DMA_MAX * 2)
2c42dd8e 1065 return -EINVAL;
1066
1067 dma_desc = &fbi->dma_buff->dma_desc[dma];
1068 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]);
1069
198fc108 1070 dma_desc->fsadr = start;
2c42dd8e 1071 dma_desc->fidr = 0;
1072 dma_desc->ldcmd = size;
1073
6e354846 1074 if (pal < 0 || pal >= PAL_MAX * 2) {
2c42dd8e 1075 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1076 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
1077 } else {
62cfcf4f
JS		 1078 pal_desc = &fbi->dma_buff->pal_desc[pal];
1079 pal_desc_off = offsetof(struct pxafb_dma_buff, pal_desc[pal]);
2c42dd8e 1080
1081 pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE;
1082 pal_desc->fidr = 0;
1083
1084 if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
1085 pal_desc->ldcmd = fbi->palette_size * sizeof(u16);
1086 else
1087 pal_desc->ldcmd = fbi->palette_size * sizeof(u32);
1088
1089 pal_desc->ldcmd |= LDCMD_PAL;
1090
1091 /* flip back and forth between palette and frame buffer */
1092 pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1093 dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off;
1094 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
1095 }
1096
1097 return 0;
1098}
1099
448ac479
SN		 1100static void setup_base_frame(struct pxafb_info *fbi,
1101 struct fb_var_screeninfo *var,
1102 int branch)
6e354846 1103{
6e354846 1104 struct fb_fix_screeninfo *fix = &fbi->fb.fix;
198fc108
EM		 1105 int nbytes, dma, pal, bpp = var->bits_per_pixel;
1106 unsigned long offset;
6e354846
EM		 1107
1108 dma = DMA_BASE + (branch ? DMA_MAX : 0);
1109 pal = (bpp >= 16) ? PAL_NONE : PAL_BASE + (branch ? PAL_MAX : 0);
1110
1111 nbytes = fix->line_length * var->yres;
198fc108 1112 offset = fix->line_length * var->yoffset + fbi->video_mem_phys;
6e354846
EM		 1113
1114 if (fbi->lccr0 & LCCR0_SDS) {
1115 nbytes = nbytes / 2;
1116 setup_frame_dma(fbi, dma + 1, PAL_NONE, offset + nbytes, nbytes);
1117 }
1118
1119 setup_frame_dma(fbi, dma, pal, offset, nbytes);
1120}
1121
3c42a449
EM		 1122#ifdef CONFIG_FB_PXA_SMARTPANEL
1123static int setup_smart_dma(struct pxafb_info *fbi)
1124{
1125 struct pxafb_dma_descriptor *dma_desc;
1126 unsigned long dma_desc_off, cmd_buff_off;
1127
1128 dma_desc = &fbi->dma_buff->dma_desc[DMA_CMD];
1129 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[DMA_CMD]);
1130 cmd_buff_off = offsetof(struct pxafb_dma_buff, cmd_buff);
1131
1132 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1133 dma_desc->fsadr = fbi->dma_buff_phys + cmd_buff_off;
1134 dma_desc->fidr = 0;
1135 dma_desc->ldcmd = fbi->n_smart_cmds * sizeof(uint16_t);
1136
1137 fbi->fdadr[DMA_CMD] = dma_desc->fdadr;
1138 return 0;
1139}
1140
1141int pxafb_smart_flush(struct fb_info *info)
1142{
1143 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
1144 uint32_t prsr;
1145 int ret = 0;
1146
1147 /* disable controller until all registers are set up */
1148 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1149
1150 /* 1. make it an even number of commands to align on 32-bit boundary
1151 * 2. add the interrupt command to the end of the chain so we can
1152 * keep track of the end of the transfer
1153 */
1154
1155 while (fbi->n_smart_cmds & 1)
1156 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_NOOP;
1157
1158 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_INTERRUPT;
1159 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_WAIT_FOR_VSYNC;
1160 setup_smart_dma(fbi);
1161
1162 /* continue to execute next command */
1163 prsr = lcd_readl(fbi, PRSR) | PRSR_ST_OK | PRSR_CON_NT;
1164 lcd_writel(fbi, PRSR, prsr);
1165
1166 /* stop the processor in case it executed "wait for sync" cmd */
1167 lcd_writel(fbi, CMDCR, 0x0001);
1168
1169 /* don't send interrupts for fifo underruns on channel 6 */
1170 lcd_writel(fbi, LCCR5, LCCR5_IUM(6));
1171
1172 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
1173 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1174 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
a0427509 1175 lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
3c42a449
EM		 1176 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1177 lcd_writel(fbi, FDADR6, fbi->fdadr[6]);
1178
1179 /* begin sending */
1180 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1181
1182 if (wait_for_completion_timeout(&fbi->command_done, HZ/2) == 0) {
1183 pr_warning("%s: timeout waiting for command done\n",
1184 __func__);
1185 ret = -ETIMEDOUT;
1186 }
1187
1188 /* quick disable */
1189 prsr = lcd_readl(fbi, PRSR) & ~(PRSR_ST_OK | PRSR_CON_NT);
1190 lcd_writel(fbi, PRSR, prsr);
1191 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1192 lcd_writel(fbi, FDADR6, 0);
1193 fbi->n_smart_cmds = 0;
1194 return ret;
1195}
1196
1197int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
1198{
1199 int i;
1200 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
1201
69bdea70
EM		 1202 for (i = 0; i < n_cmds; i++, cmds++) {
1203 /* if it is a software delay, flush and delay */
1204 if ((*cmds & 0xff00) == SMART_CMD_DELAY) {
1205 pxafb_smart_flush(info);
1206 mdelay(*cmds & 0xff);
1207 continue;
1208 }
1209
1210 /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */
3c42a449
EM		 1211 if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8)
1212 pxafb_smart_flush(info);
1213
69bdea70 1214 fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds;
3c42a449
EM		 1215 }
1216
1217 return 0;
1218}
1219
1220static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk)
1221{
1222 unsigned int t = (time_ns * (lcd_clk / 1000000) / 1000);
1223 return (t == 0) ? 1 : t;
1224}
1225
1226static void setup_smart_timing(struct pxafb_info *fbi,
1227 struct fb_var_screeninfo *var)
1228{
1229 struct pxafb_mach_info *inf = fbi->dev->platform_data;
1230 struct pxafb_mode_info *mode = &inf->modes[0];
1231 unsigned long lclk = clk_get_rate(fbi->clk);
1232 unsigned t1, t2, t3, t4;
1233
1234 t1 = max(mode->a0csrd_set_hld, mode->a0cswr_set_hld);
1235 t2 = max(mode->rd_pulse_width, mode->wr_pulse_width);
1236 t3 = mode->op_hold_time;
1237 t4 = mode->cmd_inh_time;
1238
1239 fbi->reg_lccr1 =
1240 LCCR1_DisWdth(var->xres) |
1241 LCCR1_BegLnDel(__smart_timing(t1, lclk)) |
1242 LCCR1_EndLnDel(__smart_timing(t2, lclk)) |
1243 LCCR1_HorSnchWdth(__smart_timing(t3, lclk));
1244
1245 fbi->reg_lccr2 = LCCR2_DisHght(var->yres);
c1f99c21
EM		 1246 fbi->reg_lccr3 = fbi->lccr3 | LCCR3_PixClkDiv(__smart_timing(t4, lclk));
1247 fbi->reg_lccr3 |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? LCCR3_HSP : 0;
1248 fbi->reg_lccr3 |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? LCCR3_VSP : 0;
3c42a449
EM		 1249
1250 /* FIXME: make this configurable */
1251 fbi->reg_cmdcr = 1;
1252}
1253
1254static int pxafb_smart_thread(void *arg)
1255{
7f1133cb 1256 struct pxafb_info *fbi = arg;
da2c3f0e 1257 struct pxafb_mach_info *inf = fbi->dev->platform_data;
3c42a449 1258
da2c3f0e 1259 if (!inf->smart_update) {
3c42a449
EM		 1260 pr_err("%s: not properly initialized, thread terminated\n",
1261 __func__);
1262 return -EINVAL;
1263 }
d2a34c13 1264 inf = fbi->dev->platform_data;
3c42a449
EM		 1265
1266 pr_debug("%s(): task starting\n", __func__);
1267
1268 set_freezable();
1269 while (!kthread_should_stop()) {
1270
1271 if (try_to_freeze())
1272 continue;
1273
07f651c7
EM		 1274 mutex_lock(&fbi->ctrlr_lock);
1275
3c42a449
EM		 1276 if (fbi->state == C_ENABLE) {
1277 inf->smart_update(&fbi->fb);
1278 complete(&fbi->refresh_done);
1279 }
1280
07f651c7
EM		 1281 mutex_unlock(&fbi->ctrlr_lock);
1282
3c42a449
EM		 1283 set_current_state(TASK_INTERRUPTIBLE);
1284 schedule_timeout(30 * HZ / 1000);
1285 }
1286
1287 pr_debug("%s(): task ending\n", __func__);
1288 return 0;
1289}
1290
1291static int pxafb_smart_init(struct pxafb_info *fbi)
1292{
07df1c4f 1293 if (!(fbi->lccr0 & LCCR0_LCDT))
6cc4abe4
EM		 1294 return 0;
1295
07df1c4f
EM		 1296 fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
1297 fbi->n_smart_cmds = 0;
1298
1299 init_completion(&fbi->command_done);
1300 init_completion(&fbi->refresh_done);
1301
3c42a449
EM		 1302 fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi,
1303 "lcd_refresh");
1304 if (IS_ERR(fbi->smart_thread)) {
07df1c4f 1305 pr_err("%s: unable to create kernel thread\n", __func__);
3c42a449
EM		 1306 return PTR_ERR(fbi->smart_thread);
1307 }
a5718a14 1308
3c42a449
EM		 1309 return 0;
1310}
1311#else
07df1c4f
EM		 1312static inline int pxafb_smart_init(struct pxafb_info *fbi) { return 0; }
1313#endif /* CONFIG_FB_PXA_SMARTPANEL */
3c42a449 1314
90eabbf0
EM		 1315static void setup_parallel_timing(struct pxafb_info *fbi,
1316 struct fb_var_screeninfo *var)
1317{
1318 unsigned int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
1319
1320 fbi->reg_lccr1 =
1321 LCCR1_DisWdth(var->xres) +
1322 LCCR1_HorSnchWdth(var->hsync_len) +
1323 LCCR1_BegLnDel(var->left_margin) +
1324 LCCR1_EndLnDel(var->right_margin);
1325
1326 /*
1327 * If we have a dual scan LCD, we need to halve
1328 * the YRES parameter.
1329 */
1330 lines_per_panel = var->yres;
1331 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
1332 lines_per_panel /= 2;
1333
1334 fbi->reg_lccr2 =
1335 LCCR2_DisHght(lines_per_panel) +
1336 LCCR2_VrtSnchWdth(var->vsync_len) +
1337 LCCR2_BegFrmDel(var->upper_margin) +
1338 LCCR2_EndFrmDel(var->lower_margin);
1339
1340 fbi->reg_lccr3 = fbi->lccr3 |
1341 (var->sync & FB_SYNC_HOR_HIGH_ACT ?
1342 LCCR3_HorSnchH : LCCR3_HorSnchL) |
1343 (var->sync & FB_SYNC_VERT_HIGH_ACT ?
1344 LCCR3_VrtSnchH : LCCR3_VrtSnchL);
1345
1346 if (pcd) {
1347 fbi->reg_lccr3 |= LCCR3_PixClkDiv(pcd);
1348 set_hsync_time(fbi, pcd);
1349 }
1350}
1351
1da177e4
LT		 1352/*
1353 * pxafb_activate_var():
b0086efb 1354 * Configures LCD Controller based on entries in var parameter.
1355 * Settings are only written to the controller if changes were made.
1da177e4 1356 */
b0086efb 1357static int pxafb_activate_var(struct fb_var_screeninfo *var,
1358 struct pxafb_info *fbi)
1da177e4 1359{
1da177e4 1360 u_long flags;
1da177e4 1361
90eabbf0
EM		 1362 /* Update shadow copy atomically */
1363 local_irq_save(flags);
1da177e4 1364
3c42a449
EM		 1365#ifdef CONFIG_FB_PXA_SMARTPANEL
1366 if (fbi->lccr0 & LCCR0_LCDT)
1367 setup_smart_timing(fbi, var);
1368 else
1369#endif
1370 setup_parallel_timing(fbi, var);
90eabbf0 1371
448ac479 1372 setup_base_frame(fbi, var, 0);
6e354846 1373
90eabbf0 1374 fbi->reg_lccr0 = fbi->lccr0 |
1da177e4 1375 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
b0086efb 1376 LCCR0_QDM | LCCR0_BM | LCCR0_OUM);
1da177e4 1377
878f5783 1378 fbi->reg_lccr3 |= pxafb_var_to_lccr3(var);
1da177e4 1379
a7535ba7 1380 fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK;
9ffa7396 1381 fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
1da177e4
LT		 1382 local_irq_restore(flags);
1383
1384 /*
1385 * Only update the registers if the controller is enabled
1386 * and something has changed.
1387 */
a7535ba7
EM		 1388 if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) ||
1389 (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) ||
1390 (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) ||
1391 (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) ||
a0427509 1392 (lcd_readl(fbi, LCCR4) != fbi->reg_lccr4) ||
a7535ba7 1393 (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) ||
1b98d7c4
VK		 1394 ((fbi->lccr0 & LCCR0_SDS) &&
1395 (lcd_readl(fbi, FDADR1) != fbi->fdadr[1])))
1da177e4
LT		 1396 pxafb_schedule_work(fbi, C_REENABLE);
1397
1398 return 0;
1399}
1400
1401/*
1402 * NOTE! The following functions are purely helpers for set_ctrlr_state.
1403 * Do not call them directly; set_ctrlr_state does the correct serialisation
1404 * to ensure that things happen in the right way 100% of time time.
1405 * -- rmk
1406 */
1407static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
1408{
ca5da710 1409 pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
1da177e4 1410
a5718a14
EM		 1411 if (fbi->backlight_power)
1412 fbi->backlight_power(on);
1da177e4
LT		 1413}
1414
1415static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
1416{
ca5da710 1417 pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
1da177e4 1418
a5718a14
EM		 1419 if (fbi->lcd_power)
1420 fbi->lcd_power(on, &fbi->fb.var);
1da177e4
LT		 1421}
1422
1da177e4
LT		 1423static void pxafb_enable_controller(struct pxafb_info *fbi)
1424{
ca5da710 1425 pr_debug("pxafb: Enabling LCD controller\n");
2c42dd8e 1426 pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]);
1427 pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]);
ca5da710
RK		 1428 pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
1429 pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
1430 pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
1431 pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
1da177e4 1432
8d372266 1433 /* enable LCD controller clock */
72e3524c 1434 clk_enable(fbi->clk);
8d372266 1435
3c42a449
EM		 1436 if (fbi->lccr0 & LCCR0_LCDT)
1437 return;
1438
1da177e4 1439 /* Sequence from 11.7.10 */
a0427509 1440 lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
a7535ba7
EM		 1441 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1442 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1443 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
1444 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1445
1446 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1b98d7c4
VK		 1447 if (fbi->lccr0 & LCCR0_SDS)
1448 lcd_writel(fbi, FDADR1, fbi->fdadr[1]);
a7535ba7 1449 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1da177e4
LT		 1450}
1451
1452static void pxafb_disable_controller(struct pxafb_info *fbi)
1453{
ce4fb7b8 1454 uint32_t lccr0;
1455
3c42a449
EM		 1456#ifdef CONFIG_FB_PXA_SMARTPANEL
1457 if (fbi->lccr0 & LCCR0_LCDT) {
1458 wait_for_completion_timeout(&fbi->refresh_done,
1459 200 * HZ / 1000);
1460 return;
1461 }
1462#endif
1463
ce4fb7b8 1464 /* Clear LCD Status Register */
a7535ba7 1465 lcd_writel(fbi, LCSR, 0xffffffff);
ce4fb7b8 1466
a7535ba7
EM		 1467 lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM;
1468 lcd_writel(fbi, LCCR0, lccr0);
1469 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS);
1da177e4 1470
2ba162b9 1471 wait_for_completion_timeout(&fbi->disable_done, 200 * HZ / 1000);
8d372266
NP		 1472
1473 /* disable LCD controller clock */
72e3524c 1474 clk_disable(fbi->clk);
1da177e4
LT		 1475}
1476
1477/*
1478 * pxafb_handle_irq: Handle 'LCD DONE' interrupts.
1479 */
7d12e780 1480static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
1da177e4
LT		 1481{
1482 struct pxafb_info *fbi = dev_id;
ff14ed5d 1483 unsigned int lccr0, lcsr;
1da177e4 1484
198fc108 1485 lcsr = lcd_readl(fbi, LCSR);
1da177e4 1486 if (lcsr & LCSR_LDD) {
a7535ba7
EM		 1487 lccr0 = lcd_readl(fbi, LCCR0);
1488 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM);
2ba162b9 1489 complete(&fbi->disable_done);
1da177e4
LT		 1490 }
1491
3c42a449
EM		 1492#ifdef CONFIG_FB_PXA_SMARTPANEL
1493 if (lcsr & LCSR_CMD_INT)
1494 complete(&fbi->command_done);
1495#endif
a7535ba7 1496 lcd_writel(fbi, LCSR, lcsr);
198fc108
EM		 1497
1498#ifdef CONFIG_FB_PXA_OVERLAY
ff14ed5d
DL		 1499 {
1500 unsigned int lcsr1 = lcd_readl(fbi, LCSR1);
1501 if (lcsr1 & LCSR1_BS(1))
1502 complete(&fbi->overlay[0].branch_done);
198fc108 1503
ff14ed5d
DL		 1504 if (lcsr1 & LCSR1_BS(2))
1505 complete(&fbi->overlay[1].branch_done);
198fc108 1506
ff14ed5d
DL		 1507 lcd_writel(fbi, LCSR1, lcsr1);
1508 }
198fc108 1509#endif
1da177e4
LT		 1510 return IRQ_HANDLED;
1511}
1512
1513/*
1514 * This function must be called from task context only, since it will
1515 * sleep when disabling the LCD controller, or if we get two contending
1516 * processes trying to alter state.
1517 */
1518static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
1519{
1520 u_int old_state;
1521
b91dbce5 1522 mutex_lock(&fbi->ctrlr_lock);
1da177e4
LT		 1523
1524 old_state = fbi->state;
1525
1526 /*
1527 * Hack around fbcon initialisation.
1528 */
1529 if (old_state == C_STARTUP && state == C_REENABLE)
1530 state = C_ENABLE;
1531
1532 switch (state) {
1533 case C_DISABLE_CLKCHANGE:
1534 /*
1535 * Disable controller for clock change. If the
1536 * controller is already disabled, then do nothing.
1537 */
1538 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
1539 fbi->state = state;
b0086efb 1540 /* TODO __pxafb_lcd_power(fbi, 0); */
1da177e4
LT		 1541 pxafb_disable_controller(fbi);
1542 }
1543 break;
1544
1545 case C_DISABLE_PM:
1546 case C_DISABLE:
1547 /*
1548 * Disable controller
1549 */
1550 if (old_state != C_DISABLE) {
1551 fbi->state = state;
1552 __pxafb_backlight_power(fbi, 0);
1553 __pxafb_lcd_power(fbi, 0);
1554 if (old_state != C_DISABLE_CLKCHANGE)
1555 pxafb_disable_controller(fbi);
1556 }
1557 break;
1558
1559 case C_ENABLE_CLKCHANGE:
1560 /*
1561 * Enable the controller after clock change. Only
1562 * do this if we were disabled for the clock change.
1563 */
1564 if (old_state == C_DISABLE_CLKCHANGE) {
1565 fbi->state = C_ENABLE;
1566 pxafb_enable_controller(fbi);
b0086efb 1567 /* TODO __pxafb_lcd_power(fbi, 1); */
1da177e4
LT		 1568 }
1569 break;
1570
1571 case C_REENABLE:
1572 /*
1573 * Re-enable the controller only if it was already
1574 * enabled. This is so we reprogram the control
1575 * registers.
1576 */
1577 if (old_state == C_ENABLE) {
d14b272b 1578 __pxafb_lcd_power(fbi, 0);
1da177e4 1579 pxafb_disable_controller(fbi);
1da177e4 1580 pxafb_enable_controller(fbi);
d14b272b 1581 __pxafb_lcd_power(fbi, 1);
1da177e4
LT		 1582 }
1583 break;
1584
1585 case C_ENABLE_PM:
1586 /*
1587 * Re-enable the controller after PM. This is not
1588 * perfect - think about the case where we were doing
1589 * a clock change, and we suspended half-way through.
1590 */
1591 if (old_state != C_DISABLE_PM)
1592 break;
1593 /* fall through */
1594
1595 case C_ENABLE:
1596 /*
1597 * Power up the LCD screen, enable controller, and
1598 * turn on the backlight.
1599 */
1600 if (old_state != C_ENABLE) {
1601 fbi->state = C_ENABLE;
1da177e4
LT		 1602 pxafb_enable_controller(fbi);
1603 __pxafb_lcd_power(fbi, 1);
1604 __pxafb_backlight_power(fbi, 1);
1605 }
1606 break;
1607 }
b91dbce5 1608 mutex_unlock(&fbi->ctrlr_lock);
1da177e4
LT		 1609}
1610
1611/*
1612 * Our LCD controller task (which is called when we blank or unblank)
1613 * via keventd.
1614 */
6d5aefb8 1615static void pxafb_task(struct work_struct *work)
1da177e4 1616{
6d5aefb8
DH		 1617 struct pxafb_info *fbi =
1618 container_of(work, struct pxafb_info, task);
1da177e4
LT		 1619 u_int state = xchg(&fbi->task_state, -1);
1620
1621 set_ctrlr_state(fbi, state);
1622}
1623
1624#ifdef CONFIG_CPU_FREQ
1625/*
1626 * CPU clock speed change handler. We need to adjust the LCD timing
1627 * parameters when the CPU clock is adjusted by the power management
1628 * subsystem.
1629 *
1630 * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
1631 */
1632static int
1633pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
1634{
1635 struct pxafb_info *fbi = TO_INF(nb, freq_transition);
b0086efb 1636 /* TODO struct cpufreq_freqs *f = data; */
1da177e4
LT		 1637 u_int pcd;
1638
1639 switch (val) {
1640 case CPUFREQ_PRECHANGE:
a6d710fe
MV		 1641#ifdef CONFIG_FB_PXA_OVERLAY
1642 if (!(fbi->overlay[0].usage || fbi->overlay[1].usage))
1643#endif
27be9a9e 1644 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
1da177e4
LT		 1645 break;
1646
1647 case CPUFREQ_POSTCHANGE:
72e3524c 1648 pcd = get_pcd(fbi, fbi->fb.var.pixclock);
ba44cd2d 1649 set_hsync_time(fbi, pcd);
b0086efb 1650 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) |
1651 LCCR3_PixClkDiv(pcd);
1da177e4
LT		 1652 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
1653 break;
1654 }
1655 return 0;
1656}
1657
1658static int
1659pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
1660{
1661 struct pxafb_info *fbi = TO_INF(nb, freq_policy);
1662 struct fb_var_screeninfo *var = &fbi->fb.var;
1663 struct cpufreq_policy *policy = data;
1664
1665 switch (val) {
1666 case CPUFREQ_ADJUST:
1667 case CPUFREQ_INCOMPATIBLE:
ac2bf5bd 1668 pr_debug("min dma period: %d ps, "
1da177e4
LT		 1669 "new clock %d kHz\n", pxafb_display_dma_period(var),
1670 policy->max);
b0086efb 1671 /* TODO: fill in min/max values */
1da177e4 1672 break;
1da177e4
LT		 1673 }
1674 return 0;
1675}
1676#endif
1677
1678#ifdef CONFIG_PM
1679/*
1680 * Power management hooks. Note that we won't be called from IRQ context,
1681 * unlike the blank functions above, so we may sleep.
1682 */
4f3edfe3 1683static int pxafb_suspend(struct device *dev)
1da177e4 1684{
4f3edfe3 1685 struct pxafb_info *fbi = dev_get_drvdata(dev);
1da177e4 1686
9480e307 1687 set_ctrlr_state(fbi, C_DISABLE_PM);
1da177e4
LT		 1688 return 0;
1689}
1690
4f3edfe3 1691static int pxafb_resume(struct device *dev)
1da177e4 1692{
4f3edfe3 1693 struct pxafb_info *fbi = dev_get_drvdata(dev);
1da177e4 1694
9480e307 1695 set_ctrlr_state(fbi, C_ENABLE_PM);
1da177e4
LT		 1696 return 0;
1697}
4f3edfe3 1698
47145210 1699static const struct dev_pm_ops pxafb_pm_ops = {
4f3edfe3
MR		 1700 .suspend = pxafb_suspend,
1701 .resume = pxafb_resume,
1702};
1da177e4
LT		 1703#endif
1704
77e19675 1705static int __devinit pxafb_init_video_memory(struct pxafb_info *fbi)
1da177e4 1706{
77e19675 1707 int size = PAGE_ALIGN(fbi->video_mem_size);
3c42a449 1708
77e19675
EM		 1709 fbi->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO);
1710 if (fbi->video_mem == NULL)
1711 return -ENOMEM;
1da177e4 1712
77e19675
EM		 1713 fbi->video_mem_phys = virt_to_phys(fbi->video_mem);
1714 fbi->video_mem_size = size;
1da177e4 1715
77e19675
EM		 1716 fbi->fb.fix.smem_start = fbi->video_mem_phys;
1717 fbi->fb.fix.smem_len = fbi->video_mem_size;
1718 fbi->fb.screen_base = fbi->video_mem;
84f43c30 1719
77e19675 1720 return fbi->video_mem ? 0 : -ENOMEM;
84f43c30 1721}
1722
ebdf982a
GL		 1723static void pxafb_decode_mach_info(struct pxafb_info *fbi,
1724 struct pxafb_mach_info *inf)
84f43c30 1725{
1726 unsigned int lcd_conn = inf->lcd_conn;
77e19675
EM		 1727 struct pxafb_mode_info *m;
1728 int i;
84f43c30 1729
1730 fbi->cmap_inverse = inf->cmap_inverse;
1731 fbi->cmap_static = inf->cmap_static;
a0427509 1732 fbi->lccr4 = inf->lccr4;
84f43c30 1733
1ec26db1 1734 switch (lcd_conn & LCD_TYPE_MASK) {
84f43c30 1735 case LCD_TYPE_MONO_STN:
1736 fbi->lccr0 = LCCR0_CMS;
1737 break;
1738 case LCD_TYPE_MONO_DSTN:
1739 fbi->lccr0 = LCCR0_CMS | LCCR0_SDS;
1740 break;
1741 case LCD_TYPE_COLOR_STN:
1742 fbi->lccr0 = 0;
1743 break;
1744 case LCD_TYPE_COLOR_DSTN:
1745 fbi->lccr0 = LCCR0_SDS;
1746 break;
1747 case LCD_TYPE_COLOR_TFT:
1748 fbi->lccr0 = LCCR0_PAS;
1749 break;
1750 case LCD_TYPE_SMART_PANEL:
1751 fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS;
1752 break;
1753 default:
1754 /* fall back to backward compatibility way */
1755 fbi->lccr0 = inf->lccr0;
1756 fbi->lccr3 = inf->lccr3;
ebdf982a 1757 goto decode_mode;
84f43c30 1758 }
1759
1760 if (lcd_conn == LCD_MONO_STN_8BPP)
1761 fbi->lccr0 |= LCCR0_DPD;
1762
9a1ac7e4
EM		 1763 fbi->lccr0 |= (lcd_conn & LCD_ALTERNATE_MAPPING) ? LCCR0_LDDALT : 0;
1764
84f43c30 1765 fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff);
1766 fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0;
1767 fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0;
1768
ebdf982a 1769decode_mode:
77e19675
EM		 1770 pxafb_setmode(&fbi->fb.var, &inf->modes[0]);
1771
1772 /* decide video memory size as follows:
1773 * 1. default to mode of maximum resolution
1774 * 2. allow platform to override
1775 * 3. allow module parameter to override
1776 */
1777 for (i = 0, m = &inf->modes[0]; i < inf->num_modes; i++, m++)
1778 fbi->video_mem_size = max_t(size_t, fbi->video_mem_size,
1779 m->xres * m->yres * m->bpp / 8);
1780
1781 if (inf->video_mem_size > fbi->video_mem_size)
1782 fbi->video_mem_size = inf->video_mem_size;
1783
1784 if (video_mem_size > fbi->video_mem_size)
1785 fbi->video_mem_size = video_mem_size;
84f43c30 1786}
1787
9e6c2976 1788static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
1da177e4
LT		 1789{
1790 struct pxafb_info *fbi;
1791 void *addr;
1792 struct pxafb_mach_info *inf = dev->platform_data;
1793
1794 /* Alloc the pxafb_info and pseudo_palette in one step */
1795 fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
1796 if (!fbi)
1797 return NULL;
1798
1799 memset(fbi, 0, sizeof(struct pxafb_info));
1800 fbi->dev = dev;
1801
e0d8b13a 1802 fbi->clk = clk_get(dev, NULL);
72e3524c
RK		 1803 if (IS_ERR(fbi->clk)) {
1804 kfree(fbi);
1805 return NULL;
1806 }
1807
1da177e4
LT		 1808 strcpy(fbi->fb.fix.id, PXA_NAME);
1809
1810 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
1811 fbi->fb.fix.type_aux = 0;
1812 fbi->fb.fix.xpanstep = 0;
7e4b19c9 1813 fbi->fb.fix.ypanstep = 1;
1da177e4
LT		 1814 fbi->fb.fix.ywrapstep = 0;
1815 fbi->fb.fix.accel = FB_ACCEL_NONE;
1816
1817 fbi->fb.var.nonstd = 0;
1818 fbi->fb.var.activate = FB_ACTIVATE_NOW;
1819 fbi->fb.var.height = -1;
1820 fbi->fb.var.width = -1;
7e4b19c9 1821 fbi->fb.var.accel_flags = FB_ACCELF_TEXT;
1da177e4
LT		 1822 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
1823
1824 fbi->fb.fbops = &pxafb_ops;
1825 fbi->fb.flags = FBINFO_DEFAULT;
1826 fbi->fb.node = -1;
1827
1828 addr = fbi;
1829 addr = addr + sizeof(struct pxafb_info);
1830 fbi->fb.pseudo_palette = addr;
1831
b0086efb 1832 fbi->state = C_STARTUP;
1833 fbi->task_state = (u_char)-1;
d14b272b 1834
84f43c30 1835 pxafb_decode_mach_info(fbi, inf);
1da177e4 1836
7779cee3
VK		 1837#ifdef CONFIG_FB_PXA_OVERLAY
1838 /* place overlay(s) on top of base */
1839 if (pxafb_overlay_supported())
1840 fbi->lccr0 |= LCCR0_OUC;
1841#endif
1842
1da177e4 1843 init_waitqueue_head(&fbi->ctrlr_wait);
6d5aefb8 1844 INIT_WORK(&fbi->task, pxafb_task);
b91dbce5 1845 mutex_init(&fbi->ctrlr_lock);
2ba162b9 1846 init_completion(&fbi->disable_done);
1da177e4
LT		 1847
1848 return fbi;
1849}
1850
1851#ifdef CONFIG_FB_PXA_PARAMETERS
9e6c2976 1852static int __devinit parse_opt_mode(struct device *dev, const char *this_opt)
1da177e4
LT		 1853{
1854 struct pxafb_mach_info *inf = dev->platform_data;
817daf14 1855
1856 const char *name = this_opt+5;
1857 unsigned int namelen = strlen(name);
1858 int res_specified = 0, bpp_specified = 0;
1859 unsigned int xres = 0, yres = 0, bpp = 0;
1860 int yres_specified = 0;
1861 int i;
1862 for (i = namelen-1; i >= 0; i--) {
1863 switch (name[i]) {
1864 case '-':
1865 namelen = i;
1866 if (!bpp_specified && !yres_specified) {
1867 bpp = simple_strtoul(&name[i+1], NULL, 0);
1868 bpp_specified = 1;
1869 } else
1870 goto done;
1871 break;
1872 case 'x':
1873 if (!yres_specified) {
1874 yres = simple_strtoul(&name[i+1], NULL, 0);
1875 yres_specified = 1;
1876 } else
1877 goto done;
1878 break;
1879 case '0' ... '9':
1880 break;
1881 default:
1882 goto done;
1883 }
1884 }
1885 if (i < 0 && yres_specified) {
1886 xres = simple_strtoul(name, NULL, 0);
1887 res_specified = 1;
1888 }
1889done:
1890 if (res_specified) {
1891 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1892 inf->modes[0].xres = xres; inf->modes[0].yres = yres;
1893 }
1894 if (bpp_specified)
1895 switch (bpp) {
1896 case 1:
1897 case 2:
1898 case 4:
1899 case 8:
1900 case 16:
1901 inf->modes[0].bpp = bpp;
1902 dev_info(dev, "overriding bit depth: %d\n", bpp);
1903 break;
1904 default:
1905 dev_err(dev, "Depth %d is not valid\n", bpp);
1906 return -EINVAL;
1907 }
1908 return 0;
1909}
1910
9e6c2976 1911static int __devinit parse_opt(struct device *dev, char *this_opt)
817daf14 1912{
1913 struct pxafb_mach_info *inf = dev->platform_data;
1914 struct pxafb_mode_info *mode = &inf->modes[0];
1915 char s[64];
1916
1917 s[0] = '\0';
1918
77e19675
EM		 1919 if (!strncmp(this_opt, "vmem:", 5)) {
1920 video_mem_size = memparse(this_opt + 5, NULL);
1921 } else if (!strncmp(this_opt, "mode:", 5)) {
817daf14 1922 return parse_opt_mode(dev, this_opt);
1923 } else if (!strncmp(this_opt, "pixclock:", 9)) {
1924 mode->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1925 sprintf(s, "pixclock: %ld\n", mode->pixclock);
1926 } else if (!strncmp(this_opt, "left:", 5)) {
1927 mode->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1928 sprintf(s, "left: %u\n", mode->left_margin);
1929 } else if (!strncmp(this_opt, "right:", 6)) {
1930 mode->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1931 sprintf(s, "right: %u\n", mode->right_margin);
1932 } else if (!strncmp(this_opt, "upper:", 6)) {
1933 mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1934 sprintf(s, "upper: %u\n", mode->upper_margin);
1935 } else if (!strncmp(this_opt, "lower:", 6)) {
1936 mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1937 sprintf(s, "lower: %u\n", mode->lower_margin);
1938 } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1939 mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1940 sprintf(s, "hsynclen: %u\n", mode->hsync_len);
1941 } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1942 mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1943 sprintf(s, "vsynclen: %u\n", mode->vsync_len);
1944 } else if (!strncmp(this_opt, "hsync:", 6)) {
1945 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1946 sprintf(s, "hsync: Active Low\n");
1947 mode->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1948 } else {
1949 sprintf(s, "hsync: Active High\n");
1950 mode->sync |= FB_SYNC_HOR_HIGH_ACT;
1951 }
1952 } else if (!strncmp(this_opt, "vsync:", 6)) {
1953 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1954 sprintf(s, "vsync: Active Low\n");
1955 mode->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1956 } else {
1957 sprintf(s, "vsync: Active High\n");
1958 mode->sync |= FB_SYNC_VERT_HIGH_ACT;
1959 }
1960 } else if (!strncmp(this_opt, "dpc:", 4)) {
1961 if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1962 sprintf(s, "double pixel clock: false\n");
1963 inf->lccr3 &= ~LCCR3_DPC;
1964 } else {
1965 sprintf(s, "double pixel clock: true\n");
1966 inf->lccr3 |= LCCR3_DPC;
1967 }
1968 } else if (!strncmp(this_opt, "outputen:", 9)) {
1969 if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1970 sprintf(s, "output enable: active low\n");
1971 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1972 } else {
1973 sprintf(s, "output enable: active high\n");
1974 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1975 }
1976 } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1977 if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1978 sprintf(s, "pixel clock polarity: falling edge\n");
1979 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1980 } else {
1981 sprintf(s, "pixel clock polarity: rising edge\n");
1982 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1983 }
1984 } else if (!strncmp(this_opt, "color", 5)) {
1985 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1986 } else if (!strncmp(this_opt, "mono", 4)) {
1987 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1988 } else if (!strncmp(this_opt, "active", 6)) {
1989 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1990 } else if (!strncmp(this_opt, "passive", 7)) {
1991 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1992 } else if (!strncmp(this_opt, "single", 6)) {
1993 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1994 } else if (!strncmp(this_opt, "dual", 4)) {
1995 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1996 } else if (!strncmp(this_opt, "4pix", 4)) {
1997 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1998 } else if (!strncmp(this_opt, "8pix", 4)) {
1999 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
2000 } else {
2001 dev_err(dev, "unknown option: %s\n", this_opt);
2002 return -EINVAL;
2003 }
2004
2005 if (s[0] != '\0')
2006 dev_info(dev, "override %s", s);
2007
2008 return 0;
2009}
2010
9e6c2976 2011static int __devinit pxafb_parse_options(struct device *dev, char *options)
817daf14 2012{
1da177e4 2013 char *this_opt;
817daf14 2014 int ret;
1da177e4 2015
817daf14 2016 if (!options || !*options)
2017 return 0;
1da177e4
LT		 2018
2019 dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
2020
2021 /* could be made table driven or similar?... */
817daf14 2022 while ((this_opt = strsep(&options, ",")) != NULL) {
2023 ret = parse_opt(dev, this_opt);
2024 if (ret)
2025 return ret;
2026 }
2027 return 0;
1da177e4 2028}
92ac73c1 2029
2030static char g_options[256] __devinitdata = "";
2031
f1edfc42 2032#ifndef MODULE
9e6c2976 2033static int __init pxafb_setup_options(void)
92ac73c1 2034{
2035 char *options = NULL;
2036
2037 if (fb_get_options("pxafb", &options))
2038 return -ENODEV;
2039
2040 if (options)
2041 strlcpy(g_options, options, sizeof(g_options));
2042
2043 return 0;
2044}
2045#else
2046#define pxafb_setup_options() (0)
2047
2048module_param_string(options, g_options, sizeof(g_options), 0);
2049MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
2050#endif
2051
2052#else
2053#define pxafb_parse_options(...) (0)
2054#define pxafb_setup_options() (0)
1da177e4
LT		 2055#endif
2056
1da177e4 2057#ifdef DEBUG_VAR
4f3e2664
EM		 2058/* Check for various illegal bit-combinations. Currently only
2059 * a warning is given. */
2060static void __devinit pxafb_check_options(struct device *dev,
2061 struct pxafb_mach_info *inf)
2062{
2063 if (inf->lcd_conn)
2064 return;
1da177e4 2065
b0086efb 2066 if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
4f3e2664 2067 dev_warn(dev, "machine LCCR0 setting contains "
b0086efb 2068 "illegal bits: %08x\n",
2069 inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
2070 if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
4f3e2664 2071 dev_warn(dev, "machine LCCR3 setting contains "
b0086efb 2072 "illegal bits: %08x\n",
2073 inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
2074 if (inf->lccr0 & LCCR0_DPD &&
1da177e4
LT		 2075 ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
2076 (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
2077 (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
4f3e2664 2078 dev_warn(dev, "Double Pixel Data (DPD) mode is "
b0086efb 2079 "only valid in passive mono"
2080 " single panel mode\n");
2081 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
1da177e4 2082 (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
4f3e2664 2083 dev_warn(dev, "Dual panel only valid in passive mode\n");
b0086efb 2084 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
2085 (inf->modes->upper_margin || inf->modes->lower_margin))
4f3e2664 2086 dev_warn(dev, "Upper and lower margins must be 0 in "
b0086efb 2087 "passive mode\n");
4f3e2664
EM		 2088}
2089#else
2090#define pxafb_check_options(...) do {} while (0)
1da177e4
LT		 2091#endif
2092
4f3e2664
EM		 2093static int __devinit pxafb_probe(struct platform_device *dev)
2094{
2095 struct pxafb_info *fbi;
2096 struct pxafb_mach_info *inf;
2097 struct resource *r;
2098 int irq, ret;
2099
2100 dev_dbg(&dev->dev, "pxafb_probe\n");
2101
2102 inf = dev->dev.platform_data;
2103 ret = -ENOMEM;
2104 fbi = NULL;
2105 if (!inf)
2106 goto failed;
2107
2108 ret = pxafb_parse_options(&dev->dev, g_options);
2109 if (ret < 0)
2110 goto failed;
2111
2112 pxafb_check_options(&dev->dev, inf);
2113
b0086efb 2114 dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",
2115 inf->modes->xres,
2116 inf->modes->yres,
2117 inf->modes->bpp);
2118 if (inf->modes->xres == 0 ||
2119 inf->modes->yres == 0 ||
2120 inf->modes->bpp == 0) {
3ae5eaec 2121 dev_err(&dev->dev, "Invalid resolution or bit depth\n");
1da177e4
LT		 2122 ret = -EINVAL;
2123 goto failed;
2124 }
a5718a14 2125
3ae5eaec 2126 fbi = pxafb_init_fbinfo(&dev->dev);
1da177e4 2127 if (!fbi) {
b0086efb 2128 /* only reason for pxafb_init_fbinfo to fail is kmalloc */
3ae5eaec 2129 dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
b0086efb 2130 ret = -ENOMEM;
1da177e4
LT		 2131 goto failed;
2132 }
2133
52a7a1ce
DM		 2134 if (cpu_is_pxa3xx() && inf->acceleration_enabled)
2135 fbi->fb.fix.accel = FB_ACCEL_PXA3XX;
2136
a5718a14
EM		 2137 fbi->backlight_power = inf->pxafb_backlight_power;
2138 fbi->lcd_power = inf->pxafb_lcd_power;
2139
ce4fb7b8 2140 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
2141 if (r == NULL) {
2142 dev_err(&dev->dev, "no I/O memory resource defined\n");
2143 ret = -ENODEV;
ee98476b 2144 goto failed_fbi;
ce4fb7b8 2145 }
2146
53eff417 2147 r = request_mem_region(r->start, resource_size(r), dev->name);
ce4fb7b8 2148 if (r == NULL) {
2149 dev_err(&dev->dev, "failed to request I/O memory\n");
2150 ret = -EBUSY;
ee98476b 2151 goto failed_fbi;
ce4fb7b8 2152 }
2153
53eff417 2154 fbi->mmio_base = ioremap(r->start, resource_size(r));
ce4fb7b8 2155 if (fbi->mmio_base == NULL) {
2156 dev_err(&dev->dev, "failed to map I/O memory\n");
2157 ret = -EBUSY;
2158 goto failed_free_res;
2159 }
2160
77e19675
EM		 2161 fbi->dma_buff_size = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
2162 fbi->dma_buff = dma_alloc_coherent(fbi->dev, fbi->dma_buff_size,
2163 &fbi->dma_buff_phys, GFP_KERNEL);
2164 if (fbi->dma_buff == NULL) {
2165 dev_err(&dev->dev, "failed to allocate memory for DMA\n");
2166 ret = -ENOMEM;
2167 goto failed_free_io;
2168 }
2169
2170 ret = pxafb_init_video_memory(fbi);
1da177e4 2171 if (ret) {
3ae5eaec 2172 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
1da177e4 2173 ret = -ENOMEM;
77e19675 2174 goto failed_free_dma;
1da177e4 2175 }
1da177e4 2176
ce4fb7b8 2177 irq = platform_get_irq(dev, 0);
2178 if (irq < 0) {
2179 dev_err(&dev->dev, "no IRQ defined\n");
2180 ret = -ENODEV;
2181 goto failed_free_mem;
2182 }
2183
f8798ccb 2184 ret = request_irq(irq, pxafb_handle_irq, 0, "LCD", fbi);
1da177e4 2185 if (ret) {
3ae5eaec 2186 dev_err(&dev->dev, "request_irq failed: %d\n", ret);
1da177e4 2187 ret = -EBUSY;
ce4fb7b8 2188 goto failed_free_mem;
1da177e4
LT		 2189 }
2190
3c42a449
EM		 2191 ret = pxafb_smart_init(fbi);
2192 if (ret) {
2193 dev_err(&dev->dev, "failed to initialize smartpanel\n");
2194 goto failed_free_irq;
2195 }
07df1c4f 2196
1da177e4
LT		 2197 /*
2198 * This makes sure that our colour bitfield
2199 * descriptors are correctly initialised.
2200 */
ee98476b
JK		 2201 ret = pxafb_check_var(&fbi->fb.var, &fbi->fb);
2202 if (ret) {
2203 dev_err(&dev->dev, "failed to get suitable mode\n");
2204 goto failed_free_irq;
2205 }
2206
2207 ret = pxafb_set_par(&fbi->fb);
2208 if (ret) {
2209 dev_err(&dev->dev, "Failed to set parameters\n");
2210 goto failed_free_irq;
2211 }
1da177e4 2212
3ae5eaec 2213 platform_set_drvdata(dev, fbi);
1da177e4
LT		 2214
2215 ret = register_framebuffer(&fbi->fb);
2216 if (ret < 0) {
b0086efb 2217 dev_err(&dev->dev,
2218 "Failed to register framebuffer device: %d\n", ret);
ee98476b 2219 goto failed_free_cmap;
1da177e4
LT		 2220 }
2221
198fc108
EM		 2222 pxafb_overlay_init(fbi);
2223
1da177e4
LT		 2224#ifdef CONFIG_CPU_FREQ
2225 fbi->freq_transition.notifier_call = pxafb_freq_transition;
2226 fbi->freq_policy.notifier_call = pxafb_freq_policy;
b0086efb 2227 cpufreq_register_notifier(&fbi->freq_transition,
2228 CPUFREQ_TRANSITION_NOTIFIER);
2229 cpufreq_register_notifier(&fbi->freq_policy,
2230 CPUFREQ_POLICY_NOTIFIER);
1da177e4
LT		 2231#endif
2232
2233 /*
2234 * Ok, now enable the LCD controller
2235 */
2236 set_ctrlr_state(fbi, C_ENABLE);
2237
2238 return 0;
2239
ee98476b
JK		 2240failed_free_cmap:
2241 if (fbi->fb.cmap.len)
2242 fb_dealloc_cmap(&fbi->fb.cmap);
ce4fb7b8 2243failed_free_irq:
2244 free_irq(irq, fbi);
ce4fb7b8 2245failed_free_mem:
77e19675
EM		 2246 free_pages_exact(fbi->video_mem, fbi->video_mem_size);
2247failed_free_dma:
2248 dma_free_coherent(&dev->dev, fbi->dma_buff_size,
2249 fbi->dma_buff, fbi->dma_buff_phys);
ee98476b
JK		 2250failed_free_io:
2251 iounmap(fbi->mmio_base);
2252failed_free_res:
53eff417 2253 release_mem_region(r->start, resource_size(r));
ee98476b
JK		 2254failed_fbi:
2255 clk_put(fbi->clk);
3ae5eaec 2256 platform_set_drvdata(dev, NULL);
1da177e4 2257 kfree(fbi);
ee98476b 2258failed:
1da177e4
LT		 2259 return ret;
2260}
2261
9f17f287
JK		 2262static int __devexit pxafb_remove(struct platform_device *dev)
2263{
2264 struct pxafb_info *fbi = platform_get_drvdata(dev);
2265 struct resource *r;
2266 int irq;
2267 struct fb_info *info;
2268
2269 if (!fbi)
2270 return 0;
2271
2272 info = &fbi->fb;
2273
198fc108 2274 pxafb_overlay_exit(fbi);
9f17f287
JK		 2275 unregister_framebuffer(info);
2276
2277 pxafb_disable_controller(fbi);
2278
2279 if (fbi->fb.cmap.len)
2280 fb_dealloc_cmap(&fbi->fb.cmap);
2281
2282 irq = platform_get_irq(dev, 0);
2283 free_irq(irq, fbi);
2284
77e19675
EM		 2285 free_pages_exact(fbi->video_mem, fbi->video_mem_size);
2286
2287 dma_free_writecombine(&dev->dev, fbi->dma_buff_size,
2288 fbi->dma_buff, fbi->dma_buff_phys);
9f17f287
JK		 2289
2290 iounmap(fbi->mmio_base);
2291
2292 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
53eff417 2293 release_mem_region(r->start, resource_size(r));
9f17f287
JK		 2294
2295 clk_put(fbi->clk);
2296 kfree(fbi);
2297
2298 return 0;
2299}
2300
3ae5eaec 2301static struct platform_driver pxafb_driver = {
1da177e4 2302 .probe = pxafb_probe,
bdf602bd 2303 .remove = __devexit_p(pxafb_remove),
3ae5eaec 2304 .driver = {
9f17f287 2305 .owner = THIS_MODULE,
3ae5eaec 2306 .name = "pxa2xx-fb",
4f3edfe3
MR		 2307#ifdef CONFIG_PM
2308 .pm = &pxafb_pm_ops,
2309#endif
3ae5eaec 2310 },
1da177e4
LT		 2311};
2312
9e6c2976 2313static int __init pxafb_init(void)
1da177e4 2314{
92ac73c1 2315 if (pxafb_setup_options())
2316 return -EINVAL;
1da177e4 2317
3ae5eaec 2318 return platform_driver_register(&pxafb_driver);
1da177e4
LT		 2319}
2320
9f17f287
JK		 2321static void __exit pxafb_exit(void)
2322{
2323 platform_driver_unregister(&pxafb_driver);
2324}
2325
1da177e4 2326module_init(pxafb_init);
9f17f287 2327module_exit(pxafb_exit);
1da177e4
LT		 2328
2329MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
2330MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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