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[PATCH] Video: fb, kzalloc changes
[deliverable/linux.git] / drivers / video / riva / fbdev.c
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1da177e4
LT		 1/*
2 * linux/drivers/video/riva/fbdev.c - nVidia RIVA 128/TNT/TNT2 fb driver
3 *
4 * Maintained by Ani Joshi <ajoshi@shell.unixbox.com>
5 *
6 * Copyright 1999-2000 Jeff Garzik
7 *
8 * Contributors:
9 *
10 * Ani Joshi: Lots of debugging and cleanup work, really helped
11 * get the driver going
12 *
13 * Ferenc Bakonyi: Bug fixes, cleanup, modularization
14 *
15 * Jindrich Makovicka: Accel code help, hw cursor, mtrr
16 *
17 * Paul Richards: Bug fixes, updates
18 *
19 * Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven
20 * Includes riva_hw.c from nVidia, see copyright below.
21 * KGI code provided the basis for state storage, init, and mode switching.
22 *
23 * This file is subject to the terms and conditions of the GNU General Public
24 * License. See the file COPYING in the main directory of this archive
25 * for more details.
26 *
27 * Known bugs and issues:
28 * restoring text mode fails
29 * doublescan modes are broken
30 */
31
1da177e4
LT		 32#include <linux/module.h>
33#include <linux/kernel.h>
34#include <linux/errno.h>
35#include <linux/string.h>
36#include <linux/mm.h>
1da177e4
LT		 37#include <linux/slab.h>
38#include <linux/delay.h>
39#include <linux/fb.h>
40#include <linux/init.h>
41#include <linux/pci.h>
5474c120 42#include <linux/backlight.h>
1c667682 43#include <linux/bitrev.h>
1da177e4
LT		 44#ifdef CONFIG_MTRR
45#include <asm/mtrr.h>
46#endif
47#ifdef CONFIG_PPC_OF
48#include <asm/prom.h>
49#include <asm/pci-bridge.h>
50#endif
51#ifdef CONFIG_PMAC_BACKLIGHT
e8222502 52#include <asm/machdep.h>
1da177e4
LT		 53#include <asm/backlight.h>
54#endif
55
56#include "rivafb.h"
57#include "nvreg.h"
58
59#ifndef CONFIG_PCI /* sanity check */
60#error This driver requires PCI support.
61#endif
62
63/* version number of this driver */
64#define RIVAFB_VERSION "0.9.5b"
65
66/* ------------------------------------------------------------------------- *
67 *
68 * various helpful macros and constants
69 *
70 * ------------------------------------------------------------------------- */
71#ifdef CONFIG_FB_RIVA_DEBUG
72#define NVTRACE printk
73#else
74#define NVTRACE if(0) printk
75#endif
76
77#define NVTRACE_ENTER(...) NVTRACE("%s START\n", __FUNCTION__)
78#define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __FUNCTION__)
79
80#ifdef CONFIG_FB_RIVA_DEBUG
81#define assert(expr) \
82 if(!(expr)) { \
83 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
84 #expr,__FILE__,__FUNCTION__,__LINE__); \
85 BUG(); \
86 }
87#else
88#define assert(expr)
89#endif
90
91#define PFX "rivafb: "
92
93/* macro that allows you to set overflow bits */
94#define SetBitField(value,from,to) SetBF(to,GetBF(value,from))
95#define SetBit(n) (1<<(n))
96#define Set8Bits(value) ((value)&0xff)
97
98/* HW cursor parameters */
99#define MAX_CURS 32
100
101/* ------------------------------------------------------------------------- *
102 *
103 * prototypes
104 *
105 * ------------------------------------------------------------------------- */
106
107static int rivafb_blank(int blank, struct fb_info *info);
108
109/* ------------------------------------------------------------------------- *
110 *
111 * card identification
112 *
113 * ------------------------------------------------------------------------- */
114
115static struct pci_device_id rivafb_pci_tbl[] = {
116 { PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128,
117 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
118 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT,
119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
120 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2,
121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
122 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
124 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2,
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
126 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2,
127 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
128 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2,
129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
130 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR,
131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
132 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR,
133 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
134 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO,
135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
136 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
138 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
140 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
141 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
142 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
143 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
144 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
145 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
146 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
147 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
148 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
149 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
150 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
151 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
152 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
153 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
154 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
155 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
156 // NF2/IGP version, GeForce 4 MX, NV18
157 { PCI_VENDOR_ID_NVIDIA, 0x01f0,
158 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
159 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
160 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
161 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
162 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
163 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
165 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
166 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
167 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
168 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
169 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
170 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
171 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
173 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
175 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
177 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
179 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
181 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
183 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
185 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
187 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
189 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
191 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
193 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
195 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
197 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
199 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200,
200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
201 { 0, } /* terminate list */
202};
203MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl);
204
205/* ------------------------------------------------------------------------- *
206 *
207 * global variables
208 *
209 * ------------------------------------------------------------------------- */
210
211/* command line data, set in rivafb_setup() */
212static int flatpanel __devinitdata = -1; /* Autodetect later */
213static int forceCRTC __devinitdata = -1;
214static int noaccel __devinitdata = 0;
215#ifdef CONFIG_MTRR
216static int nomtrr __devinitdata = 0;
217#endif
218
219static char *mode_option __devinitdata = NULL;
220static int strictmode = 0;
221
222static struct fb_fix_screeninfo __devinitdata rivafb_fix = {
223 .type = FB_TYPE_PACKED_PIXELS,
224 .xpanstep = 1,
225 .ypanstep = 1,
226};
227
228static struct fb_var_screeninfo __devinitdata rivafb_default_var = {
229 .xres = 640,
230 .yres = 480,
231 .xres_virtual = 640,
232 .yres_virtual = 480,
233 .bits_per_pixel = 8,
234 .red = {0, 8, 0},
235 .green = {0, 8, 0},
236 .blue = {0, 8, 0},
237 .transp = {0, 0, 0},
238 .activate = FB_ACTIVATE_NOW,
239 .height = -1,
240 .width = -1,
241 .pixclock = 39721,
242 .left_margin = 40,
243 .right_margin = 24,
244 .upper_margin = 32,
245 .lower_margin = 11,
246 .hsync_len = 96,
247 .vsync_len = 2,
248 .vmode = FB_VMODE_NONINTERLACED
249};
250
251/* from GGI */
252static const struct riva_regs reg_template = {
253 {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */
254 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
255 0x41, 0x01, 0x0F, 0x00, 0x00},
256 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* CRT */
257 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
258 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3, /* 0x10 */
259 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
260 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */
261 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
262 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x30 */
263 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
264 0x00, /* 0x40 */
265 },
266 {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, /* GRA */
267 0xFF},
268 {0x03, 0x01, 0x0F, 0x00, 0x0E}, /* SEQ */
269 0xEB /* MISC */
270};
271
272/*
273 * Backlight control
274 */
5474c120
MH		 275#ifdef CONFIG_FB_RIVA_BACKLIGHT
276/* We do not have any information about which values are allowed, thus
277 * we used safe values.
278 */
279#define MIN_LEVEL 0x158
280#define MAX_LEVEL 0x534
e01af038 281#define LEVEL_STEP ((MAX_LEVEL - MIN_LEVEL) / FB_BACKLIGHT_MAX)
1da177e4 282
5474c120
MH		 283static struct backlight_properties riva_bl_data;
284
e01af038 285/* Call with fb_info->bl_mutex held */
5474c120
MH		 286static int riva_bl_get_level_brightness(struct riva_par *par,
287 int level)
288{
289 struct fb_info *info = pci_get_drvdata(par->pdev);
290 int nlevel;
291
292 /* Get and convert the value */
e01af038 293 nlevel = MIN_LEVEL + info->bl_curve[level] * LEVEL_STEP;
5474c120
MH		 294
295 if (nlevel < 0)
296 nlevel = 0;
297 else if (nlevel < MIN_LEVEL)
298 nlevel = MIN_LEVEL;
299 else if (nlevel > MAX_LEVEL)
300 nlevel = MAX_LEVEL;
301
302 return nlevel;
303}
304
e01af038
MH		 305/* Call with fb_info->bl_mutex held */
306static int __riva_bl_update_status(struct backlight_device *bd)
5474c120
MH		 307{
308 struct riva_par *par = class_get_devdata(&bd->class_dev);
309 U032 tmp_pcrt, tmp_pmc;
310 int level;
311
312 if (bd->props->power != FB_BLANK_UNBLANK ||
313 bd->props->fb_blank != FB_BLANK_UNBLANK)
314 level = 0;
315 else
316 level = bd->props->brightness;
317
318 tmp_pmc = par->riva.PMC[0x10F0/4] & 0x0000FFFF;
319 tmp_pcrt = par->riva.PCRTC0[0x081C/4] & 0xFFFFFFFC;
320 if(level > 0) {
321 tmp_pcrt |= 0x1;
322 tmp_pmc |= (1 << 31); /* backlight bit */
323 tmp_pmc |= riva_bl_get_level_brightness(par, level) << 16; /* level */
324 }
325 par->riva.PCRTC0[0x081C/4] = tmp_pcrt;
326 par->riva.PMC[0x10F0/4] = tmp_pmc;
327
328 return 0;
329}
330
e01af038
MH		 331static int riva_bl_update_status(struct backlight_device *bd)
332{
333 struct riva_par *par = class_get_devdata(&bd->class_dev);
334 struct fb_info *info = pci_get_drvdata(par->pdev);
335 int ret;
336
337 mutex_lock(&info->bl_mutex);
338 ret = __riva_bl_update_status(bd);
339 mutex_unlock(&info->bl_mutex);
340
341 return ret;
342}
343
5474c120
MH		 344static int riva_bl_get_brightness(struct backlight_device *bd)
345{
346 return bd->props->brightness;
347}
1da177e4 348
5474c120
MH		 349static struct backlight_properties riva_bl_data = {
350 .owner = THIS_MODULE,
351 .get_brightness = riva_bl_get_brightness,
352 .update_status = riva_bl_update_status,
353 .max_brightness = (FB_BACKLIGHT_LEVELS - 1),
1da177e4 354};
5474c120 355
e01af038
MH		 356static void riva_bl_set_power(struct fb_info *info, int power)
357{
358 mutex_lock(&info->bl_mutex);
a9303638
BH		 359
360 if (info->bl_dev) {
361 down(&info->bl_dev->sem);
362 info->bl_dev->props->power = power;
363 __riva_bl_update_status(info->bl_dev);
364 up(&info->bl_dev->sem);
365 }
366
e01af038
MH		 367 mutex_unlock(&info->bl_mutex);
368}
369
5474c120
MH		 370static void riva_bl_init(struct riva_par *par)
371{
372 struct fb_info *info = pci_get_drvdata(par->pdev);
373 struct backlight_device *bd;
374 char name[12];
375
376 if (!par->FlatPanel)
377 return;
378
379#ifdef CONFIG_PMAC_BACKLIGHT
380 if (!machine_is(powermac) ||
381 !pmac_has_backlight_type("mnca"))
382 return;
383#endif
384
385 snprintf(name, sizeof(name), "rivabl%d", info->node);
386
a8274d57 387 bd = backlight_device_register(name, info->dev, par, &riva_bl_data);
5474c120
MH		 388 if (IS_ERR(bd)) {
389 info->bl_dev = NULL;
98a3c781 390 printk(KERN_WARNING "riva: Backlight registration failed\n");
5474c120
MH		 391 goto error;
392 }
393
394 mutex_lock(&info->bl_mutex);
395 info->bl_dev = bd;
396 fb_bl_default_curve(info, 0,
535a09ad
GG		 397 MIN_LEVEL * FB_BACKLIGHT_MAX / MAX_LEVEL,
398 FB_BACKLIGHT_MAX);
5474c120
MH		 399 mutex_unlock(&info->bl_mutex);
400
a9303638 401 down(&bd->sem);
5474c120
MH		 402 bd->props->brightness = riva_bl_data.max_brightness;
403 bd->props->power = FB_BLANK_UNBLANK;
404 bd->props->update_status(bd);
a9303638 405 up(&bd->sem);
5474c120
MH		 406
407#ifdef CONFIG_PMAC_BACKLIGHT
408 mutex_lock(&pmac_backlight_mutex);
409 if (!pmac_backlight)
410 pmac_backlight = bd;
411 mutex_unlock(&pmac_backlight_mutex);
412#endif
413
414 printk("riva: Backlight initialized (%s)\n", name);
415
416 return;
417
418error:
419 return;
420}
421
422static void riva_bl_exit(struct riva_par *par)
423{
424 struct fb_info *info = pci_get_drvdata(par->pdev);
425
426#ifdef CONFIG_PMAC_BACKLIGHT
427 mutex_lock(&pmac_backlight_mutex);
428#endif
429
430 mutex_lock(&info->bl_mutex);
431 if (info->bl_dev) {
432#ifdef CONFIG_PMAC_BACKLIGHT
433 if (pmac_backlight == info->bl_dev)
434 pmac_backlight = NULL;
435#endif
436
437 backlight_device_unregister(info->bl_dev);
438
439 printk("riva: Backlight unloaded\n");
440 }
441 mutex_unlock(&info->bl_mutex);
442
443#ifdef CONFIG_PMAC_BACKLIGHT
444 mutex_unlock(&pmac_backlight_mutex);
445#endif
446}
447#else
448static inline void riva_bl_init(struct riva_par *par) {}
449static inline void riva_bl_exit(struct riva_par *par) {}
e01af038 450static inline void riva_bl_set_power(struct fb_info *info, int power) {}
5474c120 451#endif /* CONFIG_FB_RIVA_BACKLIGHT */
1da177e4
LT		 452
453/* ------------------------------------------------------------------------- *
454 *
455 * MMIO access macros
456 *
457 * ------------------------------------------------------------------------- */
458
459static inline void CRTCout(struct riva_par *par, unsigned char index,
460 unsigned char val)
461{
462 VGA_WR08(par->riva.PCIO, 0x3d4, index);
463 VGA_WR08(par->riva.PCIO, 0x3d5, val);
464}
465
466static inline unsigned char CRTCin(struct riva_par *par,
467 unsigned char index)
468{
469 VGA_WR08(par->riva.PCIO, 0x3d4, index);
470 return (VGA_RD08(par->riva.PCIO, 0x3d5));
471}
472
473static inline void GRAout(struct riva_par *par, unsigned char index,
474 unsigned char val)
475{
476 VGA_WR08(par->riva.PVIO, 0x3ce, index);
477 VGA_WR08(par->riva.PVIO, 0x3cf, val);
478}
479
480static inline unsigned char GRAin(struct riva_par *par,
481 unsigned char index)
482{
483 VGA_WR08(par->riva.PVIO, 0x3ce, index);
484 return (VGA_RD08(par->riva.PVIO, 0x3cf));
485}
486
487static inline void SEQout(struct riva_par *par, unsigned char index,
488 unsigned char val)
489{
490 VGA_WR08(par->riva.PVIO, 0x3c4, index);
491 VGA_WR08(par->riva.PVIO, 0x3c5, val);
492}
493
494static inline unsigned char SEQin(struct riva_par *par,
495 unsigned char index)
496{
497 VGA_WR08(par->riva.PVIO, 0x3c4, index);
498 return (VGA_RD08(par->riva.PVIO, 0x3c5));
499}
500
501static inline void ATTRout(struct riva_par *par, unsigned char index,
502 unsigned char val)
503{
504 VGA_WR08(par->riva.PCIO, 0x3c0, index);
505 VGA_WR08(par->riva.PCIO, 0x3c0, val);
506}
507
508static inline unsigned char ATTRin(struct riva_par *par,
509 unsigned char index)
510{
511 VGA_WR08(par->riva.PCIO, 0x3c0, index);
512 return (VGA_RD08(par->riva.PCIO, 0x3c1));
513}
514
515static inline void MISCout(struct riva_par *par, unsigned char val)
516{
517 VGA_WR08(par->riva.PVIO, 0x3c2, val);
518}
519
520static inline unsigned char MISCin(struct riva_par *par)
521{
522 return (VGA_RD08(par->riva.PVIO, 0x3cc));
523}
524
1da177e4
LT		 525static inline void reverse_order(u32 *l)
526{
527 u8 *a = (u8 *)l;
1c667682
AM		 528 a[0] = bitrev8(a[0]);
529 a[1] = bitrev8(a[1]);
530 a[2] = bitrev8(a[2]);
531 a[3] = bitrev8(a[3]);
1da177e4
LT		 532}
533
534/* ------------------------------------------------------------------------- *
535 *
536 * cursor stuff
537 *
538 * ------------------------------------------------------------------------- */
539
540/**
541 * rivafb_load_cursor_image - load cursor image to hardware
542 * @data: address to monochrome bitmap (1 = foreground color, 0 = background)
543 * @par: pointer to private data
544 * @w: width of cursor image in pixels
545 * @h: height of cursor image in scanlines
546 * @bg: background color (ARGB1555) - alpha bit determines opacity
547 * @fg: foreground color (ARGB1555)
548 *
549 * DESCRIPTiON:
550 * Loads cursor image based on a monochrome source and mask bitmap. The
551 * image bits determines the color of the pixel, 0 for background, 1 for
552 * foreground. Only the affected region (as determined by @w and @h
553 * parameters) will be updated.
554 *
555 * CALLED FROM:
556 * rivafb_cursor()
557 */
558static void rivafb_load_cursor_image(struct riva_par *par, u8 *data8,
559 u16 bg, u16 fg, u32 w, u32 h)
560{
561 int i, j, k = 0;
562 u32 b, tmp;
563 u32 *data = (u32 *)data8;
564 bg = le16_to_cpu(bg);
565 fg = le16_to_cpu(fg);
566
567 w = (w + 1) & ~1;
568
569 for (i = 0; i < h; i++) {
570 b = *data++;
571 reverse_order(&b);
572
573 for (j = 0; j < w/2; j++) {
574 tmp = 0;
575#if defined (__BIG_ENDIAN)
576 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
577 b <<= 1;
578 tmp |= (b & (1 << 31)) ? fg : bg;
579 b <<= 1;
580#else
581 tmp = (b & 1) ? fg : bg;
582 b >>= 1;
583 tmp |= (b & 1) ? fg << 16 : bg << 16;
584 b >>= 1;
585#endif
586 writel(tmp, &par->riva.CURSOR[k++]);
587 }
588 k += (MAX_CURS - w)/2;
589 }
590}
591
592/* ------------------------------------------------------------------------- *
593 *
594 * general utility functions
595 *
596 * ------------------------------------------------------------------------- */
597
598/**
599 * riva_wclut - set CLUT entry
600 * @chip: pointer to RIVA_HW_INST object
601 * @regnum: register number
602 * @red: red component
603 * @green: green component
604 * @blue: blue component
605 *
606 * DESCRIPTION:
607 * Sets color register @regnum.
608 *
609 * CALLED FROM:
610 * rivafb_setcolreg()
611 */
612static void riva_wclut(RIVA_HW_INST *chip,
613 unsigned char regnum, unsigned char red,
614 unsigned char green, unsigned char blue)
615{
616 VGA_WR08(chip->PDIO, 0x3c8, regnum);
617 VGA_WR08(chip->PDIO, 0x3c9, red);
618 VGA_WR08(chip->PDIO, 0x3c9, green);
619 VGA_WR08(chip->PDIO, 0x3c9, blue);
620}
621
622/**
623 * riva_rclut - read fromCLUT register
624 * @chip: pointer to RIVA_HW_INST object
625 * @regnum: register number
626 * @red: red component
627 * @green: green component
628 * @blue: blue component
629 *
630 * DESCRIPTION:
631 * Reads red, green, and blue from color register @regnum.
632 *
633 * CALLED FROM:
634 * rivafb_setcolreg()
635 */
636static void riva_rclut(RIVA_HW_INST *chip,
637 unsigned char regnum, unsigned char *red,
638 unsigned char *green, unsigned char *blue)
639{
640
641 VGA_WR08(chip->PDIO, 0x3c7, regnum);
642 *red = VGA_RD08(chip->PDIO, 0x3c9);
643 *green = VGA_RD08(chip->PDIO, 0x3c9);
644 *blue = VGA_RD08(chip->PDIO, 0x3c9);
645}
646
647/**
648 * riva_save_state - saves current chip state
649 * @par: pointer to riva_par object containing info for current riva board
650 * @regs: pointer to riva_regs object
651 *
652 * DESCRIPTION:
653 * Saves current chip state to @regs.
654 *
655 * CALLED FROM:
656 * rivafb_probe()
657 */
658/* from GGI */
659static void riva_save_state(struct riva_par *par, struct riva_regs *regs)
660{
661 int i;
662
663 NVTRACE_ENTER();
664 par->riva.LockUnlock(&par->riva, 0);
665
666 par->riva.UnloadStateExt(&par->riva, &regs->ext);
667
668 regs->misc_output = MISCin(par);
669
670 for (i = 0; i < NUM_CRT_REGS; i++)
671 regs->crtc[i] = CRTCin(par, i);
672
673 for (i = 0; i < NUM_ATC_REGS; i++)
674 regs->attr[i] = ATTRin(par, i);
675
676 for (i = 0; i < NUM_GRC_REGS; i++)
677 regs->gra[i] = GRAin(par, i);
678
679 for (i = 0; i < NUM_SEQ_REGS; i++)
680 regs->seq[i] = SEQin(par, i);
681 NVTRACE_LEAVE();
682}
683
684/**
685 * riva_load_state - loads current chip state
686 * @par: pointer to riva_par object containing info for current riva board
687 * @regs: pointer to riva_regs object
688 *
689 * DESCRIPTION:
690 * Loads chip state from @regs.
691 *
692 * CALLED FROM:
693 * riva_load_video_mode()
694 * rivafb_probe()
695 * rivafb_remove()
696 */
697/* from GGI */
698static void riva_load_state(struct riva_par *par, struct riva_regs *regs)
699{
700 RIVA_HW_STATE *state = &regs->ext;
701 int i;
702
703 NVTRACE_ENTER();
704 CRTCout(par, 0x11, 0x00);
705
706 par->riva.LockUnlock(&par->riva, 0);
707
708 par->riva.LoadStateExt(&par->riva, state);
709
710 MISCout(par, regs->misc_output);
711
712 for (i = 0; i < NUM_CRT_REGS; i++) {
713 switch (i) {
714 case 0x19:
715 case 0x20 ... 0x40:
716 break;
717 default:
718 CRTCout(par, i, regs->crtc[i]);
719 }
720 }
721
722 for (i = 0; i < NUM_ATC_REGS; i++)
723 ATTRout(par, i, regs->attr[i]);
724
725 for (i = 0; i < NUM_GRC_REGS; i++)
726 GRAout(par, i, regs->gra[i]);
727
728 for (i = 0; i < NUM_SEQ_REGS; i++)
729 SEQout(par, i, regs->seq[i]);
730 NVTRACE_LEAVE();
731}
732
733/**
734 * riva_load_video_mode - calculate timings
735 * @info: pointer to fb_info object containing info for current riva board
736 *
737 * DESCRIPTION:
738 * Calculate some timings and then send em off to riva_load_state().
739 *
740 * CALLED FROM:
741 * rivafb_set_par()
742 */
fd717689 743static int riva_load_video_mode(struct fb_info *info)
1da177e4
LT		 744{
745 int bpp, width, hDisplaySize, hDisplay, hStart,
746 hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock;
747 int hBlankStart, hBlankEnd, vBlankStart, vBlankEnd;
fd717689 748 int rc;
f4a41836 749 struct riva_par *par = info->par;
1da177e4
LT		 750 struct riva_regs newmode;
751
752 NVTRACE_ENTER();
753 /* time to calculate */
535a09ad 754 rivafb_blank(FB_BLANK_NORMAL, info);
1da177e4
LT		 755
756 bpp = info->var.bits_per_pixel;
757 if (bpp == 16 && info->var.green.length == 5)
758 bpp = 15;
759 width = info->var.xres_virtual;
760 hDisplaySize = info->var.xres;
761 hDisplay = (hDisplaySize / 8) - 1;
762 hStart = (hDisplaySize + info->var.right_margin) / 8 - 1;
763 hEnd = (hDisplaySize + info->var.right_margin +
764 info->var.hsync_len) / 8 - 1;
765 hTotal = (hDisplaySize + info->var.right_margin +
766 info->var.hsync_len + info->var.left_margin) / 8 - 5;
767 hBlankStart = hDisplay;
768 hBlankEnd = hTotal + 4;
769
770 height = info->var.yres_virtual;
771 vDisplay = info->var.yres - 1;
772 vStart = info->var.yres + info->var.lower_margin - 1;
773 vEnd = info->var.yres + info->var.lower_margin +
774 info->var.vsync_len - 1;
775 vTotal = info->var.yres + info->var.lower_margin +
776 info->var.vsync_len + info->var.upper_margin + 2;
777 vBlankStart = vDisplay;
778 vBlankEnd = vTotal + 1;
779 dotClock = 1000000000 / info->var.pixclock;
780
781 memcpy(&newmode, &reg_template, sizeof(struct riva_regs));
782
783 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
784 vTotal |= 1;
785
786 if (par->FlatPanel) {
787 vStart = vTotal - 3;
788 vEnd = vTotal - 2;
789 vBlankStart = vStart;
790 hStart = hTotal - 3;
791 hEnd = hTotal - 2;
792 hBlankEnd = hTotal + 4;
793 }
794
795 newmode.crtc[0x0] = Set8Bits (hTotal);
796 newmode.crtc[0x1] = Set8Bits (hDisplay);
797 newmode.crtc[0x2] = Set8Bits (hBlankStart);
798 newmode.crtc[0x3] = SetBitField (hBlankEnd, 4: 0, 4:0) | SetBit (7);
799 newmode.crtc[0x4] = Set8Bits (hStart);
800 newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7)
801 | SetBitField (hEnd, 4: 0, 4:0);
802 newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0);
803 newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0)
804 | SetBitField (vDisplay, 8: 8, 1:1)
805 | SetBitField (vStart, 8: 8, 2:2)
806 | SetBitField (vBlankStart, 8: 8, 3:3)
807 | SetBit (4)
808 | SetBitField (vTotal, 9: 9, 5:5)
809 | SetBitField (vDisplay, 9: 9, 6:6)
810 | SetBitField (vStart, 9: 9, 7:7);
811 newmode.crtc[0x9] = SetBitField (vBlankStart, 9: 9, 5:5)
812 | SetBit (6);
813 newmode.crtc[0x10] = Set8Bits (vStart);
814 newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0)
815 | SetBit (5);
816 newmode.crtc[0x12] = Set8Bits (vDisplay);
817 newmode.crtc[0x13] = (width / 8) * ((bpp + 1) / 8);
818 newmode.crtc[0x15] = Set8Bits (vBlankStart);
819 newmode.crtc[0x16] = Set8Bits (vBlankEnd);
820
821 newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4)
822 | SetBitField(vBlankStart,10:10,3:3)
823 | SetBitField(vStart,10:10,2:2)
824 | SetBitField(vDisplay,10:10,1:1)
825 | SetBitField(vTotal,10:10,0:0);
826 newmode.ext.horiz = SetBitField(hTotal,8:8,0:0)
827 | SetBitField(hDisplay,8:8,1:1)
828 | SetBitField(hBlankStart,8:8,2:2)
829 | SetBitField(hStart,8:8,3:3);
830 newmode.ext.extra = SetBitField(vTotal,11:11,0:0)
831 | SetBitField(vDisplay,11:11,2:2)
832 | SetBitField(vStart,11:11,4:4)
833 | SetBitField(vBlankStart,11:11,6:6);
834
835 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
836 int tmp = (hTotal >> 1) & ~1;
837 newmode.ext.interlace = Set8Bits(tmp);
838 newmode.ext.horiz |= SetBitField(tmp, 8:8,4:4);
839 } else
840 newmode.ext.interlace = 0xff; /* interlace off */
841
842 if (par->riva.Architecture >= NV_ARCH_10)
843 par->riva.CURSOR = (U032 __iomem *)(info->screen_base + par->riva.CursorStart);
844
845 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
846 newmode.misc_output &= ~0x40;
847 else
848 newmode.misc_output |= 0x40;
849 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
850 newmode.misc_output &= ~0x80;
851 else
852 newmode.misc_output |= 0x80;
853
fd717689
JG		 854 rc = CalcStateExt(&par->riva, &newmode.ext, bpp, width,
855 hDisplaySize, height, dotClock);
856 if (rc)
857 goto out;
1da177e4
LT		 858
859 newmode.ext.scale = NV_RD32(par->riva.PRAMDAC, 0x00000848) &
860 0xfff000ff;
861 if (par->FlatPanel == 1) {
862 newmode.ext.pixel |= (1 << 7);
863 newmode.ext.scale |= (1 << 8);
864 }
865 if (par->SecondCRTC) {
866 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) &
867 ~0x00001000;
868 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) |
869 0x00001000;
870 newmode.ext.crtcOwner = 3;
871 newmode.ext.pllsel |= 0x20000800;
872 newmode.ext.vpll2 = newmode.ext.vpll;
873 } else if (par->riva.twoHeads) {
874 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) |
875 0x00001000;
876 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) &
877 ~0x00001000;
878 newmode.ext.crtcOwner = 0;
879 newmode.ext.vpll2 = NV_RD32(par->riva.PRAMDAC0, 0x00000520);
880 }
881 if (par->FlatPanel == 1) {
882 newmode.ext.pixel |= (1 << 7);
883 newmode.ext.scale |= (1 << 8);
884 }
885 newmode.ext.cursorConfig = 0x02000100;
886 par->current_state = newmode;
887 riva_load_state(par, &par->current_state);
888 par->riva.LockUnlock(&par->riva, 0); /* important for HW cursor */
fd717689
JG		 889
890out:
535a09ad 891 rivafb_blank(FB_BLANK_UNBLANK, info);
1da177e4 892 NVTRACE_LEAVE();
fd717689
JG		 893
894 return rc;
1da177e4
LT		 895}
896
897static void riva_update_var(struct fb_var_screeninfo *var, struct fb_videomode *modedb)
898{
899 NVTRACE_ENTER();
900 var->xres = var->xres_virtual = modedb->xres;
901 var->yres = modedb->yres;
902 if (var->yres_virtual < var->yres)
903 var->yres_virtual = var->yres;
904 var->xoffset = var->yoffset = 0;
905 var->pixclock = modedb->pixclock;
906 var->left_margin = modedb->left_margin;
907 var->right_margin = modedb->right_margin;
908 var->upper_margin = modedb->upper_margin;
909 var->lower_margin = modedb->lower_margin;
910 var->hsync_len = modedb->hsync_len;
911 var->vsync_len = modedb->vsync_len;
912 var->sync = modedb->sync;
913 var->vmode = modedb->vmode;
914 NVTRACE_LEAVE();
915}
916
917/**
918 * rivafb_do_maximize -
919 * @info: pointer to fb_info object containing info for current riva board
920 * @var:
921 * @nom:
922 * @den:
923 *
924 * DESCRIPTION:
925 * .
926 *
927 * RETURNS:
928 * -EINVAL on failure, 0 on success
929 *
930 *
931 * CALLED FROM:
932 * rivafb_check_var()
933 */
934static int rivafb_do_maximize(struct fb_info *info,
935 struct fb_var_screeninfo *var,
936 int nom, int den)
937{
938 static struct {
939 int xres, yres;
940 } modes[] = {
941 {1600, 1280},
942 {1280, 1024},
943 {1024, 768},
944 {800, 600},
945 {640, 480},
946 {-1, -1}
947 };
948 int i;
949
950 NVTRACE_ENTER();
951 /* use highest possible virtual resolution */
952 if (var->xres_virtual == -1 && var->yres_virtual == -1) {
953 printk(KERN_WARNING PFX
954 "using maximum available virtual resolution\n");
955 for (i = 0; modes[i].xres != -1; i++) {
956 if (modes[i].xres * nom / den * modes[i].yres <
957 info->fix.smem_len)
958 break;
959 }
960 if (modes[i].xres == -1) {
961 printk(KERN_ERR PFX
962 "could not find a virtual resolution that fits into video memory!!\n");
963 NVTRACE("EXIT - EINVAL error\n");
964 return -EINVAL;
965 }
966 var->xres_virtual = modes[i].xres;
967 var->yres_virtual = modes[i].yres;
968
969 printk(KERN_INFO PFX
970 "virtual resolution set to maximum of %dx%d\n",
971 var->xres_virtual, var->yres_virtual);
972 } else if (var->xres_virtual == -1) {
973 var->xres_virtual = (info->fix.smem_len * den /
974 (nom * var->yres_virtual)) & ~15;
975 printk(KERN_WARNING PFX
976 "setting virtual X resolution to %d\n", var->xres_virtual);
977 } else if (var->yres_virtual == -1) {
978 var->xres_virtual = (var->xres_virtual + 15) & ~15;
979 var->yres_virtual = info->fix.smem_len * den /
980 (nom * var->xres_virtual);
981 printk(KERN_WARNING PFX
982 "setting virtual Y resolution to %d\n", var->yres_virtual);
983 } else {
984 var->xres_virtual = (var->xres_virtual + 15) & ~15;
985 if (var->xres_virtual * nom / den * var->yres_virtual > info->fix.smem_len) {
986 printk(KERN_ERR PFX
987 "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n",
988 var->xres, var->yres, var->bits_per_pixel);
989 NVTRACE("EXIT - EINVAL error\n");
990 return -EINVAL;
991 }
992 }
993
994 if (var->xres_virtual * nom / den >= 8192) {
995 printk(KERN_WARNING PFX
996 "virtual X resolution (%d) is too high, lowering to %d\n",
997 var->xres_virtual, 8192 * den / nom - 16);
998 var->xres_virtual = 8192 * den / nom - 16;
999 }
1000
1001 if (var->xres_virtual < var->xres) {
1002 printk(KERN_ERR PFX
1003 "virtual X resolution (%d) is smaller than real\n", var->xres_virtual);
1004 return -EINVAL;
1005 }
1006
1007 if (var->yres_virtual < var->yres) {
1008 printk(KERN_ERR PFX
1009 "virtual Y resolution (%d) is smaller than real\n", var->yres_virtual);
1010 return -EINVAL;
1011 }
1012 if (var->yres_virtual > 0x7fff/nom)
1013 var->yres_virtual = 0x7fff/nom;
1014 if (var->xres_virtual > 0x7fff/nom)
1015 var->xres_virtual = 0x7fff/nom;
1016 NVTRACE_LEAVE();
1017 return 0;
1018}
1019
1020static void
1021riva_set_pattern(struct riva_par *par, int clr0, int clr1, int pat0, int pat1)
1022{
1023 RIVA_FIFO_FREE(par->riva, Patt, 4);
1024 NV_WR32(&par->riva.Patt->Color0, 0, clr0);
1025 NV_WR32(&par->riva.Patt->Color1, 0, clr1);
1026 NV_WR32(par->riva.Patt->Monochrome, 0, pat0);
1027 NV_WR32(par->riva.Patt->Monochrome, 4, pat1);
1028}
1029
1030/* acceleration routines */
1031static inline void wait_for_idle(struct riva_par *par)
1032{
1033 while (par->riva.Busy(&par->riva));
1034}
1035
1036/*
1037 * Set ROP. Translate X rop into ROP3. Internal routine.
1038 */
1039static void
1040riva_set_rop_solid(struct riva_par *par, int rop)
1041{
1042 riva_set_pattern(par, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
1043 RIVA_FIFO_FREE(par->riva, Rop, 1);
1044 NV_WR32(&par->riva.Rop->Rop3, 0, rop);
1045
1046}
1047
1048static void riva_setup_accel(struct fb_info *info)
1049{
f4a41836 1050 struct riva_par *par = info->par;
1da177e4
LT		 1051
1052 RIVA_FIFO_FREE(par->riva, Clip, 2);
1053 NV_WR32(&par->riva.Clip->TopLeft, 0, 0x0);
1054 NV_WR32(&par->riva.Clip->WidthHeight, 0,
1055 (info->var.xres_virtual & 0xffff) |
1056 (info->var.yres_virtual << 16));
1057 riva_set_rop_solid(par, 0xcc);
1058 wait_for_idle(par);
1059}
1060
1061/**
1062 * riva_get_cmap_len - query current color map length
1063 * @var: standard kernel fb changeable data
1064 *
1065 * DESCRIPTION:
1066 * Get current color map length.
1067 *
1068 * RETURNS:
1069 * Length of color map
1070 *
1071 * CALLED FROM:
1072 * rivafb_setcolreg()
1073 */
1074static int riva_get_cmap_len(const struct fb_var_screeninfo *var)
1075{
1076 int rc = 256; /* reasonable default */
1077
1078 switch (var->green.length) {
1079 case 8:
1080 rc = 256; /* 256 entries (2^8), 8 bpp and RGB8888 */
1081 break;
1082 case 5:
1083 rc = 32; /* 32 entries (2^5), 16 bpp, RGB555 */
1084 break;
1085 case 6:
1086 rc = 64; /* 64 entries (2^6), 16 bpp, RGB565 */
1087 break;
1088 default:
1089 /* should not occur */
1090 break;
1091 }
1092 return rc;
1093}
1094
1da177e4
LT		 1095/* ------------------------------------------------------------------------- *
1096 *
1097 * framebuffer operations
1098 *
1099 * ------------------------------------------------------------------------- */
1100
1101static int rivafb_open(struct fb_info *info, int user)
1102{
f4a41836 1103 struct riva_par *par = info->par;
1da177e4
LT		 1104
1105 NVTRACE_ENTER();
c4f28e54
JS		 1106 mutex_lock(&par->open_lock);
1107 if (!par->ref_count) {
1da177e4
LT		 1108#ifdef CONFIG_X86
1109 memset(&par->state, 0, sizeof(struct vgastate));
1110 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS;
1111 /* save the DAC for Riva128 */
1112 if (par->riva.Architecture == NV_ARCH_03)
1113 par->state.flags |= VGA_SAVE_CMAP;
1114 save_vga(&par->state);
1115#endif
1116 /* vgaHWunlock() + riva unlock (0x7F) */
1117 CRTCout(par, 0x11, 0xFF);
1118 par->riva.LockUnlock(&par->riva, 0);
1119
1120 riva_save_state(par, &par->initial_state);
1121 }
c4f28e54
JS		 1122 par->ref_count++;
1123 mutex_unlock(&par->open_lock);
1da177e4
LT		 1124 NVTRACE_LEAVE();
1125 return 0;
1126}
1127
1128static int rivafb_release(struct fb_info *info, int user)
1129{
f4a41836 1130 struct riva_par *par = info->par;
1da177e4
LT		 1131
1132 NVTRACE_ENTER();
c4f28e54
JS		 1133 mutex_lock(&par->open_lock);
1134 if (!par->ref_count) {
1135 mutex_unlock(&par->open_lock);
1da177e4 1136 return -EINVAL;
c4f28e54
JS		 1137 }
1138 if (par->ref_count == 1) {
1da177e4
LT		 1139 par->riva.LockUnlock(&par->riva, 0);
1140 par->riva.LoadStateExt(&par->riva, &par->initial_state.ext);
1141 riva_load_state(par, &par->initial_state);
1142#ifdef CONFIG_X86
1143 restore_vga(&par->state);
1144#endif
1145 par->riva.LockUnlock(&par->riva, 1);
1146 }
c4f28e54
JS		 1147 par->ref_count--;
1148 mutex_unlock(&par->open_lock);
1da177e4
LT		 1149 NVTRACE_LEAVE();
1150 return 0;
1151}
1152
1153static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1154{
1155 struct fb_videomode *mode;
f4a41836 1156 struct riva_par *par = info->par;
1da177e4
LT		 1157 int nom, den; /* translating from pixels->bytes */
1158 int mode_valid = 0;
1159
1160 NVTRACE_ENTER();
1161 switch (var->bits_per_pixel) {
1162 case 1 ... 8:
1163 var->red.offset = var->green.offset = var->blue.offset = 0;
1164 var->red.length = var->green.length = var->blue.length = 8;
1165 var->bits_per_pixel = 8;
1166 nom = den = 1;
1167 break;
1168 case 9 ... 15:
1169 var->green.length = 5;
1170 /* fall through */
1171 case 16:
1172 var->bits_per_pixel = 16;
1173 /* The Riva128 supports RGB555 only */
1174 if (par->riva.Architecture == NV_ARCH_03)
1175 var->green.length = 5;
1176 if (var->green.length == 5) {
1177 /* 0rrrrrgg gggbbbbb */
1178 var->red.offset = 10;
1179 var->green.offset = 5;
1180 var->blue.offset = 0;
1181 var->red.length = 5;
1182 var->green.length = 5;
1183 var->blue.length = 5;
1184 } else {
1185 /* rrrrrggg gggbbbbb */
1186 var->red.offset = 11;
1187 var->green.offset = 5;
1188 var->blue.offset = 0;
1189 var->red.length = 5;
1190 var->green.length = 6;
1191 var->blue.length = 5;
1192 }
1193 nom = 2;
1194 den = 1;
1195 break;
1196 case 17 ... 32:
1197 var->red.length = var->green.length = var->blue.length = 8;
1198 var->bits_per_pixel = 32;
1199 var->red.offset = 16;
1200 var->green.offset = 8;
1201 var->blue.offset = 0;
1202 nom = 4;
1203 den = 1;
1204 break;
1205 default:
1206 printk(KERN_ERR PFX
1207 "mode %dx%dx%d rejected...color depth not supported.\n",
1208 var->xres, var->yres, var->bits_per_pixel);
1209 NVTRACE("EXIT, returning -EINVAL\n");
1210 return -EINVAL;
1211 }
1212
1213 if (!strictmode) {
1214 if (!info->monspecs.vfmax || !info->monspecs.hfmax ||
1215 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
1216 mode_valid = 1;
1217 }
1218
1219 /* calculate modeline if supported by monitor */
1220 if (!mode_valid && info->monspecs.gtf) {
1221 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
1222 mode_valid = 1;
1223 }
1224
1225 if (!mode_valid) {
1226 mode = fb_find_best_mode(var, &info->modelist);
1227 if (mode) {
1228 riva_update_var(var, mode);
1229 mode_valid = 1;
1230 }
1231 }
1232
1233 if (!mode_valid && info->monspecs.modedb_len)
1234 return -EINVAL;
1235
1236 if (var->xres_virtual < var->xres)
1237 var->xres_virtual = var->xres;
1238 if (var->yres_virtual <= var->yres)
1239 var->yres_virtual = -1;
1240 if (rivafb_do_maximize(info, var, nom, den) < 0)
1241 return -EINVAL;
1242
1243 if (var->xoffset < 0)
1244 var->xoffset = 0;
1245 if (var->yoffset < 0)
1246 var->yoffset = 0;
1247
1248 /* truncate xoffset and yoffset to maximum if too high */
1249 if (var->xoffset > var->xres_virtual - var->xres)
1250 var->xoffset = var->xres_virtual - var->xres - 1;
1251
1252 if (var->yoffset > var->yres_virtual - var->yres)
1253 var->yoffset = var->yres_virtual - var->yres - 1;
1254
1255 var->red.msb_right =
1256 var->green.msb_right =
1257 var->blue.msb_right =
1258 var->transp.offset = var->transp.length = var->transp.msb_right = 0;
1259 NVTRACE_LEAVE();
1260 return 0;
1261}
1262
1263static int rivafb_set_par(struct fb_info *info)
1264{
f4a41836 1265 struct riva_par *par = info->par;
fd717689 1266 int rc = 0;
1da177e4
LT		 1267
1268 NVTRACE_ENTER();
1269 /* vgaHWunlock() + riva unlock (0x7F) */
1270 CRTCout(par, 0x11, 0xFF);
1271 par->riva.LockUnlock(&par->riva, 0);
fd717689
JG		 1272 rc = riva_load_video_mode(info);
1273 if (rc)
1274 goto out;
1da177e4
LT		 1275 if(!(info->flags & FBINFO_HWACCEL_DISABLED))
1276 riva_setup_accel(info);
1277
1278 par->cursor_reset = 1;
1279 info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3));
1280 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1281 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1282
1283 if (info->flags & FBINFO_HWACCEL_DISABLED)
1284 info->pixmap.scan_align = 1;
1285 else
1286 info->pixmap.scan_align = 4;
fd717689
JG		 1287
1288out:
1da177e4 1289 NVTRACE_LEAVE();
fd717689 1290 return rc;
1da177e4
LT		 1291}
1292
1293/**
1294 * rivafb_pan_display
1295 * @var: standard kernel fb changeable data
1296 * @con: TODO
1297 * @info: pointer to fb_info object containing info for current riva board
1298 *
1299 * DESCRIPTION:
1300 * Pan (or wrap, depending on the `vmode' field) the display using the
1301 * `xoffset' and `yoffset' fields of the `var' structure.
1302 * If the values don't fit, return -EINVAL.
1303 *
1304 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1305 */
1306static int rivafb_pan_display(struct fb_var_screeninfo *var,
1307 struct fb_info *info)
1308{
f4a41836 1309 struct riva_par *par = info->par;
1da177e4
LT		 1310 unsigned int base;
1311
1312 NVTRACE_ENTER();
1da177e4 1313 base = var->yoffset * info->fix.line_length + var->xoffset;
1da177e4 1314 par->riva.SetStartAddress(&par->riva, base);
1da177e4
LT		 1315 NVTRACE_LEAVE();
1316 return 0;
1317}
1318
1319static int rivafb_blank(int blank, struct fb_info *info)
1320{
f4a41836 1321 struct riva_par *par= info->par;
1da177e4
LT		 1322 unsigned char tmp, vesa;
1323
1324 tmp = SEQin(par, 0x01) & ~0x20; /* screen on/off */
1325 vesa = CRTCin(par, 0x1a) & ~0xc0; /* sync on/off */
1326
1327 NVTRACE_ENTER();
1328
1329 if (blank)
1330 tmp |= 0x20;
1331
1332 switch (blank) {
1333 case FB_BLANK_UNBLANK:
1334 case FB_BLANK_NORMAL:
1335 break;
1336 case FB_BLANK_VSYNC_SUSPEND:
1337 vesa |= 0x80;
1338 break;
1339 case FB_BLANK_HSYNC_SUSPEND:
1340 vesa |= 0x40;
1341 break;
1342 case FB_BLANK_POWERDOWN:
1343 vesa |= 0xc0;
1344 break;
1345 }
1346
1347 SEQout(par, 0x01, tmp);
1348 CRTCout(par, 0x1a, vesa);
1349
e01af038 1350 riva_bl_set_power(info, blank);
1da177e4
LT		 1351
1352 NVTRACE_LEAVE();
1353
1354 return 0;
1355}
1356
1357/**
1358 * rivafb_setcolreg
1359 * @regno: register index
1360 * @red: red component
1361 * @green: green component
1362 * @blue: blue component
1363 * @transp: transparency
1364 * @info: pointer to fb_info object containing info for current riva board
1365 *
1366 * DESCRIPTION:
1367 * Set a single color register. The values supplied have a 16 bit
1368 * magnitude.
1369 *
1370 * RETURNS:
1371 * Return != 0 for invalid regno.
1372 *
1373 * CALLED FROM:
1374 * fbcmap.c:fb_set_cmap()
1375 */
1376static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green,
1377 unsigned blue, unsigned transp,
1378 struct fb_info *info)
1379{
f4a41836 1380 struct riva_par *par = info->par;
1da177e4
LT		 1381 RIVA_HW_INST *chip = &par->riva;
1382 int i;
1383
1384 if (regno >= riva_get_cmap_len(&info->var))
1385 return -EINVAL;
1386
1387 if (info->var.grayscale) {
1388 /* gray = 0.30*R + 0.59*G + 0.11*B */
1389 red = green = blue =
1390 (red * 77 + green * 151 + blue * 28) >> 8;
1391 }
1392
1393 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1394 ((u32 *) info->pseudo_palette)[regno] =
1395 (regno << info->var.red.offset) |
1396 (regno << info->var.green.offset) |
1397 (regno << info->var.blue.offset);
1398 /*
1399 * The Riva128 2D engine requires color information in
1400 * TrueColor format even if framebuffer is in DirectColor
1401 */
1402 if (par->riva.Architecture == NV_ARCH_03) {
1403 switch (info->var.bits_per_pixel) {
1404 case 16:
1405 par->palette[regno] = ((red & 0xf800) >> 1) |
1406 ((green & 0xf800) >> 6) |
1407 ((blue & 0xf800) >> 11);
1408 break;
1409 case 32:
1410 par->palette[regno] = ((red & 0xff00) << 8) |
1411 ((green & 0xff00)) |
1412 ((blue & 0xff00) >> 8);
1413 break;
1414 }
1415 }
1416 }
1417
1418 switch (info->var.bits_per_pixel) {
1419 case 8:
1420 /* "transparent" stuff is completely ignored. */
1421 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1422 break;
1423 case 16:
1424 if (info->var.green.length == 5) {
1425 for (i = 0; i < 8; i++) {
1426 riva_wclut(chip, regno*8+i, red >> 8,
1427 green >> 8, blue >> 8);
1428 }
1429 } else {
1430 u8 r, g, b;
1431
1432 if (regno < 32) {
1433 for (i = 0; i < 8; i++) {
1434 riva_wclut(chip, regno*8+i,
1435 red >> 8, green >> 8,
1436 blue >> 8);
1437 }
1438 }
1439 riva_rclut(chip, regno*4, &r, &g, &b);
1440 for (i = 0; i < 4; i++)
1441 riva_wclut(chip, regno*4+i, r,
1442 green >> 8, b);
1443 }
1444 break;
1445 case 32:
1446 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1447 break;
1448 default:
1449 /* do nothing */
1450 break;
1451 }
1452 return 0;
1453}
1454
1455/**
1456 * rivafb_fillrect - hardware accelerated color fill function
1457 * @info: pointer to fb_info structure
1458 * @rect: pointer to fb_fillrect structure
1459 *
1460 * DESCRIPTION:
1461 * This function fills up a region of framebuffer memory with a solid
1462 * color with a choice of two different ROP's, copy or invert.
1463 *
1464 * CALLED FROM:
1465 * framebuffer hook
1466 */
1467static void rivafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
1468{
f4a41836 1469 struct riva_par *par = info->par;
1da177e4
LT		 1470 u_int color, rop = 0;
1471
1472 if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1473 cfb_fillrect(info, rect);
1474 return;
1475 }
1476
1477 if (info->var.bits_per_pixel == 8)
1478 color = rect->color;
1479 else {
1480 if (par->riva.Architecture != NV_ARCH_03)
1481 color = ((u32 *)info->pseudo_palette)[rect->color];
1482 else
1483 color = par->palette[rect->color];
1484 }
1485
1486 switch (rect->rop) {
1487 case ROP_XOR:
1488 rop = 0x66;
1489 break;
1490 case ROP_COPY:
1491 default:
1492 rop = 0xCC;
1493 break;
1494 }
1495
1496 riva_set_rop_solid(par, rop);
1497
1498 RIVA_FIFO_FREE(par->riva, Bitmap, 1);
1499 NV_WR32(&par->riva.Bitmap->Color1A, 0, color);
1500
1501 RIVA_FIFO_FREE(par->riva, Bitmap, 2);
1502 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].TopLeft, 0,
1503 (rect->dx << 16) | rect->dy);
1504 mb();
1505 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].WidthHeight, 0,
1506 (rect->width << 16) | rect->height);
1507 mb();
1508 riva_set_rop_solid(par, 0xcc);
1509
1510}
1511
1512/**
1513 * rivafb_copyarea - hardware accelerated blit function
1514 * @info: pointer to fb_info structure
1515 * @region: pointer to fb_copyarea structure
1516 *
1517 * DESCRIPTION:
1518 * This copies an area of pixels from one location to another
1519 *
1520 * CALLED FROM:
1521 * framebuffer hook
1522 */
1523static void rivafb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
1524{
f4a41836 1525 struct riva_par *par = info->par;
1da177e4
LT		 1526
1527 if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1528 cfb_copyarea(info, region);
1529 return;
1530 }
1531
1532 RIVA_FIFO_FREE(par->riva, Blt, 3);
1533 NV_WR32(&par->riva.Blt->TopLeftSrc, 0,
1534 (region->sy << 16) | region->sx);
1535 NV_WR32(&par->riva.Blt->TopLeftDst, 0,
1536 (region->dy << 16) | region->dx);
1537 mb();
1538 NV_WR32(&par->riva.Blt->WidthHeight, 0,
1539 (region->height << 16) | region->width);
1540 mb();
1541}
1542
1543static inline void convert_bgcolor_16(u32 *col)
1544{
1545 *col = ((*col & 0x0000F800) << 8)
1546 | ((*col & 0x00007E0) << 5)
1547 | ((*col & 0x0000001F) << 3)
1548 | 0xFF000000;
1549 mb();
1550}
1551
1552/**
1553 * rivafb_imageblit: hardware accelerated color expand function
1554 * @info: pointer to fb_info structure
1555 * @image: pointer to fb_image structure
1556 *
1557 * DESCRIPTION:
1558 * If the source is a monochrome bitmap, the function fills up a a region
1559 * of framebuffer memory with pixels whose color is determined by the bit
1560 * setting of the bitmap, 1 - foreground, 0 - background.
1561 *
1562 * If the source is not a monochrome bitmap, color expansion is not done.
1563 * In this case, it is channeled to a software function.
1564 *
1565 * CALLED FROM:
1566 * framebuffer hook
1567 */
1568static void rivafb_imageblit(struct fb_info *info,
1569 const struct fb_image *image)
1570{
f4a41836 1571 struct riva_par *par = info->par;
1da177e4
LT		 1572 u32 fgx = 0, bgx = 0, width, tmp;
1573 u8 *cdat = (u8 *) image->data;
1574 volatile u32 __iomem *d;
1575 int i, size;
1576
1577 if ((info->flags & FBINFO_HWACCEL_DISABLED) || image->depth != 1) {
1578 cfb_imageblit(info, image);
1579 return;
1580 }
1581
1582 switch (info->var.bits_per_pixel) {
1583 case 8:
1584 fgx = image->fg_color;
1585 bgx = image->bg_color;
1586 break;
1587 case 16:
1588 case 32:
1589 if (par->riva.Architecture != NV_ARCH_03) {
1590 fgx = ((u32 *)info->pseudo_palette)[image->fg_color];
1591 bgx = ((u32 *)info->pseudo_palette)[image->bg_color];
1592 } else {
1593 fgx = par->palette[image->fg_color];
1594 bgx = par->palette[image->bg_color];
1595 }
1596 if (info->var.green.length == 6)
1597 convert_bgcolor_16(&bgx);
1598 break;
1599 }
1600
1601 RIVA_FIFO_FREE(par->riva, Bitmap, 7);
1602 NV_WR32(&par->riva.Bitmap->ClipE.TopLeft, 0,
1603 (image->dy << 16) | (image->dx & 0xFFFF));
1604 NV_WR32(&par->riva.Bitmap->ClipE.BottomRight, 0,
1605 (((image->dy + image->height) << 16) |
1606 ((image->dx + image->width) & 0xffff)));
1607 NV_WR32(&par->riva.Bitmap->Color0E, 0, bgx);
1608 NV_WR32(&par->riva.Bitmap->Color1E, 0, fgx);
1609 NV_WR32(&par->riva.Bitmap->WidthHeightInE, 0,
1610 (image->height << 16) | ((image->width + 31) & ~31));
1611 NV_WR32(&par->riva.Bitmap->WidthHeightOutE, 0,
1612 (image->height << 16) | ((image->width + 31) & ~31));
1613 NV_WR32(&par->riva.Bitmap->PointE, 0,
1614 (image->dy << 16) | (image->dx & 0xFFFF));
1615
1616 d = &par->riva.Bitmap->MonochromeData01E;
1617
1618 width = (image->width + 31)/32;
1619 size = width * image->height;
1620 while (size >= 16) {
1621 RIVA_FIFO_FREE(par->riva, Bitmap, 16);
1622 for (i = 0; i < 16; i++) {
1623 tmp = *((u32 *)cdat);
1624 cdat = (u8 *)((u32 *)cdat + 1);
1625 reverse_order(&tmp);
1626 NV_WR32(d, i*4, tmp);
1627 }
1628 size -= 16;
1629 }
1630 if (size) {
1631 RIVA_FIFO_FREE(par->riva, Bitmap, size);
1632 for (i = 0; i < size; i++) {
1633 tmp = *((u32 *) cdat);
1634 cdat = (u8 *)((u32 *)cdat + 1);
1635 reverse_order(&tmp);
1636 NV_WR32(d, i*4, tmp);
1637 }
1638 }
1639}
1640
1641/**
1642 * rivafb_cursor - hardware cursor function
1643 * @info: pointer to info structure
1644 * @cursor: pointer to fbcursor structure
1645 *
1646 * DESCRIPTION:
1647 * A cursor function that supports displaying a cursor image via hardware.
1648 * Within the kernel, copy and invert rops are supported. If exported
1649 * to user space, only the copy rop will be supported.
1650 *
1651 * CALLED FROM
1652 * framebuffer hook
1653 */
1654static int rivafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1655{
f4a41836 1656 struct riva_par *par = info->par;
1da177e4 1657 u8 data[MAX_CURS * MAX_CURS/8];
1da177e4 1658 int i, set = cursor->set;
f1ab5dac 1659 u16 fg, bg;
1da177e4 1660
f1ab5dac
JS		 1661 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
1662 return -ENXIO;
1da177e4
LT		 1663
1664 par->riva.ShowHideCursor(&par->riva, 0);
1665
1666 if (par->cursor_reset) {
1667 set = FB_CUR_SETALL;
1668 par->cursor_reset = 0;
1669 }
1670
1671 if (set & FB_CUR_SETSIZE)
1672 memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2);
1673
1674 if (set & FB_CUR_SETPOS) {
1675 u32 xx, yy, temp;
1676
1677 yy = cursor->image.dy - info->var.yoffset;
1678 xx = cursor->image.dx - info->var.xoffset;
1679 temp = xx & 0xFFFF;
1680 temp |= yy << 16;
1681
1682 NV_WR32(par->riva.PRAMDAC, 0x0000300, temp);
1683 }
1684
1685
1686 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
1687 u32 bg_idx = cursor->image.bg_color;
1688 u32 fg_idx = cursor->image.fg_color;
1689 u32 s_pitch = (cursor->image.width+7) >> 3;
1690 u32 d_pitch = MAX_CURS/8;
1691 u8 *dat = (u8 *) cursor->image.data;
1692 u8 *msk = (u8 *) cursor->mask;
1693 u8 *src;
1694
1695 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC);
1696
1697 if (src) {
1698 switch (cursor->rop) {
1699 case ROP_XOR:
f1ab5dac 1700 for (i = 0; i < s_pitch * cursor->image.height; i++)
1da177e4
LT		 1701 src[i] = dat[i] ^ msk[i];
1702 break;
1703 case ROP_COPY:
1704 default:
f1ab5dac 1705 for (i = 0; i < s_pitch * cursor->image.height; i++)
1da177e4
LT		 1706 src[i] = dat[i] & msk[i];
1707 break;
1708 }
1709
f1ab5dac
JS		 1710 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch,
1711 cursor->image.height);
1da177e4
LT		 1712
1713 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
1714 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
1715 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) |
1716 1 << 15;
1717
1718 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
1719 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
1720 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) |
1721 1 << 15;
1722
1723 par->riva.LockUnlock(&par->riva, 0);
1724
1725 rivafb_load_cursor_image(par, data, bg, fg,
1726 cursor->image.width,
1727 cursor->image.height);
1728 kfree(src);
1729 }
1730 }
1731
1732 if (cursor->enable)
1733 par->riva.ShowHideCursor(&par->riva, 1);
1734
1735 return 0;
1736}
1737
1738static int rivafb_sync(struct fb_info *info)
1739{
f4a41836 1740 struct riva_par *par = info->par;
1da177e4
LT		 1741
1742 wait_for_idle(par);
1743 return 0;
1744}
1745
1746/* ------------------------------------------------------------------------- *
1747 *
1748 * initialization helper functions
1749 *
1750 * ------------------------------------------------------------------------- */
1751
1752/* kernel interface */
1753static struct fb_ops riva_fb_ops = {
1754 .owner = THIS_MODULE,
1755 .fb_open = rivafb_open,
1756 .fb_release = rivafb_release,
1757 .fb_check_var = rivafb_check_var,
1758 .fb_set_par = rivafb_set_par,
1759 .fb_setcolreg = rivafb_setcolreg,
1760 .fb_pan_display = rivafb_pan_display,
1761 .fb_blank = rivafb_blank,
1762 .fb_fillrect = rivafb_fillrect,
1763 .fb_copyarea = rivafb_copyarea,
1764 .fb_imageblit = rivafb_imageblit,
1765 .fb_cursor = rivafb_cursor,
1766 .fb_sync = rivafb_sync,
1767};
1768
1769static int __devinit riva_set_fbinfo(struct fb_info *info)
1770{
1771 unsigned int cmap_len;
f4a41836 1772 struct riva_par *par = info->par;
1da177e4
LT		 1773
1774 NVTRACE_ENTER();
1775 info->flags = FBINFO_DEFAULT
1776 | FBINFO_HWACCEL_XPAN
1777 | FBINFO_HWACCEL_YPAN
1778 | FBINFO_HWACCEL_COPYAREA
1779 | FBINFO_HWACCEL_FILLRECT
1780 | FBINFO_HWACCEL_IMAGEBLIT;
1781
1782 /* Accel seems to not work properly on NV30 yet...*/
1783 if ((par->riva.Architecture == NV_ARCH_30) || noaccel) {
1784 printk(KERN_DEBUG PFX "disabling acceleration\n");
1785 info->flags |= FBINFO_HWACCEL_DISABLED;
1786 }
1787
1788 info->var = rivafb_default_var;
1789 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1790 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1791
1792 info->pseudo_palette = par->pseudo_palette;
1793
1794 cmap_len = riva_get_cmap_len(&info->var);
1795 fb_alloc_cmap(&info->cmap, cmap_len, 0);
1796
1797 info->pixmap.size = 8 * 1024;
1798 info->pixmap.buf_align = 4;
58a60643 1799 info->pixmap.access_align = 32;
1da177e4
LT		 1800 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1801 info->var.yres_virtual = -1;
1802 NVTRACE_LEAVE();
1803 return (rivafb_check_var(&info->var, info));
1804}
1805
1806#ifdef CONFIG_PPC_OF
1807static int __devinit riva_get_EDID_OF(struct fb_info *info, struct pci_dev *pd)
1808{
f4a41836 1809 struct riva_par *par = info->par;
1da177e4 1810 struct device_node *dp;
79da342c 1811 const unsigned char *pedid = NULL;
13b5aecc 1812 const unsigned char *disptype = NULL;
1da177e4
LT		 1813 static char *propnames[] = {
1814 "DFP,EDID", "LCD,EDID", "EDID", "EDID1", "EDID,B", "EDID,A", NULL };
1815 int i;
1816
1817 NVTRACE_ENTER();
1818 dp = pci_device_to_OF_node(pd);
1819 for (; dp != NULL; dp = dp->child) {
b04e3dd4 1820 disptype = get_property(dp, "display-type", NULL);
1da177e4
LT		 1821 if (disptype == NULL)
1822 continue;
1823 if (strncmp(disptype, "LCD", 3) != 0)
1824 continue;
1825 for (i = 0; propnames[i] != NULL; ++i) {
b04e3dd4 1826 pedid = get_property(dp, propnames[i], NULL);
1da177e4 1827 if (pedid != NULL) {
0271eb94 1828 par->EDID = (unsigned char *)pedid;
1da177e4
LT		 1829 NVTRACE("LCD found.\n");
1830 return 1;
1831 }
1832 }
1833 }
1834 NVTRACE_LEAVE();
1835 return 0;
1836}
1837#endif /* CONFIG_PPC_OF */
1838
1839#if defined(CONFIG_FB_RIVA_I2C) && !defined(CONFIG_PPC_OF)
1840static int __devinit riva_get_EDID_i2c(struct fb_info *info)
1841{
f4a41836 1842 struct riva_par *par = info->par;
1da177e4
LT		 1843 struct fb_var_screeninfo var;
1844 int i;
1845
1846 NVTRACE_ENTER();
1847 riva_create_i2c_busses(par);
1848 for (i = 0; i < par->bus; i++) {
1849 riva_probe_i2c_connector(par, i+1, &par->EDID);
1850 if (par->EDID && !fb_parse_edid(par->EDID, &var)) {
1851 printk(PFX "Found EDID Block from BUS %i\n", i);
1852 break;
1853 }
1854 }
1855
1856 NVTRACE_LEAVE();
1857 return (par->EDID) ? 1 : 0;
1858}
1859#endif /* CONFIG_FB_RIVA_I2C */
1860
1861static void __devinit riva_update_default_var(struct fb_var_screeninfo *var,
1862 struct fb_info *info)
1863{
1864 struct fb_monspecs *specs = &info->monspecs;
1865 struct fb_videomode modedb;
1866
1867 NVTRACE_ENTER();
1868 /* respect mode options */
1869 if (mode_option) {
1870 fb_find_mode(var, info, mode_option,
1871 specs->modedb, specs->modedb_len,
1872 NULL, 8);
1873 } else if (specs->modedb != NULL) {
1874 /* get preferred timing */
1875 if (info->monspecs.misc & FB_MISC_1ST_DETAIL) {
1876 int i;
1877
1878 for (i = 0; i < specs->modedb_len; i++) {
1879 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
1880 modedb = specs->modedb[i];
1881 break;
1882 }
1883 }
1884 } else {
1885 /* otherwise, get first mode in database */
1886 modedb = specs->modedb[0];
1887 }
1888 var->bits_per_pixel = 8;
1889 riva_update_var(var, &modedb);
1890 }
1891 NVTRACE_LEAVE();
1892}
1893
1894
1895static void __devinit riva_get_EDID(struct fb_info *info, struct pci_dev *pdev)
1896{
1897 NVTRACE_ENTER();
1898#ifdef CONFIG_PPC_OF
1899 if (!riva_get_EDID_OF(info, pdev))
1900 printk(PFX "could not retrieve EDID from OF\n");
44456d37 1901#elif defined(CONFIG_FB_RIVA_I2C)
1da177e4
LT		 1902 if (!riva_get_EDID_i2c(info))
1903 printk(PFX "could not retrieve EDID from DDC/I2C\n");
1904#endif
1905 NVTRACE_LEAVE();
1906}
1907
1908
1909static void __devinit riva_get_edidinfo(struct fb_info *info)
1910{
1911 struct fb_var_screeninfo *var = &rivafb_default_var;
f4a41836 1912 struct riva_par *par = info->par;
1da177e4
LT		 1913
1914 fb_edid_to_monspecs(par->EDID, &info->monspecs);
1915 fb_videomode_to_modelist(info->monspecs.modedb, info->monspecs.modedb_len,
1916 &info->modelist);
1917 riva_update_default_var(var, info);
1918
1919 /* if user specified flatpanel, we respect that */
1920 if (info->monspecs.input & FB_DISP_DDI)
1921 par->FlatPanel = 1;
1922}
1923
1924/* ------------------------------------------------------------------------- *
1925 *
1926 * PCI bus
1927 *
1928 * ------------------------------------------------------------------------- */
1929
1930static u32 __devinit riva_get_arch(struct pci_dev *pd)
1931{
1932 u32 arch = 0;
1933
1934 switch (pd->device & 0x0ff0) {
1935 case 0x0100: /* GeForce 256 */
1936 case 0x0110: /* GeForce2 MX */
1937 case 0x0150: /* GeForce2 */
1938 case 0x0170: /* GeForce4 MX */
1939 case 0x0180: /* GeForce4 MX (8x AGP) */
1940 case 0x01A0: /* nForce */
1941 case 0x01F0: /* nForce2 */
1942 arch = NV_ARCH_10;
1943 break;
1944 case 0x0200: /* GeForce3 */
1945 case 0x0250: /* GeForce4 Ti */
1946 case 0x0280: /* GeForce4 Ti (8x AGP) */
1947 arch = NV_ARCH_20;
1948 break;
1949 case 0x0300: /* GeForceFX 5800 */
1950 case 0x0310: /* GeForceFX 5600 */
1951 case 0x0320: /* GeForceFX 5200 */
1952 case 0x0330: /* GeForceFX 5900 */
1953 case 0x0340: /* GeForceFX 5700 */
1954 arch = NV_ARCH_30;
1955 break;
1956 case 0x0020: /* TNT, TNT2 */
1957 arch = NV_ARCH_04;
1958 break;
1959 case 0x0010: /* Riva128 */
1960 arch = NV_ARCH_03;
1961 break;
1962 default: /* unknown architecture */
1963 break;
1964 }
1965 return arch;
1966}
1967
1968static int __devinit rivafb_probe(struct pci_dev *pd,
1969 const struct pci_device_id *ent)
1970{
1971 struct riva_par *default_par;
1972 struct fb_info *info;
1973 int ret;
1974
1975 NVTRACE_ENTER();
1976 assert(pd != NULL);
1977
1978 info = framebuffer_alloc(sizeof(struct riva_par), &pd->dev);
1979 if (!info) {
1980 printk (KERN_ERR PFX "could not allocate memory\n");
1981 ret = -ENOMEM;
1982 goto err_ret;
1983 }
f4a41836 1984 default_par = info->par;
1da177e4
LT		 1985 default_par->pdev = pd;
1986
f5610b9c 1987 info->pixmap.addr = kzalloc(8 * 1024, GFP_KERNEL);
1da177e4
LT		 1988 if (info->pixmap.addr == NULL) {
1989 ret = -ENOMEM;
1990 goto err_framebuffer_release;
1991 }
1da177e4
LT		 1992
1993 ret = pci_enable_device(pd);
1994 if (ret < 0) {
1995 printk(KERN_ERR PFX "cannot enable PCI device\n");
1996 goto err_free_pixmap;
1997 }
1998
1999 ret = pci_request_regions(pd, "rivafb");
2000 if (ret < 0) {
2001 printk(KERN_ERR PFX "cannot request PCI regions\n");
2002 goto err_disable_device;
2003 }
2004
c4f28e54 2005 mutex_init(&default_par->open_lock);
1da177e4
LT		 2006 default_par->riva.Architecture = riva_get_arch(pd);
2007
2008 default_par->Chipset = (pd->vendor << 16) | pd->device;
2009 printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset);
2010
1da177e4
LT		 2011 if(default_par->riva.Architecture == 0) {
2012 printk(KERN_ERR PFX "unknown NV_ARCH\n");
2013 ret=-ENODEV;
2014 goto err_release_region;
2015 }
2016 if(default_par->riva.Architecture == NV_ARCH_10 ||
2017 default_par->riva.Architecture == NV_ARCH_20 ||
2018 default_par->riva.Architecture == NV_ARCH_30) {
2019 sprintf(rivafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
2020 } else {
2021 sprintf(rivafb_fix.id, "NV%x", default_par->riva.Architecture);
2022 }
2023
2024 default_par->FlatPanel = flatpanel;
2025 if (flatpanel == 1)
2026 printk(KERN_INFO PFX "flatpanel support enabled\n");
2027 default_par->forceCRTC = forceCRTC;
2028
2029 rivafb_fix.mmio_len = pci_resource_len(pd, 0);
2030 rivafb_fix.smem_len = pci_resource_len(pd, 1);
2031
2032 {
2033 /* enable IO and mem if not already done */
2034 unsigned short cmd;
2035
2036 pci_read_config_word(pd, PCI_COMMAND, &cmd);
2037 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
2038 pci_write_config_word(pd, PCI_COMMAND, cmd);
2039 }
2040
2041 rivafb_fix.mmio_start = pci_resource_start(pd, 0);
2042 rivafb_fix.smem_start = pci_resource_start(pd, 1);
2043
2044 default_par->ctrl_base = ioremap(rivafb_fix.mmio_start,
2045 rivafb_fix.mmio_len);
2046 if (!default_par->ctrl_base) {
2047 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
2048 ret = -EIO;
2049 goto err_release_region;
2050 }
2051
2052 switch (default_par->riva.Architecture) {
2053 case NV_ARCH_03:
2054 /* Riva128's PRAMIN is in the "framebuffer" space
2055 * Since these cards were never made with more than 8 megabytes
2056 * we can safely allocate this separately.
2057 */
2058 default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000);
2059 if (!default_par->riva.PRAMIN) {
2060 printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n");
2061 ret = -EIO;
2062 goto err_iounmap_ctrl_base;
2063 }
2064 break;
2065 case NV_ARCH_04:
2066 case NV_ARCH_10:
2067 case NV_ARCH_20:
2068 case NV_ARCH_30:
2069 default_par->riva.PCRTC0 =
2070 (u32 __iomem *)(default_par->ctrl_base + 0x00600000);
2071 default_par->riva.PRAMIN =
2072 (u32 __iomem *)(default_par->ctrl_base + 0x00710000);
2073 break;
2074 }
2075 riva_common_setup(default_par);
2076
2077 if (default_par->riva.Architecture == NV_ARCH_03) {
2078 default_par->riva.PCRTC = default_par->riva.PCRTC0
2079 = default_par->riva.PGRAPH;
2080 }
2081
2082 rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024;
2083 default_par->dclk_max = riva_get_maxdclk(default_par) * 1000;
2084 info->screen_base = ioremap(rivafb_fix.smem_start,
2085 rivafb_fix.smem_len);
2086 if (!info->screen_base) {
2087 printk(KERN_ERR PFX "cannot ioremap FB base\n");
2088 ret = -EIO;
2089 goto err_iounmap_pramin;
2090 }
2091
2092#ifdef CONFIG_MTRR
2093 if (!nomtrr) {
2094 default_par->mtrr.vram = mtrr_add(rivafb_fix.smem_start,
2095 rivafb_fix.smem_len,
2096 MTRR_TYPE_WRCOMB, 1);
2097 if (default_par->mtrr.vram < 0) {
2098 printk(KERN_ERR PFX "unable to setup MTRR\n");
2099 } else {
2100 default_par->mtrr.vram_valid = 1;
2101 /* let there be speed */
2102 printk(KERN_INFO PFX "RIVA MTRR set to ON\n");
2103 }
2104 }
2105#endif /* CONFIG_MTRR */
2106
2107 info->fbops = &riva_fb_ops;
2108 info->fix = rivafb_fix;
2109 riva_get_EDID(info, pd);
2110 riva_get_edidinfo(info);
2111
2112 ret=riva_set_fbinfo(info);
2113 if (ret < 0) {
2114 printk(KERN_ERR PFX "error setting initial video mode\n");
2115 goto err_iounmap_screen_base;
2116 }
2117
2118 fb_destroy_modedb(info->monspecs.modedb);
2119 info->monspecs.modedb = NULL;
ce38cac4
GG		 2120
2121 pci_set_drvdata(pd, info);
2122 riva_bl_init(info->par);
1da177e4
LT		 2123 ret = register_framebuffer(info);
2124 if (ret < 0) {
2125 printk(KERN_ERR PFX
2126 "error registering riva framebuffer\n");
2127 goto err_iounmap_screen_base;
2128 }
2129
1da177e4
LT		 2130 printk(KERN_INFO PFX
2131 "PCI nVidia %s framebuffer ver %s (%dMB @ 0x%lX)\n",
2132 info->fix.id,
2133 RIVAFB_VERSION,
2134 info->fix.smem_len / (1024 * 1024),
2135 info->fix.smem_start);
5474c120 2136
1da177e4
LT		 2137 NVTRACE_LEAVE();
2138 return 0;
2139
2140err_iounmap_screen_base:
2141#ifdef CONFIG_FB_RIVA_I2C
f4a41836 2142 riva_delete_i2c_busses(info->par);
1da177e4
LT		 2143#endif
2144 iounmap(info->screen_base);
2145err_iounmap_pramin:
2146 if (default_par->riva.Architecture == NV_ARCH_03)
2147 iounmap(default_par->riva.PRAMIN);
2148err_iounmap_ctrl_base:
2149 iounmap(default_par->ctrl_base);
2150err_release_region:
2151 pci_release_regions(pd);
2152err_disable_device:
1da177e4
LT		 2153err_free_pixmap:
2154 kfree(info->pixmap.addr);
2155err_framebuffer_release:
2156 framebuffer_release(info);
2157err_ret:
2158 return ret;
2159}
2160
2161static void __exit rivafb_remove(struct pci_dev *pd)
2162{
2163 struct fb_info *info = pci_get_drvdata(pd);
f4a41836 2164 struct riva_par *par = info->par;
1da177e4
LT		 2165
2166 NVTRACE_ENTER();
1da177e4 2167
5474c120
MH		 2168 riva_bl_exit(par);
2169
1da177e4
LT		 2170#ifdef CONFIG_FB_RIVA_I2C
2171 riva_delete_i2c_busses(par);
2172 kfree(par->EDID);
2173#endif
2174
2175 unregister_framebuffer(info);
2176#ifdef CONFIG_MTRR
2177 if (par->mtrr.vram_valid)
2178 mtrr_del(par->mtrr.vram, info->fix.smem_start,
2179 info->fix.smem_len);
2180#endif /* CONFIG_MTRR */
2181
2182 iounmap(par->ctrl_base);
2183 iounmap(info->screen_base);
2184 if (par->riva.Architecture == NV_ARCH_03)
2185 iounmap(par->riva.PRAMIN);
2186 pci_release_regions(pd);
1da177e4
LT		 2187 kfree(info->pixmap.addr);
2188 framebuffer_release(info);
2189 pci_set_drvdata(pd, NULL);
2190 NVTRACE_LEAVE();
2191}
2192
2193/* ------------------------------------------------------------------------- *
2194 *
2195 * initialization
2196 *
2197 * ------------------------------------------------------------------------- */
2198
2199#ifndef MODULE
2200static int __init rivafb_setup(char *options)
2201{
2202 char *this_opt;
2203
2204 NVTRACE_ENTER();
2205 if (!options || !*options)
2206 return 0;
2207
2208 while ((this_opt = strsep(&options, ",")) != NULL) {
2209 if (!strncmp(this_opt, "forceCRTC", 9)) {
2210 char *p;
2211
2212 p = this_opt + 9;
2213 if (!*p || !*(++p)) continue;
2214 forceCRTC = *p - '0';
2215 if (forceCRTC < 0 || forceCRTC > 1)
2216 forceCRTC = -1;
2217 } else if (!strncmp(this_opt, "flatpanel", 9)) {
2218 flatpanel = 1;
2219#ifdef CONFIG_MTRR
2220 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2221 nomtrr = 1;
2222#endif
2223 } else if (!strncmp(this_opt, "strictmode", 10)) {
2224 strictmode = 1;
2225 } else if (!strncmp(this_opt, "noaccel", 7)) {
2226 noaccel = 1;
2227 } else
2228 mode_option = this_opt;
2229 }
2230 NVTRACE_LEAVE();
2231 return 0;
2232}
2233#endif /* !MODULE */
2234
2235static struct pci_driver rivafb_driver = {
2236 .name = "rivafb",
2237 .id_table = rivafb_pci_tbl,
2238 .probe = rivafb_probe,
2239 .remove = __exit_p(rivafb_remove),
2240};
2241
2242
2243
2244/* ------------------------------------------------------------------------- *
2245 *
2246 * modularization
2247 *
2248 * ------------------------------------------------------------------------- */
2249
2250static int __devinit rivafb_init(void)
2251{
2252#ifndef MODULE
2253 char *option = NULL;
2254
2255 if (fb_get_options("rivafb", &option))
2256 return -ENODEV;
2257 rivafb_setup(option);
2258#endif
2259 return pci_register_driver(&rivafb_driver);
2260}
2261
2262
2263module_init(rivafb_init);
2264
2265#ifdef MODULE
2266static void __exit rivafb_exit(void)
2267{
2268 pci_unregister_driver(&rivafb_driver);
2269}
2270
2271module_exit(rivafb_exit);
2272#endif /* MODULE */
2273
2274module_param(noaccel, bool, 0);
2275MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2276module_param(flatpanel, int, 0);
2277MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)");
2278module_param(forceCRTC, int, 0);
2279MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)");
2280#ifdef CONFIG_MTRR
2281module_param(nomtrr, bool, 0);
2282MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)");
2283#endif
2284module_param(strictmode, bool, 0);
2285MODULE_PARM_DESC(strictmode, "Only use video modes from EDID");
2286
2287MODULE_AUTHOR("Ani Joshi, maintainer");
2288MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series");
2289MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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