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1 | /***************************************************************************\ |
2 | |* *| | |
3 | |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *| | |
4 | |* *| | |
5 | |* NOTICE TO USER: The source code is copyrighted under U.S. and *| | |
6 | |* international laws. Users and possessors of this source code are *| | |
7 | |* hereby granted a nonexclusive, royalty-free copyright license to *| | |
8 | |* use this code in individual and commercial software. *| | |
9 | |* *| | |
10 | |* Any use of this source code must include, in the user documenta- *| | |
11 | |* tion and internal comments to the code, notices to the end user *| | |
12 | |* as follows: *| | |
13 | |* *| | |
14 | |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *| | |
15 | |* *| | |
16 | |* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| | |
17 | |* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| | |
18 | |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *| | |
19 | |* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *| | |
20 | |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *| | |
21 | |* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *| | |
22 | |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *| | |
23 | |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *| | |
24 | |* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *| | |
25 | |* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *| | |
26 | |* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *| | |
27 | |* *| | |
28 | |* U.S. Government End Users. This source code is a "commercial *| | |
29 | |* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *| | |
30 | |* consisting of "commercial computer software" and "commercial *| | |
31 | |* computer software documentation," as such terms are used in *| | |
32 | |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *| | |
33 | |* ment only as a commercial end item. Consistent with 48 C.F.R. *| | |
34 | |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *| | |
35 | |* all U.S. Government End Users acquire the source code with only *| | |
36 | |* those rights set forth herein. *| | |
37 | |* *| | |
38 | \***************************************************************************/ | |
39 | ||
40 | /* | |
41 | * GPL licensing note -- nVidia is allowing a liberal interpretation of | |
42 | * the documentation restriction above, to merely say that this nVidia's | |
43 | * copyright and disclaimer should be included with all code derived | |
44 | * from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99 | |
45 | */ | |
46 | ||
47 | /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.c,v 1.33 2002/08/05 20:47:06 mvojkovi Exp $ */ | |
48 | ||
49 | #include <linux/kernel.h> | |
50 | #include <linux/pci.h> | |
51 | #include <linux/pci_ids.h> | |
52 | #include "riva_hw.h" | |
53 | #include "riva_tbl.h" | |
54 | #include "nv_type.h" | |
55 | ||
56 | /* | |
57 | * This file is an OS-agnostic file used to make RIVA 128 and RIVA TNT | |
58 | * operate identically (except TNT has more memory and better 3D quality. | |
59 | */ | |
60 | static int nv3Busy | |
61 | ( | |
62 | RIVA_HW_INST *chip | |
63 | ) | |
64 | { | |
65 | return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || | |
66 | NV_RD32(&chip->PGRAPH[0x000006B0/4], 0) & 0x01); | |
67 | } | |
68 | static int nv4Busy | |
69 | ( | |
70 | RIVA_HW_INST *chip | |
71 | ) | |
72 | { | |
73 | return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || | |
74 | NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01); | |
75 | } | |
76 | static int nv10Busy | |
77 | ( | |
78 | RIVA_HW_INST *chip | |
79 | ) | |
80 | { | |
81 | return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || | |
82 | NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01); | |
83 | } | |
84 | ||
85 | static void vgaLockUnlock | |
86 | ( | |
87 | RIVA_HW_INST *chip, | |
88 | int Lock | |
89 | ) | |
90 | { | |
91 | U008 cr11; | |
92 | VGA_WR08(chip->PCIO, 0x3D4, 0x11); | |
93 | cr11 = VGA_RD08(chip->PCIO, 0x3D5); | |
94 | if(Lock) cr11 |= 0x80; | |
95 | else cr11 &= ~0x80; | |
96 | VGA_WR08(chip->PCIO, 0x3D5, cr11); | |
97 | } | |
98 | static void nv3LockUnlock | |
99 | ( | |
100 | RIVA_HW_INST *chip, | |
101 | int Lock | |
102 | ) | |
103 | { | |
104 | VGA_WR08(chip->PVIO, 0x3C4, 0x06); | |
105 | VGA_WR08(chip->PVIO, 0x3C5, Lock ? 0x99 : 0x57); | |
106 | vgaLockUnlock(chip, Lock); | |
107 | } | |
108 | static void nv4LockUnlock | |
109 | ( | |
110 | RIVA_HW_INST *chip, | |
111 | int Lock | |
112 | ) | |
113 | { | |
114 | VGA_WR08(chip->PCIO, 0x3D4, 0x1F); | |
115 | VGA_WR08(chip->PCIO, 0x3D5, Lock ? 0x99 : 0x57); | |
116 | vgaLockUnlock(chip, Lock); | |
117 | } | |
118 | ||
119 | static int ShowHideCursor | |
120 | ( | |
121 | RIVA_HW_INST *chip, | |
122 | int ShowHide | |
123 | ) | |
124 | { | |
125 | int cursor; | |
126 | cursor = chip->CurrentState->cursor1; | |
127 | chip->CurrentState->cursor1 = (chip->CurrentState->cursor1 & 0xFE) | | |
128 | (ShowHide & 0x01); | |
129 | VGA_WR08(chip->PCIO, 0x3D4, 0x31); | |
130 | VGA_WR08(chip->PCIO, 0x3D5, chip->CurrentState->cursor1); | |
131 | return (cursor & 0x01); | |
132 | } | |
133 | ||
134 | /****************************************************************************\ | |
135 | * * | |
136 | * The video arbitration routines calculate some "magic" numbers. Fixes * | |
137 | * the snow seen when accessing the framebuffer without it. * | |
138 | * It just works (I hope). * | |
139 | * * | |
140 | \****************************************************************************/ | |
141 | ||
142 | #define DEFAULT_GR_LWM 100 | |
143 | #define DEFAULT_VID_LWM 100 | |
144 | #define DEFAULT_GR_BURST_SIZE 256 | |
145 | #define DEFAULT_VID_BURST_SIZE 128 | |
146 | #define VIDEO 0 | |
147 | #define GRAPHICS 1 | |
148 | #define MPORT 2 | |
149 | #define ENGINE 3 | |
150 | #define GFIFO_SIZE 320 | |
151 | #define GFIFO_SIZE_128 256 | |
152 | #define MFIFO_SIZE 120 | |
153 | #define VFIFO_SIZE 256 | |
154 | ||
155 | typedef struct { | |
156 | int gdrain_rate; | |
157 | int vdrain_rate; | |
158 | int mdrain_rate; | |
159 | int gburst_size; | |
160 | int vburst_size; | |
161 | char vid_en; | |
162 | char gr_en; | |
163 | int wcmocc, wcgocc, wcvocc, wcvlwm, wcglwm; | |
164 | int by_gfacc; | |
165 | char vid_only_once; | |
166 | char gr_only_once; | |
167 | char first_vacc; | |
168 | char first_gacc; | |
169 | char first_macc; | |
170 | int vocc; | |
171 | int gocc; | |
172 | int mocc; | |
173 | char cur; | |
174 | char engine_en; | |
175 | char converged; | |
176 | int priority; | |
177 | } nv3_arb_info; | |
178 | typedef struct { | |
179 | int graphics_lwm; | |
180 | int video_lwm; | |
181 | int graphics_burst_size; | |
182 | int video_burst_size; | |
183 | int graphics_hi_priority; | |
184 | int media_hi_priority; | |
185 | int rtl_values; | |
186 | int valid; | |
187 | } nv3_fifo_info; | |
188 | typedef struct { | |
189 | char pix_bpp; | |
190 | char enable_video; | |
191 | char gr_during_vid; | |
192 | char enable_mp; | |
193 | int memory_width; | |
194 | int video_scale; | |
195 | int pclk_khz; | |
196 | int mclk_khz; | |
197 | int mem_page_miss; | |
198 | int mem_latency; | |
199 | char mem_aligned; | |
200 | } nv3_sim_state; | |
201 | typedef struct { | |
202 | int graphics_lwm; | |
203 | int video_lwm; | |
204 | int graphics_burst_size; | |
205 | int video_burst_size; | |
206 | int valid; | |
207 | } nv4_fifo_info; | |
208 | typedef struct { | |
209 | int pclk_khz; | |
210 | int mclk_khz; | |
211 | int nvclk_khz; | |
212 | char mem_page_miss; | |
213 | char mem_latency; | |
214 | int memory_width; | |
215 | char enable_video; | |
216 | char gr_during_vid; | |
217 | char pix_bpp; | |
218 | char mem_aligned; | |
219 | char enable_mp; | |
220 | } nv4_sim_state; | |
221 | typedef struct { | |
222 | int graphics_lwm; | |
223 | int video_lwm; | |
224 | int graphics_burst_size; | |
225 | int video_burst_size; | |
226 | int valid; | |
227 | } nv10_fifo_info; | |
228 | typedef struct { | |
229 | int pclk_khz; | |
230 | int mclk_khz; | |
231 | int nvclk_khz; | |
232 | char mem_page_miss; | |
233 | char mem_latency; | |
7d345b22 | 234 | u32 memory_type; |
1da177e4 LT |
235 | int memory_width; |
236 | char enable_video; | |
237 | char gr_during_vid; | |
238 | char pix_bpp; | |
239 | char mem_aligned; | |
240 | char enable_mp; | |
241 | } nv10_sim_state; | |
242 | static int nv3_iterate(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo) | |
243 | { | |
244 | int iter = 0; | |
245 | int tmp; | |
246 | int vfsize, mfsize, gfsize; | |
247 | int mburst_size = 32; | |
248 | int mmisses, gmisses, vmisses; | |
249 | int misses; | |
250 | int vlwm, glwm, mlwm; | |
251 | int last, next, cur; | |
252 | int max_gfsize ; | |
253 | long ns; | |
254 | ||
255 | vlwm = 0; | |
256 | glwm = 0; | |
257 | mlwm = 0; | |
258 | vfsize = 0; | |
259 | gfsize = 0; | |
260 | cur = ainfo->cur; | |
261 | mmisses = 2; | |
262 | gmisses = 2; | |
263 | vmisses = 2; | |
264 | if (ainfo->gburst_size == 128) max_gfsize = GFIFO_SIZE_128; | |
265 | else max_gfsize = GFIFO_SIZE; | |
266 | max_gfsize = GFIFO_SIZE; | |
267 | while (1) | |
268 | { | |
269 | if (ainfo->vid_en) | |
270 | { | |
271 | if (ainfo->wcvocc > ainfo->vocc) ainfo->wcvocc = ainfo->vocc; | |
272 | if (ainfo->wcvlwm > vlwm) ainfo->wcvlwm = vlwm ; | |
273 | ns = 1000000 * ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz; | |
274 | vfsize = ns * ainfo->vdrain_rate / 1000000; | |
275 | vfsize = ainfo->wcvlwm - ainfo->vburst_size + vfsize; | |
276 | } | |
277 | if (state->enable_mp) | |
278 | { | |
279 | if (ainfo->wcmocc > ainfo->mocc) ainfo->wcmocc = ainfo->mocc; | |
280 | } | |
281 | if (ainfo->gr_en) | |
282 | { | |
283 | if (ainfo->wcglwm > glwm) ainfo->wcglwm = glwm ; | |
284 | if (ainfo->wcgocc > ainfo->gocc) ainfo->wcgocc = ainfo->gocc; | |
285 | ns = 1000000 * (ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz; | |
286 | gfsize = (ns * (long) ainfo->gdrain_rate)/1000000; | |
287 | gfsize = ainfo->wcglwm - ainfo->gburst_size + gfsize; | |
288 | } | |
289 | mfsize = 0; | |
290 | if (!state->gr_during_vid && ainfo->vid_en) | |
291 | if (ainfo->vid_en && (ainfo->vocc < 0) && !ainfo->vid_only_once) | |
292 | next = VIDEO; | |
293 | else if (ainfo->mocc < 0) | |
294 | next = MPORT; | |
295 | else if (ainfo->gocc< ainfo->by_gfacc) | |
296 | next = GRAPHICS; | |
297 | else return (0); | |
298 | else switch (ainfo->priority) | |
299 | { | |
300 | case VIDEO: | |
301 | if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once) | |
302 | next = VIDEO; | |
303 | else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once) | |
304 | next = GRAPHICS; | |
305 | else if (ainfo->mocc<0) | |
306 | next = MPORT; | |
307 | else return (0); | |
308 | break; | |
309 | case GRAPHICS: | |
310 | if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once) | |
311 | next = GRAPHICS; | |
312 | else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once) | |
313 | next = VIDEO; | |
314 | else if (ainfo->mocc<0) | |
315 | next = MPORT; | |
316 | else return (0); | |
317 | break; | |
318 | default: | |
319 | if (ainfo->mocc<0) | |
320 | next = MPORT; | |
321 | else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once) | |
322 | next = GRAPHICS; | |
323 | else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once) | |
324 | next = VIDEO; | |
325 | else return (0); | |
326 | break; | |
327 | } | |
328 | last = cur; | |
329 | cur = next; | |
330 | iter++; | |
331 | switch (cur) | |
332 | { | |
333 | case VIDEO: | |
334 | if (last==cur) misses = 0; | |
335 | else if (ainfo->first_vacc) misses = vmisses; | |
336 | else misses = 1; | |
337 | ainfo->first_vacc = 0; | |
338 | if (last!=cur) | |
339 | { | |
340 | ns = 1000000 * (vmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz; | |
341 | vlwm = ns * ainfo->vdrain_rate/ 1000000; | |
342 | vlwm = ainfo->vocc - vlwm; | |
343 | } | |
344 | ns = 1000000*(misses*state->mem_page_miss + ainfo->vburst_size)/(state->memory_width/8)/state->mclk_khz; | |
345 | ainfo->vocc = ainfo->vocc + ainfo->vburst_size - ns*ainfo->vdrain_rate/1000000; | |
346 | ainfo->gocc = ainfo->gocc - ns*ainfo->gdrain_rate/1000000; | |
347 | ainfo->mocc = ainfo->mocc - ns*ainfo->mdrain_rate/1000000; | |
348 | break; | |
349 | case GRAPHICS: | |
350 | if (last==cur) misses = 0; | |
351 | else if (ainfo->first_gacc) misses = gmisses; | |
352 | else misses = 1; | |
353 | ainfo->first_gacc = 0; | |
354 | if (last!=cur) | |
355 | { | |
356 | ns = 1000000*(gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz ; | |
357 | glwm = ns * ainfo->gdrain_rate/1000000; | |
358 | glwm = ainfo->gocc - glwm; | |
359 | } | |
360 | ns = 1000000*(misses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz; | |
361 | ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000; | |
362 | ainfo->gocc = ainfo->gocc + ainfo->gburst_size - ns*ainfo->gdrain_rate/1000000; | |
363 | ainfo->mocc = ainfo->mocc + 0 - ns*ainfo->mdrain_rate/1000000; | |
364 | break; | |
365 | default: | |
366 | if (last==cur) misses = 0; | |
367 | else if (ainfo->first_macc) misses = mmisses; | |
368 | else misses = 1; | |
369 | ainfo->first_macc = 0; | |
370 | ns = 1000000*(misses*state->mem_page_miss + mburst_size/(state->memory_width/8))/state->mclk_khz; | |
371 | ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000; | |
372 | ainfo->gocc = ainfo->gocc + 0 - ns*ainfo->gdrain_rate/1000000; | |
373 | ainfo->mocc = ainfo->mocc + mburst_size - ns*ainfo->mdrain_rate/1000000; | |
374 | break; | |
375 | } | |
376 | if (iter>100) | |
377 | { | |
378 | ainfo->converged = 0; | |
379 | return (1); | |
380 | } | |
381 | ns = 1000000*ainfo->gburst_size/(state->memory_width/8)/state->mclk_khz; | |
382 | tmp = ns * ainfo->gdrain_rate/1000000; | |
383 | if (abs(ainfo->gburst_size) + ((abs(ainfo->wcglwm) + 16 ) & ~0x7) - tmp > max_gfsize) | |
384 | { | |
385 | ainfo->converged = 0; | |
386 | return (1); | |
387 | } | |
388 | ns = 1000000*ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz; | |
389 | tmp = ns * ainfo->vdrain_rate/1000000; | |
390 | if (abs(ainfo->vburst_size) + (abs(ainfo->wcvlwm + 32) & ~0xf) - tmp> VFIFO_SIZE) | |
391 | { | |
392 | ainfo->converged = 0; | |
393 | return (1); | |
394 | } | |
395 | if (abs(ainfo->gocc) > max_gfsize) | |
396 | { | |
397 | ainfo->converged = 0; | |
398 | return (1); | |
399 | } | |
400 | if (abs(ainfo->vocc) > VFIFO_SIZE) | |
401 | { | |
402 | ainfo->converged = 0; | |
403 | return (1); | |
404 | } | |
405 | if (abs(ainfo->mocc) > MFIFO_SIZE) | |
406 | { | |
407 | ainfo->converged = 0; | |
408 | return (1); | |
409 | } | |
410 | if (abs(vfsize) > VFIFO_SIZE) | |
411 | { | |
412 | ainfo->converged = 0; | |
413 | return (1); | |
414 | } | |
415 | if (abs(gfsize) > max_gfsize) | |
416 | { | |
417 | ainfo->converged = 0; | |
418 | return (1); | |
419 | } | |
420 | if (abs(mfsize) > MFIFO_SIZE) | |
421 | { | |
422 | ainfo->converged = 0; | |
423 | return (1); | |
424 | } | |
425 | } | |
426 | } | |
427 | static char nv3_arb(nv3_fifo_info * res_info, nv3_sim_state * state, nv3_arb_info *ainfo) | |
428 | { | |
429 | long ens, vns, mns, gns; | |
430 | int mmisses, gmisses, vmisses, eburst_size, mburst_size; | |
431 | int refresh_cycle; | |
432 | ||
433 | refresh_cycle = 0; | |
434 | refresh_cycle = 2*(state->mclk_khz/state->pclk_khz) + 5; | |
435 | mmisses = 2; | |
436 | if (state->mem_aligned) gmisses = 2; | |
437 | else gmisses = 3; | |
438 | vmisses = 2; | |
439 | eburst_size = state->memory_width * 1; | |
440 | mburst_size = 32; | |
441 | gns = 1000000 * (gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz; | |
442 | ainfo->by_gfacc = gns*ainfo->gdrain_rate/1000000; | |
443 | ainfo->wcmocc = 0; | |
444 | ainfo->wcgocc = 0; | |
445 | ainfo->wcvocc = 0; | |
446 | ainfo->wcvlwm = 0; | |
447 | ainfo->wcglwm = 0; | |
448 | ainfo->engine_en = 1; | |
449 | ainfo->converged = 1; | |
450 | if (ainfo->engine_en) | |
451 | { | |
452 | ens = 1000000*(state->mem_page_miss + eburst_size/(state->memory_width/8) +refresh_cycle)/state->mclk_khz; | |
453 | ainfo->mocc = state->enable_mp ? 0-ens*ainfo->mdrain_rate/1000000 : 0; | |
454 | ainfo->vocc = ainfo->vid_en ? 0-ens*ainfo->vdrain_rate/1000000 : 0; | |
455 | ainfo->gocc = ainfo->gr_en ? 0-ens*ainfo->gdrain_rate/1000000 : 0; | |
456 | ainfo->cur = ENGINE; | |
457 | ainfo->first_vacc = 1; | |
458 | ainfo->first_gacc = 1; | |
459 | ainfo->first_macc = 1; | |
460 | nv3_iterate(res_info, state,ainfo); | |
461 | } | |
462 | if (state->enable_mp) | |
463 | { | |
464 | mns = 1000000 * (mmisses*state->mem_page_miss + mburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz; | |
465 | ainfo->mocc = state->enable_mp ? 0 : mburst_size - mns*ainfo->mdrain_rate/1000000; | |
466 | ainfo->vocc = ainfo->vid_en ? 0 : 0- mns*ainfo->vdrain_rate/1000000; | |
467 | ainfo->gocc = ainfo->gr_en ? 0: 0- mns*ainfo->gdrain_rate/1000000; | |
468 | ainfo->cur = MPORT; | |
469 | ainfo->first_vacc = 1; | |
470 | ainfo->first_gacc = 1; | |
471 | ainfo->first_macc = 0; | |
472 | nv3_iterate(res_info, state,ainfo); | |
473 | } | |
474 | if (ainfo->gr_en) | |
475 | { | |
476 | ainfo->first_vacc = 1; | |
477 | ainfo->first_gacc = 0; | |
478 | ainfo->first_macc = 1; | |
479 | gns = 1000000*(gmisses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz; | |
480 | ainfo->gocc = ainfo->gburst_size - gns*ainfo->gdrain_rate/1000000; | |
481 | ainfo->vocc = ainfo->vid_en? 0-gns*ainfo->vdrain_rate/1000000 : 0; | |
482 | ainfo->mocc = state->enable_mp ? 0-gns*ainfo->mdrain_rate/1000000: 0; | |
483 | ainfo->cur = GRAPHICS; | |
484 | nv3_iterate(res_info, state,ainfo); | |
485 | } | |
486 | if (ainfo->vid_en) | |
487 | { | |
488 | ainfo->first_vacc = 0; | |
489 | ainfo->first_gacc = 1; | |
490 | ainfo->first_macc = 1; | |
491 | vns = 1000000*(vmisses*state->mem_page_miss + ainfo->vburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz; | |
492 | ainfo->vocc = ainfo->vburst_size - vns*ainfo->vdrain_rate/1000000; | |
493 | ainfo->gocc = ainfo->gr_en? (0-vns*ainfo->gdrain_rate/1000000) : 0; | |
494 | ainfo->mocc = state->enable_mp? 0-vns*ainfo->mdrain_rate/1000000 :0 ; | |
495 | ainfo->cur = VIDEO; | |
496 | nv3_iterate(res_info, state, ainfo); | |
497 | } | |
498 | if (ainfo->converged) | |
499 | { | |
500 | res_info->graphics_lwm = (int)abs(ainfo->wcglwm) + 16; | |
501 | res_info->video_lwm = (int)abs(ainfo->wcvlwm) + 32; | |
502 | res_info->graphics_burst_size = ainfo->gburst_size; | |
503 | res_info->video_burst_size = ainfo->vburst_size; | |
504 | res_info->graphics_hi_priority = (ainfo->priority == GRAPHICS); | |
505 | res_info->media_hi_priority = (ainfo->priority == MPORT); | |
506 | if (res_info->video_lwm > 160) | |
507 | { | |
508 | res_info->graphics_lwm = 256; | |
509 | res_info->video_lwm = 128; | |
510 | res_info->graphics_burst_size = 64; | |
511 | res_info->video_burst_size = 64; | |
512 | res_info->graphics_hi_priority = 0; | |
513 | res_info->media_hi_priority = 0; | |
514 | ainfo->converged = 0; | |
515 | return (0); | |
516 | } | |
517 | if (res_info->video_lwm > 128) | |
518 | { | |
519 | res_info->video_lwm = 128; | |
520 | } | |
521 | return (1); | |
522 | } | |
523 | else | |
524 | { | |
525 | res_info->graphics_lwm = 256; | |
526 | res_info->video_lwm = 128; | |
527 | res_info->graphics_burst_size = 64; | |
528 | res_info->video_burst_size = 64; | |
529 | res_info->graphics_hi_priority = 0; | |
530 | res_info->media_hi_priority = 0; | |
531 | return (0); | |
532 | } | |
533 | } | |
534 | static char nv3_get_param(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo) | |
535 | { | |
536 | int done, g,v, p; | |
537 | ||
538 | done = 0; | |
539 | for (p=0; p < 2; p++) | |
540 | { | |
541 | for (g=128 ; g > 32; g= g>> 1) | |
542 | { | |
543 | for (v=128; v >=32; v = v>> 1) | |
544 | { | |
545 | ainfo->priority = p; | |
546 | ainfo->gburst_size = g; | |
547 | ainfo->vburst_size = v; | |
548 | done = nv3_arb(res_info, state,ainfo); | |
549 | if (done && (g==128)) | |
550 | if ((res_info->graphics_lwm + g) > 256) | |
551 | done = 0; | |
552 | if (done) | |
553 | goto Done; | |
554 | } | |
555 | } | |
556 | } | |
557 | ||
558 | Done: | |
559 | return done; | |
560 | } | |
561 | static void nv3CalcArbitration | |
562 | ( | |
563 | nv3_fifo_info * res_info, | |
564 | nv3_sim_state * state | |
565 | ) | |
566 | { | |
567 | nv3_fifo_info save_info; | |
568 | nv3_arb_info ainfo; | |
569 | char res_gr, res_vid; | |
570 | ||
571 | ainfo.gr_en = 1; | |
572 | ainfo.vid_en = state->enable_video; | |
573 | ainfo.vid_only_once = 0; | |
574 | ainfo.gr_only_once = 0; | |
575 | ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8); | |
576 | ainfo.vdrain_rate = (int) state->pclk_khz * 2; | |
577 | if (state->video_scale != 0) | |
578 | ainfo.vdrain_rate = ainfo.vdrain_rate/state->video_scale; | |
579 | ainfo.mdrain_rate = 33000; | |
580 | res_info->rtl_values = 0; | |
581 | if (!state->gr_during_vid && state->enable_video) | |
582 | { | |
583 | ainfo.gr_only_once = 1; | |
584 | ainfo.gr_en = 1; | |
585 | ainfo.gdrain_rate = 0; | |
586 | res_vid = nv3_get_param(res_info, state, &ainfo); | |
587 | res_vid = ainfo.converged; | |
588 | save_info.video_lwm = res_info->video_lwm; | |
589 | save_info.video_burst_size = res_info->video_burst_size; | |
590 | ainfo.vid_en = 1; | |
591 | ainfo.vid_only_once = 1; | |
592 | ainfo.gr_en = 1; | |
593 | ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8); | |
594 | ainfo.vdrain_rate = 0; | |
595 | res_gr = nv3_get_param(res_info, state, &ainfo); | |
596 | res_gr = ainfo.converged; | |
597 | res_info->video_lwm = save_info.video_lwm; | |
598 | res_info->video_burst_size = save_info.video_burst_size; | |
599 | res_info->valid = res_gr & res_vid; | |
600 | } | |
601 | else | |
602 | { | |
603 | if (!ainfo.gr_en) ainfo.gdrain_rate = 0; | |
604 | if (!ainfo.vid_en) ainfo.vdrain_rate = 0; | |
605 | res_gr = nv3_get_param(res_info, state, &ainfo); | |
606 | res_info->valid = ainfo.converged; | |
607 | } | |
608 | } | |
609 | static void nv3UpdateArbitrationSettings | |
610 | ( | |
611 | unsigned VClk, | |
612 | unsigned pixelDepth, | |
613 | unsigned *burst, | |
614 | unsigned *lwm, | |
615 | RIVA_HW_INST *chip | |
616 | ) | |
617 | { | |
618 | nv3_fifo_info fifo_data; | |
619 | nv3_sim_state sim_data; | |
620 | unsigned int M, N, P, pll, MClk; | |
621 | ||
622 | pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); | |
623 | M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; | |
624 | MClk = (N * chip->CrystalFreqKHz / M) >> P; | |
625 | sim_data.pix_bpp = (char)pixelDepth; | |
626 | sim_data.enable_video = 0; | |
627 | sim_data.enable_mp = 0; | |
628 | sim_data.video_scale = 1; | |
629 | sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ? | |
630 | 128 : 64; | |
631 | sim_data.memory_width = 128; | |
632 | ||
633 | sim_data.mem_latency = 9; | |
634 | sim_data.mem_aligned = 1; | |
635 | sim_data.mem_page_miss = 11; | |
636 | sim_data.gr_during_vid = 0; | |
637 | sim_data.pclk_khz = VClk; | |
638 | sim_data.mclk_khz = MClk; | |
639 | nv3CalcArbitration(&fifo_data, &sim_data); | |
640 | if (fifo_data.valid) | |
641 | { | |
642 | int b = fifo_data.graphics_burst_size >> 4; | |
643 | *burst = 0; | |
644 | while (b >>= 1) | |
645 | (*burst)++; | |
646 | *lwm = fifo_data.graphics_lwm >> 3; | |
647 | } | |
648 | else | |
649 | { | |
650 | *lwm = 0x24; | |
651 | *burst = 0x2; | |
652 | } | |
653 | } | |
654 | static void nv4CalcArbitration | |
655 | ( | |
656 | nv4_fifo_info *fifo, | |
657 | nv4_sim_state *arb | |
658 | ) | |
659 | { | |
660 | int data, pagemiss, cas,width, video_enable, color_key_enable, bpp, align; | |
661 | int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs; | |
662 | int found, mclk_extra, mclk_loop, cbs, m1, p1; | |
663 | int mclk_freq, pclk_freq, nvclk_freq, mp_enable; | |
664 | int us_m, us_n, us_p, video_drain_rate, crtc_drain_rate; | |
665 | int vpm_us, us_video, vlwm, video_fill_us, cpm_us, us_crt,clwm; | |
666 | int craw, vraw; | |
667 | ||
668 | fifo->valid = 1; | |
669 | pclk_freq = arb->pclk_khz; | |
670 | mclk_freq = arb->mclk_khz; | |
671 | nvclk_freq = arb->nvclk_khz; | |
672 | pagemiss = arb->mem_page_miss; | |
673 | cas = arb->mem_latency; | |
674 | width = arb->memory_width >> 6; | |
675 | video_enable = arb->enable_video; | |
676 | color_key_enable = arb->gr_during_vid; | |
677 | bpp = arb->pix_bpp; | |
678 | align = arb->mem_aligned; | |
679 | mp_enable = arb->enable_mp; | |
680 | clwm = 0; | |
681 | vlwm = 0; | |
682 | cbs = 128; | |
683 | pclks = 2; | |
684 | nvclks = 2; | |
685 | nvclks += 2; | |
686 | nvclks += 1; | |
687 | mclks = 5; | |
688 | mclks += 3; | |
689 | mclks += 1; | |
690 | mclks += cas; | |
691 | mclks += 1; | |
692 | mclks += 1; | |
693 | mclks += 1; | |
694 | mclks += 1; | |
695 | mclk_extra = 3; | |
696 | nvclks += 2; | |
697 | nvclks += 1; | |
698 | nvclks += 1; | |
699 | nvclks += 1; | |
700 | if (mp_enable) | |
701 | mclks+=4; | |
702 | nvclks += 0; | |
703 | pclks += 0; | |
704 | found = 0; | |
705 | vbs = 0; | |
706 | while (found != 1) | |
707 | { | |
708 | fifo->valid = 1; | |
709 | found = 1; | |
710 | mclk_loop = mclks+mclk_extra; | |
711 | us_m = mclk_loop *1000*1000 / mclk_freq; | |
712 | us_n = nvclks*1000*1000 / nvclk_freq; | |
713 | us_p = nvclks*1000*1000 / pclk_freq; | |
714 | if (video_enable) | |
715 | { | |
716 | video_drain_rate = pclk_freq * 2; | |
717 | crtc_drain_rate = pclk_freq * bpp/8; | |
718 | vpagemiss = 2; | |
719 | vpagemiss += 1; | |
720 | crtpagemiss = 2; | |
721 | vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq; | |
722 | if (nvclk_freq * 2 > mclk_freq * width) | |
723 | video_fill_us = cbs*1000*1000 / 16 / nvclk_freq ; | |
724 | else | |
725 | video_fill_us = cbs*1000*1000 / (8 * width) / mclk_freq; | |
726 | us_video = vpm_us + us_m + us_n + us_p + video_fill_us; | |
727 | vlwm = us_video * video_drain_rate/(1000*1000); | |
728 | vlwm++; | |
729 | vbs = 128; | |
730 | if (vlwm > 128) vbs = 64; | |
731 | if (vlwm > (256-64)) vbs = 32; | |
732 | if (nvclk_freq * 2 > mclk_freq * width) | |
733 | video_fill_us = vbs *1000*1000/ 16 / nvclk_freq ; | |
734 | else | |
735 | video_fill_us = vbs*1000*1000 / (8 * width) / mclk_freq; | |
736 | cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq; | |
737 | us_crt = | |
738 | us_video | |
739 | +video_fill_us | |
740 | +cpm_us | |
741 | +us_m + us_n +us_p | |
742 | ; | |
743 | clwm = us_crt * crtc_drain_rate/(1000*1000); | |
744 | clwm++; | |
745 | } | |
746 | else | |
747 | { | |
748 | crtc_drain_rate = pclk_freq * bpp/8; | |
749 | crtpagemiss = 2; | |
750 | crtpagemiss += 1; | |
751 | cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq; | |
752 | us_crt = cpm_us + us_m + us_n + us_p ; | |
753 | clwm = us_crt * crtc_drain_rate/(1000*1000); | |
754 | clwm++; | |
755 | } | |
756 | m1 = clwm + cbs - 512; | |
757 | p1 = m1 * pclk_freq / mclk_freq; | |
758 | p1 = p1 * bpp / 8; | |
759 | if ((p1 < m1) && (m1 > 0)) | |
760 | { | |
761 | fifo->valid = 0; | |
762 | found = 0; | |
763 | if (mclk_extra ==0) found = 1; | |
764 | mclk_extra--; | |
765 | } | |
766 | else if (video_enable) | |
767 | { | |
768 | if ((clwm > 511) || (vlwm > 255)) | |
769 | { | |
770 | fifo->valid = 0; | |
771 | found = 0; | |
772 | if (mclk_extra ==0) found = 1; | |
773 | mclk_extra--; | |
774 | } | |
775 | } | |
776 | else | |
777 | { | |
778 | if (clwm > 519) | |
779 | { | |
780 | fifo->valid = 0; | |
781 | found = 0; | |
782 | if (mclk_extra ==0) found = 1; | |
783 | mclk_extra--; | |
784 | } | |
785 | } | |
786 | craw = clwm; | |
787 | vraw = vlwm; | |
788 | if (clwm < 384) clwm = 384; | |
789 | if (vlwm < 128) vlwm = 128; | |
790 | data = (int)(clwm); | |
791 | fifo->graphics_lwm = data; | |
792 | fifo->graphics_burst_size = 128; | |
793 | data = (int)((vlwm+15)); | |
794 | fifo->video_lwm = data; | |
795 | fifo->video_burst_size = vbs; | |
796 | } | |
797 | } | |
798 | static void nv4UpdateArbitrationSettings | |
799 | ( | |
800 | unsigned VClk, | |
801 | unsigned pixelDepth, | |
802 | unsigned *burst, | |
803 | unsigned *lwm, | |
804 | RIVA_HW_INST *chip | |
805 | ) | |
806 | { | |
807 | nv4_fifo_info fifo_data; | |
808 | nv4_sim_state sim_data; | |
809 | unsigned int M, N, P, pll, MClk, NVClk, cfg1; | |
810 | ||
811 | pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); | |
812 | M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; | |
813 | MClk = (N * chip->CrystalFreqKHz / M) >> P; | |
814 | pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0); | |
815 | M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; | |
816 | NVClk = (N * chip->CrystalFreqKHz / M) >> P; | |
817 | cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0); | |
818 | sim_data.pix_bpp = (char)pixelDepth; | |
819 | sim_data.enable_video = 0; | |
820 | sim_data.enable_mp = 0; | |
821 | sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ? | |
822 | 128 : 64; | |
823 | sim_data.mem_latency = (char)cfg1 & 0x0F; | |
824 | sim_data.mem_aligned = 1; | |
825 | sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01)); | |
826 | sim_data.gr_during_vid = 0; | |
827 | sim_data.pclk_khz = VClk; | |
828 | sim_data.mclk_khz = MClk; | |
829 | sim_data.nvclk_khz = NVClk; | |
830 | nv4CalcArbitration(&fifo_data, &sim_data); | |
831 | if (fifo_data.valid) | |
832 | { | |
833 | int b = fifo_data.graphics_burst_size >> 4; | |
834 | *burst = 0; | |
835 | while (b >>= 1) | |
836 | (*burst)++; | |
837 | *lwm = fifo_data.graphics_lwm >> 3; | |
838 | } | |
839 | } | |
840 | static void nv10CalcArbitration | |
841 | ( | |
842 | nv10_fifo_info *fifo, | |
843 | nv10_sim_state *arb | |
844 | ) | |
845 | { | |
846 | int data, pagemiss, cas,width, video_enable, color_key_enable, bpp, align; | |
847 | int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs; | |
848 | int nvclk_fill, us_extra; | |
849 | int found, mclk_extra, mclk_loop, cbs, m1; | |
850 | int mclk_freq, pclk_freq, nvclk_freq, mp_enable; | |
851 | int us_m, us_m_min, us_n, us_p, video_drain_rate, crtc_drain_rate; | |
852 | int vus_m, vus_n, vus_p; | |
853 | int vpm_us, us_video, vlwm, cpm_us, us_crt,clwm; | |
854 | int clwm_rnd_down; | |
855 | int craw, m2us, us_pipe, us_pipe_min, vus_pipe, p1clk, p2; | |
856 | int pclks_2_top_fifo, min_mclk_extra; | |
857 | int us_min_mclk_extra; | |
858 | ||
859 | fifo->valid = 1; | |
860 | pclk_freq = arb->pclk_khz; /* freq in KHz */ | |
861 | mclk_freq = arb->mclk_khz; | |
862 | nvclk_freq = arb->nvclk_khz; | |
863 | pagemiss = arb->mem_page_miss; | |
864 | cas = arb->mem_latency; | |
865 | width = arb->memory_width/64; | |
866 | video_enable = arb->enable_video; | |
867 | color_key_enable = arb->gr_during_vid; | |
868 | bpp = arb->pix_bpp; | |
869 | align = arb->mem_aligned; | |
870 | mp_enable = arb->enable_mp; | |
871 | clwm = 0; | |
872 | vlwm = 1024; | |
873 | ||
874 | cbs = 512; | |
875 | vbs = 512; | |
876 | ||
877 | pclks = 4; /* lwm detect. */ | |
878 | ||
879 | nvclks = 3; /* lwm -> sync. */ | |
880 | nvclks += 2; /* fbi bus cycles (1 req + 1 busy) */ | |
881 | ||
882 | mclks = 1; /* 2 edge sync. may be very close to edge so just put one. */ | |
883 | ||
884 | mclks += 1; /* arb_hp_req */ | |
885 | mclks += 5; /* ap_hp_req tiling pipeline */ | |
886 | ||
887 | mclks += 2; /* tc_req latency fifo */ | |
888 | mclks += 2; /* fb_cas_n_ memory request to fbio block */ | |
889 | mclks += 7; /* sm_d_rdv data returned from fbio block */ | |
890 | ||
891 | /* fb.rd.d.Put_gc need to accumulate 256 bits for read */ | |
892 | if (arb->memory_type == 0) | |
893 | if (arb->memory_width == 64) /* 64 bit bus */ | |
894 | mclks += 4; | |
895 | else | |
896 | mclks += 2; | |
897 | else | |
898 | if (arb->memory_width == 64) /* 64 bit bus */ | |
899 | mclks += 2; | |
900 | else | |
901 | mclks += 1; | |
902 | ||
903 | if ((!video_enable) && (arb->memory_width == 128)) | |
904 | { | |
905 | mclk_extra = (bpp == 32) ? 31 : 42; /* Margin of error */ | |
906 | min_mclk_extra = 17; | |
907 | } | |
908 | else | |
909 | { | |
910 | mclk_extra = (bpp == 32) ? 8 : 4; /* Margin of error */ | |
911 | /* mclk_extra = 4; */ /* Margin of error */ | |
912 | min_mclk_extra = 18; | |
913 | } | |
914 | ||
915 | nvclks += 1; /* 2 edge sync. may be very close to edge so just put one. */ | |
916 | nvclks += 1; /* fbi_d_rdv_n */ | |
917 | nvclks += 1; /* Fbi_d_rdata */ | |
918 | nvclks += 1; /* crtfifo load */ | |
919 | ||
920 | if(mp_enable) | |
921 | mclks+=4; /* Mp can get in with a burst of 8. */ | |
922 | /* Extra clocks determined by heuristics */ | |
923 | ||
924 | nvclks += 0; | |
925 | pclks += 0; | |
926 | found = 0; | |
927 | while(found != 1) { | |
928 | fifo->valid = 1; | |
929 | found = 1; | |
930 | mclk_loop = mclks+mclk_extra; | |
931 | us_m = mclk_loop *1000*1000 / mclk_freq; /* Mclk latency in us */ | |
932 | us_m_min = mclks * 1000*1000 / mclk_freq; /* Minimum Mclk latency in us */ | |
933 | us_min_mclk_extra = min_mclk_extra *1000*1000 / mclk_freq; | |
934 | us_n = nvclks*1000*1000 / nvclk_freq;/* nvclk latency in us */ | |
935 | us_p = pclks*1000*1000 / pclk_freq;/* nvclk latency in us */ | |
936 | us_pipe = us_m + us_n + us_p; | |
937 | us_pipe_min = us_m_min + us_n + us_p; | |
938 | us_extra = 0; | |
939 | ||
940 | vus_m = mclk_loop *1000*1000 / mclk_freq; /* Mclk latency in us */ | |
941 | vus_n = (4)*1000*1000 / nvclk_freq;/* nvclk latency in us */ | |
942 | vus_p = 0*1000*1000 / pclk_freq;/* pclk latency in us */ | |
943 | vus_pipe = vus_m + vus_n + vus_p; | |
944 | ||
945 | if(video_enable) { | |
946 | video_drain_rate = pclk_freq * 4; /* MB/s */ | |
947 | crtc_drain_rate = pclk_freq * bpp/8; /* MB/s */ | |
948 | ||
949 | vpagemiss = 1; /* self generating page miss */ | |
950 | vpagemiss += 1; /* One higher priority before */ | |
951 | ||
952 | crtpagemiss = 2; /* self generating page miss */ | |
953 | if(mp_enable) | |
954 | crtpagemiss += 1; /* if MA0 conflict */ | |
955 | ||
956 | vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq; | |
957 | ||
958 | us_video = vpm_us + vus_m; /* Video has separate read return path */ | |
959 | ||
960 | cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq; | |
961 | us_crt = | |
962 | us_video /* Wait for video */ | |
963 | +cpm_us /* CRT Page miss */ | |
964 | +us_m + us_n +us_p /* other latency */ | |
965 | ; | |
966 | ||
967 | clwm = us_crt * crtc_drain_rate/(1000*1000); | |
968 | clwm++; /* fixed point <= float_point - 1. Fixes that */ | |
969 | } else { | |
970 | crtc_drain_rate = pclk_freq * bpp/8; /* bpp * pclk/8 */ | |
971 | ||
972 | crtpagemiss = 1; /* self generating page miss */ | |
973 | crtpagemiss += 1; /* MA0 page miss */ | |
974 | if(mp_enable) | |
975 | crtpagemiss += 1; /* if MA0 conflict */ | |
976 | cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq; | |
977 | us_crt = cpm_us + us_m + us_n + us_p ; | |
978 | clwm = us_crt * crtc_drain_rate/(1000*1000); | |
979 | clwm++; /* fixed point <= float_point - 1. Fixes that */ | |
980 | ||
981 | /* | |
982 | // | |
983 | // Another concern, only for high pclks so don't do this | |
984 | // with video: | |
985 | // What happens if the latency to fetch the cbs is so large that | |
986 | // fifo empties. In that case we need to have an alternate clwm value | |
987 | // based off the total burst fetch | |
988 | // | |
989 | us_crt = (cbs * 1000 * 1000)/ (8*width)/mclk_freq ; | |
990 | us_crt = us_crt + us_m + us_n + us_p + (4 * 1000 * 1000)/mclk_freq; | |
991 | clwm_mt = us_crt * crtc_drain_rate/(1000*1000); | |
992 | clwm_mt ++; | |
993 | if(clwm_mt > clwm) | |
994 | clwm = clwm_mt; | |
995 | */ | |
996 | /* Finally, a heuristic check when width == 64 bits */ | |
997 | if(width == 1){ | |
998 | nvclk_fill = nvclk_freq * 8; | |
999 | if(crtc_drain_rate * 100 >= nvclk_fill * 102) | |
1000 | clwm = 0xfff; /*Large number to fail */ | |
1001 | ||
1002 | else if(crtc_drain_rate * 100 >= nvclk_fill * 98) { | |
1003 | clwm = 1024; | |
1004 | cbs = 512; | |
1005 | us_extra = (cbs * 1000 * 1000)/ (8*width)/mclk_freq ; | |
1006 | } | |
1007 | } | |
1008 | } | |
1009 | ||
1010 | ||
1011 | /* | |
1012 | Overfill check: | |
1013 | ||
1014 | */ | |
1015 | ||
1016 | clwm_rnd_down = ((int)clwm/8)*8; | |
1017 | if (clwm_rnd_down < clwm) | |
1018 | clwm += 8; | |
1019 | ||
1020 | m1 = clwm + cbs - 1024; /* Amount of overfill */ | |
1021 | m2us = us_pipe_min + us_min_mclk_extra; | |
1022 | pclks_2_top_fifo = (1024-clwm)/(8*width); | |
1023 | ||
1024 | /* pclk cycles to drain */ | |
1025 | p1clk = m2us * pclk_freq/(1000*1000); | |
1026 | p2 = p1clk * bpp / 8; /* bytes drained. */ | |
1027 | ||
1028 | if((p2 < m1) && (m1 > 0)) { | |
1029 | fifo->valid = 0; | |
1030 | found = 0; | |
1031 | if(min_mclk_extra == 0) { | |
1032 | if(cbs <= 32) { | |
1033 | found = 1; /* Can't adjust anymore! */ | |
1034 | } else { | |
1035 | cbs = cbs/2; /* reduce the burst size */ | |
1036 | } | |
1037 | } else { | |
1038 | min_mclk_extra--; | |
1039 | } | |
1040 | } else { | |
1041 | if (clwm > 1023){ /* Have some margin */ | |
1042 | fifo->valid = 0; | |
1043 | found = 0; | |
1044 | if(min_mclk_extra == 0) | |
1045 | found = 1; /* Can't adjust anymore! */ | |
1046 | else | |
1047 | min_mclk_extra--; | |
1048 | } | |
1049 | } | |
1050 | craw = clwm; | |
1051 | ||
1052 | if(clwm < (1024-cbs+8)) clwm = 1024-cbs+8; | |
1053 | data = (int)(clwm); | |
1054 | /* printf("CRT LWM: %f bytes, prog: 0x%x, bs: 256\n", clwm, data ); */ | |
1055 | fifo->graphics_lwm = data; fifo->graphics_burst_size = cbs; | |
1056 | ||
1057 | /* printf("VID LWM: %f bytes, prog: 0x%x, bs: %d\n, ", vlwm, data, vbs ); */ | |
1058 | fifo->video_lwm = 1024; fifo->video_burst_size = 512; | |
1059 | } | |
1060 | } | |
1061 | static void nv10UpdateArbitrationSettings | |
1062 | ( | |
1063 | unsigned VClk, | |
1064 | unsigned pixelDepth, | |
1065 | unsigned *burst, | |
1066 | unsigned *lwm, | |
1067 | RIVA_HW_INST *chip | |
1068 | ) | |
1069 | { | |
1070 | nv10_fifo_info fifo_data; | |
1071 | nv10_sim_state sim_data; | |
1072 | unsigned int M, N, P, pll, MClk, NVClk, cfg1; | |
1073 | ||
1074 | pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); | |
1075 | M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; | |
1076 | MClk = (N * chip->CrystalFreqKHz / M) >> P; | |
1077 | pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0); | |
1078 | M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; | |
1079 | NVClk = (N * chip->CrystalFreqKHz / M) >> P; | |
1080 | cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0); | |
1081 | sim_data.pix_bpp = (char)pixelDepth; | |
1082 | sim_data.enable_video = 0; | |
1083 | sim_data.enable_mp = 0; | |
1084 | sim_data.memory_type = (NV_RD32(&chip->PFB[0x00000200/4], 0) & 0x01) ? | |
1085 | 1 : 0; | |
1086 | sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ? | |
1087 | 128 : 64; | |
1088 | sim_data.mem_latency = (char)cfg1 & 0x0F; | |
1089 | sim_data.mem_aligned = 1; | |
1090 | sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01)); | |
1091 | sim_data.gr_during_vid = 0; | |
1092 | sim_data.pclk_khz = VClk; | |
1093 | sim_data.mclk_khz = MClk; | |
1094 | sim_data.nvclk_khz = NVClk; | |
1095 | nv10CalcArbitration(&fifo_data, &sim_data); | |
1096 | if (fifo_data.valid) | |
1097 | { | |
1098 | int b = fifo_data.graphics_burst_size >> 4; | |
1099 | *burst = 0; | |
1100 | while (b >>= 1) | |
1101 | (*burst)++; | |
1102 | *lwm = fifo_data.graphics_lwm >> 3; | |
1103 | } | |
1104 | } | |
1105 | ||
1106 | static void nForceUpdateArbitrationSettings | |
1107 | ( | |
1108 | unsigned VClk, | |
1109 | unsigned pixelDepth, | |
1110 | unsigned *burst, | |
1111 | unsigned *lwm, | |
1112 | RIVA_HW_INST *chip | |
1113 | ) | |
1114 | { | |
1115 | nv10_fifo_info fifo_data; | |
1116 | nv10_sim_state sim_data; | |
1117 | unsigned int M, N, P, pll, MClk, NVClk; | |
1118 | unsigned int uMClkPostDiv; | |
1119 | struct pci_dev *dev; | |
1120 | ||
d3736340 | 1121 | dev = pci_get_bus_and_slot(0, 3); |
1da177e4 | 1122 | pci_read_config_dword(dev, 0x6C, &uMClkPostDiv); |
d3736340 | 1123 | pci_dev_put(dev); |
1da177e4 LT |
1124 | uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf; |
1125 | ||
1126 | if(!uMClkPostDiv) uMClkPostDiv = 4; | |
1127 | MClk = 400000 / uMClkPostDiv; | |
1128 | ||
1129 | pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0); | |
1130 | M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; | |
1131 | NVClk = (N * chip->CrystalFreqKHz / M) >> P; | |
1132 | sim_data.pix_bpp = (char)pixelDepth; | |
1133 | sim_data.enable_video = 0; | |
1134 | sim_data.enable_mp = 0; | |
1135 | ||
d3736340 | 1136 | dev = pci_get_bus_and_slot(0, 1); |
1da177e4 | 1137 | pci_read_config_dword(dev, 0x7C, &sim_data.memory_type); |
d3736340 | 1138 | pci_dev_put(dev); |
1da177e4 LT |
1139 | sim_data.memory_type = (sim_data.memory_type >> 12) & 1; |
1140 | ||
1141 | sim_data.memory_width = 64; | |
1142 | sim_data.mem_latency = 3; | |
1143 | sim_data.mem_aligned = 1; | |
1144 | sim_data.mem_page_miss = 10; | |
1145 | sim_data.gr_during_vid = 0; | |
1146 | sim_data.pclk_khz = VClk; | |
1147 | sim_data.mclk_khz = MClk; | |
1148 | sim_data.nvclk_khz = NVClk; | |
1149 | nv10CalcArbitration(&fifo_data, &sim_data); | |
1150 | if (fifo_data.valid) | |
1151 | { | |
1152 | int b = fifo_data.graphics_burst_size >> 4; | |
1153 | *burst = 0; | |
1154 | while (b >>= 1) | |
1155 | (*burst)++; | |
1156 | *lwm = fifo_data.graphics_lwm >> 3; | |
1157 | } | |
1158 | } | |
1159 | ||
1160 | /****************************************************************************\ | |
1161 | * * | |
1162 | * RIVA Mode State Routines * | |
1163 | * * | |
1164 | \****************************************************************************/ | |
1165 | ||
1166 | /* | |
1167 | * Calculate the Video Clock parameters for the PLL. | |
1168 | */ | |
1169 | static int CalcVClock | |
1170 | ( | |
1171 | int clockIn, | |
1172 | int *clockOut, | |
1173 | int *mOut, | |
1174 | int *nOut, | |
1175 | int *pOut, | |
1176 | RIVA_HW_INST *chip | |
1177 | ) | |
1178 | { | |
1179 | unsigned lowM, highM, highP; | |
1180 | unsigned DeltaNew, DeltaOld; | |
1181 | unsigned VClk, Freq; | |
1182 | unsigned M, N, P; | |
1183 | ||
1184 | DeltaOld = 0xFFFFFFFF; | |
1185 | ||
1186 | VClk = (unsigned)clockIn; | |
1187 | ||
1188 | if (chip->CrystalFreqKHz == 13500) | |
1189 | { | |
1190 | lowM = 7; | |
1191 | highM = 13 - (chip->Architecture == NV_ARCH_03); | |
1192 | } | |
1193 | else | |
1194 | { | |
1195 | lowM = 8; | |
1196 | highM = 14 - (chip->Architecture == NV_ARCH_03); | |
1197 | } | |
1198 | ||
1199 | highP = 4 - (chip->Architecture == NV_ARCH_03); | |
1200 | for (P = 0; P <= highP; P ++) | |
1201 | { | |
1202 | Freq = VClk << P; | |
1203 | if ((Freq >= 128000) && (Freq <= chip->MaxVClockFreqKHz)) | |
1204 | { | |
1205 | for (M = lowM; M <= highM; M++) | |
1206 | { | |
1207 | N = (VClk << P) * M / chip->CrystalFreqKHz; | |
1208 | if(N <= 255) { | |
1209 | Freq = (chip->CrystalFreqKHz * N / M) >> P; | |
1210 | if (Freq > VClk) | |
1211 | DeltaNew = Freq - VClk; | |
1212 | else | |
1213 | DeltaNew = VClk - Freq; | |
1214 | if (DeltaNew < DeltaOld) | |
1215 | { | |
1216 | *mOut = M; | |
1217 | *nOut = N; | |
1218 | *pOut = P; | |
1219 | *clockOut = Freq; | |
1220 | DeltaOld = DeltaNew; | |
1221 | } | |
1222 | } | |
1223 | } | |
1224 | } | |
1225 | } | |
a6343afb JG |
1226 | |
1227 | /* non-zero: M/N/P/clock values assigned. zero: error (not set) */ | |
1da177e4 LT |
1228 | return (DeltaOld != 0xFFFFFFFF); |
1229 | } | |
1230 | /* | |
1231 | * Calculate extended mode parameters (SVGA) and save in a | |
1232 | * mode state structure. | |
1233 | */ | |
fd717689 | 1234 | int CalcStateExt |
1da177e4 LT |
1235 | ( |
1236 | RIVA_HW_INST *chip, | |
1237 | RIVA_HW_STATE *state, | |
1238 | int bpp, | |
1239 | int width, | |
1240 | int hDisplaySize, | |
1241 | int height, | |
1242 | int dotClock | |
1243 | ) | |
1244 | { | |
a6343afb JG |
1245 | int pixelDepth; |
1246 | int uninitialized_var(VClk),uninitialized_var(m), | |
1247 | uninitialized_var(n), uninitialized_var(p); | |
1248 | ||
1da177e4 LT |
1249 | /* |
1250 | * Save mode parameters. | |
1251 | */ | |
1252 | state->bpp = bpp; /* this is not bitsPerPixel, it's 8,15,16,32 */ | |
1253 | state->width = width; | |
1254 | state->height = height; | |
1255 | /* | |
1256 | * Extended RIVA registers. | |
1257 | */ | |
1258 | pixelDepth = (bpp + 1)/8; | |
fd717689 JG |
1259 | if (!CalcVClock(dotClock, &VClk, &m, &n, &p, chip)) |
1260 | return -EINVAL; | |
1da177e4 LT |
1261 | |
1262 | switch (chip->Architecture) | |
1263 | { | |
1264 | case NV_ARCH_03: | |
1265 | nv3UpdateArbitrationSettings(VClk, | |
1266 | pixelDepth * 8, | |
1267 | &(state->arbitration0), | |
1268 | &(state->arbitration1), | |
1269 | chip); | |
1270 | state->cursor0 = 0x00; | |
1271 | state->cursor1 = 0x78; | |
1272 | state->cursor2 = 0x00000000; | |
1273 | state->pllsel = 0x10010100; | |
1274 | state->config = ((width + 31)/32) | |
1275 | | (((pixelDepth > 2) ? 3 : pixelDepth) << 8) | |
1276 | | 0x1000; | |
1277 | state->general = 0x00100100; | |
1278 | state->repaint1 = hDisplaySize < 1280 ? 0x06 : 0x02; | |
1279 | break; | |
1280 | case NV_ARCH_04: | |
1281 | nv4UpdateArbitrationSettings(VClk, | |
1282 | pixelDepth * 8, | |
1283 | &(state->arbitration0), | |
1284 | &(state->arbitration1), | |
1285 | chip); | |
1286 | state->cursor0 = 0x00; | |
1287 | state->cursor1 = 0xFC; | |
1288 | state->cursor2 = 0x00000000; | |
1289 | state->pllsel = 0x10000700; | |
1290 | state->config = 0x00001114; | |
1291 | state->general = bpp == 16 ? 0x00101100 : 0x00100100; | |
1292 | state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00; | |
1293 | break; | |
1294 | case NV_ARCH_10: | |
1295 | case NV_ARCH_20: | |
1296 | case NV_ARCH_30: | |
1297 | if((chip->Chipset == NV_CHIP_IGEFORCE2) || | |
1298 | (chip->Chipset == NV_CHIP_0x01F0)) | |
1299 | { | |
1300 | nForceUpdateArbitrationSettings(VClk, | |
1301 | pixelDepth * 8, | |
1302 | &(state->arbitration0), | |
1303 | &(state->arbitration1), | |
1304 | chip); | |
1305 | } else { | |
1306 | nv10UpdateArbitrationSettings(VClk, | |
1307 | pixelDepth * 8, | |
1308 | &(state->arbitration0), | |
1309 | &(state->arbitration1), | |
1310 | chip); | |
1311 | } | |
1312 | state->cursor0 = 0x80 | (chip->CursorStart >> 17); | |
1313 | state->cursor1 = (chip->CursorStart >> 11) << 2; | |
1314 | state->cursor2 = chip->CursorStart >> 24; | |
1315 | state->pllsel = 0x10000700; | |
1316 | state->config = NV_RD32(&chip->PFB[0x00000200/4], 0); | |
1317 | state->general = bpp == 16 ? 0x00101100 : 0x00100100; | |
1318 | state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00; | |
1319 | break; | |
1320 | } | |
1321 | ||
1322 | /* Paul Richards: below if block borks things in kernel for some reason */ | |
1323 | /* Tony: Below is needed to set hardware in DirectColor */ | |
1324 | if((bpp != 8) && (chip->Architecture != NV_ARCH_03)) | |
1325 | state->general |= 0x00000030; | |
1326 | ||
1327 | state->vpll = (p << 16) | (n << 8) | m; | |
1328 | state->repaint0 = (((width/8)*pixelDepth) & 0x700) >> 3; | |
1329 | state->pixel = pixelDepth > 2 ? 3 : pixelDepth; | |
1330 | state->offset0 = | |
1331 | state->offset1 = | |
1332 | state->offset2 = | |
1333 | state->offset3 = 0; | |
1334 | state->pitch0 = | |
1335 | state->pitch1 = | |
1336 | state->pitch2 = | |
1337 | state->pitch3 = pixelDepth * width; | |
fd717689 JG |
1338 | |
1339 | return 0; | |
1da177e4 LT |
1340 | } |
1341 | /* | |
1342 | * Load fixed function state and pre-calculated/stored state. | |
1343 | */ | |
1344 | #if 0 | |
1345 | #define LOAD_FIXED_STATE(tbl,dev) \ | |
1346 | for (i = 0; i < sizeof(tbl##Table##dev)/8; i++) \ | |
1347 | chip->dev[tbl##Table##dev[i][0]] = tbl##Table##dev[i][1] | |
1348 | #define LOAD_FIXED_STATE_8BPP(tbl,dev) \ | |
1349 | for (i = 0; i < sizeof(tbl##Table##dev##_8BPP)/8; i++) \ | |
1350 | chip->dev[tbl##Table##dev##_8BPP[i][0]] = tbl##Table##dev##_8BPP[i][1] | |
1351 | #define LOAD_FIXED_STATE_15BPP(tbl,dev) \ | |
1352 | for (i = 0; i < sizeof(tbl##Table##dev##_15BPP)/8; i++) \ | |
1353 | chip->dev[tbl##Table##dev##_15BPP[i][0]] = tbl##Table##dev##_15BPP[i][1] | |
1354 | #define LOAD_FIXED_STATE_16BPP(tbl,dev) \ | |
1355 | for (i = 0; i < sizeof(tbl##Table##dev##_16BPP)/8; i++) \ | |
1356 | chip->dev[tbl##Table##dev##_16BPP[i][0]] = tbl##Table##dev##_16BPP[i][1] | |
1357 | #define LOAD_FIXED_STATE_32BPP(tbl,dev) \ | |
1358 | for (i = 0; i < sizeof(tbl##Table##dev##_32BPP)/8; i++) \ | |
1359 | chip->dev[tbl##Table##dev##_32BPP[i][0]] = tbl##Table##dev##_32BPP[i][1] | |
1360 | #endif | |
1361 | ||
1362 | #define LOAD_FIXED_STATE(tbl,dev) \ | |
1363 | for (i = 0; i < sizeof(tbl##Table##dev)/8; i++) \ | |
1364 | NV_WR32(&chip->dev[tbl##Table##dev[i][0]], 0, tbl##Table##dev[i][1]) | |
1365 | #define LOAD_FIXED_STATE_8BPP(tbl,dev) \ | |
1366 | for (i = 0; i < sizeof(tbl##Table##dev##_8BPP)/8; i++) \ | |
1367 | NV_WR32(&chip->dev[tbl##Table##dev##_8BPP[i][0]], 0, tbl##Table##dev##_8BPP[i][1]) | |
1368 | #define LOAD_FIXED_STATE_15BPP(tbl,dev) \ | |
1369 | for (i = 0; i < sizeof(tbl##Table##dev##_15BPP)/8; i++) \ | |
1370 | NV_WR32(&chip->dev[tbl##Table##dev##_15BPP[i][0]], 0, tbl##Table##dev##_15BPP[i][1]) | |
1371 | #define LOAD_FIXED_STATE_16BPP(tbl,dev) \ | |
1372 | for (i = 0; i < sizeof(tbl##Table##dev##_16BPP)/8; i++) \ | |
1373 | NV_WR32(&chip->dev[tbl##Table##dev##_16BPP[i][0]], 0, tbl##Table##dev##_16BPP[i][1]) | |
1374 | #define LOAD_FIXED_STATE_32BPP(tbl,dev) \ | |
1375 | for (i = 0; i < sizeof(tbl##Table##dev##_32BPP)/8; i++) \ | |
1376 | NV_WR32(&chip->dev[tbl##Table##dev##_32BPP[i][0]], 0, tbl##Table##dev##_32BPP[i][1]) | |
1377 | ||
1378 | static void UpdateFifoState | |
1379 | ( | |
1380 | RIVA_HW_INST *chip | |
1381 | ) | |
1382 | { | |
1383 | int i; | |
1384 | ||
1385 | switch (chip->Architecture) | |
1386 | { | |
1387 | case NV_ARCH_04: | |
1388 | LOAD_FIXED_STATE(nv4,FIFO); | |
1389 | chip->Tri03 = NULL; | |
1390 | chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]); | |
1391 | break; | |
1392 | case NV_ARCH_10: | |
1393 | case NV_ARCH_20: | |
1394 | case NV_ARCH_30: | |
1395 | /* | |
1396 | * Initialize state for the RivaTriangle3D05 routines. | |
1397 | */ | |
1398 | LOAD_FIXED_STATE(nv10tri05,PGRAPH); | |
1399 | LOAD_FIXED_STATE(nv10,FIFO); | |
1400 | chip->Tri03 = NULL; | |
1401 | chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]); | |
1402 | break; | |
1403 | } | |
1404 | } | |
1405 | static void LoadStateExt | |
1406 | ( | |
1407 | RIVA_HW_INST *chip, | |
1408 | RIVA_HW_STATE *state | |
1409 | ) | |
1410 | { | |
1411 | int i; | |
1412 | ||
1413 | /* | |
1414 | * Load HW fixed function state. | |
1415 | */ | |
1416 | LOAD_FIXED_STATE(Riva,PMC); | |
1417 | LOAD_FIXED_STATE(Riva,PTIMER); | |
1418 | switch (chip->Architecture) | |
1419 | { | |
1420 | case NV_ARCH_03: | |
1421 | /* | |
1422 | * Make sure frame buffer config gets set before loading PRAMIN. | |
1423 | */ | |
1424 | NV_WR32(chip->PFB, 0x00000200, state->config); | |
1425 | LOAD_FIXED_STATE(nv3,PFIFO); | |
1426 | LOAD_FIXED_STATE(nv3,PRAMIN); | |
1427 | LOAD_FIXED_STATE(nv3,PGRAPH); | |
1428 | switch (state->bpp) | |
1429 | { | |
1430 | case 15: | |
1431 | case 16: | |
1432 | LOAD_FIXED_STATE_15BPP(nv3,PRAMIN); | |
1433 | LOAD_FIXED_STATE_15BPP(nv3,PGRAPH); | |
1434 | chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); | |
1435 | break; | |
1436 | case 24: | |
1437 | case 32: | |
1438 | LOAD_FIXED_STATE_32BPP(nv3,PRAMIN); | |
1439 | LOAD_FIXED_STATE_32BPP(nv3,PGRAPH); | |
1440 | chip->Tri03 = NULL; | |
1441 | break; | |
1442 | case 8: | |
1443 | default: | |
1444 | LOAD_FIXED_STATE_8BPP(nv3,PRAMIN); | |
1445 | LOAD_FIXED_STATE_8BPP(nv3,PGRAPH); | |
1446 | chip->Tri03 = NULL; | |
1447 | break; | |
1448 | } | |
1449 | for (i = 0x00000; i < 0x00800; i++) | |
1450 | NV_WR32(&chip->PRAMIN[0x00000502 + i], 0, (i << 12) | 0x03); | |
1451 | NV_WR32(chip->PGRAPH, 0x00000630, state->offset0); | |
1452 | NV_WR32(chip->PGRAPH, 0x00000634, state->offset1); | |
1453 | NV_WR32(chip->PGRAPH, 0x00000638, state->offset2); | |
1454 | NV_WR32(chip->PGRAPH, 0x0000063C, state->offset3); | |
1455 | NV_WR32(chip->PGRAPH, 0x00000650, state->pitch0); | |
1456 | NV_WR32(chip->PGRAPH, 0x00000654, state->pitch1); | |
1457 | NV_WR32(chip->PGRAPH, 0x00000658, state->pitch2); | |
1458 | NV_WR32(chip->PGRAPH, 0x0000065C, state->pitch3); | |
1459 | break; | |
1460 | case NV_ARCH_04: | |
1461 | /* | |
1462 | * Make sure frame buffer config gets set before loading PRAMIN. | |
1463 | */ | |
1464 | NV_WR32(chip->PFB, 0x00000200, state->config); | |
1465 | LOAD_FIXED_STATE(nv4,PFIFO); | |
1466 | LOAD_FIXED_STATE(nv4,PRAMIN); | |
1467 | LOAD_FIXED_STATE(nv4,PGRAPH); | |
1468 | switch (state->bpp) | |
1469 | { | |
1470 | case 15: | |
1471 | LOAD_FIXED_STATE_15BPP(nv4,PRAMIN); | |
1472 | LOAD_FIXED_STATE_15BPP(nv4,PGRAPH); | |
1473 | chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); | |
1474 | break; | |
1475 | case 16: | |
1476 | LOAD_FIXED_STATE_16BPP(nv4,PRAMIN); | |
1477 | LOAD_FIXED_STATE_16BPP(nv4,PGRAPH); | |
1478 | chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); | |
1479 | break; | |
1480 | case 24: | |
1481 | case 32: | |
1482 | LOAD_FIXED_STATE_32BPP(nv4,PRAMIN); | |
1483 | LOAD_FIXED_STATE_32BPP(nv4,PGRAPH); | |
1484 | chip->Tri03 = NULL; | |
1485 | break; | |
1486 | case 8: | |
1487 | default: | |
1488 | LOAD_FIXED_STATE_8BPP(nv4,PRAMIN); | |
1489 | LOAD_FIXED_STATE_8BPP(nv4,PGRAPH); | |
1490 | chip->Tri03 = NULL; | |
1491 | break; | |
1492 | } | |
1493 | NV_WR32(chip->PGRAPH, 0x00000640, state->offset0); | |
1494 | NV_WR32(chip->PGRAPH, 0x00000644, state->offset1); | |
1495 | NV_WR32(chip->PGRAPH, 0x00000648, state->offset2); | |
1496 | NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3); | |
1497 | NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0); | |
1498 | NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1); | |
1499 | NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2); | |
1500 | NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3); | |
1501 | break; | |
1502 | case NV_ARCH_10: | |
1503 | case NV_ARCH_20: | |
1504 | case NV_ARCH_30: | |
1505 | if(chip->twoHeads) { | |
1506 | VGA_WR08(chip->PCIO, 0x03D4, 0x44); | |
1507 | VGA_WR08(chip->PCIO, 0x03D5, state->crtcOwner); | |
1508 | chip->LockUnlock(chip, 0); | |
1509 | } | |
1510 | ||
1511 | LOAD_FIXED_STATE(nv10,PFIFO); | |
1512 | LOAD_FIXED_STATE(nv10,PRAMIN); | |
1513 | LOAD_FIXED_STATE(nv10,PGRAPH); | |
1514 | switch (state->bpp) | |
1515 | { | |
1516 | case 15: | |
1517 | LOAD_FIXED_STATE_15BPP(nv10,PRAMIN); | |
1518 | LOAD_FIXED_STATE_15BPP(nv10,PGRAPH); | |
1519 | chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); | |
1520 | break; | |
1521 | case 16: | |
1522 | LOAD_FIXED_STATE_16BPP(nv10,PRAMIN); | |
1523 | LOAD_FIXED_STATE_16BPP(nv10,PGRAPH); | |
1524 | chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); | |
1525 | break; | |
1526 | case 24: | |
1527 | case 32: | |
1528 | LOAD_FIXED_STATE_32BPP(nv10,PRAMIN); | |
1529 | LOAD_FIXED_STATE_32BPP(nv10,PGRAPH); | |
1530 | chip->Tri03 = NULL; | |
1531 | break; | |
1532 | case 8: | |
1533 | default: | |
1534 | LOAD_FIXED_STATE_8BPP(nv10,PRAMIN); | |
1535 | LOAD_FIXED_STATE_8BPP(nv10,PGRAPH); | |
1536 | chip->Tri03 = NULL; | |
1537 | break; | |
1538 | } | |
1539 | ||
1540 | if(chip->Architecture == NV_ARCH_10) { | |
1541 | NV_WR32(chip->PGRAPH, 0x00000640, state->offset0); | |
1542 | NV_WR32(chip->PGRAPH, 0x00000644, state->offset1); | |
1543 | NV_WR32(chip->PGRAPH, 0x00000648, state->offset2); | |
1544 | NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3); | |
1545 | NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0); | |
1546 | NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1); | |
1547 | NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2); | |
1548 | NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3); | |
1549 | NV_WR32(chip->PGRAPH, 0x00000680, state->pitch3); | |
1550 | } else { | |
1551 | NV_WR32(chip->PGRAPH, 0x00000820, state->offset0); | |
1552 | NV_WR32(chip->PGRAPH, 0x00000824, state->offset1); | |
1553 | NV_WR32(chip->PGRAPH, 0x00000828, state->offset2); | |
1554 | NV_WR32(chip->PGRAPH, 0x0000082C, state->offset3); | |
1555 | NV_WR32(chip->PGRAPH, 0x00000850, state->pitch0); | |
1556 | NV_WR32(chip->PGRAPH, 0x00000854, state->pitch1); | |
1557 | NV_WR32(chip->PGRAPH, 0x00000858, state->pitch2); | |
1558 | NV_WR32(chip->PGRAPH, 0x0000085C, state->pitch3); | |
1559 | NV_WR32(chip->PGRAPH, 0x00000860, state->pitch3); | |
1560 | NV_WR32(chip->PGRAPH, 0x00000864, state->pitch3); | |
1561 | NV_WR32(chip->PGRAPH, 0x000009A4, NV_RD32(chip->PFB, 0x00000200)); | |
1562 | NV_WR32(chip->PGRAPH, 0x000009A8, NV_RD32(chip->PFB, 0x00000204)); | |
1563 | } | |
1564 | if(chip->twoHeads) { | |
1565 | NV_WR32(chip->PCRTC0, 0x00000860, state->head); | |
1566 | NV_WR32(chip->PCRTC0, 0x00002860, state->head2); | |
1567 | } | |
1568 | NV_WR32(chip->PRAMDAC, 0x00000404, NV_RD32(chip->PRAMDAC, 0x00000404) | (1 << 25)); | |
1569 | ||
1570 | NV_WR32(chip->PMC, 0x00008704, 1); | |
1571 | NV_WR32(chip->PMC, 0x00008140, 0); | |
1572 | NV_WR32(chip->PMC, 0x00008920, 0); | |
1573 | NV_WR32(chip->PMC, 0x00008924, 0); | |
1574 | NV_WR32(chip->PMC, 0x00008908, 0x01ffffff); | |
1575 | NV_WR32(chip->PMC, 0x0000890C, 0x01ffffff); | |
1576 | NV_WR32(chip->PMC, 0x00001588, 0); | |
1577 | ||
1578 | NV_WR32(chip->PFB, 0x00000240, 0); | |
1579 | NV_WR32(chip->PFB, 0x00000250, 0); | |
1580 | NV_WR32(chip->PFB, 0x00000260, 0); | |
1581 | NV_WR32(chip->PFB, 0x00000270, 0); | |
1582 | NV_WR32(chip->PFB, 0x00000280, 0); | |
1583 | NV_WR32(chip->PFB, 0x00000290, 0); | |
1584 | NV_WR32(chip->PFB, 0x000002A0, 0); | |
1585 | NV_WR32(chip->PFB, 0x000002B0, 0); | |
1586 | ||
1587 | NV_WR32(chip->PGRAPH, 0x00000B00, NV_RD32(chip->PFB, 0x00000240)); | |
1588 | NV_WR32(chip->PGRAPH, 0x00000B04, NV_RD32(chip->PFB, 0x00000244)); | |
1589 | NV_WR32(chip->PGRAPH, 0x00000B08, NV_RD32(chip->PFB, 0x00000248)); | |
1590 | NV_WR32(chip->PGRAPH, 0x00000B0C, NV_RD32(chip->PFB, 0x0000024C)); | |
1591 | NV_WR32(chip->PGRAPH, 0x00000B10, NV_RD32(chip->PFB, 0x00000250)); | |
1592 | NV_WR32(chip->PGRAPH, 0x00000B14, NV_RD32(chip->PFB, 0x00000254)); | |
1593 | NV_WR32(chip->PGRAPH, 0x00000B18, NV_RD32(chip->PFB, 0x00000258)); | |
1594 | NV_WR32(chip->PGRAPH, 0x00000B1C, NV_RD32(chip->PFB, 0x0000025C)); | |
1595 | NV_WR32(chip->PGRAPH, 0x00000B20, NV_RD32(chip->PFB, 0x00000260)); | |
1596 | NV_WR32(chip->PGRAPH, 0x00000B24, NV_RD32(chip->PFB, 0x00000264)); | |
1597 | NV_WR32(chip->PGRAPH, 0x00000B28, NV_RD32(chip->PFB, 0x00000268)); | |
1598 | NV_WR32(chip->PGRAPH, 0x00000B2C, NV_RD32(chip->PFB, 0x0000026C)); | |
1599 | NV_WR32(chip->PGRAPH, 0x00000B30, NV_RD32(chip->PFB, 0x00000270)); | |
1600 | NV_WR32(chip->PGRAPH, 0x00000B34, NV_RD32(chip->PFB, 0x00000274)); | |
1601 | NV_WR32(chip->PGRAPH, 0x00000B38, NV_RD32(chip->PFB, 0x00000278)); | |
1602 | NV_WR32(chip->PGRAPH, 0x00000B3C, NV_RD32(chip->PFB, 0x0000027C)); | |
1603 | NV_WR32(chip->PGRAPH, 0x00000B40, NV_RD32(chip->PFB, 0x00000280)); | |
1604 | NV_WR32(chip->PGRAPH, 0x00000B44, NV_RD32(chip->PFB, 0x00000284)); | |
1605 | NV_WR32(chip->PGRAPH, 0x00000B48, NV_RD32(chip->PFB, 0x00000288)); | |
1606 | NV_WR32(chip->PGRAPH, 0x00000B4C, NV_RD32(chip->PFB, 0x0000028C)); | |
1607 | NV_WR32(chip->PGRAPH, 0x00000B50, NV_RD32(chip->PFB, 0x00000290)); | |
1608 | NV_WR32(chip->PGRAPH, 0x00000B54, NV_RD32(chip->PFB, 0x00000294)); | |
1609 | NV_WR32(chip->PGRAPH, 0x00000B58, NV_RD32(chip->PFB, 0x00000298)); | |
1610 | NV_WR32(chip->PGRAPH, 0x00000B5C, NV_RD32(chip->PFB, 0x0000029C)); | |
1611 | NV_WR32(chip->PGRAPH, 0x00000B60, NV_RD32(chip->PFB, 0x000002A0)); | |
1612 | NV_WR32(chip->PGRAPH, 0x00000B64, NV_RD32(chip->PFB, 0x000002A4)); | |
1613 | NV_WR32(chip->PGRAPH, 0x00000B68, NV_RD32(chip->PFB, 0x000002A8)); | |
1614 | NV_WR32(chip->PGRAPH, 0x00000B6C, NV_RD32(chip->PFB, 0x000002AC)); | |
1615 | NV_WR32(chip->PGRAPH, 0x00000B70, NV_RD32(chip->PFB, 0x000002B0)); | |
1616 | NV_WR32(chip->PGRAPH, 0x00000B74, NV_RD32(chip->PFB, 0x000002B4)); | |
1617 | NV_WR32(chip->PGRAPH, 0x00000B78, NV_RD32(chip->PFB, 0x000002B8)); | |
1618 | NV_WR32(chip->PGRAPH, 0x00000B7C, NV_RD32(chip->PFB, 0x000002BC)); | |
1619 | NV_WR32(chip->PGRAPH, 0x00000F40, 0x10000000); | |
1620 | NV_WR32(chip->PGRAPH, 0x00000F44, 0x00000000); | |
1621 | NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040); | |
1622 | NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000008); | |
1623 | NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000200); | |
1624 | for (i = 0; i < (3*16); i++) | |
1625 | NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); | |
1626 | NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040); | |
1627 | NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); | |
1628 | NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000800); | |
1629 | for (i = 0; i < (16*16); i++) | |
1630 | NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); | |
1631 | NV_WR32(chip->PGRAPH, 0x00000F40, 0x30000000); | |
1632 | NV_WR32(chip->PGRAPH, 0x00000F44, 0x00000004); | |
1633 | NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006400); | |
1634 | for (i = 0; i < (59*4); i++) | |
1635 | NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); | |
1636 | NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006800); | |
1637 | for (i = 0; i < (47*4); i++) | |
1638 | NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); | |
1639 | NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006C00); | |
1640 | for (i = 0; i < (3*4); i++) | |
1641 | NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); | |
1642 | NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007000); | |
1643 | for (i = 0; i < (19*4); i++) | |
1644 | NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); | |
1645 | NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007400); | |
1646 | for (i = 0; i < (12*4); i++) | |
1647 | NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); | |
1648 | NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007800); | |
1649 | for (i = 0; i < (12*4); i++) | |
1650 | NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); | |
1651 | NV_WR32(chip->PGRAPH, 0x00000F50, 0x00004400); | |
1652 | for (i = 0; i < (8*4); i++) | |
1653 | NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); | |
1654 | NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000000); | |
1655 | for (i = 0; i < 16; i++) | |
1656 | NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); | |
1657 | NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040); | |
1658 | for (i = 0; i < 4; i++) | |
1659 | NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); | |
1660 | ||
1661 | NV_WR32(chip->PCRTC, 0x00000810, state->cursorConfig); | |
1662 | ||
1663 | if(chip->flatPanel) { | |
1664 | if((chip->Chipset & 0x0ff0) == 0x0110) { | |
1665 | NV_WR32(chip->PRAMDAC, 0x0528, state->dither); | |
1666 | } else | |
1667 | if((chip->Chipset & 0x0ff0) >= 0x0170) { | |
1668 | NV_WR32(chip->PRAMDAC, 0x083C, state->dither); | |
1669 | } | |
1670 | ||
1671 | VGA_WR08(chip->PCIO, 0x03D4, 0x53); | |
1672 | VGA_WR08(chip->PCIO, 0x03D5, 0); | |
1673 | VGA_WR08(chip->PCIO, 0x03D4, 0x54); | |
1674 | VGA_WR08(chip->PCIO, 0x03D5, 0); | |
1675 | VGA_WR08(chip->PCIO, 0x03D4, 0x21); | |
1676 | VGA_WR08(chip->PCIO, 0x03D5, 0xfa); | |
1677 | } | |
1678 | ||
1679 | VGA_WR08(chip->PCIO, 0x03D4, 0x41); | |
1680 | VGA_WR08(chip->PCIO, 0x03D5, state->extra); | |
1681 | } | |
1682 | LOAD_FIXED_STATE(Riva,FIFO); | |
1683 | UpdateFifoState(chip); | |
1684 | /* | |
1685 | * Load HW mode state. | |
1686 | */ | |
1687 | VGA_WR08(chip->PCIO, 0x03D4, 0x19); | |
1688 | VGA_WR08(chip->PCIO, 0x03D5, state->repaint0); | |
1689 | VGA_WR08(chip->PCIO, 0x03D4, 0x1A); | |
1690 | VGA_WR08(chip->PCIO, 0x03D5, state->repaint1); | |
1691 | VGA_WR08(chip->PCIO, 0x03D4, 0x25); | |
1692 | VGA_WR08(chip->PCIO, 0x03D5, state->screen); | |
1693 | VGA_WR08(chip->PCIO, 0x03D4, 0x28); | |
1694 | VGA_WR08(chip->PCIO, 0x03D5, state->pixel); | |
1695 | VGA_WR08(chip->PCIO, 0x03D4, 0x2D); | |
1696 | VGA_WR08(chip->PCIO, 0x03D5, state->horiz); | |
1697 | VGA_WR08(chip->PCIO, 0x03D4, 0x1B); | |
1698 | VGA_WR08(chip->PCIO, 0x03D5, state->arbitration0); | |
1699 | VGA_WR08(chip->PCIO, 0x03D4, 0x20); | |
1700 | VGA_WR08(chip->PCIO, 0x03D5, state->arbitration1); | |
1701 | VGA_WR08(chip->PCIO, 0x03D4, 0x30); | |
1702 | VGA_WR08(chip->PCIO, 0x03D5, state->cursor0); | |
1703 | VGA_WR08(chip->PCIO, 0x03D4, 0x31); | |
1704 | VGA_WR08(chip->PCIO, 0x03D5, state->cursor1); | |
1705 | VGA_WR08(chip->PCIO, 0x03D4, 0x2F); | |
1706 | VGA_WR08(chip->PCIO, 0x03D5, state->cursor2); | |
1707 | VGA_WR08(chip->PCIO, 0x03D4, 0x39); | |
1708 | VGA_WR08(chip->PCIO, 0x03D5, state->interlace); | |
1709 | ||
1710 | if(!chip->flatPanel) { | |
1711 | NV_WR32(chip->PRAMDAC0, 0x00000508, state->vpll); | |
1712 | NV_WR32(chip->PRAMDAC0, 0x0000050C, state->pllsel); | |
1713 | if(chip->twoHeads) | |
1714 | NV_WR32(chip->PRAMDAC0, 0x00000520, state->vpll2); | |
1715 | } else { | |
1716 | NV_WR32(chip->PRAMDAC, 0x00000848 , state->scale); | |
1717 | } | |
1718 | NV_WR32(chip->PRAMDAC, 0x00000600 , state->general); | |
1719 | ||
1720 | /* | |
1721 | * Turn off VBlank enable and reset. | |
1722 | */ | |
1723 | NV_WR32(chip->PCRTC, 0x00000140, 0); | |
1724 | NV_WR32(chip->PCRTC, 0x00000100, chip->VBlankBit); | |
1725 | /* | |
1726 | * Set interrupt enable. | |
1727 | */ | |
1728 | NV_WR32(chip->PMC, 0x00000140, chip->EnableIRQ & 0x01); | |
1729 | /* | |
1730 | * Set current state pointer. | |
1731 | */ | |
1732 | chip->CurrentState = state; | |
1733 | /* | |
1734 | * Reset FIFO free and empty counts. | |
1735 | */ | |
1736 | chip->FifoFreeCount = 0; | |
1737 | /* Free count from first subchannel */ | |
1738 | chip->FifoEmptyCount = NV_RD32(&chip->Rop->FifoFree, 0); | |
1739 | } | |
1740 | static void UnloadStateExt | |
1741 | ( | |
1742 | RIVA_HW_INST *chip, | |
1743 | RIVA_HW_STATE *state | |
1744 | ) | |
1745 | { | |
1746 | /* | |
1747 | * Save current HW state. | |
1748 | */ | |
1749 | VGA_WR08(chip->PCIO, 0x03D4, 0x19); | |
1750 | state->repaint0 = VGA_RD08(chip->PCIO, 0x03D5); | |
1751 | VGA_WR08(chip->PCIO, 0x03D4, 0x1A); | |
1752 | state->repaint1 = VGA_RD08(chip->PCIO, 0x03D5); | |
1753 | VGA_WR08(chip->PCIO, 0x03D4, 0x25); | |
1754 | state->screen = VGA_RD08(chip->PCIO, 0x03D5); | |
1755 | VGA_WR08(chip->PCIO, 0x03D4, 0x28); | |
1756 | state->pixel = VGA_RD08(chip->PCIO, 0x03D5); | |
1757 | VGA_WR08(chip->PCIO, 0x03D4, 0x2D); | |
1758 | state->horiz = VGA_RD08(chip->PCIO, 0x03D5); | |
1759 | VGA_WR08(chip->PCIO, 0x03D4, 0x1B); | |
1760 | state->arbitration0 = VGA_RD08(chip->PCIO, 0x03D5); | |
1761 | VGA_WR08(chip->PCIO, 0x03D4, 0x20); | |
1762 | state->arbitration1 = VGA_RD08(chip->PCIO, 0x03D5); | |
1763 | VGA_WR08(chip->PCIO, 0x03D4, 0x30); | |
1764 | state->cursor0 = VGA_RD08(chip->PCIO, 0x03D5); | |
1765 | VGA_WR08(chip->PCIO, 0x03D4, 0x31); | |
1766 | state->cursor1 = VGA_RD08(chip->PCIO, 0x03D5); | |
1767 | VGA_WR08(chip->PCIO, 0x03D4, 0x2F); | |
1768 | state->cursor2 = VGA_RD08(chip->PCIO, 0x03D5); | |
1769 | VGA_WR08(chip->PCIO, 0x03D4, 0x39); | |
1770 | state->interlace = VGA_RD08(chip->PCIO, 0x03D5); | |
1771 | state->vpll = NV_RD32(chip->PRAMDAC0, 0x00000508); | |
1772 | state->vpll2 = NV_RD32(chip->PRAMDAC0, 0x00000520); | |
1773 | state->pllsel = NV_RD32(chip->PRAMDAC0, 0x0000050C); | |
1774 | state->general = NV_RD32(chip->PRAMDAC, 0x00000600); | |
1775 | state->scale = NV_RD32(chip->PRAMDAC, 0x00000848); | |
1776 | state->config = NV_RD32(chip->PFB, 0x00000200); | |
1777 | switch (chip->Architecture) | |
1778 | { | |
1779 | case NV_ARCH_03: | |
1780 | state->offset0 = NV_RD32(chip->PGRAPH, 0x00000630); | |
1781 | state->offset1 = NV_RD32(chip->PGRAPH, 0x00000634); | |
1782 | state->offset2 = NV_RD32(chip->PGRAPH, 0x00000638); | |
1783 | state->offset3 = NV_RD32(chip->PGRAPH, 0x0000063C); | |
1784 | state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000650); | |
1785 | state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000654); | |
1786 | state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000658); | |
1787 | state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000065C); | |
1788 | break; | |
1789 | case NV_ARCH_04: | |
1790 | state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640); | |
1791 | state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644); | |
1792 | state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648); | |
1793 | state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C); | |
1794 | state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670); | |
1795 | state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674); | |
1796 | state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678); | |
1797 | state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C); | |
1798 | break; | |
1799 | case NV_ARCH_10: | |
1800 | case NV_ARCH_20: | |
1801 | case NV_ARCH_30: | |
1802 | state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640); | |
1803 | state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644); | |
1804 | state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648); | |
1805 | state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C); | |
1806 | state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670); | |
1807 | state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674); | |
1808 | state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678); | |
1809 | state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C); | |
1810 | if(chip->twoHeads) { | |
1811 | state->head = NV_RD32(chip->PCRTC0, 0x00000860); | |
1812 | state->head2 = NV_RD32(chip->PCRTC0, 0x00002860); | |
1813 | VGA_WR08(chip->PCIO, 0x03D4, 0x44); | |
1814 | state->crtcOwner = VGA_RD08(chip->PCIO, 0x03D5); | |
1815 | } | |
1816 | VGA_WR08(chip->PCIO, 0x03D4, 0x41); | |
1817 | state->extra = VGA_RD08(chip->PCIO, 0x03D5); | |
1818 | state->cursorConfig = NV_RD32(chip->PCRTC, 0x00000810); | |
1819 | ||
1820 | if((chip->Chipset & 0x0ff0) == 0x0110) { | |
1821 | state->dither = NV_RD32(chip->PRAMDAC, 0x0528); | |
1822 | } else | |
1823 | if((chip->Chipset & 0x0ff0) >= 0x0170) { | |
1824 | state->dither = NV_RD32(chip->PRAMDAC, 0x083C); | |
1825 | } | |
1826 | break; | |
1827 | } | |
1828 | } | |
1829 | static void SetStartAddress | |
1830 | ( | |
1831 | RIVA_HW_INST *chip, | |
1832 | unsigned start | |
1833 | ) | |
1834 | { | |
1835 | NV_WR32(chip->PCRTC, 0x800, start); | |
1836 | } | |
1837 | ||
1838 | static void SetStartAddress3 | |
1839 | ( | |
1840 | RIVA_HW_INST *chip, | |
1841 | unsigned start | |
1842 | ) | |
1843 | { | |
1844 | int offset = start >> 2; | |
1845 | int pan = (start & 3) << 1; | |
1846 | unsigned char tmp; | |
1847 | ||
1848 | /* | |
1849 | * Unlock extended registers. | |
1850 | */ | |
1851 | chip->LockUnlock(chip, 0); | |
1852 | /* | |
1853 | * Set start address. | |
1854 | */ | |
1855 | VGA_WR08(chip->PCIO, 0x3D4, 0x0D); VGA_WR08(chip->PCIO, 0x3D5, offset); | |
1856 | offset >>= 8; | |
1857 | VGA_WR08(chip->PCIO, 0x3D4, 0x0C); VGA_WR08(chip->PCIO, 0x3D5, offset); | |
1858 | offset >>= 8; | |
1859 | VGA_WR08(chip->PCIO, 0x3D4, 0x19); tmp = VGA_RD08(chip->PCIO, 0x3D5); | |
1860 | VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x01F) | (tmp & ~0x1F)); | |
1861 | VGA_WR08(chip->PCIO, 0x3D4, 0x2D); tmp = VGA_RD08(chip->PCIO, 0x3D5); | |
1862 | VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x60) | (tmp & ~0x60)); | |
1863 | /* | |
1864 | * 4 pixel pan register. | |
1865 | */ | |
1866 | offset = VGA_RD08(chip->PCIO, chip->IO + 0x0A); | |
1867 | VGA_WR08(chip->PCIO, 0x3C0, 0x13); | |
1868 | VGA_WR08(chip->PCIO, 0x3C0, pan); | |
1869 | } | |
1870 | static void nv3SetSurfaces2D | |
1871 | ( | |
1872 | RIVA_HW_INST *chip, | |
1873 | unsigned surf0, | |
1874 | unsigned surf1 | |
1875 | ) | |
1876 | { | |
1877 | RivaSurface __iomem *Surface = | |
1878 | (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); | |
1879 | ||
1880 | RIVA_FIFO_FREE(*chip,Tri03,5); | |
1881 | NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003); | |
1882 | NV_WR32(&Surface->Offset, 0, surf0); | |
1883 | NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004); | |
1884 | NV_WR32(&Surface->Offset, 0, surf1); | |
1885 | NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000013); | |
1886 | } | |
1887 | static void nv4SetSurfaces2D | |
1888 | ( | |
1889 | RIVA_HW_INST *chip, | |
1890 | unsigned surf0, | |
1891 | unsigned surf1 | |
1892 | ) | |
1893 | { | |
1894 | RivaSurface __iomem *Surface = | |
1895 | (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); | |
1896 | ||
1897 | NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003); | |
1898 | NV_WR32(&Surface->Offset, 0, surf0); | |
1899 | NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004); | |
1900 | NV_WR32(&Surface->Offset, 0, surf1); | |
1901 | NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); | |
1902 | } | |
1903 | static void nv10SetSurfaces2D | |
1904 | ( | |
1905 | RIVA_HW_INST *chip, | |
1906 | unsigned surf0, | |
1907 | unsigned surf1 | |
1908 | ) | |
1909 | { | |
1910 | RivaSurface __iomem *Surface = | |
1911 | (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); | |
1912 | ||
1913 | NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003); | |
1914 | NV_WR32(&Surface->Offset, 0, surf0); | |
1915 | NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004); | |
1916 | NV_WR32(&Surface->Offset, 0, surf1); | |
1917 | NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); | |
1918 | } | |
1919 | static void nv3SetSurfaces3D | |
1920 | ( | |
1921 | RIVA_HW_INST *chip, | |
1922 | unsigned surf0, | |
1923 | unsigned surf1 | |
1924 | ) | |
1925 | { | |
1926 | RivaSurface __iomem *Surface = | |
1927 | (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); | |
1928 | ||
1929 | RIVA_FIFO_FREE(*chip,Tri03,5); | |
1930 | NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000005); | |
1931 | NV_WR32(&Surface->Offset, 0, surf0); | |
1932 | NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000006); | |
1933 | NV_WR32(&Surface->Offset, 0, surf1); | |
1934 | NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000013); | |
1935 | } | |
1936 | static void nv4SetSurfaces3D | |
1937 | ( | |
1938 | RIVA_HW_INST *chip, | |
1939 | unsigned surf0, | |
1940 | unsigned surf1 | |
1941 | ) | |
1942 | { | |
1943 | RivaSurface __iomem *Surface = | |
1944 | (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); | |
1945 | ||
1946 | NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000005); | |
1947 | NV_WR32(&Surface->Offset, 0, surf0); | |
1948 | NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000006); | |
1949 | NV_WR32(&Surface->Offset, 0, surf1); | |
1950 | NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); | |
1951 | } | |
1952 | static void nv10SetSurfaces3D | |
1953 | ( | |
1954 | RIVA_HW_INST *chip, | |
1955 | unsigned surf0, | |
1956 | unsigned surf1 | |
1957 | ) | |
1958 | { | |
1959 | RivaSurface3D __iomem *Surfaces3D = | |
1960 | (RivaSurface3D __iomem *)&(chip->FIFO[0x0000E000/4]); | |
1961 | ||
1962 | RIVA_FIFO_FREE(*chip,Tri03,4); | |
1963 | NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000007); | |
1964 | NV_WR32(&Surfaces3D->RenderBufferOffset, 0, surf0); | |
1965 | NV_WR32(&Surfaces3D->ZBufferOffset, 0, surf1); | |
1966 | NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); | |
1967 | } | |
1968 | ||
1969 | /****************************************************************************\ | |
1970 | * * | |
1971 | * Probe RIVA Chip Configuration * | |
1972 | * * | |
1973 | \****************************************************************************/ | |
1974 | ||
1975 | static void nv3GetConfig | |
1976 | ( | |
1977 | RIVA_HW_INST *chip | |
1978 | ) | |
1979 | { | |
1980 | /* | |
1981 | * Fill in chip configuration. | |
1982 | */ | |
1983 | if (NV_RD32(&chip->PFB[0x00000000/4], 0) & 0x00000020) | |
1984 | { | |
1985 | if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20) | |
1986 | && ((NV_RD32(chip->PMC, 0x00000000) & 0x0F) >= 0x02)) | |
1987 | { | |
1988 | /* | |
1989 | * SDRAM 128 ZX. | |
1990 | */ | |
1991 | chip->RamBandwidthKBytesPerSec = 800000; | |
1992 | switch (NV_RD32(chip->PFB, 0x00000000) & 0x03) | |
1993 | { | |
1994 | case 2: | |
1995 | chip->RamAmountKBytes = 1024 * 4; | |
1996 | break; | |
1997 | case 1: | |
1998 | chip->RamAmountKBytes = 1024 * 2; | |
1999 | break; | |
2000 | default: | |
2001 | chip->RamAmountKBytes = 1024 * 8; | |
2002 | break; | |
2003 | } | |
2004 | } | |
2005 | else | |
2006 | { | |
2007 | chip->RamBandwidthKBytesPerSec = 1000000; | |
2008 | chip->RamAmountKBytes = 1024 * 8; | |
2009 | } | |
2010 | } | |
2011 | else | |
2012 | { | |
2013 | /* | |
2014 | * SGRAM 128. | |
2015 | */ | |
2016 | chip->RamBandwidthKBytesPerSec = 1000000; | |
2017 | switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) | |
2018 | { | |
2019 | case 0: | |
2020 | chip->RamAmountKBytes = 1024 * 8; | |
2021 | break; | |
2022 | case 2: | |
2023 | chip->RamAmountKBytes = 1024 * 4; | |
2024 | break; | |
2025 | default: | |
2026 | chip->RamAmountKBytes = 1024 * 2; | |
2027 | break; | |
2028 | } | |
2029 | } | |
2030 | chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500; | |
2031 | chip->CURSOR = &(chip->PRAMIN[0x00008000/4 - 0x0800/4]); | |
2032 | chip->VBlankBit = 0x00000100; | |
2033 | chip->MaxVClockFreqKHz = 256000; | |
2034 | /* | |
2035 | * Set chip functions. | |
2036 | */ | |
2037 | chip->Busy = nv3Busy; | |
2038 | chip->ShowHideCursor = ShowHideCursor; | |
1da177e4 LT |
2039 | chip->LoadStateExt = LoadStateExt; |
2040 | chip->UnloadStateExt = UnloadStateExt; | |
2041 | chip->SetStartAddress = SetStartAddress3; | |
2042 | chip->SetSurfaces2D = nv3SetSurfaces2D; | |
2043 | chip->SetSurfaces3D = nv3SetSurfaces3D; | |
2044 | chip->LockUnlock = nv3LockUnlock; | |
2045 | } | |
2046 | static void nv4GetConfig | |
2047 | ( | |
2048 | RIVA_HW_INST *chip | |
2049 | ) | |
2050 | { | |
2051 | /* | |
2052 | * Fill in chip configuration. | |
2053 | */ | |
2054 | if (NV_RD32(chip->PFB, 0x00000000) & 0x00000100) | |
2055 | { | |
2056 | chip->RamAmountKBytes = ((NV_RD32(chip->PFB, 0x00000000) >> 12) & 0x0F) * 1024 * 2 | |
2057 | + 1024 * 2; | |
2058 | } | |
2059 | else | |
2060 | { | |
2061 | switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) | |
2062 | { | |
2063 | case 0: | |
2064 | chip->RamAmountKBytes = 1024 * 32; | |
2065 | break; | |
2066 | case 1: | |
2067 | chip->RamAmountKBytes = 1024 * 4; | |
2068 | break; | |
2069 | case 2: | |
2070 | chip->RamAmountKBytes = 1024 * 8; | |
2071 | break; | |
2072 | case 3: | |
2073 | default: | |
2074 | chip->RamAmountKBytes = 1024 * 16; | |
2075 | break; | |
2076 | } | |
2077 | } | |
2078 | switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003) | |
2079 | { | |
2080 | case 3: | |
2081 | chip->RamBandwidthKBytesPerSec = 800000; | |
2082 | break; | |
2083 | default: | |
2084 | chip->RamBandwidthKBytesPerSec = 1000000; | |
2085 | break; | |
2086 | } | |
2087 | chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500; | |
2088 | chip->CURSOR = &(chip->PRAMIN[0x00010000/4 - 0x0800/4]); | |
2089 | chip->VBlankBit = 0x00000001; | |
2090 | chip->MaxVClockFreqKHz = 350000; | |
2091 | /* | |
2092 | * Set chip functions. | |
2093 | */ | |
2094 | chip->Busy = nv4Busy; | |
2095 | chip->ShowHideCursor = ShowHideCursor; | |
1da177e4 LT |
2096 | chip->LoadStateExt = LoadStateExt; |
2097 | chip->UnloadStateExt = UnloadStateExt; | |
2098 | chip->SetStartAddress = SetStartAddress; | |
2099 | chip->SetSurfaces2D = nv4SetSurfaces2D; | |
2100 | chip->SetSurfaces3D = nv4SetSurfaces3D; | |
2101 | chip->LockUnlock = nv4LockUnlock; | |
2102 | } | |
2103 | static void nv10GetConfig | |
2104 | ( | |
2105 | RIVA_HW_INST *chip, | |
2106 | unsigned int chipset | |
2107 | ) | |
2108 | { | |
2109 | struct pci_dev* dev; | |
7d345b22 | 2110 | u32 amt; |
1da177e4 LT |
2111 | |
2112 | #ifdef __BIG_ENDIAN | |
2113 | /* turn on big endian register access */ | |
2114 | if(!(NV_RD32(chip->PMC, 0x00000004) & 0x01000001)) | |
2115 | NV_WR32(chip->PMC, 0x00000004, 0x01000001); | |
2116 | #endif | |
2117 | ||
2118 | /* | |
2119 | * Fill in chip configuration. | |
2120 | */ | |
2121 | if(chipset == NV_CHIP_IGEFORCE2) { | |
d3736340 | 2122 | dev = pci_get_bus_and_slot(0, 1); |
1da177e4 | 2123 | pci_read_config_dword(dev, 0x7C, &amt); |
d3736340 | 2124 | pci_dev_put(dev); |
1da177e4 LT |
2125 | chip->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024; |
2126 | } else if(chipset == NV_CHIP_0x01F0) { | |
d3736340 | 2127 | dev = pci_get_bus_and_slot(0, 1); |
1da177e4 | 2128 | pci_read_config_dword(dev, 0x84, &amt); |
d3736340 | 2129 | pci_dev_put(dev); |
1da177e4 LT |
2130 | chip->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024; |
2131 | } else { | |
2132 | switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) & 0x000000FF) | |
2133 | { | |
2134 | case 0x02: | |
2135 | chip->RamAmountKBytes = 1024 * 2; | |
2136 | break; | |
2137 | case 0x04: | |
2138 | chip->RamAmountKBytes = 1024 * 4; | |
2139 | break; | |
2140 | case 0x08: | |
2141 | chip->RamAmountKBytes = 1024 * 8; | |
2142 | break; | |
2143 | case 0x10: | |
2144 | chip->RamAmountKBytes = 1024 * 16; | |
2145 | break; | |
2146 | case 0x20: | |
2147 | chip->RamAmountKBytes = 1024 * 32; | |
2148 | break; | |
2149 | case 0x40: | |
2150 | chip->RamAmountKBytes = 1024 * 64; | |
2151 | break; | |
2152 | case 0x80: | |
2153 | chip->RamAmountKBytes = 1024 * 128; | |
2154 | break; | |
2155 | default: | |
2156 | chip->RamAmountKBytes = 1024 * 16; | |
2157 | break; | |
2158 | } | |
2159 | } | |
2160 | switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003) | |
2161 | { | |
2162 | case 3: | |
2163 | chip->RamBandwidthKBytesPerSec = 800000; | |
2164 | break; | |
2165 | default: | |
2166 | chip->RamBandwidthKBytesPerSec = 1000000; | |
2167 | break; | |
2168 | } | |
2169 | chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 6)) ? | |
2170 | 14318 : 13500; | |
2171 | ||
2172 | switch (chipset & 0x0ff0) { | |
2173 | case 0x0170: | |
2174 | case 0x0180: | |
2175 | case 0x01F0: | |
2176 | case 0x0250: | |
2177 | case 0x0280: | |
2178 | case 0x0300: | |
2179 | case 0x0310: | |
2180 | case 0x0320: | |
2181 | case 0x0330: | |
2182 | case 0x0340: | |
2183 | if(NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 22)) | |
2184 | chip->CrystalFreqKHz = 27000; | |
2185 | break; | |
2186 | default: | |
2187 | break; | |
2188 | } | |
2189 | ||
2190 | chip->CursorStart = (chip->RamAmountKBytes - 128) * 1024; | |
2191 | chip->CURSOR = NULL; /* can't set this here */ | |
2192 | chip->VBlankBit = 0x00000001; | |
2193 | chip->MaxVClockFreqKHz = 350000; | |
2194 | /* | |
2195 | * Set chip functions. | |
2196 | */ | |
2197 | chip->Busy = nv10Busy; | |
2198 | chip->ShowHideCursor = ShowHideCursor; | |
1da177e4 LT |
2199 | chip->LoadStateExt = LoadStateExt; |
2200 | chip->UnloadStateExt = UnloadStateExt; | |
2201 | chip->SetStartAddress = SetStartAddress; | |
2202 | chip->SetSurfaces2D = nv10SetSurfaces2D; | |
2203 | chip->SetSurfaces3D = nv10SetSurfaces3D; | |
2204 | chip->LockUnlock = nv4LockUnlock; | |
2205 | ||
2206 | switch(chipset & 0x0ff0) { | |
2207 | case 0x0110: | |
2208 | case 0x0170: | |
2209 | case 0x0180: | |
2210 | case 0x01F0: | |
2211 | case 0x0250: | |
2212 | case 0x0280: | |
2213 | case 0x0300: | |
2214 | case 0x0310: | |
2215 | case 0x0320: | |
2216 | case 0x0330: | |
2217 | case 0x0340: | |
2218 | chip->twoHeads = TRUE; | |
2219 | break; | |
2220 | default: | |
2221 | chip->twoHeads = FALSE; | |
2222 | break; | |
2223 | } | |
2224 | } | |
2225 | int RivaGetConfig | |
2226 | ( | |
2227 | RIVA_HW_INST *chip, | |
2228 | unsigned int chipset | |
2229 | ) | |
2230 | { | |
2231 | /* | |
2232 | * Save this so future SW know whats it's dealing with. | |
2233 | */ | |
2234 | chip->Version = RIVA_SW_VERSION; | |
2235 | /* | |
2236 | * Chip specific configuration. | |
2237 | */ | |
2238 | switch (chip->Architecture) | |
2239 | { | |
2240 | case NV_ARCH_03: | |
2241 | nv3GetConfig(chip); | |
2242 | break; | |
2243 | case NV_ARCH_04: | |
2244 | nv4GetConfig(chip); | |
2245 | break; | |
2246 | case NV_ARCH_10: | |
2247 | case NV_ARCH_20: | |
2248 | case NV_ARCH_30: | |
2249 | nv10GetConfig(chip, chipset); | |
2250 | break; | |
2251 | default: | |
2252 | return (-1); | |
2253 | } | |
2254 | chip->Chipset = chipset; | |
2255 | /* | |
2256 | * Fill in FIFO pointers. | |
2257 | */ | |
2258 | chip->Rop = (RivaRop __iomem *)&(chip->FIFO[0x00000000/4]); | |
2259 | chip->Clip = (RivaClip __iomem *)&(chip->FIFO[0x00002000/4]); | |
2260 | chip->Patt = (RivaPattern __iomem *)&(chip->FIFO[0x00004000/4]); | |
2261 | chip->Pixmap = (RivaPixmap __iomem *)&(chip->FIFO[0x00006000/4]); | |
2262 | chip->Blt = (RivaScreenBlt __iomem *)&(chip->FIFO[0x00008000/4]); | |
2263 | chip->Bitmap = (RivaBitmap __iomem *)&(chip->FIFO[0x0000A000/4]); | |
2264 | chip->Line = (RivaLine __iomem *)&(chip->FIFO[0x0000C000/4]); | |
2265 | chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); | |
2266 | return (0); | |
2267 | } | |
2268 |