Commit | Line | Data |
---|---|---|
ec549a0f BD |
1 | /* linux/drivers/video/s3c-fb.c |
2 | * | |
3 | * Copyright 2008 Openmoko Inc. | |
50a5503a | 4 | * Copyright 2008-2010 Simtec Electronics |
ec549a0f BD |
5 | * Ben Dooks <ben@simtec.co.uk> |
6 | * http://armlinux.simtec.co.uk/ | |
7 | * | |
8 | * Samsung SoC Framebuffer driver | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
c4bb6ffa | 12 | * published by the Free Software FoundatIon. |
ec549a0f BD |
13 | */ |
14 | ||
15 | #include <linux/kernel.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/dma-mapping.h> | |
5a0e3ad6 | 19 | #include <linux/slab.h> |
ec549a0f | 20 | #include <linux/init.h> |
ec549a0f BD |
21 | #include <linux/clk.h> |
22 | #include <linux/fb.h> | |
23 | #include <linux/io.h> | |
efdc846d PO |
24 | #include <linux/uaccess.h> |
25 | #include <linux/interrupt.h> | |
4959212c | 26 | #include <linux/pm_runtime.h> |
ec549a0f BD |
27 | |
28 | #include <mach/map.h> | |
c4bb6ffa | 29 | #include <plat/regs-fb-v4.h> |
ec549a0f BD |
30 | #include <plat/fb.h> |
31 | ||
32 | /* This driver will export a number of framebuffer interfaces depending | |
33 | * on the configuration passed in via the platform data. Each fb instance | |
34 | * maps to a hardware window. Currently there is no support for runtime | |
35 | * setting of the alpha-blending functions that each window has, so only | |
36 | * window 0 is actually useful. | |
37 | * | |
38 | * Window 0 is treated specially, it is used for the basis of the LCD | |
39 | * output timings and as the control for the output power-down state. | |
40 | */ | |
41 | ||
50a5503a BD |
42 | /* note, the previous use of <mach/regs-fb.h> to get platform specific data |
43 | * has been replaced by using the platform device name to pick the correct | |
44 | * configuration data for the system. | |
ec549a0f BD |
45 | */ |
46 | ||
47 | #ifdef CONFIG_FB_S3C_DEBUG_REGWRITE | |
48 | #undef writel | |
49 | #define writel(v, r) do { \ | |
65302e48 | 50 | pr_debug("%s: %08x => %p\n", __func__, (unsigned int)v, r); \ |
05e52b4b JH |
51 | __raw_writel(v, r); \ |
52 | } while (0) | |
ec549a0f BD |
53 | #endif /* FB_S3C_DEBUG_REGWRITE */ |
54 | ||
efdc846d PO |
55 | /* irq_flags bits */ |
56 | #define S3C_FB_VSYNC_IRQ_EN 0 | |
57 | ||
58 | #define VSYNC_TIMEOUT_MSEC 50 | |
59 | ||
ec549a0f BD |
60 | struct s3c_fb; |
61 | ||
50a5503a BD |
62 | #define VALID_BPP(x) (1 << ((x) - 1)) |
63 | ||
c4bb6ffa BD |
64 | #define OSD_BASE(win, variant) ((variant).osd + ((win) * (variant).osd_stride)) |
65 | #define VIDOSD_A(win, variant) (OSD_BASE(win, variant) + 0x00) | |
66 | #define VIDOSD_B(win, variant) (OSD_BASE(win, variant) + 0x04) | |
67 | #define VIDOSD_C(win, variant) (OSD_BASE(win, variant) + 0x08) | |
68 | #define VIDOSD_D(win, variant) (OSD_BASE(win, variant) + 0x0C) | |
69 | ||
50a5503a BD |
70 | /** |
71 | * struct s3c_fb_variant - fb variant information | |
c4bb6ffa | 72 | * @is_2443: Set if S3C2443/S3C2416 style hardware. |
50a5503a | 73 | * @nr_windows: The number of windows. |
c4bb6ffa BD |
74 | * @vidtcon: The base for the VIDTCONx registers |
75 | * @wincon: The base for the WINxCON registers. | |
76 | * @winmap: The base for the WINxMAP registers. | |
77 | * @keycon: The abse for the WxKEYCON registers. | |
78 | * @buf_start: Offset of buffer start registers. | |
79 | * @buf_size: Offset of buffer size registers. | |
80 | * @buf_end: Offset of buffer end registers. | |
81 | * @osd: The base for the OSD registers. | |
50a5503a | 82 | * @palette: Address of palette memory, or 0 if none. |
067b226b | 83 | * @has_prtcon: Set if has PRTCON register. |
f5ec546f | 84 | * @has_shadowcon: Set if has SHADOWCON register. |
f7f31e50 | 85 | * @has_blendcon: Set if has BLENDCON register. |
b5480ed7 | 86 | * @has_clksel: Set if VIDCON0 register has CLKSEL bit. |
d8b97db4 | 87 | * @has_fixvclk: Set if VIDCON1 register has FIXVCLK bits. |
50a5503a BD |
88 | */ |
89 | struct s3c_fb_variant { | |
c4bb6ffa | 90 | unsigned int is_2443:1; |
50a5503a | 91 | unsigned short nr_windows; |
5c44778e | 92 | unsigned int vidtcon; |
c4bb6ffa BD |
93 | unsigned short wincon; |
94 | unsigned short winmap; | |
95 | unsigned short keycon; | |
96 | unsigned short buf_start; | |
97 | unsigned short buf_end; | |
98 | unsigned short buf_size; | |
99 | unsigned short osd; | |
100 | unsigned short osd_stride; | |
50a5503a | 101 | unsigned short palette[S3C_FB_MAX_WIN]; |
067b226b PO |
102 | |
103 | unsigned int has_prtcon:1; | |
f5ec546f | 104 | unsigned int has_shadowcon:1; |
f7f31e50 | 105 | unsigned int has_blendcon:1; |
b5480ed7 | 106 | unsigned int has_clksel:1; |
d8b97db4 | 107 | unsigned int has_fixvclk:1; |
50a5503a BD |
108 | }; |
109 | ||
110 | /** | |
111 | * struct s3c_fb_win_variant | |
112 | * @has_osd_c: Set if has OSD C register. | |
113 | * @has_osd_d: Set if has OSD D register. | |
f676ec2a | 114 | * @has_osd_alpha: Set if can change alpha transparency for a window. |
50a5503a BD |
115 | * @palette_sz: Size of palette in entries. |
116 | * @palette_16bpp: Set if palette is 16bits wide. | |
f676ec2a PO |
117 | * @osd_size_off: If != 0, supports setting up OSD for a window; the appropriate |
118 | * register is located at the given offset from OSD_BASE. | |
50a5503a BD |
119 | * @valid_bpp: 1 bit per BPP setting to show valid bits-per-pixel. |
120 | * | |
121 | * valid_bpp bit x is set if (x+1)BPP is supported. | |
122 | */ | |
123 | struct s3c_fb_win_variant { | |
124 | unsigned int has_osd_c:1; | |
125 | unsigned int has_osd_d:1; | |
f676ec2a | 126 | unsigned int has_osd_alpha:1; |
50a5503a | 127 | unsigned int palette_16bpp:1; |
f676ec2a | 128 | unsigned short osd_size_off; |
50a5503a BD |
129 | unsigned short palette_sz; |
130 | u32 valid_bpp; | |
131 | }; | |
132 | ||
133 | /** | |
134 | * struct s3c_fb_driverdata - per-device type driver data for init time. | |
135 | * @variant: The variant information for this driver. | |
136 | * @win: The window information for each window. | |
137 | */ | |
138 | struct s3c_fb_driverdata { | |
139 | struct s3c_fb_variant variant; | |
140 | struct s3c_fb_win_variant *win[S3C_FB_MAX_WIN]; | |
141 | }; | |
142 | ||
bc2da1b6 BD |
143 | /** |
144 | * struct s3c_fb_palette - palette information | |
145 | * @r: Red bitfield. | |
146 | * @g: Green bitfield. | |
147 | * @b: Blue bitfield. | |
148 | * @a: Alpha bitfield. | |
149 | */ | |
150 | struct s3c_fb_palette { | |
151 | struct fb_bitfield r; | |
152 | struct fb_bitfield g; | |
153 | struct fb_bitfield b; | |
154 | struct fb_bitfield a; | |
155 | }; | |
156 | ||
ec549a0f BD |
157 | /** |
158 | * struct s3c_fb_win - per window private data for each framebuffer. | |
159 | * @windata: The platform data supplied for the window configuration. | |
160 | * @parent: The hardware that this window is part of. | |
161 | * @fbinfo: Pointer pack to the framebuffer info for this window. | |
50a5503a | 162 | * @varint: The variant information for this window. |
ec549a0f BD |
163 | * @palette_buffer: Buffer/cache to hold palette entries. |
164 | * @pseudo_palette: For use in TRUECOLOUR modes for entries 0..15/ | |
165 | * @index: The window number of this window. | |
166 | * @palette: The bitfields for changing r/g/b into a hardware palette entry. | |
167 | */ | |
168 | struct s3c_fb_win { | |
169 | struct s3c_fb_pd_win *windata; | |
170 | struct s3c_fb *parent; | |
171 | struct fb_info *fbinfo; | |
172 | struct s3c_fb_palette palette; | |
50a5503a | 173 | struct s3c_fb_win_variant variant; |
ec549a0f BD |
174 | |
175 | u32 *palette_buffer; | |
176 | u32 pseudo_palette[16]; | |
177 | unsigned int index; | |
178 | }; | |
179 | ||
efdc846d PO |
180 | /** |
181 | * struct s3c_fb_vsync - vsync information | |
182 | * @wait: a queue for processes waiting for vsync | |
183 | * @count: vsync interrupt count | |
184 | */ | |
185 | struct s3c_fb_vsync { | |
186 | wait_queue_head_t wait; | |
187 | unsigned int count; | |
188 | }; | |
189 | ||
ec549a0f BD |
190 | /** |
191 | * struct s3c_fb - overall hardware state of the hardware | |
b07f3bbe | 192 | * @slock: The spinlock protection for this data sturcture. |
ec549a0f | 193 | * @dev: The device that we bound to, for printing, etc. |
ec549a0f | 194 | * @bus_clk: The clk (hclk) feeding our interface and possibly pixclk. |
b5480ed7 | 195 | * @lcd_clk: The clk (sclk) feeding pixclk. |
ec549a0f | 196 | * @regs: The mapped hardware registers. |
50a5503a | 197 | * @variant: Variant information for this hardware. |
ec549a0f | 198 | * @enabled: A bitmask of enabled hardware windows. |
f4f51473 | 199 | * @output_on: Flag if the physical output is enabled. |
ec549a0f BD |
200 | * @pdata: The platform configuration data passed with the device. |
201 | * @windows: The hardware windows that have been claimed. | |
efdc846d PO |
202 | * @irq_no: IRQ line number |
203 | * @irq_flags: irq flags | |
204 | * @vsync_info: VSYNC-related information (count, queues...) | |
ec549a0f BD |
205 | */ |
206 | struct s3c_fb { | |
b07f3bbe | 207 | spinlock_t slock; |
ec549a0f | 208 | struct device *dev; |
ec549a0f | 209 | struct clk *bus_clk; |
b5480ed7 | 210 | struct clk *lcd_clk; |
ec549a0f | 211 | void __iomem *regs; |
50a5503a | 212 | struct s3c_fb_variant variant; |
ec549a0f BD |
213 | |
214 | unsigned char enabled; | |
f4f51473 | 215 | bool output_on; |
ec549a0f BD |
216 | |
217 | struct s3c_fb_platdata *pdata; | |
218 | struct s3c_fb_win *windows[S3C_FB_MAX_WIN]; | |
efdc846d PO |
219 | |
220 | int irq_no; | |
221 | unsigned long irq_flags; | |
222 | struct s3c_fb_vsync vsync_info; | |
ec549a0f BD |
223 | }; |
224 | ||
225 | /** | |
50a5503a BD |
226 | * s3c_fb_validate_win_bpp - validate the bits-per-pixel for this mode. |
227 | * @win: The device window. | |
228 | * @bpp: The bit depth. | |
ec549a0f | 229 | */ |
50a5503a | 230 | static bool s3c_fb_validate_win_bpp(struct s3c_fb_win *win, unsigned int bpp) |
ec549a0f | 231 | { |
50a5503a | 232 | return win->variant.valid_bpp & VALID_BPP(bpp); |
ec549a0f BD |
233 | } |
234 | ||
235 | /** | |
236 | * s3c_fb_check_var() - framebuffer layer request to verify a given mode. | |
237 | * @var: The screen information to verify. | |
238 | * @info: The framebuffer device. | |
239 | * | |
240 | * Framebuffer layer call to verify the given information and allow us to | |
241 | * update various information depending on the hardware capabilities. | |
242 | */ | |
243 | static int s3c_fb_check_var(struct fb_var_screeninfo *var, | |
244 | struct fb_info *info) | |
245 | { | |
246 | struct s3c_fb_win *win = info->par; | |
ec549a0f BD |
247 | struct s3c_fb *sfb = win->parent; |
248 | ||
249 | dev_dbg(sfb->dev, "checking parameters\n"); | |
250 | ||
13e6af88 JH |
251 | var->xres_virtual = max(var->xres_virtual, var->xres); |
252 | var->yres_virtual = max(var->yres_virtual, var->yres); | |
ec549a0f | 253 | |
50a5503a | 254 | if (!s3c_fb_validate_win_bpp(win, var->bits_per_pixel)) { |
ec549a0f BD |
255 | dev_dbg(sfb->dev, "win %d: unsupported bpp %d\n", |
256 | win->index, var->bits_per_pixel); | |
257 | return -EINVAL; | |
258 | } | |
259 | ||
260 | /* always ensure these are zero, for drop through cases below */ | |
261 | var->transp.offset = 0; | |
262 | var->transp.length = 0; | |
263 | ||
264 | switch (var->bits_per_pixel) { | |
265 | case 1: | |
266 | case 2: | |
267 | case 4: | |
268 | case 8: | |
50a5503a | 269 | if (sfb->variant.palette[win->index] != 0) { |
ec549a0f BD |
270 | /* non palletised, A:1,R:2,G:3,B:2 mode */ |
271 | var->red.offset = 4; | |
272 | var->green.offset = 2; | |
273 | var->blue.offset = 0; | |
274 | var->red.length = 5; | |
275 | var->green.length = 3; | |
276 | var->blue.length = 2; | |
277 | var->transp.offset = 7; | |
278 | var->transp.length = 1; | |
279 | } else { | |
280 | var->red.offset = 0; | |
281 | var->red.length = var->bits_per_pixel; | |
282 | var->green = var->red; | |
283 | var->blue = var->red; | |
284 | } | |
285 | break; | |
286 | ||
287 | case 19: | |
288 | /* 666 with one bit alpha/transparency */ | |
289 | var->transp.offset = 18; | |
290 | var->transp.length = 1; | |
291 | case 18: | |
292 | var->bits_per_pixel = 32; | |
293 | ||
294 | /* 666 format */ | |
295 | var->red.offset = 12; | |
296 | var->green.offset = 6; | |
297 | var->blue.offset = 0; | |
298 | var->red.length = 6; | |
299 | var->green.length = 6; | |
300 | var->blue.length = 6; | |
301 | break; | |
302 | ||
303 | case 16: | |
304 | /* 16 bpp, 565 format */ | |
305 | var->red.offset = 11; | |
306 | var->green.offset = 5; | |
307 | var->blue.offset = 0; | |
308 | var->red.length = 5; | |
309 | var->green.length = 6; | |
310 | var->blue.length = 5; | |
311 | break; | |
312 | ||
af1ce6b2 | 313 | case 32: |
ec549a0f BD |
314 | case 28: |
315 | case 25: | |
316 | var->transp.length = var->bits_per_pixel - 24; | |
317 | var->transp.offset = 24; | |
318 | /* drop through */ | |
319 | case 24: | |
320 | /* our 24bpp is unpacked, so 32bpp */ | |
321 | var->bits_per_pixel = 32; | |
ec549a0f BD |
322 | var->red.offset = 16; |
323 | var->red.length = 8; | |
324 | var->green.offset = 8; | |
325 | var->green.length = 8; | |
326 | var->blue.offset = 0; | |
327 | var->blue.length = 8; | |
328 | break; | |
329 | ||
330 | default: | |
331 | dev_err(sfb->dev, "invalid bpp\n"); | |
332 | } | |
333 | ||
334 | dev_dbg(sfb->dev, "%s: verified parameters\n", __func__); | |
335 | return 0; | |
336 | } | |
337 | ||
338 | /** | |
339 | * s3c_fb_calc_pixclk() - calculate the divider to create the pixel clock. | |
340 | * @sfb: The hardware state. | |
341 | * @pixclock: The pixel clock wanted, in picoseconds. | |
342 | * | |
343 | * Given the specified pixel clock, work out the necessary divider to get | |
344 | * close to the output frequency. | |
345 | */ | |
eb29a5cc | 346 | static int s3c_fb_calc_pixclk(struct s3c_fb *sfb, unsigned int pixclk) |
ec549a0f | 347 | { |
b5480ed7 | 348 | unsigned long clk; |
eb29a5cc | 349 | unsigned long long tmp; |
ec549a0f BD |
350 | unsigned int result; |
351 | ||
b5480ed7 JH |
352 | if (sfb->variant.has_clksel) |
353 | clk = clk_get_rate(sfb->bus_clk); | |
354 | else | |
355 | clk = clk_get_rate(sfb->lcd_clk); | |
356 | ||
eb29a5cc MB |
357 | tmp = (unsigned long long)clk; |
358 | tmp *= pixclk; | |
359 | ||
360 | do_div(tmp, 1000000000UL); | |
361 | result = (unsigned int)tmp / 1000; | |
ec549a0f BD |
362 | |
363 | dev_dbg(sfb->dev, "pixclk=%u, clk=%lu, div=%d (%lu)\n", | |
b6798951 | 364 | pixclk, clk, result, result ? clk / result : clk); |
ec549a0f BD |
365 | |
366 | return result; | |
367 | } | |
368 | ||
369 | /** | |
370 | * s3c_fb_align_word() - align pixel count to word boundary | |
371 | * @bpp: The number of bits per pixel | |
372 | * @pix: The value to be aligned. | |
373 | * | |
374 | * Align the given pixel count so that it will start on an 32bit word | |
375 | * boundary. | |
376 | */ | |
377 | static int s3c_fb_align_word(unsigned int bpp, unsigned int pix) | |
378 | { | |
379 | int pix_per_word; | |
380 | ||
381 | if (bpp > 16) | |
382 | return pix; | |
383 | ||
384 | pix_per_word = (8 * 32) / bpp; | |
385 | return ALIGN(pix, pix_per_word); | |
386 | } | |
387 | ||
f676ec2a PO |
388 | /** |
389 | * vidosd_set_size() - set OSD size for a window | |
390 | * | |
391 | * @win: the window to set OSD size for | |
392 | * @size: OSD size register value | |
393 | */ | |
394 | static void vidosd_set_size(struct s3c_fb_win *win, u32 size) | |
395 | { | |
396 | struct s3c_fb *sfb = win->parent; | |
397 | ||
398 | /* OSD can be set up if osd_size_off != 0 for this window */ | |
399 | if (win->variant.osd_size_off) | |
400 | writel(size, sfb->regs + OSD_BASE(win->index, sfb->variant) | |
401 | + win->variant.osd_size_off); | |
402 | } | |
403 | ||
404 | /** | |
405 | * vidosd_set_alpha() - set alpha transparency for a window | |
406 | * | |
407 | * @win: the window to set OSD size for | |
408 | * @alpha: alpha register value | |
409 | */ | |
410 | static void vidosd_set_alpha(struct s3c_fb_win *win, u32 alpha) | |
411 | { | |
412 | struct s3c_fb *sfb = win->parent; | |
413 | ||
414 | if (win->variant.has_osd_alpha) | |
415 | writel(alpha, sfb->regs + VIDOSD_C(win->index, sfb->variant)); | |
416 | } | |
417 | ||
f5ec546f PO |
418 | /** |
419 | * shadow_protect_win() - disable updating values from shadow registers at vsync | |
420 | * | |
421 | * @win: window to protect registers for | |
422 | * @protect: 1 to protect (disable updates) | |
423 | */ | |
424 | static void shadow_protect_win(struct s3c_fb_win *win, bool protect) | |
425 | { | |
426 | struct s3c_fb *sfb = win->parent; | |
427 | u32 reg; | |
428 | ||
429 | if (protect) { | |
430 | if (sfb->variant.has_prtcon) { | |
431 | writel(PRTCON_PROTECT, sfb->regs + PRTCON); | |
432 | } else if (sfb->variant.has_shadowcon) { | |
433 | reg = readl(sfb->regs + SHADOWCON); | |
434 | writel(reg | SHADOWCON_WINx_PROTECT(win->index), | |
435 | sfb->regs + SHADOWCON); | |
436 | } | |
437 | } else { | |
438 | if (sfb->variant.has_prtcon) { | |
439 | writel(0, sfb->regs + PRTCON); | |
440 | } else if (sfb->variant.has_shadowcon) { | |
441 | reg = readl(sfb->regs + SHADOWCON); | |
442 | writel(reg & ~SHADOWCON_WINx_PROTECT(win->index), | |
443 | sfb->regs + SHADOWCON); | |
444 | } | |
445 | } | |
446 | } | |
447 | ||
a2b77dce MB |
448 | /** |
449 | * s3c_fb_enable() - Set the state of the main LCD output | |
450 | * @sfb: The main framebuffer state. | |
451 | * @enable: The state to set. | |
452 | */ | |
453 | static void s3c_fb_enable(struct s3c_fb *sfb, int enable) | |
454 | { | |
455 | u32 vidcon0 = readl(sfb->regs + VIDCON0); | |
456 | ||
f4f51473 MB |
457 | if (enable && !sfb->output_on) |
458 | pm_runtime_get_sync(sfb->dev); | |
459 | ||
460 | if (enable) { | |
a2b77dce | 461 | vidcon0 |= VIDCON0_ENVID | VIDCON0_ENVID_F; |
f4f51473 | 462 | } else { |
a2b77dce MB |
463 | /* see the note in the framebuffer datasheet about |
464 | * why you cannot take both of these bits down at the | |
465 | * same time. */ | |
466 | ||
f4f51473 MB |
467 | if (vidcon0 & VIDCON0_ENVID) { |
468 | vidcon0 |= VIDCON0_ENVID; | |
469 | vidcon0 &= ~VIDCON0_ENVID_F; | |
470 | } | |
a2b77dce MB |
471 | } |
472 | ||
473 | writel(vidcon0, sfb->regs + VIDCON0); | |
f4f51473 MB |
474 | |
475 | if (!enable && sfb->output_on) | |
476 | pm_runtime_put_sync(sfb->dev); | |
477 | ||
478 | sfb->output_on = enable; | |
a2b77dce MB |
479 | } |
480 | ||
ec549a0f BD |
481 | /** |
482 | * s3c_fb_set_par() - framebuffer request to set new framebuffer state. | |
483 | * @info: The framebuffer to change. | |
484 | * | |
485 | * Framebuffer layer request to set a new mode for the specified framebuffer | |
486 | */ | |
487 | static int s3c_fb_set_par(struct fb_info *info) | |
488 | { | |
489 | struct fb_var_screeninfo *var = &info->var; | |
490 | struct s3c_fb_win *win = info->par; | |
491 | struct s3c_fb *sfb = win->parent; | |
492 | void __iomem *regs = sfb->regs; | |
c4bb6ffa | 493 | void __iomem *buf = regs; |
ec549a0f | 494 | int win_no = win->index; |
f676ec2a | 495 | u32 alpha = 0; |
ec549a0f BD |
496 | u32 data; |
497 | u32 pagewidth; | |
ec549a0f BD |
498 | |
499 | dev_dbg(sfb->dev, "setting framebuffer parameters\n"); | |
500 | ||
5751b23e MB |
501 | pm_runtime_get_sync(sfb->dev); |
502 | ||
a8bdabca PO |
503 | shadow_protect_win(win, 1); |
504 | ||
ec549a0f BD |
505 | switch (var->bits_per_pixel) { |
506 | case 32: | |
507 | case 24: | |
508 | case 16: | |
509 | case 12: | |
510 | info->fix.visual = FB_VISUAL_TRUECOLOR; | |
511 | break; | |
512 | case 8: | |
50a5503a | 513 | if (win->variant.palette_sz >= 256) |
ec549a0f BD |
514 | info->fix.visual = FB_VISUAL_PSEUDOCOLOR; |
515 | else | |
516 | info->fix.visual = FB_VISUAL_TRUECOLOR; | |
517 | break; | |
518 | case 1: | |
519 | info->fix.visual = FB_VISUAL_MONO01; | |
520 | break; | |
521 | default: | |
522 | info->fix.visual = FB_VISUAL_PSEUDOCOLOR; | |
523 | break; | |
524 | } | |
525 | ||
526 | info->fix.line_length = (var->xres_virtual * var->bits_per_pixel) / 8; | |
527 | ||
067b226b PO |
528 | info->fix.xpanstep = info->var.xres_virtual > info->var.xres ? 1 : 0; |
529 | info->fix.ypanstep = info->var.yres_virtual > info->var.yres ? 1 : 0; | |
530 | ||
ec549a0f BD |
531 | /* disable the window whilst we update it */ |
532 | writel(0, regs + WINCON(win_no)); | |
533 | ||
3c582647 | 534 | if (!sfb->output_on) |
a2b77dce MB |
535 | s3c_fb_enable(sfb, 1); |
536 | ||
ec549a0f BD |
537 | /* write the buffer address */ |
538 | ||
c4bb6ffa BD |
539 | /* start and end registers stride is 8 */ |
540 | buf = regs + win_no * 8; | |
541 | ||
542 | writel(info->fix.smem_start, buf + sfb->variant.buf_start); | |
ec549a0f BD |
543 | |
544 | data = info->fix.smem_start + info->fix.line_length * var->yres; | |
c4bb6ffa | 545 | writel(data, buf + sfb->variant.buf_end); |
ec549a0f BD |
546 | |
547 | pagewidth = (var->xres * var->bits_per_pixel) >> 3; | |
548 | data = VIDW_BUF_SIZE_OFFSET(info->fix.line_length - pagewidth) | | |
5c44778e JH |
549 | VIDW_BUF_SIZE_PAGEWIDTH(pagewidth) | |
550 | VIDW_BUF_SIZE_OFFSET_E(info->fix.line_length - pagewidth) | | |
551 | VIDW_BUF_SIZE_PAGEWIDTH_E(pagewidth); | |
c4bb6ffa | 552 | writel(data, regs + sfb->variant.buf_size + (win_no * 4)); |
ec549a0f BD |
553 | |
554 | /* write 'OSD' registers to control position of framebuffer */ | |
555 | ||
5c44778e JH |
556 | data = VIDOSDxA_TOPLEFT_X(0) | VIDOSDxA_TOPLEFT_Y(0) | |
557 | VIDOSDxA_TOPLEFT_X_E(0) | VIDOSDxA_TOPLEFT_Y_E(0); | |
c4bb6ffa | 558 | writel(data, regs + VIDOSD_A(win_no, sfb->variant)); |
ec549a0f BD |
559 | |
560 | data = VIDOSDxB_BOTRIGHT_X(s3c_fb_align_word(var->bits_per_pixel, | |
561 | var->xres - 1)) | | |
5c44778e JH |
562 | VIDOSDxB_BOTRIGHT_Y(var->yres - 1) | |
563 | VIDOSDxB_BOTRIGHT_X_E(s3c_fb_align_word(var->bits_per_pixel, | |
564 | var->xres - 1)) | | |
565 | VIDOSDxB_BOTRIGHT_Y_E(var->yres - 1); | |
ec549a0f | 566 | |
c4bb6ffa | 567 | writel(data, regs + VIDOSD_B(win_no, sfb->variant)); |
ec549a0f BD |
568 | |
569 | data = var->xres * var->yres; | |
39000d65 | 570 | |
f676ec2a | 571 | alpha = VIDISD14C_ALPHA1_R(0xf) | |
39000d65 ID |
572 | VIDISD14C_ALPHA1_G(0xf) | |
573 | VIDISD14C_ALPHA1_B(0xf); | |
574 | ||
f676ec2a PO |
575 | vidosd_set_alpha(win, alpha); |
576 | vidosd_set_size(win, data); | |
ec549a0f | 577 | |
fab7c5b7 JH |
578 | /* Enable DMA channel for this window */ |
579 | if (sfb->variant.has_shadowcon) { | |
580 | data = readl(sfb->regs + SHADOWCON); | |
581 | data |= SHADOWCON_CHx_ENABLE(win_no); | |
582 | writel(data, sfb->regs + SHADOWCON); | |
583 | } | |
584 | ||
ec549a0f | 585 | data = WINCONx_ENWIN; |
2d9ae7ac | 586 | sfb->enabled |= (1 << win->index); |
ec549a0f BD |
587 | |
588 | /* note, since we have to round up the bits-per-pixel, we end up | |
589 | * relying on the bitfield information for r/g/b/a to work out | |
590 | * exactly which mode of operation is intended. */ | |
591 | ||
592 | switch (var->bits_per_pixel) { | |
593 | case 1: | |
594 | data |= WINCON0_BPPMODE_1BPP; | |
595 | data |= WINCONx_BITSWP; | |
596 | data |= WINCONx_BURSTLEN_4WORD; | |
597 | break; | |
598 | case 2: | |
599 | data |= WINCON0_BPPMODE_2BPP; | |
600 | data |= WINCONx_BITSWP; | |
601 | data |= WINCONx_BURSTLEN_8WORD; | |
602 | break; | |
603 | case 4: | |
604 | data |= WINCON0_BPPMODE_4BPP; | |
605 | data |= WINCONx_BITSWP; | |
606 | data |= WINCONx_BURSTLEN_8WORD; | |
607 | break; | |
608 | case 8: | |
609 | if (var->transp.length != 0) | |
610 | data |= WINCON1_BPPMODE_8BPP_1232; | |
611 | else | |
612 | data |= WINCON0_BPPMODE_8BPP_PALETTE; | |
613 | data |= WINCONx_BURSTLEN_8WORD; | |
614 | data |= WINCONx_BYTSWP; | |
615 | break; | |
616 | case 16: | |
617 | if (var->transp.length != 0) | |
618 | data |= WINCON1_BPPMODE_16BPP_A1555; | |
619 | else | |
620 | data |= WINCON0_BPPMODE_16BPP_565; | |
621 | data |= WINCONx_HAWSWP; | |
622 | data |= WINCONx_BURSTLEN_16WORD; | |
623 | break; | |
624 | case 24: | |
625 | case 32: | |
626 | if (var->red.length == 6) { | |
627 | if (var->transp.length != 0) | |
628 | data |= WINCON1_BPPMODE_19BPP_A1666; | |
629 | else | |
630 | data |= WINCON1_BPPMODE_18BPP_666; | |
39000d65 ID |
631 | } else if (var->transp.length == 1) |
632 | data |= WINCON1_BPPMODE_25BPP_A1888 | |
633 | | WINCON1_BLD_PIX; | |
4420dd2b JH |
634 | else if ((var->transp.length == 4) || |
635 | (var->transp.length == 8)) | |
39000d65 ID |
636 | data |= WINCON1_BPPMODE_28BPP_A4888 |
637 | | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL; | |
ec549a0f BD |
638 | else |
639 | data |= WINCON0_BPPMODE_24BPP_888; | |
640 | ||
dc8498c0 | 641 | data |= WINCONx_WSWP; |
ec549a0f BD |
642 | data |= WINCONx_BURSTLEN_16WORD; |
643 | break; | |
644 | } | |
645 | ||
c4bb6ffa | 646 | /* Enable the colour keying for the window below this one */ |
39000d65 ID |
647 | if (win_no > 0) { |
648 | u32 keycon0_data = 0, keycon1_data = 0; | |
c4bb6ffa | 649 | void __iomem *keycon = regs + sfb->variant.keycon; |
39000d65 ID |
650 | |
651 | keycon0_data = ~(WxKEYCON0_KEYBL_EN | | |
652 | WxKEYCON0_KEYEN_F | | |
653 | WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); | |
654 | ||
655 | keycon1_data = WxKEYCON1_COLVAL(0xffffff); | |
656 | ||
c4bb6ffa BD |
657 | keycon += (win_no - 1) * 8; |
658 | ||
659 | writel(keycon0_data, keycon + WKEYCON0); | |
660 | writel(keycon1_data, keycon + WKEYCON1); | |
39000d65 ID |
661 | } |
662 | ||
c4bb6ffa BD |
663 | writel(data, regs + sfb->variant.wincon + (win_no * 4)); |
664 | writel(0x0, regs + sfb->variant.winmap + (win_no * 4)); | |
ec549a0f | 665 | |
f7f31e50 JH |
666 | /* Set alpha value width */ |
667 | if (sfb->variant.has_blendcon) { | |
668 | data = readl(sfb->regs + BLENDCON); | |
669 | data &= ~BLENDCON_NEW_MASK; | |
670 | if (var->transp.length > 4) | |
671 | data |= BLENDCON_NEW_8BIT_ALPHA_VALUE; | |
672 | else | |
673 | data |= BLENDCON_NEW_4BIT_ALPHA_VALUE; | |
674 | writel(data, sfb->regs + BLENDCON); | |
675 | } | |
676 | ||
a8bdabca PO |
677 | shadow_protect_win(win, 0); |
678 | ||
5751b23e MB |
679 | pm_runtime_put_sync(sfb->dev); |
680 | ||
ec549a0f BD |
681 | return 0; |
682 | } | |
683 | ||
684 | /** | |
685 | * s3c_fb_update_palette() - set or schedule a palette update. | |
686 | * @sfb: The hardware information. | |
687 | * @win: The window being updated. | |
688 | * @reg: The palette index being changed. | |
689 | * @value: The computed palette value. | |
690 | * | |
691 | * Change the value of a palette register, either by directly writing to | |
692 | * the palette (this requires the palette RAM to be disconnected from the | |
693 | * hardware whilst this is in progress) or schedule the update for later. | |
694 | * | |
695 | * At the moment, since we have no VSYNC interrupt support, we simply set | |
696 | * the palette entry directly. | |
697 | */ | |
698 | static void s3c_fb_update_palette(struct s3c_fb *sfb, | |
699 | struct s3c_fb_win *win, | |
700 | unsigned int reg, | |
701 | u32 value) | |
702 | { | |
703 | void __iomem *palreg; | |
704 | u32 palcon; | |
705 | ||
50a5503a | 706 | palreg = sfb->regs + sfb->variant.palette[win->index]; |
ec549a0f BD |
707 | |
708 | dev_dbg(sfb->dev, "%s: win %d, reg %d (%p): %08x\n", | |
709 | __func__, win->index, reg, palreg, value); | |
710 | ||
711 | win->palette_buffer[reg] = value; | |
712 | ||
713 | palcon = readl(sfb->regs + WPALCON); | |
714 | writel(palcon | WPALCON_PAL_UPDATE, sfb->regs + WPALCON); | |
715 | ||
50a5503a BD |
716 | if (win->variant.palette_16bpp) |
717 | writew(value, palreg + (reg * 2)); | |
ec549a0f | 718 | else |
50a5503a | 719 | writel(value, palreg + (reg * 4)); |
ec549a0f BD |
720 | |
721 | writel(palcon, sfb->regs + WPALCON); | |
722 | } | |
723 | ||
724 | static inline unsigned int chan_to_field(unsigned int chan, | |
725 | struct fb_bitfield *bf) | |
726 | { | |
727 | chan &= 0xffff; | |
728 | chan >>= 16 - bf->length; | |
729 | return chan << bf->offset; | |
730 | } | |
731 | ||
732 | /** | |
733 | * s3c_fb_setcolreg() - framebuffer layer request to change palette. | |
734 | * @regno: The palette index to change. | |
735 | * @red: The red field for the palette data. | |
736 | * @green: The green field for the palette data. | |
737 | * @blue: The blue field for the palette data. | |
738 | * @trans: The transparency (alpha) field for the palette data. | |
739 | * @info: The framebuffer being changed. | |
740 | */ | |
741 | static int s3c_fb_setcolreg(unsigned regno, | |
742 | unsigned red, unsigned green, unsigned blue, | |
743 | unsigned transp, struct fb_info *info) | |
744 | { | |
745 | struct s3c_fb_win *win = info->par; | |
746 | struct s3c_fb *sfb = win->parent; | |
747 | unsigned int val; | |
748 | ||
749 | dev_dbg(sfb->dev, "%s: win %d: %d => rgb=%d/%d/%d\n", | |
750 | __func__, win->index, regno, red, green, blue); | |
751 | ||
5751b23e MB |
752 | pm_runtime_get_sync(sfb->dev); |
753 | ||
ec549a0f BD |
754 | switch (info->fix.visual) { |
755 | case FB_VISUAL_TRUECOLOR: | |
756 | /* true-colour, use pseudo-palette */ | |
757 | ||
758 | if (regno < 16) { | |
759 | u32 *pal = info->pseudo_palette; | |
760 | ||
761 | val = chan_to_field(red, &info->var.red); | |
762 | val |= chan_to_field(green, &info->var.green); | |
763 | val |= chan_to_field(blue, &info->var.blue); | |
764 | ||
765 | pal[regno] = val; | |
766 | } | |
767 | break; | |
768 | ||
769 | case FB_VISUAL_PSEUDOCOLOR: | |
50a5503a | 770 | if (regno < win->variant.palette_sz) { |
ec549a0f BD |
771 | val = chan_to_field(red, &win->palette.r); |
772 | val |= chan_to_field(green, &win->palette.g); | |
773 | val |= chan_to_field(blue, &win->palette.b); | |
774 | ||
775 | s3c_fb_update_palette(sfb, win, regno, val); | |
776 | } | |
777 | ||
778 | break; | |
779 | ||
780 | default: | |
5751b23e | 781 | pm_runtime_put_sync(sfb->dev); |
ec549a0f BD |
782 | return 1; /* unknown type */ |
783 | } | |
784 | ||
5751b23e | 785 | pm_runtime_put_sync(sfb->dev); |
ec549a0f BD |
786 | return 0; |
787 | } | |
788 | ||
ec549a0f BD |
789 | /** |
790 | * s3c_fb_blank() - blank or unblank the given window | |
791 | * @blank_mode: The blank state from FB_BLANK_* | |
792 | * @info: The framebuffer to blank. | |
793 | * | |
794 | * Framebuffer layer request to change the power state. | |
795 | */ | |
796 | static int s3c_fb_blank(int blank_mode, struct fb_info *info) | |
797 | { | |
798 | struct s3c_fb_win *win = info->par; | |
799 | struct s3c_fb *sfb = win->parent; | |
800 | unsigned int index = win->index; | |
801 | u32 wincon; | |
3c582647 | 802 | u32 output_on = sfb->output_on; |
ec549a0f BD |
803 | |
804 | dev_dbg(sfb->dev, "blank mode %d\n", blank_mode); | |
805 | ||
5751b23e MB |
806 | pm_runtime_get_sync(sfb->dev); |
807 | ||
c4bb6ffa | 808 | wincon = readl(sfb->regs + sfb->variant.wincon + (index * 4)); |
ec549a0f BD |
809 | |
810 | switch (blank_mode) { | |
811 | case FB_BLANK_POWERDOWN: | |
812 | wincon &= ~WINCONx_ENWIN; | |
813 | sfb->enabled &= ~(1 << index); | |
814 | /* fall through to FB_BLANK_NORMAL */ | |
815 | ||
816 | case FB_BLANK_NORMAL: | |
817 | /* disable the DMA and display 0x0 (black) */ | |
ff8c9107 | 818 | shadow_protect_win(win, 1); |
ec549a0f | 819 | writel(WINxMAP_MAP | WINxMAP_MAP_COLOUR(0x0), |
c4bb6ffa | 820 | sfb->regs + sfb->variant.winmap + (index * 4)); |
ff8c9107 | 821 | shadow_protect_win(win, 0); |
ec549a0f BD |
822 | break; |
823 | ||
824 | case FB_BLANK_UNBLANK: | |
ff8c9107 | 825 | shadow_protect_win(win, 1); |
c4bb6ffa | 826 | writel(0x0, sfb->regs + sfb->variant.winmap + (index * 4)); |
ff8c9107 | 827 | shadow_protect_win(win, 0); |
ec549a0f BD |
828 | wincon |= WINCONx_ENWIN; |
829 | sfb->enabled |= (1 << index); | |
830 | break; | |
831 | ||
832 | case FB_BLANK_VSYNC_SUSPEND: | |
833 | case FB_BLANK_HSYNC_SUSPEND: | |
834 | default: | |
5751b23e | 835 | pm_runtime_put_sync(sfb->dev); |
ec549a0f BD |
836 | return 1; |
837 | } | |
838 | ||
ff8c9107 | 839 | shadow_protect_win(win, 1); |
c4bb6ffa | 840 | writel(wincon, sfb->regs + sfb->variant.wincon + (index * 4)); |
ec549a0f BD |
841 | |
842 | /* Check the enabled state to see if we need to be running the | |
843 | * main LCD interface, as if there are no active windows then | |
844 | * it is highly likely that we also do not need to output | |
845 | * anything. | |
846 | */ | |
3c582647 TA |
847 | s3c_fb_enable(sfb, sfb->enabled ? 1 : 0); |
848 | shadow_protect_win(win, 0); | |
ec549a0f | 849 | |
5751b23e MB |
850 | pm_runtime_put_sync(sfb->dev); |
851 | ||
3c582647 | 852 | return output_on == sfb->output_on; |
ec549a0f BD |
853 | } |
854 | ||
067b226b PO |
855 | /** |
856 | * s3c_fb_pan_display() - Pan the display. | |
857 | * | |
858 | * Note that the offsets can be written to the device at any time, as their | |
859 | * values are latched at each vsync automatically. This also means that only | |
860 | * the last call to this function will have any effect on next vsync, but | |
861 | * there is no need to sleep waiting for it to prevent tearing. | |
862 | * | |
863 | * @var: The screen information to verify. | |
864 | * @info: The framebuffer device. | |
865 | */ | |
866 | static int s3c_fb_pan_display(struct fb_var_screeninfo *var, | |
867 | struct fb_info *info) | |
868 | { | |
869 | struct s3c_fb_win *win = info->par; | |
870 | struct s3c_fb *sfb = win->parent; | |
871 | void __iomem *buf = sfb->regs + win->index * 8; | |
872 | unsigned int start_boff, end_boff; | |
873 | ||
5751b23e MB |
874 | pm_runtime_get_sync(sfb->dev); |
875 | ||
067b226b PO |
876 | /* Offset in bytes to the start of the displayed area */ |
877 | start_boff = var->yoffset * info->fix.line_length; | |
878 | /* X offset depends on the current bpp */ | |
879 | if (info->var.bits_per_pixel >= 8) { | |
880 | start_boff += var->xoffset * (info->var.bits_per_pixel >> 3); | |
881 | } else { | |
882 | switch (info->var.bits_per_pixel) { | |
883 | case 4: | |
884 | start_boff += var->xoffset >> 1; | |
885 | break; | |
886 | case 2: | |
887 | start_boff += var->xoffset >> 2; | |
888 | break; | |
889 | case 1: | |
890 | start_boff += var->xoffset >> 3; | |
891 | break; | |
892 | default: | |
893 | dev_err(sfb->dev, "invalid bpp\n"); | |
5751b23e | 894 | pm_runtime_put_sync(sfb->dev); |
067b226b PO |
895 | return -EINVAL; |
896 | } | |
897 | } | |
898 | /* Offset in bytes to the end of the displayed area */ | |
d8e7a74b | 899 | end_boff = start_boff + info->var.yres * info->fix.line_length; |
067b226b PO |
900 | |
901 | /* Temporarily turn off per-vsync update from shadow registers until | |
902 | * both start and end addresses are updated to prevent corruption */ | |
f5ec546f | 903 | shadow_protect_win(win, 1); |
067b226b PO |
904 | |
905 | writel(info->fix.smem_start + start_boff, buf + sfb->variant.buf_start); | |
906 | writel(info->fix.smem_start + end_boff, buf + sfb->variant.buf_end); | |
907 | ||
f5ec546f | 908 | shadow_protect_win(win, 0); |
067b226b | 909 | |
5751b23e | 910 | pm_runtime_put_sync(sfb->dev); |
067b226b PO |
911 | return 0; |
912 | } | |
913 | ||
efdc846d PO |
914 | /** |
915 | * s3c_fb_enable_irq() - enable framebuffer interrupts | |
916 | * @sfb: main hardware state | |
917 | */ | |
918 | static void s3c_fb_enable_irq(struct s3c_fb *sfb) | |
919 | { | |
920 | void __iomem *regs = sfb->regs; | |
921 | u32 irq_ctrl_reg; | |
922 | ||
923 | if (!test_and_set_bit(S3C_FB_VSYNC_IRQ_EN, &sfb->irq_flags)) { | |
924 | /* IRQ disabled, enable it */ | |
925 | irq_ctrl_reg = readl(regs + VIDINTCON0); | |
926 | ||
927 | irq_ctrl_reg |= VIDINTCON0_INT_ENABLE; | |
928 | irq_ctrl_reg |= VIDINTCON0_INT_FRAME; | |
929 | ||
930 | irq_ctrl_reg &= ~VIDINTCON0_FRAMESEL0_MASK; | |
931 | irq_ctrl_reg |= VIDINTCON0_FRAMESEL0_VSYNC; | |
932 | irq_ctrl_reg &= ~VIDINTCON0_FRAMESEL1_MASK; | |
933 | irq_ctrl_reg |= VIDINTCON0_FRAMESEL1_NONE; | |
934 | ||
935 | writel(irq_ctrl_reg, regs + VIDINTCON0); | |
936 | } | |
937 | } | |
938 | ||
939 | /** | |
940 | * s3c_fb_disable_irq() - disable framebuffer interrupts | |
941 | * @sfb: main hardware state | |
942 | */ | |
943 | static void s3c_fb_disable_irq(struct s3c_fb *sfb) | |
944 | { | |
945 | void __iomem *regs = sfb->regs; | |
946 | u32 irq_ctrl_reg; | |
947 | ||
948 | if (test_and_clear_bit(S3C_FB_VSYNC_IRQ_EN, &sfb->irq_flags)) { | |
949 | /* IRQ enabled, disable it */ | |
950 | irq_ctrl_reg = readl(regs + VIDINTCON0); | |
951 | ||
952 | irq_ctrl_reg &= ~VIDINTCON0_INT_FRAME; | |
953 | irq_ctrl_reg &= ~VIDINTCON0_INT_ENABLE; | |
954 | ||
955 | writel(irq_ctrl_reg, regs + VIDINTCON0); | |
956 | } | |
957 | } | |
958 | ||
959 | static irqreturn_t s3c_fb_irq(int irq, void *dev_id) | |
960 | { | |
961 | struct s3c_fb *sfb = dev_id; | |
962 | void __iomem *regs = sfb->regs; | |
963 | u32 irq_sts_reg; | |
964 | ||
b07f3bbe JH |
965 | spin_lock(&sfb->slock); |
966 | ||
efdc846d PO |
967 | irq_sts_reg = readl(regs + VIDINTCON1); |
968 | ||
969 | if (irq_sts_reg & VIDINTCON1_INT_FRAME) { | |
970 | ||
971 | /* VSYNC interrupt, accept it */ | |
972 | writel(VIDINTCON1_INT_FRAME, regs + VIDINTCON1); | |
973 | ||
974 | sfb->vsync_info.count++; | |
975 | wake_up_interruptible(&sfb->vsync_info.wait); | |
976 | } | |
977 | ||
978 | /* We only support waiting for VSYNC for now, so it's safe | |
979 | * to always disable irqs here. | |
980 | */ | |
981 | s3c_fb_disable_irq(sfb); | |
982 | ||
b07f3bbe | 983 | spin_unlock(&sfb->slock); |
efdc846d PO |
984 | return IRQ_HANDLED; |
985 | } | |
986 | ||
987 | /** | |
988 | * s3c_fb_wait_for_vsync() - sleep until next VSYNC interrupt or timeout | |
989 | * @sfb: main hardware state | |
990 | * @crtc: head index. | |
991 | */ | |
992 | static int s3c_fb_wait_for_vsync(struct s3c_fb *sfb, u32 crtc) | |
993 | { | |
994 | unsigned long count; | |
995 | int ret; | |
996 | ||
997 | if (crtc != 0) | |
998 | return -ENODEV; | |
999 | ||
5751b23e MB |
1000 | pm_runtime_get_sync(sfb->dev); |
1001 | ||
efdc846d PO |
1002 | count = sfb->vsync_info.count; |
1003 | s3c_fb_enable_irq(sfb); | |
1004 | ret = wait_event_interruptible_timeout(sfb->vsync_info.wait, | |
1005 | count != sfb->vsync_info.count, | |
1006 | msecs_to_jiffies(VSYNC_TIMEOUT_MSEC)); | |
5751b23e MB |
1007 | |
1008 | pm_runtime_put_sync(sfb->dev); | |
1009 | ||
efdc846d PO |
1010 | if (ret == 0) |
1011 | return -ETIMEDOUT; | |
1012 | ||
1013 | return 0; | |
1014 | } | |
1015 | ||
1016 | static int s3c_fb_ioctl(struct fb_info *info, unsigned int cmd, | |
1017 | unsigned long arg) | |
1018 | { | |
1019 | struct s3c_fb_win *win = info->par; | |
1020 | struct s3c_fb *sfb = win->parent; | |
1021 | int ret; | |
1022 | u32 crtc; | |
1023 | ||
1024 | switch (cmd) { | |
1025 | case FBIO_WAITFORVSYNC: | |
1026 | if (get_user(crtc, (u32 __user *)arg)) { | |
1027 | ret = -EFAULT; | |
1028 | break; | |
1029 | } | |
1030 | ||
1031 | ret = s3c_fb_wait_for_vsync(sfb, crtc); | |
1032 | break; | |
1033 | default: | |
1034 | ret = -ENOTTY; | |
1035 | } | |
1036 | ||
1037 | return ret; | |
1038 | } | |
1039 | ||
ec549a0f BD |
1040 | static struct fb_ops s3c_fb_ops = { |
1041 | .owner = THIS_MODULE, | |
1042 | .fb_check_var = s3c_fb_check_var, | |
1043 | .fb_set_par = s3c_fb_set_par, | |
1044 | .fb_blank = s3c_fb_blank, | |
1045 | .fb_setcolreg = s3c_fb_setcolreg, | |
1046 | .fb_fillrect = cfb_fillrect, | |
1047 | .fb_copyarea = cfb_copyarea, | |
1048 | .fb_imageblit = cfb_imageblit, | |
067b226b | 1049 | .fb_pan_display = s3c_fb_pan_display, |
efdc846d | 1050 | .fb_ioctl = s3c_fb_ioctl, |
ec549a0f BD |
1051 | }; |
1052 | ||
2bb567a3 MC |
1053 | /** |
1054 | * s3c_fb_missing_pixclock() - calculates pixel clock | |
1055 | * @mode: The video mode to change. | |
1056 | * | |
1057 | * Calculate the pixel clock when none has been given through platform data. | |
1058 | */ | |
2293d620 | 1059 | static void s3c_fb_missing_pixclock(struct fb_videomode *mode) |
2bb567a3 MC |
1060 | { |
1061 | u64 pixclk = 1000000000000ULL; | |
1062 | u32 div; | |
1063 | ||
1064 | div = mode->left_margin + mode->hsync_len + mode->right_margin + | |
1065 | mode->xres; | |
1066 | div *= mode->upper_margin + mode->vsync_len + mode->lower_margin + | |
1067 | mode->yres; | |
1068 | div *= mode->refresh ? : 60; | |
1069 | ||
1070 | do_div(pixclk, div); | |
1071 | ||
1072 | mode->pixclock = pixclk; | |
1073 | } | |
1074 | ||
ec549a0f BD |
1075 | /** |
1076 | * s3c_fb_alloc_memory() - allocate display memory for framebuffer window | |
1077 | * @sfb: The base resources for the hardware. | |
1078 | * @win: The window to initialise memory for. | |
1079 | * | |
1080 | * Allocate memory for the given framebuffer. | |
1081 | */ | |
1082 | static int __devinit s3c_fb_alloc_memory(struct s3c_fb *sfb, | |
1083 | struct s3c_fb_win *win) | |
1084 | { | |
1085 | struct s3c_fb_pd_win *windata = win->windata; | |
1086 | unsigned int real_size, virt_size, size; | |
1087 | struct fb_info *fbi = win->fbinfo; | |
1088 | dma_addr_t map_dma; | |
1089 | ||
1090 | dev_dbg(sfb->dev, "allocating memory for display\n"); | |
1091 | ||
a4196feb | 1092 | real_size = windata->xres * windata->yres; |
ec549a0f BD |
1093 | virt_size = windata->virtual_x * windata->virtual_y; |
1094 | ||
1095 | dev_dbg(sfb->dev, "real_size=%u (%u.%u), virt_size=%u (%u.%u)\n", | |
a4196feb | 1096 | real_size, windata->xres, windata->yres, |
ec549a0f BD |
1097 | virt_size, windata->virtual_x, windata->virtual_y); |
1098 | ||
1099 | size = (real_size > virt_size) ? real_size : virt_size; | |
1100 | size *= (windata->max_bpp > 16) ? 32 : windata->max_bpp; | |
1101 | size /= 8; | |
1102 | ||
1103 | fbi->fix.smem_len = size; | |
1104 | size = PAGE_ALIGN(size); | |
1105 | ||
1106 | dev_dbg(sfb->dev, "want %u bytes for window\n", size); | |
1107 | ||
1108 | fbi->screen_base = dma_alloc_writecombine(sfb->dev, size, | |
1109 | &map_dma, GFP_KERNEL); | |
1110 | if (!fbi->screen_base) | |
1111 | return -ENOMEM; | |
1112 | ||
1113 | dev_dbg(sfb->dev, "mapped %x to %p\n", | |
1114 | (unsigned int)map_dma, fbi->screen_base); | |
1115 | ||
1116 | memset(fbi->screen_base, 0x0, size); | |
1117 | fbi->fix.smem_start = map_dma; | |
1118 | ||
1119 | return 0; | |
1120 | } | |
1121 | ||
1122 | /** | |
1123 | * s3c_fb_free_memory() - free the display memory for the given window | |
1124 | * @sfb: The base resources for the hardware. | |
1125 | * @win: The window to free the display memory for. | |
1126 | * | |
1127 | * Free the display memory allocated by s3c_fb_alloc_memory(). | |
1128 | */ | |
1129 | static void s3c_fb_free_memory(struct s3c_fb *sfb, struct s3c_fb_win *win) | |
1130 | { | |
1131 | struct fb_info *fbi = win->fbinfo; | |
1132 | ||
cd7d7e02 PO |
1133 | if (fbi->screen_base) |
1134 | dma_free_writecombine(sfb->dev, PAGE_ALIGN(fbi->fix.smem_len), | |
ec549a0f BD |
1135 | fbi->screen_base, fbi->fix.smem_start); |
1136 | } | |
1137 | ||
1138 | /** | |
1139 | * s3c_fb_release_win() - release resources for a framebuffer window. | |
1140 | * @win: The window to cleanup the resources for. | |
1141 | * | |
1142 | * Release the resources that where claimed for the hardware window, | |
1143 | * such as the framebuffer instance and any memory claimed for it. | |
1144 | */ | |
1145 | static void s3c_fb_release_win(struct s3c_fb *sfb, struct s3c_fb_win *win) | |
1146 | { | |
04ab9ef9 PO |
1147 | u32 data; |
1148 | ||
ddc518d9 | 1149 | if (win->fbinfo) { |
04ab9ef9 PO |
1150 | if (sfb->variant.has_shadowcon) { |
1151 | data = readl(sfb->regs + SHADOWCON); | |
1152 | data &= ~SHADOWCON_CHx_ENABLE(win->index); | |
1153 | data &= ~SHADOWCON_CHx_LOCAL_ENABLE(win->index); | |
1154 | writel(data, sfb->regs + SHADOWCON); | |
1155 | } | |
ddc518d9 | 1156 | unregister_framebuffer(win->fbinfo); |
cd7d7e02 PO |
1157 | if (win->fbinfo->cmap.len) |
1158 | fb_dealloc_cmap(&win->fbinfo->cmap); | |
ddc518d9 KH |
1159 | s3c_fb_free_memory(sfb, win); |
1160 | framebuffer_release(win->fbinfo); | |
1161 | } | |
ec549a0f BD |
1162 | } |
1163 | ||
1164 | /** | |
1165 | * s3c_fb_probe_win() - register an hardware window | |
1166 | * @sfb: The base resources for the hardware | |
50a5503a | 1167 | * @variant: The variant information for this window. |
ec549a0f BD |
1168 | * @res: Pointer to where to place the resultant window. |
1169 | * | |
1170 | * Allocate and do the basic initialisation for one of the hardware's graphics | |
1171 | * windows. | |
1172 | */ | |
1173 | static int __devinit s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no, | |
50a5503a | 1174 | struct s3c_fb_win_variant *variant, |
ec549a0f BD |
1175 | struct s3c_fb_win **res) |
1176 | { | |
1177 | struct fb_var_screeninfo *var; | |
a4196feb | 1178 | struct fb_videomode initmode; |
ec549a0f BD |
1179 | struct s3c_fb_pd_win *windata; |
1180 | struct s3c_fb_win *win; | |
1181 | struct fb_info *fbinfo; | |
1182 | int palette_size; | |
1183 | int ret; | |
1184 | ||
c4bb6ffa | 1185 | dev_dbg(sfb->dev, "probing window %d, variant %p\n", win_no, variant); |
ec549a0f | 1186 | |
efdc846d PO |
1187 | init_waitqueue_head(&sfb->vsync_info.wait); |
1188 | ||
50a5503a | 1189 | palette_size = variant->palette_sz * 4; |
ec549a0f BD |
1190 | |
1191 | fbinfo = framebuffer_alloc(sizeof(struct s3c_fb_win) + | |
1192 | palette_size * sizeof(u32), sfb->dev); | |
1193 | if (!fbinfo) { | |
1194 | dev_err(sfb->dev, "failed to allocate framebuffer\n"); | |
1195 | return -ENOENT; | |
1196 | } | |
1197 | ||
1198 | windata = sfb->pdata->win[win_no]; | |
a4196feb | 1199 | initmode = *sfb->pdata->vtiming; |
ec549a0f BD |
1200 | |
1201 | WARN_ON(windata->max_bpp == 0); | |
a4196feb TA |
1202 | WARN_ON(windata->xres == 0); |
1203 | WARN_ON(windata->yres == 0); | |
ec549a0f BD |
1204 | |
1205 | win = fbinfo->par; | |
cd7d7e02 | 1206 | *res = win; |
ec549a0f | 1207 | var = &fbinfo->var; |
50a5503a | 1208 | win->variant = *variant; |
ec549a0f BD |
1209 | win->fbinfo = fbinfo; |
1210 | win->parent = sfb; | |
1211 | win->windata = windata; | |
1212 | win->index = win_no; | |
1213 | win->palette_buffer = (u32 *)(win + 1); | |
1214 | ||
1215 | ret = s3c_fb_alloc_memory(sfb, win); | |
1216 | if (ret) { | |
1217 | dev_err(sfb->dev, "failed to allocate display memory\n"); | |
ddc518d9 | 1218 | return ret; |
ec549a0f BD |
1219 | } |
1220 | ||
1221 | /* setup the r/b/g positions for the window's palette */ | |
bc2da1b6 BD |
1222 | if (win->variant.palette_16bpp) { |
1223 | /* Set RGB 5:6:5 as default */ | |
1224 | win->palette.r.offset = 11; | |
1225 | win->palette.r.length = 5; | |
1226 | win->palette.g.offset = 5; | |
1227 | win->palette.g.length = 6; | |
1228 | win->palette.b.offset = 0; | |
1229 | win->palette.b.length = 5; | |
1230 | ||
1231 | } else { | |
1232 | /* Set 8bpp or 8bpp and 1bit alpha */ | |
1233 | win->palette.r.offset = 16; | |
1234 | win->palette.r.length = 8; | |
1235 | win->palette.g.offset = 8; | |
1236 | win->palette.g.length = 8; | |
1237 | win->palette.b.offset = 0; | |
1238 | win->palette.b.length = 8; | |
1239 | } | |
ec549a0f BD |
1240 | |
1241 | /* setup the initial video mode from the window */ | |
a4196feb TA |
1242 | initmode.xres = windata->xres; |
1243 | initmode.yres = windata->yres; | |
1244 | fb_videomode_to_var(&fbinfo->var, &initmode); | |
ec549a0f BD |
1245 | |
1246 | fbinfo->fix.type = FB_TYPE_PACKED_PIXELS; | |
1247 | fbinfo->fix.accel = FB_ACCEL_NONE; | |
1248 | fbinfo->var.activate = FB_ACTIVATE_NOW; | |
1249 | fbinfo->var.vmode = FB_VMODE_NONINTERLACED; | |
1250 | fbinfo->var.bits_per_pixel = windata->default_bpp; | |
1251 | fbinfo->fbops = &s3c_fb_ops; | |
1252 | fbinfo->flags = FBINFO_FLAG_DEFAULT; | |
1253 | fbinfo->pseudo_palette = &win->pseudo_palette; | |
1254 | ||
1255 | /* prepare to actually start the framebuffer */ | |
1256 | ||
1257 | ret = s3c_fb_check_var(&fbinfo->var, fbinfo); | |
1258 | if (ret < 0) { | |
1259 | dev_err(sfb->dev, "check_var failed on initial video params\n"); | |
ddc518d9 | 1260 | return ret; |
ec549a0f BD |
1261 | } |
1262 | ||
1263 | /* create initial colour map */ | |
1264 | ||
50a5503a | 1265 | ret = fb_alloc_cmap(&fbinfo->cmap, win->variant.palette_sz, 1); |
ec549a0f BD |
1266 | if (ret == 0) |
1267 | fb_set_cmap(&fbinfo->cmap, fbinfo); | |
1268 | else | |
1269 | dev_err(sfb->dev, "failed to allocate fb cmap\n"); | |
1270 | ||
1271 | s3c_fb_set_par(fbinfo); | |
1272 | ||
1273 | dev_dbg(sfb->dev, "about to register framebuffer\n"); | |
1274 | ||
1275 | /* run the check_var and set_par on our configuration. */ | |
1276 | ||
1277 | ret = register_framebuffer(fbinfo); | |
1278 | if (ret < 0) { | |
1279 | dev_err(sfb->dev, "failed to register framebuffer\n"); | |
ddc518d9 | 1280 | return ret; |
ec549a0f BD |
1281 | } |
1282 | ||
ec549a0f BD |
1283 | dev_info(sfb->dev, "window %d: fb %s\n", win_no, fbinfo->fix.id); |
1284 | ||
1285 | return 0; | |
ec549a0f BD |
1286 | } |
1287 | ||
a4196feb TA |
1288 | /** |
1289 | * s3c_fb_set_rgb_timing() - set video timing for rgb interface. | |
1290 | * @sfb: The base resources for the hardware. | |
1291 | * | |
1292 | * Set horizontal and vertical lcd rgb interface timing. | |
1293 | */ | |
1294 | static void s3c_fb_set_rgb_timing(struct s3c_fb *sfb) | |
1295 | { | |
1296 | struct fb_videomode *vmode = sfb->pdata->vtiming; | |
1297 | void __iomem *regs = sfb->regs; | |
1298 | int clkdiv; | |
1299 | u32 data; | |
1300 | ||
1301 | if (!vmode->pixclock) | |
1302 | s3c_fb_missing_pixclock(vmode); | |
1303 | ||
1304 | clkdiv = s3c_fb_calc_pixclk(sfb, vmode->pixclock); | |
1305 | ||
1306 | data = sfb->pdata->vidcon0; | |
1307 | data &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR); | |
1308 | ||
1309 | if (clkdiv > 1) | |
1310 | data |= VIDCON0_CLKVAL_F(clkdiv-1) | VIDCON0_CLKDIR; | |
1311 | else | |
1312 | data &= ~VIDCON0_CLKDIR; /* 1:1 clock */ | |
1313 | ||
1314 | if (sfb->variant.is_2443) | |
1315 | data |= (1 << 5); | |
1316 | writel(data, regs + VIDCON0); | |
1317 | ||
1318 | data = VIDTCON0_VBPD(vmode->upper_margin - 1) | | |
1319 | VIDTCON0_VFPD(vmode->lower_margin - 1) | | |
1320 | VIDTCON0_VSPW(vmode->vsync_len - 1); | |
1321 | writel(data, regs + sfb->variant.vidtcon); | |
1322 | ||
1323 | data = VIDTCON1_HBPD(vmode->left_margin - 1) | | |
1324 | VIDTCON1_HFPD(vmode->right_margin - 1) | | |
1325 | VIDTCON1_HSPW(vmode->hsync_len - 1); | |
1326 | writel(data, regs + sfb->variant.vidtcon + 4); | |
1327 | ||
1328 | data = VIDTCON2_LINEVAL(vmode->yres - 1) | | |
1329 | VIDTCON2_HOZVAL(vmode->xres - 1) | | |
1330 | VIDTCON2_LINEVAL_E(vmode->yres - 1) | | |
1331 | VIDTCON2_HOZVAL_E(vmode->xres - 1); | |
1332 | writel(data, regs + sfb->variant.vidtcon + 8); | |
1333 | } | |
1334 | ||
ec549a0f BD |
1335 | /** |
1336 | * s3c_fb_clear_win() - clear hardware window registers. | |
1337 | * @sfb: The base resources for the hardware. | |
1338 | * @win: The window to process. | |
1339 | * | |
1340 | * Reset the specific window registers to a known state. | |
1341 | */ | |
1342 | static void s3c_fb_clear_win(struct s3c_fb *sfb, int win) | |
1343 | { | |
1344 | void __iomem *regs = sfb->regs; | |
a8bdabca | 1345 | u32 reg; |
ec549a0f | 1346 | |
c4bb6ffa BD |
1347 | writel(0, regs + sfb->variant.wincon + (win * 4)); |
1348 | writel(0, regs + VIDOSD_A(win, sfb->variant)); | |
1349 | writel(0, regs + VIDOSD_B(win, sfb->variant)); | |
1350 | writel(0, regs + VIDOSD_C(win, sfb->variant)); | |
ecd57ae2 JH |
1351 | |
1352 | if (sfb->variant.has_shadowcon) { | |
1353 | reg = readl(sfb->regs + SHADOWCON); | |
1354 | reg &= ~(SHADOWCON_WINx_PROTECT(win) | | |
1355 | SHADOWCON_CHx_ENABLE(win) | | |
1356 | SHADOWCON_CHx_LOCAL_ENABLE(win)); | |
1357 | writel(reg, sfb->regs + SHADOWCON); | |
1358 | } | |
ec549a0f BD |
1359 | } |
1360 | ||
1361 | static int __devinit s3c_fb_probe(struct platform_device *pdev) | |
1362 | { | |
b73a21fc | 1363 | const struct platform_device_id *platid; |
50a5503a | 1364 | struct s3c_fb_driverdata *fbdrv; |
ec549a0f BD |
1365 | struct device *dev = &pdev->dev; |
1366 | struct s3c_fb_platdata *pd; | |
1367 | struct s3c_fb *sfb; | |
1368 | struct resource *res; | |
1369 | int win; | |
1370 | int ret = 0; | |
d8b97db4 | 1371 | u32 reg; |
ec549a0f | 1372 | |
b73a21fc JH |
1373 | platid = platform_get_device_id(pdev); |
1374 | fbdrv = (struct s3c_fb_driverdata *)platid->driver_data; | |
50a5503a BD |
1375 | |
1376 | if (fbdrv->variant.nr_windows > S3C_FB_MAX_WIN) { | |
1377 | dev_err(dev, "too many windows, cannot attach\n"); | |
1378 | return -EINVAL; | |
1379 | } | |
1380 | ||
ec549a0f BD |
1381 | pd = pdev->dev.platform_data; |
1382 | if (!pd) { | |
1383 | dev_err(dev, "no platform data specified\n"); | |
1384 | return -EINVAL; | |
1385 | } | |
1386 | ||
857a8df9 | 1387 | sfb = devm_kzalloc(dev, sizeof(struct s3c_fb), GFP_KERNEL); |
ec549a0f BD |
1388 | if (!sfb) { |
1389 | dev_err(dev, "no memory for framebuffers\n"); | |
1390 | return -ENOMEM; | |
1391 | } | |
1392 | ||
c4bb6ffa BD |
1393 | dev_dbg(dev, "allocate new framebuffer %p\n", sfb); |
1394 | ||
ec549a0f BD |
1395 | sfb->dev = dev; |
1396 | sfb->pdata = pd; | |
50a5503a | 1397 | sfb->variant = fbdrv->variant; |
ec549a0f | 1398 | |
b07f3bbe JH |
1399 | spin_lock_init(&sfb->slock); |
1400 | ||
ec549a0f BD |
1401 | sfb->bus_clk = clk_get(dev, "lcd"); |
1402 | if (IS_ERR(sfb->bus_clk)) { | |
1403 | dev_err(dev, "failed to get bus clock\n"); | |
942b8d05 | 1404 | ret = PTR_ERR(sfb->bus_clk); |
ec549a0f BD |
1405 | goto err_sfb; |
1406 | } | |
1407 | ||
1408 | clk_enable(sfb->bus_clk); | |
1409 | ||
b5480ed7 JH |
1410 | if (!sfb->variant.has_clksel) { |
1411 | sfb->lcd_clk = clk_get(dev, "sclk_fimd"); | |
1412 | if (IS_ERR(sfb->lcd_clk)) { | |
1413 | dev_err(dev, "failed to get lcd clock\n"); | |
1414 | ret = PTR_ERR(sfb->lcd_clk); | |
1415 | goto err_bus_clk; | |
1416 | } | |
1417 | ||
1418 | clk_enable(sfb->lcd_clk); | |
1419 | } | |
1420 | ||
4959212c JH |
1421 | pm_runtime_enable(sfb->dev); |
1422 | ||
ec549a0f BD |
1423 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1424 | if (!res) { | |
1425 | dev_err(dev, "failed to find registers\n"); | |
1426 | ret = -ENOENT; | |
b5480ed7 | 1427 | goto err_lcd_clk; |
ec549a0f BD |
1428 | } |
1429 | ||
857a8df9 | 1430 | sfb->regs = devm_request_and_ioremap(dev, res); |
ec549a0f BD |
1431 | if (!sfb->regs) { |
1432 | dev_err(dev, "failed to map registers\n"); | |
1433 | ret = -ENXIO; | |
857a8df9 | 1434 | goto err_lcd_clk; |
ec549a0f BD |
1435 | } |
1436 | ||
efdc846d PO |
1437 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
1438 | if (!res) { | |
1439 | dev_err(dev, "failed to acquire irq resource\n"); | |
1440 | ret = -ENOENT; | |
857a8df9 | 1441 | goto err_lcd_clk; |
efdc846d PO |
1442 | } |
1443 | sfb->irq_no = res->start; | |
327e2768 | 1444 | ret = devm_request_irq(dev, sfb->irq_no, s3c_fb_irq, |
efdc846d PO |
1445 | 0, "s3c_fb", sfb); |
1446 | if (ret) { | |
1447 | dev_err(dev, "irq request failed\n"); | |
857a8df9 | 1448 | goto err_lcd_clk; |
efdc846d PO |
1449 | } |
1450 | ||
ec549a0f BD |
1451 | dev_dbg(dev, "got resources (regs %p), probing windows\n", sfb->regs); |
1452 | ||
4959212c JH |
1453 | platform_set_drvdata(pdev, sfb); |
1454 | pm_runtime_get_sync(sfb->dev); | |
1455 | ||
ec549a0f BD |
1456 | /* setup gpio and output polarity controls */ |
1457 | ||
1458 | pd->setup_gpio(); | |
1459 | ||
1460 | writel(pd->vidcon1, sfb->regs + VIDCON1); | |
1461 | ||
d8b97db4 JH |
1462 | /* set video clock running at under-run */ |
1463 | if (sfb->variant.has_fixvclk) { | |
1464 | reg = readl(sfb->regs + VIDCON1); | |
1465 | reg &= ~VIDCON1_VCLK_MASK; | |
1466 | reg |= VIDCON1_VCLK_RUN; | |
1467 | writel(reg, sfb->regs + VIDCON1); | |
1468 | } | |
1469 | ||
ec549a0f BD |
1470 | /* zero all windows before we do anything */ |
1471 | ||
50a5503a | 1472 | for (win = 0; win < fbdrv->variant.nr_windows; win++) |
ec549a0f BD |
1473 | s3c_fb_clear_win(sfb, win); |
1474 | ||
94947037 | 1475 | /* initialise colour key controls */ |
50a5503a | 1476 | for (win = 0; win < (fbdrv->variant.nr_windows - 1); win++) { |
c4bb6ffa BD |
1477 | void __iomem *regs = sfb->regs + sfb->variant.keycon; |
1478 | ||
1479 | regs += (win * 8); | |
1480 | writel(0xffffff, regs + WKEYCON0); | |
1481 | writel(0xffffff, regs + WKEYCON1); | |
94947037 BD |
1482 | } |
1483 | ||
a4196feb TA |
1484 | s3c_fb_set_rgb_timing(sfb); |
1485 | ||
ec549a0f BD |
1486 | /* we have the register setup, start allocating framebuffers */ |
1487 | ||
50a5503a | 1488 | for (win = 0; win < fbdrv->variant.nr_windows; win++) { |
ec549a0f BD |
1489 | if (!pd->win[win]) |
1490 | continue; | |
1491 | ||
50a5503a BD |
1492 | ret = s3c_fb_probe_win(sfb, win, fbdrv->win[win], |
1493 | &sfb->windows[win]); | |
ec549a0f BD |
1494 | if (ret < 0) { |
1495 | dev_err(dev, "failed to create window %d\n", win); | |
1496 | for (; win >= 0; win--) | |
1497 | s3c_fb_release_win(sfb, sfb->windows[win]); | |
3500b0be | 1498 | goto err_pm_runtime; |
ec549a0f BD |
1499 | } |
1500 | } | |
1501 | ||
1502 | platform_set_drvdata(pdev, sfb); | |
fe05f8b1 | 1503 | pm_runtime_put_sync(sfb->dev); |
ec549a0f BD |
1504 | |
1505 | return 0; | |
1506 | ||
3500b0be MB |
1507 | err_pm_runtime: |
1508 | pm_runtime_put_sync(sfb->dev); | |
efdc846d | 1509 | |
b5480ed7 | 1510 | err_lcd_clk: |
3500b0be MB |
1511 | pm_runtime_disable(sfb->dev); |
1512 | ||
b5480ed7 JH |
1513 | if (!sfb->variant.has_clksel) { |
1514 | clk_disable(sfb->lcd_clk); | |
1515 | clk_put(sfb->lcd_clk); | |
1516 | } | |
1517 | ||
1518 | err_bus_clk: | |
ec549a0f BD |
1519 | clk_disable(sfb->bus_clk); |
1520 | clk_put(sfb->bus_clk); | |
1521 | ||
1522 | err_sfb: | |
ec549a0f BD |
1523 | return ret; |
1524 | } | |
1525 | ||
1526 | /** | |
1527 | * s3c_fb_remove() - Cleanup on module finalisation | |
1528 | * @pdev: The platform device we are bound to. | |
1529 | * | |
1530 | * Shutdown and then release all the resources that the driver allocated | |
1531 | * on initialisation. | |
1532 | */ | |
1533 | static int __devexit s3c_fb_remove(struct platform_device *pdev) | |
1534 | { | |
1535 | struct s3c_fb *sfb = platform_get_drvdata(pdev); | |
1536 | int win; | |
1537 | ||
fe05f8b1 MB |
1538 | pm_runtime_get_sync(sfb->dev); |
1539 | ||
c42b110c | 1540 | for (win = 0; win < S3C_FB_MAX_WIN; win++) |
17663e59 MS |
1541 | if (sfb->windows[win]) |
1542 | s3c_fb_release_win(sfb, sfb->windows[win]); | |
ec549a0f | 1543 | |
b5480ed7 JH |
1544 | if (!sfb->variant.has_clksel) { |
1545 | clk_disable(sfb->lcd_clk); | |
1546 | clk_put(sfb->lcd_clk); | |
1547 | } | |
1548 | ||
ec549a0f BD |
1549 | clk_disable(sfb->bus_clk); |
1550 | clk_put(sfb->bus_clk); | |
1551 | ||
4959212c JH |
1552 | pm_runtime_put_sync(sfb->dev); |
1553 | pm_runtime_disable(sfb->dev); | |
1554 | ||
ec549a0f BD |
1555 | return 0; |
1556 | } | |
1557 | ||
f4f51473 | 1558 | #ifdef CONFIG_PM_SLEEP |
4959212c JH |
1559 | static int s3c_fb_suspend(struct device *dev) |
1560 | { | |
1561 | struct platform_device *pdev = to_platform_device(dev); | |
1562 | struct s3c_fb *sfb = platform_get_drvdata(pdev); | |
1563 | struct s3c_fb_win *win; | |
1564 | int win_no; | |
1565 | ||
4e0dd49d JH |
1566 | pm_runtime_get_sync(sfb->dev); |
1567 | ||
4959212c JH |
1568 | for (win_no = S3C_FB_MAX_WIN - 1; win_no >= 0; win_no--) { |
1569 | win = sfb->windows[win_no]; | |
1570 | if (!win) | |
1571 | continue; | |
1572 | ||
1573 | /* use the blank function to push into power-down */ | |
1574 | s3c_fb_blank(FB_BLANK_POWERDOWN, win->fbinfo); | |
1575 | } | |
1576 | ||
b5480ed7 JH |
1577 | if (!sfb->variant.has_clksel) |
1578 | clk_disable(sfb->lcd_clk); | |
1579 | ||
4959212c | 1580 | clk_disable(sfb->bus_clk); |
4e0dd49d JH |
1581 | |
1582 | pm_runtime_put_sync(sfb->dev); | |
1583 | ||
4959212c JH |
1584 | return 0; |
1585 | } | |
1586 | ||
1587 | static int s3c_fb_resume(struct device *dev) | |
1588 | { | |
1589 | struct platform_device *pdev = to_platform_device(dev); | |
1590 | struct s3c_fb *sfb = platform_get_drvdata(pdev); | |
1591 | struct s3c_fb_platdata *pd = sfb->pdata; | |
1592 | struct s3c_fb_win *win; | |
1593 | int win_no; | |
d8b97db4 | 1594 | u32 reg; |
4959212c | 1595 | |
4e0dd49d JH |
1596 | pm_runtime_get_sync(sfb->dev); |
1597 | ||
4959212c JH |
1598 | clk_enable(sfb->bus_clk); |
1599 | ||
b5480ed7 JH |
1600 | if (!sfb->variant.has_clksel) |
1601 | clk_enable(sfb->lcd_clk); | |
1602 | ||
6aa96811 JH |
1603 | /* setup gpio and output polarity controls */ |
1604 | pd->setup_gpio(); | |
4959212c JH |
1605 | writel(pd->vidcon1, sfb->regs + VIDCON1); |
1606 | ||
d8b97db4 JH |
1607 | /* set video clock running at under-run */ |
1608 | if (sfb->variant.has_fixvclk) { | |
1609 | reg = readl(sfb->regs + VIDCON1); | |
1610 | reg &= ~VIDCON1_VCLK_MASK; | |
1611 | reg |= VIDCON1_VCLK_RUN; | |
1612 | writel(reg, sfb->regs + VIDCON1); | |
1613 | } | |
1614 | ||
4959212c JH |
1615 | /* zero all windows before we do anything */ |
1616 | for (win_no = 0; win_no < sfb->variant.nr_windows; win_no++) | |
1617 | s3c_fb_clear_win(sfb, win_no); | |
1618 | ||
1619 | for (win_no = 0; win_no < sfb->variant.nr_windows - 1; win_no++) { | |
1620 | void __iomem *regs = sfb->regs + sfb->variant.keycon; | |
ff8c9107 JH |
1621 | win = sfb->windows[win_no]; |
1622 | if (!win) | |
1623 | continue; | |
4959212c | 1624 | |
ff8c9107 | 1625 | shadow_protect_win(win, 1); |
4959212c JH |
1626 | regs += (win_no * 8); |
1627 | writel(0xffffff, regs + WKEYCON0); | |
1628 | writel(0xffffff, regs + WKEYCON1); | |
ff8c9107 | 1629 | shadow_protect_win(win, 0); |
4959212c JH |
1630 | } |
1631 | ||
a4196feb TA |
1632 | s3c_fb_set_rgb_timing(sfb); |
1633 | ||
4959212c JH |
1634 | /* restore framebuffers */ |
1635 | for (win_no = 0; win_no < S3C_FB_MAX_WIN; win_no++) { | |
1636 | win = sfb->windows[win_no]; | |
1637 | if (!win) | |
1638 | continue; | |
1639 | ||
1640 | dev_dbg(&pdev->dev, "resuming window %d\n", win_no); | |
1641 | s3c_fb_set_par(win->fbinfo); | |
1642 | } | |
1643 | ||
4e0dd49d JH |
1644 | pm_runtime_put_sync(sfb->dev); |
1645 | ||
4959212c JH |
1646 | return 0; |
1647 | } | |
ec549a0f BD |
1648 | #endif |
1649 | ||
f4f51473 MB |
1650 | #ifdef CONFIG_PM_RUNTIME |
1651 | static int s3c_fb_runtime_suspend(struct device *dev) | |
1652 | { | |
1653 | struct platform_device *pdev = to_platform_device(dev); | |
1654 | struct s3c_fb *sfb = platform_get_drvdata(pdev); | |
1655 | ||
1656 | if (!sfb->variant.has_clksel) | |
1657 | clk_disable(sfb->lcd_clk); | |
1658 | ||
1659 | clk_disable(sfb->bus_clk); | |
1660 | ||
1661 | return 0; | |
1662 | } | |
1663 | ||
1664 | static int s3c_fb_runtime_resume(struct device *dev) | |
1665 | { | |
1666 | struct platform_device *pdev = to_platform_device(dev); | |
1667 | struct s3c_fb *sfb = platform_get_drvdata(pdev); | |
1668 | struct s3c_fb_platdata *pd = sfb->pdata; | |
1669 | ||
1670 | clk_enable(sfb->bus_clk); | |
1671 | ||
1672 | if (!sfb->variant.has_clksel) | |
1673 | clk_enable(sfb->lcd_clk); | |
1674 | ||
1675 | /* setup gpio and output polarity controls */ | |
1676 | pd->setup_gpio(); | |
1677 | writel(pd->vidcon1, sfb->regs + VIDCON1); | |
1678 | ||
1679 | return 0; | |
1680 | } | |
1681 | #endif | |
50a5503a BD |
1682 | |
1683 | #define VALID_BPP124 (VALID_BPP(1) | VALID_BPP(2) | VALID_BPP(4)) | |
1684 | #define VALID_BPP1248 (VALID_BPP124 | VALID_BPP(8)) | |
1685 | ||
8cfdcb23 | 1686 | static struct s3c_fb_win_variant s3c_fb_data_64xx_wins[] = { |
50a5503a BD |
1687 | [0] = { |
1688 | .has_osd_c = 1, | |
f676ec2a | 1689 | .osd_size_off = 0x8, |
50a5503a | 1690 | .palette_sz = 256, |
cd74ebaf JH |
1691 | .valid_bpp = (VALID_BPP1248 | VALID_BPP(16) | |
1692 | VALID_BPP(18) | VALID_BPP(24)), | |
50a5503a BD |
1693 | }, |
1694 | [1] = { | |
1695 | .has_osd_c = 1, | |
1696 | .has_osd_d = 1, | |
c9d503e9 | 1697 | .osd_size_off = 0xc, |
f676ec2a | 1698 | .has_osd_alpha = 1, |
50a5503a BD |
1699 | .palette_sz = 256, |
1700 | .valid_bpp = (VALID_BPP1248 | VALID_BPP(16) | | |
1701 | VALID_BPP(18) | VALID_BPP(19) | | |
cd74ebaf JH |
1702 | VALID_BPP(24) | VALID_BPP(25) | |
1703 | VALID_BPP(28)), | |
50a5503a BD |
1704 | }, |
1705 | [2] = { | |
1706 | .has_osd_c = 1, | |
1707 | .has_osd_d = 1, | |
c9d503e9 | 1708 | .osd_size_off = 0xc, |
f676ec2a | 1709 | .has_osd_alpha = 1, |
50a5503a BD |
1710 | .palette_sz = 16, |
1711 | .palette_16bpp = 1, | |
1712 | .valid_bpp = (VALID_BPP1248 | VALID_BPP(16) | | |
1713 | VALID_BPP(18) | VALID_BPP(19) | | |
cd74ebaf JH |
1714 | VALID_BPP(24) | VALID_BPP(25) | |
1715 | VALID_BPP(28)), | |
50a5503a BD |
1716 | }, |
1717 | [3] = { | |
1718 | .has_osd_c = 1, | |
f676ec2a | 1719 | .has_osd_alpha = 1, |
50a5503a BD |
1720 | .palette_sz = 16, |
1721 | .palette_16bpp = 1, | |
1722 | .valid_bpp = (VALID_BPP124 | VALID_BPP(16) | | |
1723 | VALID_BPP(18) | VALID_BPP(19) | | |
cd74ebaf JH |
1724 | VALID_BPP(24) | VALID_BPP(25) | |
1725 | VALID_BPP(28)), | |
50a5503a BD |
1726 | }, |
1727 | [4] = { | |
1728 | .has_osd_c = 1, | |
f676ec2a | 1729 | .has_osd_alpha = 1, |
50a5503a BD |
1730 | .palette_sz = 4, |
1731 | .palette_16bpp = 1, | |
1732 | .valid_bpp = (VALID_BPP(1) | VALID_BPP(2) | | |
1733 | VALID_BPP(16) | VALID_BPP(18) | | |
cd74ebaf JH |
1734 | VALID_BPP(19) | VALID_BPP(24) | |
1735 | VALID_BPP(25) | VALID_BPP(28)), | |
50a5503a BD |
1736 | }, |
1737 | }; | |
1738 | ||
af4a835b JH |
1739 | static struct s3c_fb_win_variant s3c_fb_data_s5p_wins[] = { |
1740 | [0] = { | |
1741 | .has_osd_c = 1, | |
1742 | .osd_size_off = 0x8, | |
1743 | .palette_sz = 256, | |
1744 | .valid_bpp = (VALID_BPP1248 | VALID_BPP(13) | | |
1745 | VALID_BPP(15) | VALID_BPP(16) | | |
1746 | VALID_BPP(18) | VALID_BPP(19) | | |
1747 | VALID_BPP(24) | VALID_BPP(25) | | |
1748 | VALID_BPP(32)), | |
1749 | }, | |
1750 | [1] = { | |
1751 | .has_osd_c = 1, | |
1752 | .has_osd_d = 1, | |
1753 | .osd_size_off = 0xc, | |
1754 | .has_osd_alpha = 1, | |
1755 | .palette_sz = 256, | |
1756 | .valid_bpp = (VALID_BPP1248 | VALID_BPP(13) | | |
1757 | VALID_BPP(15) | VALID_BPP(16) | | |
1758 | VALID_BPP(18) | VALID_BPP(19) | | |
1759 | VALID_BPP(24) | VALID_BPP(25) | | |
1760 | VALID_BPP(32)), | |
1761 | }, | |
1762 | [2] = { | |
1763 | .has_osd_c = 1, | |
1764 | .has_osd_d = 1, | |
1765 | .osd_size_off = 0xc, | |
1766 | .has_osd_alpha = 1, | |
1767 | .palette_sz = 256, | |
1768 | .valid_bpp = (VALID_BPP1248 | VALID_BPP(13) | | |
1769 | VALID_BPP(15) | VALID_BPP(16) | | |
1770 | VALID_BPP(18) | VALID_BPP(19) | | |
1771 | VALID_BPP(24) | VALID_BPP(25) | | |
1772 | VALID_BPP(32)), | |
1773 | }, | |
1774 | [3] = { | |
1775 | .has_osd_c = 1, | |
1776 | .has_osd_alpha = 1, | |
1777 | .palette_sz = 256, | |
1778 | .valid_bpp = (VALID_BPP1248 | VALID_BPP(13) | | |
1779 | VALID_BPP(15) | VALID_BPP(16) | | |
1780 | VALID_BPP(18) | VALID_BPP(19) | | |
1781 | VALID_BPP(24) | VALID_BPP(25) | | |
1782 | VALID_BPP(32)), | |
1783 | }, | |
1784 | [4] = { | |
1785 | .has_osd_c = 1, | |
1786 | .has_osd_alpha = 1, | |
1787 | .palette_sz = 256, | |
1788 | .valid_bpp = (VALID_BPP1248 | VALID_BPP(13) | | |
1789 | VALID_BPP(15) | VALID_BPP(16) | | |
1790 | VALID_BPP(18) | VALID_BPP(19) | | |
1791 | VALID_BPP(24) | VALID_BPP(25) | | |
1792 | VALID_BPP(32)), | |
1793 | }, | |
1794 | }; | |
1795 | ||
8cfdcb23 | 1796 | static struct s3c_fb_driverdata s3c_fb_data_64xx = { |
50a5503a BD |
1797 | .variant = { |
1798 | .nr_windows = 5, | |
c4bb6ffa BD |
1799 | .vidtcon = VIDTCON0, |
1800 | .wincon = WINCON(0), | |
1801 | .winmap = WINxMAP(0), | |
1802 | .keycon = WKEYCON, | |
1803 | .osd = VIDOSD_BASE, | |
1804 | .osd_stride = 16, | |
1805 | .buf_start = VIDW_BUF_START(0), | |
1806 | .buf_size = VIDW_BUF_SIZE(0), | |
1807 | .buf_end = VIDW_BUF_END(0), | |
50a5503a BD |
1808 | |
1809 | .palette = { | |
1810 | [0] = 0x400, | |
1811 | [1] = 0x800, | |
1812 | [2] = 0x300, | |
1813 | [3] = 0x320, | |
1814 | [4] = 0x340, | |
1815 | }, | |
067b226b PO |
1816 | |
1817 | .has_prtcon = 1, | |
b5480ed7 | 1818 | .has_clksel = 1, |
50a5503a BD |
1819 | }, |
1820 | .win[0] = &s3c_fb_data_64xx_wins[0], | |
1821 | .win[1] = &s3c_fb_data_64xx_wins[1], | |
1822 | .win[2] = &s3c_fb_data_64xx_wins[2], | |
1823 | .win[3] = &s3c_fb_data_64xx_wins[3], | |
1824 | .win[4] = &s3c_fb_data_64xx_wins[4], | |
1825 | }; | |
1826 | ||
8cfdcb23 | 1827 | static struct s3c_fb_driverdata s3c_fb_data_s5pc100 = { |
4e591ac6 PO |
1828 | .variant = { |
1829 | .nr_windows = 5, | |
1830 | .vidtcon = VIDTCON0, | |
1831 | .wincon = WINCON(0), | |
1832 | .winmap = WINxMAP(0), | |
1833 | .keycon = WKEYCON, | |
1834 | .osd = VIDOSD_BASE, | |
1835 | .osd_stride = 16, | |
1836 | .buf_start = VIDW_BUF_START(0), | |
1837 | .buf_size = VIDW_BUF_SIZE(0), | |
1838 | .buf_end = VIDW_BUF_END(0), | |
1839 | ||
1840 | .palette = { | |
1841 | [0] = 0x2400, | |
1842 | [1] = 0x2800, | |
1843 | [2] = 0x2c00, | |
1844 | [3] = 0x3000, | |
1845 | [4] = 0x3400, | |
1846 | }, | |
067b226b PO |
1847 | |
1848 | .has_prtcon = 1, | |
f7f31e50 | 1849 | .has_blendcon = 1, |
b5480ed7 | 1850 | .has_clksel = 1, |
4e591ac6 | 1851 | }, |
af4a835b JH |
1852 | .win[0] = &s3c_fb_data_s5p_wins[0], |
1853 | .win[1] = &s3c_fb_data_s5p_wins[1], | |
1854 | .win[2] = &s3c_fb_data_s5p_wins[2], | |
1855 | .win[3] = &s3c_fb_data_s5p_wins[3], | |
1856 | .win[4] = &s3c_fb_data_s5p_wins[4], | |
4e591ac6 PO |
1857 | }; |
1858 | ||
8cfdcb23 | 1859 | static struct s3c_fb_driverdata s3c_fb_data_s5pv210 = { |
b5480ed7 JH |
1860 | .variant = { |
1861 | .nr_windows = 5, | |
1862 | .vidtcon = VIDTCON0, | |
1863 | .wincon = WINCON(0), | |
1864 | .winmap = WINxMAP(0), | |
1865 | .keycon = WKEYCON, | |
1866 | .osd = VIDOSD_BASE, | |
1867 | .osd_stride = 16, | |
1868 | .buf_start = VIDW_BUF_START(0), | |
1869 | .buf_size = VIDW_BUF_SIZE(0), | |
1870 | .buf_end = VIDW_BUF_END(0), | |
1871 | ||
1872 | .palette = { | |
1873 | [0] = 0x2400, | |
1874 | [1] = 0x2800, | |
1875 | [2] = 0x2c00, | |
1876 | [3] = 0x3000, | |
1877 | [4] = 0x3400, | |
1878 | }, | |
1879 | ||
1880 | .has_shadowcon = 1, | |
f7f31e50 | 1881 | .has_blendcon = 1, |
b5480ed7 | 1882 | .has_clksel = 1, |
d8b97db4 | 1883 | .has_fixvclk = 1, |
b5480ed7 JH |
1884 | }, |
1885 | .win[0] = &s3c_fb_data_s5p_wins[0], | |
1886 | .win[1] = &s3c_fb_data_s5p_wins[1], | |
1887 | .win[2] = &s3c_fb_data_s5p_wins[2], | |
1888 | .win[3] = &s3c_fb_data_s5p_wins[3], | |
1889 | .win[4] = &s3c_fb_data_s5p_wins[4], | |
1890 | }; | |
1891 | ||
1892 | static struct s3c_fb_driverdata s3c_fb_data_exynos4 = { | |
50a5503a BD |
1893 | .variant = { |
1894 | .nr_windows = 5, | |
c4bb6ffa BD |
1895 | .vidtcon = VIDTCON0, |
1896 | .wincon = WINCON(0), | |
1897 | .winmap = WINxMAP(0), | |
1898 | .keycon = WKEYCON, | |
1899 | .osd = VIDOSD_BASE, | |
1900 | .osd_stride = 16, | |
1901 | .buf_start = VIDW_BUF_START(0), | |
1902 | .buf_size = VIDW_BUF_SIZE(0), | |
1903 | .buf_end = VIDW_BUF_END(0), | |
50a5503a BD |
1904 | |
1905 | .palette = { | |
1906 | [0] = 0x2400, | |
1907 | [1] = 0x2800, | |
1908 | [2] = 0x2c00, | |
1909 | [3] = 0x3000, | |
1910 | [4] = 0x3400, | |
1911 | }, | |
f5ec546f PO |
1912 | |
1913 | .has_shadowcon = 1, | |
f7f31e50 | 1914 | .has_blendcon = 1, |
d8b97db4 | 1915 | .has_fixvclk = 1, |
50a5503a | 1916 | }, |
af4a835b JH |
1917 | .win[0] = &s3c_fb_data_s5p_wins[0], |
1918 | .win[1] = &s3c_fb_data_s5p_wins[1], | |
1919 | .win[2] = &s3c_fb_data_s5p_wins[2], | |
1920 | .win[3] = &s3c_fb_data_s5p_wins[3], | |
1921 | .win[4] = &s3c_fb_data_s5p_wins[4], | |
50a5503a BD |
1922 | }; |
1923 | ||
5c44778e JH |
1924 | static struct s3c_fb_driverdata s3c_fb_data_exynos5 = { |
1925 | .variant = { | |
1926 | .nr_windows = 5, | |
1927 | .vidtcon = VIDTCON0, | |
1928 | .wincon = WINCON(0), | |
1929 | .winmap = WINxMAP(0), | |
1930 | .keycon = WKEYCON, | |
1931 | .osd = VIDOSD_BASE, | |
1932 | .osd_stride = 16, | |
1933 | .buf_start = VIDW_BUF_START(0), | |
1934 | .buf_size = VIDW_BUF_SIZE(0), | |
1935 | .buf_end = VIDW_BUF_END(0), | |
1936 | ||
1937 | .palette = { | |
1938 | [0] = 0x2400, | |
1939 | [1] = 0x2800, | |
1940 | [2] = 0x2c00, | |
1941 | [3] = 0x3000, | |
1942 | [4] = 0x3400, | |
1943 | }, | |
1944 | .has_shadowcon = 1, | |
1945 | .has_blendcon = 1, | |
1946 | .has_fixvclk = 1, | |
1947 | }, | |
1948 | .win[0] = &s3c_fb_data_s5p_wins[0], | |
1949 | .win[1] = &s3c_fb_data_s5p_wins[1], | |
1950 | .win[2] = &s3c_fb_data_s5p_wins[2], | |
1951 | .win[3] = &s3c_fb_data_s5p_wins[3], | |
1952 | .win[4] = &s3c_fb_data_s5p_wins[4], | |
1953 | }; | |
1954 | ||
c4bb6ffa | 1955 | /* S3C2443/S3C2416 style hardware */ |
8cfdcb23 | 1956 | static struct s3c_fb_driverdata s3c_fb_data_s3c2443 = { |
c4bb6ffa BD |
1957 | .variant = { |
1958 | .nr_windows = 2, | |
1959 | .is_2443 = 1, | |
1960 | ||
1961 | .vidtcon = 0x08, | |
1962 | .wincon = 0x14, | |
1963 | .winmap = 0xd0, | |
1964 | .keycon = 0xb0, | |
1965 | .osd = 0x28, | |
1966 | .osd_stride = 12, | |
1967 | .buf_start = 0x64, | |
1968 | .buf_size = 0x94, | |
1969 | .buf_end = 0x7c, | |
1970 | ||
1971 | .palette = { | |
1972 | [0] = 0x400, | |
1973 | [1] = 0x800, | |
1974 | }, | |
b5480ed7 | 1975 | .has_clksel = 1, |
c4bb6ffa BD |
1976 | }, |
1977 | .win[0] = &(struct s3c_fb_win_variant) { | |
1978 | .palette_sz = 256, | |
1979 | .valid_bpp = VALID_BPP1248 | VALID_BPP(16) | VALID_BPP(24), | |
1980 | }, | |
1981 | .win[1] = &(struct s3c_fb_win_variant) { | |
1982 | .has_osd_c = 1, | |
f676ec2a | 1983 | .has_osd_alpha = 1, |
c4bb6ffa BD |
1984 | .palette_sz = 256, |
1985 | .valid_bpp = (VALID_BPP1248 | VALID_BPP(16) | | |
1986 | VALID_BPP(18) | VALID_BPP(19) | | |
1987 | VALID_BPP(24) | VALID_BPP(25) | | |
1988 | VALID_BPP(28)), | |
1989 | }, | |
1990 | }; | |
1991 | ||
21b5a3ad AK |
1992 | static struct s3c_fb_driverdata s3c_fb_data_s5p64x0 = { |
1993 | .variant = { | |
1994 | .nr_windows = 3, | |
1995 | .vidtcon = VIDTCON0, | |
1996 | .wincon = WINCON(0), | |
1997 | .winmap = WINxMAP(0), | |
1998 | .keycon = WKEYCON, | |
1999 | .osd = VIDOSD_BASE, | |
2000 | .osd_stride = 16, | |
2001 | .buf_start = VIDW_BUF_START(0), | |
2002 | .buf_size = VIDW_BUF_SIZE(0), | |
2003 | .buf_end = VIDW_BUF_END(0), | |
2004 | ||
2005 | .palette = { | |
2006 | [0] = 0x2400, | |
2007 | [1] = 0x2800, | |
2008 | [2] = 0x2c00, | |
2009 | }, | |
f7f31e50 JH |
2010 | |
2011 | .has_blendcon = 1, | |
d8b97db4 | 2012 | .has_fixvclk = 1, |
21b5a3ad AK |
2013 | }, |
2014 | .win[0] = &s3c_fb_data_s5p_wins[0], | |
2015 | .win[1] = &s3c_fb_data_s5p_wins[1], | |
2016 | .win[2] = &s3c_fb_data_s5p_wins[2], | |
2017 | }; | |
2018 | ||
50a5503a BD |
2019 | static struct platform_device_id s3c_fb_driver_ids[] = { |
2020 | { | |
2021 | .name = "s3c-fb", | |
2022 | .driver_data = (unsigned long)&s3c_fb_data_64xx, | |
2023 | }, { | |
4e591ac6 PO |
2024 | .name = "s5pc100-fb", |
2025 | .driver_data = (unsigned long)&s3c_fb_data_s5pc100, | |
2026 | }, { | |
2027 | .name = "s5pv210-fb", | |
2028 | .driver_data = (unsigned long)&s3c_fb_data_s5pv210, | |
b5480ed7 JH |
2029 | }, { |
2030 | .name = "exynos4-fb", | |
2031 | .driver_data = (unsigned long)&s3c_fb_data_exynos4, | |
5c44778e JH |
2032 | }, { |
2033 | .name = "exynos5-fb", | |
2034 | .driver_data = (unsigned long)&s3c_fb_data_exynos5, | |
c4bb6ffa BD |
2035 | }, { |
2036 | .name = "s3c2443-fb", | |
2037 | .driver_data = (unsigned long)&s3c_fb_data_s3c2443, | |
21b5a3ad AK |
2038 | }, { |
2039 | .name = "s5p64x0-fb", | |
2040 | .driver_data = (unsigned long)&s3c_fb_data_s5p64x0, | |
50a5503a BD |
2041 | }, |
2042 | {}, | |
2043 | }; | |
2044 | MODULE_DEVICE_TABLE(platform, s3c_fb_driver_ids); | |
2045 | ||
f4f51473 MB |
2046 | static const struct dev_pm_ops s3cfb_pm_ops = { |
2047 | SET_SYSTEM_SLEEP_PM_OPS(s3c_fb_suspend, s3c_fb_resume) | |
2048 | SET_RUNTIME_PM_OPS(s3c_fb_runtime_suspend, s3c_fb_runtime_resume, | |
2049 | NULL) | |
2050 | }; | |
4959212c | 2051 | |
ec549a0f BD |
2052 | static struct platform_driver s3c_fb_driver = { |
2053 | .probe = s3c_fb_probe, | |
3163eaba | 2054 | .remove = __devexit_p(s3c_fb_remove), |
50a5503a | 2055 | .id_table = s3c_fb_driver_ids, |
ec549a0f BD |
2056 | .driver = { |
2057 | .name = "s3c-fb", | |
2058 | .owner = THIS_MODULE, | |
fe05f8b1 | 2059 | .pm = &s3cfb_pm_ops, |
ec549a0f BD |
2060 | }, |
2061 | }; | |
2062 | ||
4277f2c4 | 2063 | module_platform_driver(s3c_fb_driver); |
ec549a0f BD |
2064 | |
2065 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); | |
2066 | MODULE_DESCRIPTION("Samsung S3C SoC Framebuffer driver"); | |
2067 | MODULE_LICENSE("GPL"); | |
2068 | MODULE_ALIAS("platform:s3c-fb"); |