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vt8623fb: Don't clobber par->state.vgabase during open method.
[deliverable/linux.git] / drivers / video / s3fb.c
CommitLineData
a268422d
OZ		 1/*
2 * linux/drivers/video/s3fb.c -- Frame buffer device driver for S3 Trio/Virge
3 *
4 * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive for
8 * more details.
9 *
10 * Code is based on David Boucher's viafb (http://davesdomain.org.uk/viafb/)
11 * which is based on the code of neofb.
12 */
13
a268422d
OZ		 14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/errno.h>
17#include <linux/string.h>
18#include <linux/mm.h>
19#include <linux/tty.h>
a268422d
OZ		 20#include <linux/delay.h>
21#include <linux/fb.h>
22#include <linux/svga.h>
23#include <linux/init.h>
24#include <linux/pci.h>
ac751efa 25#include <linux/console.h> /* Why should fb driver call console functions? because console_lock() */
a268422d
OZ		 26#include <video/vga.h>
27
28#ifdef CONFIG_MTRR
29#include <asm/mtrr.h>
30#endif
31
32struct s3fb_info {
33 int chip, rev, mclk_freq;
34 int mtrr_reg;
35 struct vgastate state;
36 struct mutex open_lock;
37 unsigned int ref_count;
38 u32 pseudo_palette[16];
39};
40
41
42/* ------------------------------------------------------------------------- */
43
44static const struct svga_fb_format s3fb_formats[] = {
45 { 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
46 FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4, FB_VISUAL_PSEUDOCOLOR, 8, 16},
c26d7b29 47 { 4, {0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0}, 0,
a268422d 48 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 16},
c26d7b29 49 { 4, {0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0}, 1,
a268422d 50 FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 8, 16},
c26d7b29 51 { 8, {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
a268422d
OZ		 52 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 4, 8},
53 {16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0,
54 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4},
55 {16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0,
56 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4},
57 {24, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
58 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2},
59 {32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
60 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2},
61 SVGA_FORMAT_END
62};
63
64
65static const struct svga_pll s3_pll = {3, 129, 3, 33, 0, 3,
249bdbbf 66 35000, 240000, 14318};
a268422d
OZ		 67
68static const int s3_memsizes[] = {4096, 0, 3072, 8192, 2048, 6144, 1024, 512};
69
70static const char * const s3_names[] = {"S3 Unknown", "S3 Trio32", "S3 Trio64", "S3 Trio64V+",
71 "S3 Trio64UV+", "S3 Trio64V2/DX", "S3 Trio64V2/GX",
72 "S3 Plato/PX", "S3 Aurora64VP", "S3 Virge",
73 "S3 Virge/VX", "S3 Virge/DX", "S3 Virge/GX",
9966c4fe
OZ		 74 "S3 Virge/GX2", "S3 Virge/GX2P", "S3 Virge/GX2P",
75 "S3 Trio3D/1X", "S3 Trio3D/2X", "S3 Trio3D/2X"};
a268422d
OZ		 76
77#define CHIP_UNKNOWN 0x00
78#define CHIP_732_TRIO32 0x01
79#define CHIP_764_TRIO64 0x02
80#define CHIP_765_TRIO64VP 0x03
81#define CHIP_767_TRIO64UVP 0x04
82#define CHIP_775_TRIO64V2_DX 0x05
83#define CHIP_785_TRIO64V2_GX 0x06
84#define CHIP_551_PLATO_PX 0x07
85#define CHIP_M65_AURORA64VP 0x08
86#define CHIP_325_VIRGE 0x09
87#define CHIP_988_VIRGE_VX 0x0A
88#define CHIP_375_VIRGE_DX 0x0B
89#define CHIP_385_VIRGE_GX 0x0C
90#define CHIP_356_VIRGE_GX2 0x0D
91#define CHIP_357_VIRGE_GX2P 0x0E
92#define CHIP_359_VIRGE_GX2P 0x0F
9966c4fe
OZ		 93#define CHIP_360_TRIO3D_1X 0x10
94#define CHIP_362_TRIO3D_2X 0x11
95#define CHIP_368_TRIO3D_2X 0x12
a268422d
OZ		 96
97#define CHIP_XXX_TRIO 0x80
98#define CHIP_XXX_TRIO64V2_DXGX 0x81
99#define CHIP_XXX_VIRGE_DXGX 0x82
9966c4fe 100#define CHIP_36X_TRIO3D_1X_2X 0x83
a268422d
OZ		 101
102#define CHIP_UNDECIDED_FLAG 0x80
103#define CHIP_MASK 0xFF
104
105/* CRT timing register sets */
106
107static const struct vga_regset s3_h_total_regs[] = {{0x00, 0, 7}, {0x5D, 0, 0}, VGA_REGSET_END};
108static const struct vga_regset s3_h_display_regs[] = {{0x01, 0, 7}, {0x5D, 1, 1}, VGA_REGSET_END};
109static const struct vga_regset s3_h_blank_start_regs[] = {{0x02, 0, 7}, {0x5D, 2, 2}, VGA_REGSET_END};
110static const struct vga_regset s3_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7}, VGA_REGSET_END};
111static const struct vga_regset s3_h_sync_start_regs[] = {{0x04, 0, 7}, {0x5D, 4, 4}, VGA_REGSET_END};
112static const struct vga_regset s3_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END};
113
114static const struct vga_regset s3_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x5E, 0, 0}, VGA_REGSET_END};
115static const struct vga_regset s3_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x5E, 1, 1}, VGA_REGSET_END};
116static const struct vga_regset s3_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x5E, 2, 2}, VGA_REGSET_END};
117static const struct vga_regset s3_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END};
118static const struct vga_regset s3_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x5E, 4, 4}, VGA_REGSET_END};
119static const struct vga_regset s3_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END};
120
121static const struct vga_regset s3_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, {0x5E, 6, 6}, VGA_REGSET_END};
122static const struct vga_regset s3_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x31, 4, 5}, {0x51, 0, 1}, VGA_REGSET_END};
123static const struct vga_regset s3_offset_regs[] = {{0x13, 0, 7}, {0x51, 4, 5}, VGA_REGSET_END}; /* set 0x43 bit 2 to 0 */
124
125static const struct svga_timing_regs s3_timing_regs = {
126 s3_h_total_regs, s3_h_display_regs, s3_h_blank_start_regs,
127 s3_h_blank_end_regs, s3_h_sync_start_regs, s3_h_sync_end_regs,
128 s3_v_total_regs, s3_v_display_regs, s3_v_blank_start_regs,
129 s3_v_blank_end_regs, s3_v_sync_start_regs, s3_v_sync_end_regs,
130};
131
132
133/* ------------------------------------------------------------------------- */
134
135/* Module parameters */
136
137
a8140543 138static char *mode_option __devinitdata = "640x480-8@60";
a268422d
OZ		 139
140#ifdef CONFIG_MTRR
a8140543 141static int mtrr __devinitdata = 1;
a268422d
OZ		 142#endif
143
144static int fasttext = 1;
145
146
147MODULE_AUTHOR("(c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>");
148MODULE_LICENSE("GPL");
149MODULE_DESCRIPTION("fbdev driver for S3 Trio/Virge");
150
a8140543
KH		 151module_param(mode_option, charp, 0444);
152MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)");
153module_param_named(mode, mode_option, charp, 0444);
154MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc) (deprecated)");
a268422d
OZ		 155
156#ifdef CONFIG_MTRR
157module_param(mtrr, int, 0444);
158MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");
159#endif
160
161module_param(fasttext, int, 0644);
162MODULE_PARM_DESC(fasttext, "Enable S3 fast text mode (1=enable, 0=disable, default=1)");
163
164
165/* ------------------------------------------------------------------------- */
166
167/* Set font in S3 fast text mode */
168
169static void s3fb_settile_fast(struct fb_info *info, struct fb_tilemap *map)
170{
171 const u8 *font = map->data;
75814d87 172 u8 __iomem *fb = (u8 __iomem *) info->screen_base;
a268422d
OZ		 173 int i, c;
174
175 if ((map->width != 8) || (map->height != 16) ||
176 (map->depth != 1) || (map->length != 256)) {
177 printk(KERN_ERR "fb%d: unsupported font parameters: width %d, height %d, depth %d, length %d\n",
178 info->node, map->width, map->height, map->depth, map->length);
179 return;
180 }
181
182 fb += 2;
183 for (i = 0; i < map->height; i++) {
184 for (c = 0; c < map->length; c++) {
75814d87 185 fb_writeb(font[c * map->height + i], fb + c * 4);
a268422d
OZ		 186 }
187 fb += 1024;
188 }
189}
190
55db0923
DM		 191static void s3fb_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor)
192{
193 struct s3fb_info *par = info->par;
194
195 svga_tilecursor(par->state.vgabase, info, cursor);
196}
197
a268422d
OZ		 198static struct fb_tile_ops s3fb_tile_ops = {
199 .fb_settile = svga_settile,
200 .fb_tilecopy = svga_tilecopy,
201 .fb_tilefill = svga_tilefill,
202 .fb_tileblit = svga_tileblit,
55db0923 203 .fb_tilecursor = s3fb_tilecursor,
34ed25f5 204 .fb_get_tilemax = svga_get_tilemax,
a268422d
OZ		 205};
206
207static struct fb_tile_ops s3fb_fast_tile_ops = {
208 .fb_settile = s3fb_settile_fast,
209 .fb_tilecopy = svga_tilecopy,
210 .fb_tilefill = svga_tilefill,
211 .fb_tileblit = svga_tileblit,
55db0923 212 .fb_tilecursor = s3fb_tilecursor,
34ed25f5 213 .fb_get_tilemax = svga_get_tilemax,
a268422d
OZ		 214};
215
216
217/* ------------------------------------------------------------------------- */
218
219/* image data is MSB-first, fb structure is MSB-first too */
220static inline u32 expand_color(u32 c)
221{
222 return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF;
223}
224
225/* s3fb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */
226static void s3fb_iplan_imageblit(struct fb_info *info, const struct fb_image *image)
227{
228 u32 fg = expand_color(image->fg_color);
229 u32 bg = expand_color(image->bg_color);
230 const u8 *src1, *src;
231 u8 __iomem *dst1;
232 u32 __iomem *dst;
233 u32 val;
234 int x, y;
235
236 src1 = image->data;
237 dst1 = info->screen_base + (image->dy * info->fix.line_length)
238 + ((image->dx / 8) * 4);
239
240 for (y = 0; y < image->height; y++) {
241 src = src1;
242 dst = (u32 __iomem *) dst1;
243 for (x = 0; x < image->width; x += 8) {
244 val = *(src++) * 0x01010101;
245 val = (val & fg) | (~val & bg);
246 fb_writel(val, dst++);
247 }
248 src1 += image->width / 8;
249 dst1 += info->fix.line_length;
250 }
251
252}
253
254/* s3fb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */
255static void s3fb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
256{
257 u32 fg = expand_color(rect->color);
258 u8 __iomem *dst1;
259 u32 __iomem *dst;
260 int x, y;
261
262 dst1 = info->screen_base + (rect->dy * info->fix.line_length)
263 + ((rect->dx / 8) * 4);
264
265 for (y = 0; y < rect->height; y++) {
266 dst = (u32 __iomem *) dst1;
267 for (x = 0; x < rect->width; x += 8) {
268 fb_writel(fg, dst++);
269 }
270 dst1 += info->fix.line_length;
271 }
272}
273
274
275/* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */
276static inline u32 expand_pixel(u32 c)
277{
278 return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) |
279 ((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF;
280}
281
282/* s3fb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */
283static void s3fb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image)
284{
285 u32 fg = image->fg_color * 0x11111111;
286 u32 bg = image->bg_color * 0x11111111;
287 const u8 *src1, *src;
288 u8 __iomem *dst1;
289 u32 __iomem *dst;
290 u32 val;
291 int x, y;
292
293 src1 = image->data;
294 dst1 = info->screen_base + (image->dy * info->fix.line_length)
295 + ((image->dx / 8) * 4);
296
297 for (y = 0; y < image->height; y++) {
298 src = src1;
299 dst = (u32 __iomem *) dst1;
300 for (x = 0; x < image->width; x += 8) {
301 val = expand_pixel(*(src++));
302 val = (val & fg) | (~val & bg);
303 fb_writel(val, dst++);
304 }
305 src1 += image->width / 8;
306 dst1 += info->fix.line_length;
307 }
308}
309
310static void s3fb_imageblit(struct fb_info *info, const struct fb_image *image)
311{
312 if ((info->var.bits_per_pixel == 4) && (image->depth == 1)
313 && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) {
314 if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)
315 s3fb_iplan_imageblit(info, image);
316 else
317 s3fb_cfb4_imageblit(info, image);
318 } else
319 cfb_imageblit(info, image);
320}
321
322static void s3fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
323{
324 if ((info->var.bits_per_pixel == 4)
325 && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0)
326 && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES))
327 s3fb_iplan_fillrect(info, rect);
328 else
329 cfb_fillrect(info, rect);
330}
331
332
333
334/* ------------------------------------------------------------------------- */
335
336
337static void s3_set_pixclock(struct fb_info *info, u32 pixclock)
338{
9966c4fe 339 struct s3fb_info *par = info->par;
a268422d
OZ		 340 u16 m, n, r;
341 u8 regval;
249bdbbf 342 int rv;
a268422d 343
249bdbbf
OZ		 344 rv = svga_compute_pll(&s3_pll, 1000000000 / pixclock, &m, &n, &r, info->node);
345 if (rv < 0) {
346 printk(KERN_ERR "fb%d: cannot set requested pixclock, keeping old value\n", info->node);
347 return;
348 }
a268422d
OZ		 349
350 /* Set VGA misc register */
f8645933
DM		 351 regval = vga_r(par->state.vgabase, VGA_MIS_R);
352 vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
a268422d
OZ		 353
354 /* Set S3 clock registers */
9966c4fe
OZ		 355 if (par->chip == CHIP_360_TRIO3D_1X ||
356 par->chip == CHIP_362_TRIO3D_2X ||
357 par->chip == CHIP_368_TRIO3D_2X) {
f8645933
DM		 358 vga_wseq(par->state.vgabase, 0x12, (n - 2) | ((r & 3) << 6)); /* n and two bits of r */
359 vga_wseq(par->state.vgabase, 0x29, r >> 2); /* remaining highest bit of r */
9966c4fe 360 } else
f8645933
DM		 361 vga_wseq(par->state.vgabase, 0x12, (n - 2) | (r << 5));
362 vga_wseq(par->state.vgabase, 0x13, m - 2);
a268422d
OZ		 363
364 udelay(1000);
365
366 /* Activate clock - write 0, 1, 0 to seq/15 bit 5 */
f8645933
DM		 367 regval = vga_rseq (par->state.vgabase, 0x15); /* | 0x80; */
368 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5));
369 vga_wseq(par->state.vgabase, 0x15, regval | (1<<5));
370 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5));
a268422d
OZ		 371}
372
373
374/* Open framebuffer */
375
376static int s3fb_open(struct fb_info *info, int user)
377{
378 struct s3fb_info *par = info->par;
379
380 mutex_lock(&(par->open_lock));
381 if (par->ref_count == 0) {
3ff259f2
DM		 382 void __iomem *vgabase = par->state.vgabase;
383
a268422d 384 memset(&(par->state), 0, sizeof(struct vgastate));
3ff259f2 385 par->state.vgabase = vgabase;
a268422d
OZ		 386 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP;
387 par->state.num_crtc = 0x70;
388 par->state.num_seq = 0x20;
389 save_vga(&(par->state));
390 }
391
392 par->ref_count++;
393 mutex_unlock(&(par->open_lock));
394
395 return 0;
396}
397
398/* Close framebuffer */
399
400static int s3fb_release(struct fb_info *info, int user)
401{
402 struct s3fb_info *par = info->par;
403
404 mutex_lock(&(par->open_lock));
405 if (par->ref_count == 0) {
406 mutex_unlock(&(par->open_lock));
407 return -EINVAL;
408 }
409
410 if (par->ref_count == 1)
411 restore_vga(&(par->state));
412
413 par->ref_count--;
414 mutex_unlock(&(par->open_lock));
415
416 return 0;
417}
418
419/* Validate passed in var */
420
421static int s3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
422{
423 struct s3fb_info *par = info->par;
424 int rv, mem, step;
c3ca34f9 425 u16 m, n, r;
a268422d
OZ		 426
427 /* Find appropriate format */
428 rv = svga_match_format (s3fb_formats, var, NULL);
d4b766a0
OZ		 429
430 /* 32bpp mode is not supported on VIRGE VX,
431 24bpp is not supported on others */
432 if ((par->chip == CHIP_988_VIRGE_VX) ? (rv == 7) : (rv == 6))
433 rv = -EINVAL;
434
435 if (rv < 0) {
a268422d
OZ		 436 printk(KERN_ERR "fb%d: unsupported mode requested\n", info->node);
437 return rv;
438 }
439
440 /* Do not allow to have real resoulution larger than virtual */
441 if (var->xres > var->xres_virtual)
442 var->xres_virtual = var->xres;
443
444 if (var->yres > var->yres_virtual)
445 var->yres_virtual = var->yres;
446
447 /* Round up xres_virtual to have proper alignment of lines */
448 step = s3fb_formats[rv].xresstep - 1;
449 var->xres_virtual = (var->xres_virtual+step) & ~step;
450
451 /* Check whether have enough memory */
452 mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual;
c3ca34f9 453 if (mem > info->screen_size) {
a268422d
OZ		 454 printk(KERN_ERR "fb%d: not enough framebuffer memory (%d kB requested , %d kB available)\n",
455 info->node, mem >> 10, (unsigned int) (info->screen_size >> 10));
456 return -EINVAL;
457 }
458
459 rv = svga_check_timings (&s3_timing_regs, var, info->node);
c3ca34f9 460 if (rv < 0) {
a268422d
OZ		 461 printk(KERN_ERR "fb%d: invalid timings requested\n", info->node);
462 return rv;
463 }
464
c3ca34f9
KH		 465 rv = svga_compute_pll(&s3_pll, PICOS2KHZ(var->pixclock), &m, &n, &r,
466 info->node);
467 if (rv < 0) {
468 printk(KERN_ERR "fb%d: invalid pixclock value requested\n",
469 info->node);
470 return rv;
471 }
472
a268422d
OZ		 473 return 0;
474}
475
476/* Set video mode from par */
477
478static int s3fb_set_par(struct fb_info *info)
479{
480 struct s3fb_info *par = info->par;
9966c4fe 481 u32 value, mode, hmul, offset_value, screen_size, multiplex, dbytes;
a268422d
OZ		 482 u32 bpp = info->var.bits_per_pixel;
483
484 if (bpp != 0) {
485 info->fix.ypanstep = 1;
486 info->fix.line_length = (info->var.xres_virtual * bpp) / 8;
487
488 info->flags &= ~FBINFO_MISC_TILEBLITTING;
489 info->tileops = NULL;
490
34ed25f5
OZ		 491 /* in 4bpp supports 8p wide tiles only, any tiles otherwise */
492 info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0);
8db51668 493 info->pixmap.blit_y = ~(u32)0;
34ed25f5 494
a268422d
OZ		 495 offset_value = (info->var.xres_virtual * bpp) / 64;
496 screen_size = info->var.yres_virtual * info->fix.line_length;
497 } else {
498 info->fix.ypanstep = 16;
499 info->fix.line_length = 0;
500
501 info->flags |= FBINFO_MISC_TILEBLITTING;
502 info->tileops = fasttext ? &s3fb_fast_tile_ops : &s3fb_tile_ops;
34ed25f5 503
8db51668
AD		 504 /* supports 8x16 tiles only */
505 info->pixmap.blit_x = 1 << (8 - 1);
506 info->pixmap.blit_y = 1 << (16 - 1);
a268422d
OZ		 507
508 offset_value = info->var.xres_virtual / 16;
509 screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64;
510 }
511
512 info->var.xoffset = 0;
513 info->var.yoffset = 0;
514 info->var.activate = FB_ACTIVATE_NOW;
515
516 /* Unlock registers */
f8645933
DM		 517 vga_wcrt(par->state.vgabase, 0x38, 0x48);
518 vga_wcrt(par->state.vgabase, 0x39, 0xA5);
519 vga_wseq(par->state.vgabase, 0x08, 0x06);
ea770789 520 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80);
a268422d
OZ		 521
522 /* Blank screen and turn off sync */
d907ec04 523 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
ea770789 524 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
a268422d
OZ		 525
526 /* Set default values */
e2fade2c 527 svga_set_default_gfx_regs(par->state.vgabase);
f51a14dd 528 svga_set_default_atc_regs(par->state.vgabase);
a4ade839 529 svga_set_default_seq_regs(par->state.vgabase);
1d28fcad 530 svga_set_default_crt_regs(par->state.vgabase);
21da386d
DM		 531 svga_wcrt_multi(par->state.vgabase, s3_line_compare_regs, 0xFFFFFFFF);
532 svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, 0);
a268422d
OZ		 533
534 /* S3 specific initialization */
ea770789
DM		 535 svga_wcrt_mask(par->state.vgabase, 0x58, 0x10, 0x10); /* enable linear framebuffer */
536 svga_wcrt_mask(par->state.vgabase, 0x31, 0x08, 0x08); /* enable sequencer access to framebuffer above 256 kB */
a268422d 537
ea770789
DM		 538/* svga_wcrt_mask(par->state.vgabase, 0x33, 0x08, 0x08); */ /* DDR ? */
539/* svga_wcrt_mask(par->state.vgabase, 0x43, 0x01, 0x01); */ /* DDR ? */
540 svga_wcrt_mask(par->state.vgabase, 0x33, 0x00, 0x08); /* no DDR ? */
541 svga_wcrt_mask(par->state.vgabase, 0x43, 0x00, 0x01); /* no DDR ? */
a268422d 542
ea770789 543 svga_wcrt_mask(par->state.vgabase, 0x5D, 0x00, 0x28); /* Clear strange HSlen bits */
a268422d 544
ea770789 545/* svga_wcrt_mask(par->state.vgabase, 0x58, 0x03, 0x03); */
a268422d 546
ea770789
DM		 547/* svga_wcrt_mask(par->state.vgabase, 0x53, 0x12, 0x13); */ /* enable MMIO */
548/* svga_wcrt_mask(par->state.vgabase, 0x40, 0x08, 0x08); */ /* enable write buffer */
a268422d
OZ		 549
550
551 /* Set the offset register */
552 pr_debug("fb%d: offset register : %d\n", info->node, offset_value);
21da386d 553 svga_wcrt_multi(par->state.vgabase, s3_offset_regs, offset_value);
a268422d 554
9966c4fe
OZ		 555 if (par->chip != CHIP_360_TRIO3D_1X &&
556 par->chip != CHIP_362_TRIO3D_2X &&
557 par->chip != CHIP_368_TRIO3D_2X) {
f8645933
DM		 558 vga_wcrt(par->state.vgabase, 0x54, 0x18); /* M parameter */
559 vga_wcrt(par->state.vgabase, 0x60, 0xff); /* N parameter */
560 vga_wcrt(par->state.vgabase, 0x61, 0xff); /* L parameter */
561 vga_wcrt(par->state.vgabase, 0x62, 0xff); /* L parameter */
9966c4fe 562 }
a268422d 563
f8645933 564 vga_wcrt(par->state.vgabase, 0x3A, 0x35);
f6b0cc47 565 svga_wattr(par->state.vgabase, 0x33, 0x00);
a268422d
OZ		 566
567 if (info->var.vmode & FB_VMODE_DOUBLE)
ea770789 568 svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80);
a268422d 569 else
ea770789 570 svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80);
a268422d
OZ		 571
572 if (info->var.vmode & FB_VMODE_INTERLACED)
ea770789 573 svga_wcrt_mask(par->state.vgabase, 0x42, 0x20, 0x20);
a268422d 574 else
ea770789 575 svga_wcrt_mask(par->state.vgabase, 0x42, 0x00, 0x20);
a268422d
OZ		 576
577 /* Disable hardware graphics cursor */
ea770789 578 svga_wcrt_mask(par->state.vgabase, 0x45, 0x00, 0x01);
a268422d 579 /* Disable Streams engine */
ea770789 580 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0x0C);
a268422d
OZ		 581
582 mode = svga_match_format(s3fb_formats, &(info->var), &(info->fix));
583
584 /* S3 virge DX hack */
585 if (par->chip == CHIP_375_VIRGE_DX) {
f8645933
DM		 586 vga_wcrt(par->state.vgabase, 0x86, 0x80);
587 vga_wcrt(par->state.vgabase, 0x90, 0x00);
a268422d
OZ		 588 }
589
590 /* S3 virge VX hack */
591 if (par->chip == CHIP_988_VIRGE_VX) {
f8645933
DM		 592 vga_wcrt(par->state.vgabase, 0x50, 0x00);
593 vga_wcrt(par->state.vgabase, 0x67, 0x50);
a268422d 594
f8645933
DM		 595 vga_wcrt(par->state.vgabase, 0x63, (mode <= 2) ? 0x90 : 0x09);
596 vga_wcrt(par->state.vgabase, 0x66, 0x90);
a268422d
OZ		 597 }
598
9966c4fe
OZ		 599 if (par->chip == CHIP_360_TRIO3D_1X ||
600 par->chip == CHIP_362_TRIO3D_2X ||
601 par->chip == CHIP_368_TRIO3D_2X) {
602 dbytes = info->var.xres * ((bpp+7)/8);
f8645933
DM		 603 vga_wcrt(par->state.vgabase, 0x91, (dbytes + 7) / 8);
604 vga_wcrt(par->state.vgabase, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80);
9966c4fe 605
f8645933 606 vga_wcrt(par->state.vgabase, 0x66, 0x81);
9966c4fe
OZ		 607 }
608
ea770789 609 svga_wcrt_mask(par->state.vgabase, 0x31, 0x00, 0x40);
a268422d
OZ		 610 multiplex = 0;
611 hmul = 1;
612
613 /* Set mode-specific register values */
614 switch (mode) {
615 case 0:
616 pr_debug("fb%d: text mode\n", info->node);
9c96394b 617 svga_set_textmode_vga_regs(par->state.vgabase);
a268422d
OZ		 618
619 /* Set additional registers like in 8-bit mode */
ea770789
DM		 620 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
621 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
a268422d
OZ		 622
623 /* Disable enhanced mode */
ea770789 624 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
a268422d
OZ		 625
626 if (fasttext) {
627 pr_debug("fb%d: high speed text mode set\n", info->node);
ea770789 628 svga_wcrt_mask(par->state.vgabase, 0x31, 0x40, 0x40);
a268422d
OZ		 629 }
630 break;
631 case 1:
632 pr_debug("fb%d: 4 bit pseudocolor\n", info->node);
f8645933 633 vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40);
a268422d
OZ		 634
635 /* Set additional registers like in 8-bit mode */
ea770789
DM		 636 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
637 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
a268422d
OZ		 638
639 /* disable enhanced mode */
ea770789 640 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
a268422d
OZ		 641 break;
642 case 2:
643 pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node);
644
645 /* Set additional registers like in 8-bit mode */
ea770789
DM		 646 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
647 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
a268422d
OZ		 648
649 /* disable enhanced mode */
ea770789 650 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
a268422d
OZ		 651 break;
652 case 3:
653 pr_debug("fb%d: 8 bit pseudocolor\n", info->node);
ea770789 654 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
9966c4fe
OZ		 655 if (info->var.pixclock > 20000 ||
656 par->chip == CHIP_360_TRIO3D_1X ||
657 par->chip == CHIP_362_TRIO3D_2X ||
658 par->chip == CHIP_368_TRIO3D_2X)
ea770789 659 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
9966c4fe 660 else {
ea770789 661 svga_wcrt_mask(par->state.vgabase, 0x67, 0x10, 0xF0);
a268422d
OZ		 662 multiplex = 1;
663 }
664 break;
665 case 4:
666 pr_debug("fb%d: 5/5/5 truecolor\n", info->node);
667 if (par->chip == CHIP_988_VIRGE_VX) {
668 if (info->var.pixclock > 20000)
ea770789 669 svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0);
a268422d 670 else
ea770789 671 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
a268422d 672 } else {
ea770789
DM		 673 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
674 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
9966c4fe
OZ		 675 if (par->chip != CHIP_360_TRIO3D_1X &&
676 par->chip != CHIP_362_TRIO3D_2X &&
677 par->chip != CHIP_368_TRIO3D_2X)
678 hmul = 2;
a268422d
OZ		 679 }
680 break;
681 case 5:
682 pr_debug("fb%d: 5/6/5 truecolor\n", info->node);
683 if (par->chip == CHIP_988_VIRGE_VX) {
684 if (info->var.pixclock > 20000)
ea770789 685 svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0);
a268422d 686 else
ea770789 687 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
a268422d 688 } else {
ea770789
DM		 689 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
690 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
9966c4fe
OZ		 691 if (par->chip != CHIP_360_TRIO3D_1X &&
692 par->chip != CHIP_362_TRIO3D_2X &&
693 par->chip != CHIP_368_TRIO3D_2X)
694 hmul = 2;
a268422d
OZ		 695 }
696 break;
697 case 6:
698 /* VIRGE VX case */
699 pr_debug("fb%d: 8/8/8 truecolor\n", info->node);
ea770789 700 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0);
a268422d
OZ		 701 break;
702 case 7:
703 pr_debug("fb%d: 8/8/8/8 truecolor\n", info->node);
ea770789
DM		 704 svga_wcrt_mask(par->state.vgabase, 0x50, 0x30, 0x30);
705 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0);
a268422d
OZ		 706 break;
707 default:
708 printk(KERN_ERR "fb%d: unsupported mode - bug\n", info->node);
709 return -EINVAL;
710 }
711
712 if (par->chip != CHIP_988_VIRGE_VX) {
d907ec04
DM		 713 svga_wseq_mask(par->state.vgabase, 0x15, multiplex ? 0x10 : 0x00, 0x10);
714 svga_wseq_mask(par->state.vgabase, 0x18, multiplex ? 0x80 : 0x00, 0x80);
a268422d
OZ		 715 }
716
717 s3_set_pixclock(info, info->var.pixclock);
38d2620e 718 svga_set_timings(par->state.vgabase, &s3_timing_regs, &(info->var), hmul, 1,
a268422d
OZ		 719 (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1,
720 (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1,
721 hmul, info->node);
722
723 /* Set interlaced mode start/end register */
724 value = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len;
725 value = ((value * hmul) / 8) - 5;
f8645933 726 vga_wcrt(par->state.vgabase, 0x3C, (value + 1) / 2);
a268422d 727
75814d87 728 memset_io(info->screen_base, 0x00, screen_size);
a268422d 729 /* Device and screen back on */
ea770789 730 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
d907ec04 731 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
a268422d
OZ		 732
733 return 0;
734}
735
736/* Set a colour register */
737
738static int s3fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
739 u_int transp, struct fb_info *fb)
740{
741 switch (fb->var.bits_per_pixel) {
742 case 0:
743 case 4:
744 if (regno >= 16)
745 return -EINVAL;
746
747 if ((fb->var.bits_per_pixel == 4) &&
748 (fb->var.nonstd == 0)) {
749 outb(0xF0, VGA_PEL_MSK);
750 outb(regno*16, VGA_PEL_IW);
751 } else {
752 outb(0x0F, VGA_PEL_MSK);
753 outb(regno, VGA_PEL_IW);
754 }
755 outb(red >> 10, VGA_PEL_D);
756 outb(green >> 10, VGA_PEL_D);
757 outb(blue >> 10, VGA_PEL_D);
758 break;
759 case 8:
760 if (regno >= 256)
761 return -EINVAL;
762
763 outb(0xFF, VGA_PEL_MSK);
764 outb(regno, VGA_PEL_IW);
765 outb(red >> 10, VGA_PEL_D);
766 outb(green >> 10, VGA_PEL_D);
767 outb(blue >> 10, VGA_PEL_D);
768 break;
769 case 16:
770 if (regno >= 16)
249bdbbf 771 return 0;
a268422d
OZ		 772
773 if (fb->var.green.length == 5)
774 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) |
775 ((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11);
776 else if (fb->var.green.length == 6)
777 ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) |
778 ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11);
779 else return -EINVAL;
780 break;
781 case 24:
782 case 32:
783 if (regno >= 16)
249bdbbf 784 return 0;
a268422d 785
249bdbbf 786 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) |
a268422d
OZ		 787 (green & 0xFF00) | ((blue & 0xFF00) >> 8);
788 break;
789 default:
790 return -EINVAL;
791 }
792
793 return 0;
794}
795
796
797/* Set the display blanking state */
798
799static int s3fb_blank(int blank_mode, struct fb_info *info)
800{
d907ec04
DM		 801 struct s3fb_info *par = info->par;
802
a268422d
OZ		 803 switch (blank_mode) {
804 case FB_BLANK_UNBLANK:
805 pr_debug("fb%d: unblank\n", info->node);
ea770789 806 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06);
d907ec04 807 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
a268422d
OZ		 808 break;
809 case FB_BLANK_NORMAL:
810 pr_debug("fb%d: blank\n", info->node);
ea770789 811 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06);
d907ec04 812 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
a268422d
OZ		 813 break;
814 case FB_BLANK_HSYNC_SUSPEND:
815 pr_debug("fb%d: hsync\n", info->node);
ea770789 816 svga_wcrt_mask(par->state.vgabase, 0x56, 0x02, 0x06);
d907ec04 817 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
a268422d
OZ		 818 break;
819 case FB_BLANK_VSYNC_SUSPEND:
820 pr_debug("fb%d: vsync\n", info->node);
ea770789 821 svga_wcrt_mask(par->state.vgabase, 0x56, 0x04, 0x06);
d907ec04 822 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
a268422d
OZ		 823 break;
824 case FB_BLANK_POWERDOWN:
825 pr_debug("fb%d: sync down\n", info->node);
ea770789 826 svga_wcrt_mask(par->state.vgabase, 0x56, 0x06, 0x06);
d907ec04 827 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
a268422d
OZ		 828 break;
829 }
830
831 return 0;
832}
833
834
835/* Pan the display */
836
21da386d
DM		 837static int s3fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
838{
839 struct s3fb_info *par = info->par;
a268422d
OZ		 840 unsigned int offset;
841
a268422d
OZ		 842 /* Calculate the offset */
843 if (var->bits_per_pixel == 0) {
844 offset = (var->yoffset / 16) * (var->xres_virtual / 2) + (var->xoffset / 2);
845 offset = offset >> 2;
846 } else {
847 offset = (var->yoffset * info->fix.line_length) +
848 (var->xoffset * var->bits_per_pixel / 8);
849 offset = offset >> 2;
850 }
851
852 /* Set the offset */
21da386d 853 svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, offset);
a268422d
OZ		 854
855 return 0;
856}
857
858/* ------------------------------------------------------------------------- */
859
860/* Frame buffer operations */
861
862static struct fb_ops s3fb_ops = {
863 .owner = THIS_MODULE,
864 .fb_open = s3fb_open,
865 .fb_release = s3fb_release,
866 .fb_check_var = s3fb_check_var,
867 .fb_set_par = s3fb_set_par,
868 .fb_setcolreg = s3fb_setcolreg,
869 .fb_blank = s3fb_blank,
870 .fb_pan_display = s3fb_pan_display,
871 .fb_fillrect = s3fb_fillrect,
872 .fb_copyarea = cfb_copyarea,
873 .fb_imageblit = s3fb_imageblit,
5a87ede9 874 .fb_get_caps = svga_get_caps,
a268422d
OZ		 875};
876
877/* ------------------------------------------------------------------------- */
878
f8645933 879static int __devinit s3_identification(struct s3fb_info *par)
a268422d 880{
f8645933
DM		 881 int chip = par->chip;
882
a268422d 883 if (chip == CHIP_XXX_TRIO) {
f8645933
DM		 884 u8 cr30 = vga_rcrt(par->state.vgabase, 0x30);
885 u8 cr2e = vga_rcrt(par->state.vgabase, 0x2e);
886 u8 cr2f = vga_rcrt(par->state.vgabase, 0x2f);
a268422d
OZ		 887
888 if ((cr30 == 0xE0) || (cr30 == 0xE1)) {
889 if (cr2e == 0x10)
890 return CHIP_732_TRIO32;
891 if (cr2e == 0x11) {
892 if (! (cr2f & 0x40))
893 return CHIP_764_TRIO64;
894 else
895 return CHIP_765_TRIO64VP;
896 }
897 }
898 }
899
900 if (chip == CHIP_XXX_TRIO64V2_DXGX) {
f8645933 901 u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f);
a268422d
OZ		 902
903 if (! (cr6f & 0x01))
904 return CHIP_775_TRIO64V2_DX;
905 else
906 return CHIP_785_TRIO64V2_GX;
907 }
908
909 if (chip == CHIP_XXX_VIRGE_DXGX) {
f8645933 910 u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f);
a268422d
OZ		 911
912 if (! (cr6f & 0x01))
913 return CHIP_375_VIRGE_DX;
914 else
915 return CHIP_385_VIRGE_GX;
916 }
917
9966c4fe 918 if (chip == CHIP_36X_TRIO3D_1X_2X) {
f8645933 919 switch (vga_rcrt(par->state.vgabase, 0x2f)) {
9966c4fe
OZ		 920 case 0x00:
921 return CHIP_360_TRIO3D_1X;
922 case 0x01:
923 return CHIP_362_TRIO3D_2X;
924 case 0x02:
925 return CHIP_368_TRIO3D_2X;
926 }
927 }
928
a268422d
OZ		 929 return CHIP_UNKNOWN;
930}
931
932
933/* PCI probe */
934
935static int __devinit s3_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
936{
937 struct fb_info *info;
938 struct s3fb_info *par;
939 int rc;
940 u8 regval, cr38, cr39;
941
942 /* Ignore secondary VGA device because there is no VGA arbitration */
943 if (! svga_primary_device(dev)) {
944 dev_info(&(dev->dev), "ignoring secondary device\n");
945 return -ENODEV;
946 }
947
948 /* Allocate and fill driver data structure */
20e061fb 949 info = framebuffer_alloc(sizeof(struct s3fb_info), &(dev->dev));
a268422d
OZ		 950 if (!info) {
951 dev_err(&(dev->dev), "cannot allocate memory\n");
952 return -ENOMEM;
953 }
954
955 par = info->par;
956 mutex_init(&par->open_lock);
957
958 info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN;
959 info->fbops = &s3fb_ops;
960
961 /* Prepare PCI device */
962 rc = pci_enable_device(dev);
963 if (rc < 0) {
594a8819 964 dev_err(info->device, "cannot enable PCI device\n");
a268422d
OZ		 965 goto err_enable_device;
966 }
967
968 rc = pci_request_regions(dev, "s3fb");
969 if (rc < 0) {
594a8819 970 dev_err(info->device, "cannot reserve framebuffer region\n");
a268422d
OZ		 971 goto err_request_regions;
972 }
973
974
975 info->fix.smem_start = pci_resource_start(dev, 0);
976 info->fix.smem_len = pci_resource_len(dev, 0);
977
978 /* Map physical IO memory address into kernel space */
979 info->screen_base = pci_iomap(dev, 0, 0);
980 if (! info->screen_base) {
981 rc = -ENOMEM;
594a8819 982 dev_err(info->device, "iomap for framebuffer failed\n");
a268422d
OZ		 983 goto err_iomap;
984 }
985
986 /* Unlock regs */
f8645933
DM		 987 cr38 = vga_rcrt(par->state.vgabase, 0x38);
988 cr39 = vga_rcrt(par->state.vgabase, 0x39);
989 vga_wseq(par->state.vgabase, 0x08, 0x06);
990 vga_wcrt(par->state.vgabase, 0x38, 0x48);
991 vga_wcrt(par->state.vgabase, 0x39, 0xA5);
a268422d 992
9966c4fe 993 /* Identify chip type */
a268422d 994 par->chip = id->driver_data & CHIP_MASK;
f8645933 995 par->rev = vga_rcrt(par->state.vgabase, 0x2f);
a268422d 996 if (par->chip & CHIP_UNDECIDED_FLAG)
f8645933 997 par->chip = s3_identification(par);
a268422d 998
9966c4fe
OZ		 999 /* Find how many physical memory there is on card */
1000 /* 0x36 register is accessible even if other registers are locked */
f8645933 1001 regval = vga_rcrt(par->state.vgabase, 0x36);
9966c4fe
OZ		 1002 if (par->chip == CHIP_360_TRIO3D_1X ||
1003 par->chip == CHIP_362_TRIO3D_2X ||
1004 par->chip == CHIP_368_TRIO3D_2X) {
1005 switch ((regval & 0xE0) >> 5) {
1006 case 0: /* 8MB -- only 4MB usable for display */
1007 case 1: /* 4MB with 32-bit bus */
1008 case 2: /* 4MB */
1009 info->screen_size = 4 << 20;
1010 break;
1011 case 6: /* 2MB */
1012 info->screen_size = 2 << 20;
1013 break;
1014 }
1015 } else
1016 info->screen_size = s3_memsizes[regval >> 5] << 10;
1017 info->fix.smem_len = info->screen_size;
1018
a268422d 1019 /* Find MCLK frequency */
f8645933
DM		 1020 regval = vga_rseq(par->state.vgabase, 0x10);
1021 par->mclk_freq = ((vga_rseq(par->state.vgabase, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2);
a268422d
OZ		 1022 par->mclk_freq = par->mclk_freq >> (regval >> 5);
1023
1024 /* Restore locks */
f8645933
DM		 1025 vga_wcrt(par->state.vgabase, 0x38, cr38);
1026 vga_wcrt(par->state.vgabase, 0x39, cr39);
a268422d
OZ		 1027
1028 strcpy(info->fix.id, s3_names [par->chip]);
1029 info->fix.mmio_start = 0;
1030 info->fix.mmio_len = 0;
1031 info->fix.type = FB_TYPE_PACKED_PIXELS;
1032 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1033 info->fix.ypanstep = 0;
1034 info->fix.accel = FB_ACCEL_NONE;
1035 info->pseudo_palette = (void*) (par->pseudo_palette);
1036
1037 /* Prepare startup mode */
a8140543 1038 rc = fb_find_mode(&(info->var), info, mode_option, NULL, 0, NULL, 8);
a268422d
OZ		 1039 if (! ((rc == 1) || (rc == 2))) {
1040 rc = -EINVAL;
594a8819 1041 dev_err(info->device, "mode %s not found\n", mode_option);
a268422d
OZ		 1042 goto err_find_mode;
1043 }
1044
1045 rc = fb_alloc_cmap(&info->cmap, 256, 0);
1046 if (rc < 0) {
594a8819 1047 dev_err(info->device, "cannot allocate colormap\n");
a268422d
OZ		 1048 goto err_alloc_cmap;
1049 }
1050
1051 rc = register_framebuffer(info);
1052 if (rc < 0) {
594a8819 1053 dev_err(info->device, "cannot register framebuffer\n");
a268422d
OZ		 1054 goto err_reg_fb;
1055 }
1056
1057 printk(KERN_INFO "fb%d: %s on %s, %d MB RAM, %d MHz MCLK\n", info->node, info->fix.id,
1058 pci_name(dev), info->fix.smem_len >> 20, (par->mclk_freq + 500) / 1000);
1059
1060 if (par->chip == CHIP_UNKNOWN)
1061 printk(KERN_INFO "fb%d: unknown chip, CR2D=%x, CR2E=%x, CRT2F=%x, CRT30=%x\n",
f8645933
DM		 1062 info->node, vga_rcrt(par->state.vgabase, 0x2d), vga_rcrt(par->state.vgabase, 0x2e),
1063 vga_rcrt(par->state.vgabase, 0x2f), vga_rcrt(par->state.vgabase, 0x30));
a268422d
OZ		 1064
1065 /* Record a reference to the driver data */
1066 pci_set_drvdata(dev, info);
1067
1068#ifdef CONFIG_MTRR
1069 if (mtrr) {
1070 par->mtrr_reg = -1;
1071 par->mtrr_reg = mtrr_add(info->fix.smem_start, info->fix.smem_len, MTRR_TYPE_WRCOMB, 1);
1072 }
1073#endif
1074
1075 return 0;
1076
1077 /* Error handling */
1078err_reg_fb:
1079 fb_dealloc_cmap(&info->cmap);
1080err_alloc_cmap:
1081err_find_mode:
1082 pci_iounmap(dev, info->screen_base);
1083err_iomap:
1084 pci_release_regions(dev);
1085err_request_regions:
1086/* pci_disable_device(dev); */
1087err_enable_device:
1088 framebuffer_release(info);
1089 return rc;
1090}
1091
1092
1093/* PCI remove */
1094
1095static void __devexit s3_pci_remove(struct pci_dev *dev)
1096{
1097 struct fb_info *info = pci_get_drvdata(dev);
a268422d
OZ		 1098
1099 if (info) {
1100
1101#ifdef CONFIG_MTRR
47ebea83
AB		 1102 struct s3fb_info *par = info->par;
1103
a268422d
OZ		 1104 if (par->mtrr_reg >= 0) {
1105 mtrr_del(par->mtrr_reg, 0, 0);
1106 par->mtrr_reg = -1;
1107 }
1108#endif
1109
1110 unregister_framebuffer(info);
1111 fb_dealloc_cmap(&info->cmap);
1112
1113 pci_iounmap(dev, info->screen_base);
1114 pci_release_regions(dev);
1115/* pci_disable_device(dev); */
1116
1117 pci_set_drvdata(dev, NULL);
1118 framebuffer_release(info);
1119 }
1120}
1121
1122/* PCI suspend */
1123
1124static int s3_pci_suspend(struct pci_dev* dev, pm_message_t state)
1125{
1126 struct fb_info *info = pci_get_drvdata(dev);
1127 struct s3fb_info *par = info->par;
1128
594a8819 1129 dev_info(info->device, "suspend\n");
a268422d 1130
ac751efa 1131 console_lock();
a268422d
OZ		 1132 mutex_lock(&(par->open_lock));
1133
1134 if ((state.event == PM_EVENT_FREEZE) || (par->ref_count == 0)) {
1135 mutex_unlock(&(par->open_lock));
ac751efa 1136 console_unlock();
a268422d
OZ		 1137 return 0;
1138 }
1139
1140 fb_set_suspend(info, 1);
1141
1142 pci_save_state(dev);
1143 pci_disable_device(dev);
1144 pci_set_power_state(dev, pci_choose_state(dev, state));
1145
1146 mutex_unlock(&(par->open_lock));
ac751efa 1147 console_unlock();
a268422d
OZ		 1148
1149 return 0;
1150}
1151
1152
1153/* PCI resume */
1154
1155static int s3_pci_resume(struct pci_dev* dev)
1156{
1157 struct fb_info *info = pci_get_drvdata(dev);
1158 struct s3fb_info *par = info->par;
6314db41 1159 int err;
a268422d 1160
594a8819 1161 dev_info(info->device, "resume\n");
a268422d 1162
ac751efa 1163 console_lock();
a268422d
OZ		 1164 mutex_lock(&(par->open_lock));
1165
1166 if (par->ref_count == 0) {
1167 mutex_unlock(&(par->open_lock));
ac751efa 1168 console_unlock();
a268422d
OZ		 1169 return 0;
1170 }
1171
1172 pci_set_power_state(dev, PCI_D0);
1173 pci_restore_state(dev);
6314db41
RD		 1174 err = pci_enable_device(dev);
1175 if (err) {
1176 mutex_unlock(&(par->open_lock));
ac751efa 1177 console_unlock();
594a8819 1178 dev_err(info->device, "error %d enabling device for resume\n", err);
6314db41
RD		 1179 return err;
1180 }
a268422d
OZ		 1181 pci_set_master(dev);
1182
1183 s3fb_set_par(info);
1184 fb_set_suspend(info, 0);
1185
1186 mutex_unlock(&(par->open_lock));
ac751efa 1187 console_unlock();
a268422d
OZ		 1188
1189 return 0;
1190}
1191
1192
1193/* List of boards that we are trying to support */
1194
1195static struct pci_device_id s3_devices[] __devinitdata = {
1196 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8810), .driver_data = CHIP_XXX_TRIO},
1197 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8811), .driver_data = CHIP_XXX_TRIO},
1198 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8812), .driver_data = CHIP_M65_AURORA64VP},
1199 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8814), .driver_data = CHIP_767_TRIO64UVP},
1200 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8901), .driver_data = CHIP_XXX_TRIO64V2_DXGX},
1201 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8902), .driver_data = CHIP_551_PLATO_PX},
1202
1203 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x5631), .driver_data = CHIP_325_VIRGE},
1204 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x883D), .driver_data = CHIP_988_VIRGE_VX},
1205 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A01), .driver_data = CHIP_XXX_VIRGE_DXGX},
1206 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A10), .driver_data = CHIP_356_VIRGE_GX2},
1207 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A11), .driver_data = CHIP_357_VIRGE_GX2P},
1208 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A12), .driver_data = CHIP_359_VIRGE_GX2P},
9966c4fe 1209 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A13), .driver_data = CHIP_36X_TRIO3D_1X_2X},
a268422d
OZ		 1210
1211 {0, 0, 0, 0, 0, 0, 0}
1212};
1213
1214
1215MODULE_DEVICE_TABLE(pci, s3_devices);
1216
1217static struct pci_driver s3fb_pci_driver = {
1218 .name = "s3fb",
1219 .id_table = s3_devices,
1220 .probe = s3_pci_probe,
1221 .remove = __devexit_p(s3_pci_remove),
1222 .suspend = s3_pci_suspend,
1223 .resume = s3_pci_resume,
1224};
1225
1226/* Parse user speficied options */
1227
1228#ifndef MODULE
1229static int __init s3fb_setup(char *options)
1230{
1231 char *opt;
1232
1233 if (!options || !*options)
1234 return 0;
1235
1236 while ((opt = strsep(&options, ",")) != NULL) {
1237
1238 if (!*opt)
1239 continue;
1240#ifdef CONFIG_MTRR
62fa4dc7 1241 else if (!strncmp(opt, "mtrr:", 5))
a268422d
OZ		 1242 mtrr = simple_strtoul(opt + 5, NULL, 0);
1243#endif
62fa4dc7
OZ		 1244 else if (!strncmp(opt, "fasttext:", 9))
1245 fasttext = simple_strtoul(opt + 9, NULL, 0);
a268422d 1246 else
a8140543 1247 mode_option = opt;
a268422d
OZ		 1248 }
1249
1250 return 0;
1251}
1252#endif
1253
1254/* Cleanup */
1255
1256static void __exit s3fb_cleanup(void)
1257{
1258 pr_debug("s3fb: cleaning up\n");
1259 pci_unregister_driver(&s3fb_pci_driver);
1260}
1261
1262/* Driver Initialisation */
1263
1264static int __init s3fb_init(void)
1265{
1266
1267#ifndef MODULE
1268 char *option = NULL;
1269
1270 if (fb_get_options("s3fb", &option))
1271 return -ENODEV;
1272 s3fb_setup(option);
1273#endif
1274
1275 pr_debug("s3fb: initializing\n");
1276 return pci_register_driver(&s3fb_pci_driver);
1277}
1278
1279/* ------------------------------------------------------------------------- */
1280
1281/* Modularization */
1282
1283module_init(s3fb_init);
1284module_exit(s3fb_cleanup);
Linux kernel - Deliverables
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