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svga: Make svga_tilecursor() take an iomem regbase pointer.
[deliverable/linux.git] / drivers / video / s3fb.c
CommitLineData
a268422d
OZ		 1/*
2 * linux/drivers/video/s3fb.c -- Frame buffer device driver for S3 Trio/Virge
3 *
4 * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive for
8 * more details.
9 *
10 * Code is based on David Boucher's viafb (http://davesdomain.org.uk/viafb/)
11 * which is based on the code of neofb.
12 */
13
a268422d
OZ		 14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/errno.h>
17#include <linux/string.h>
18#include <linux/mm.h>
19#include <linux/tty.h>
a268422d
OZ		 20#include <linux/delay.h>
21#include <linux/fb.h>
22#include <linux/svga.h>
23#include <linux/init.h>
24#include <linux/pci.h>
ac751efa 25#include <linux/console.h> /* Why should fb driver call console functions? because console_lock() */
a268422d
OZ		 26#include <video/vga.h>
27
28#ifdef CONFIG_MTRR
29#include <asm/mtrr.h>
30#endif
31
32struct s3fb_info {
33 int chip, rev, mclk_freq;
34 int mtrr_reg;
35 struct vgastate state;
36 struct mutex open_lock;
37 unsigned int ref_count;
38 u32 pseudo_palette[16];
39};
40
41
42/* ------------------------------------------------------------------------- */
43
44static const struct svga_fb_format s3fb_formats[] = {
45 { 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
46 FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4, FB_VISUAL_PSEUDOCOLOR, 8, 16},
c26d7b29 47 { 4, {0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0}, 0,
a268422d 48 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 16},
c26d7b29 49 { 4, {0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0}, 1,
a268422d 50 FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 8, 16},
c26d7b29 51 { 8, {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
a268422d
OZ		 52 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 4, 8},
53 {16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0,
54 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4},
55 {16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0,
56 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4},
57 {24, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
58 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2},
59 {32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
60 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2},
61 SVGA_FORMAT_END
62};
63
64
65static const struct svga_pll s3_pll = {3, 129, 3, 33, 0, 3,
249bdbbf 66 35000, 240000, 14318};
a268422d
OZ		 67
68static const int s3_memsizes[] = {4096, 0, 3072, 8192, 2048, 6144, 1024, 512};
69
70static const char * const s3_names[] = {"S3 Unknown", "S3 Trio32", "S3 Trio64", "S3 Trio64V+",
71 "S3 Trio64UV+", "S3 Trio64V2/DX", "S3 Trio64V2/GX",
72 "S3 Plato/PX", "S3 Aurora64VP", "S3 Virge",
73 "S3 Virge/VX", "S3 Virge/DX", "S3 Virge/GX",
9966c4fe
OZ		 74 "S3 Virge/GX2", "S3 Virge/GX2P", "S3 Virge/GX2P",
75 "S3 Trio3D/1X", "S3 Trio3D/2X", "S3 Trio3D/2X"};
a268422d
OZ		 76
77#define CHIP_UNKNOWN 0x00
78#define CHIP_732_TRIO32 0x01
79#define CHIP_764_TRIO64 0x02
80#define CHIP_765_TRIO64VP 0x03
81#define CHIP_767_TRIO64UVP 0x04
82#define CHIP_775_TRIO64V2_DX 0x05
83#define CHIP_785_TRIO64V2_GX 0x06
84#define CHIP_551_PLATO_PX 0x07
85#define CHIP_M65_AURORA64VP 0x08
86#define CHIP_325_VIRGE 0x09
87#define CHIP_988_VIRGE_VX 0x0A
88#define CHIP_375_VIRGE_DX 0x0B
89#define CHIP_385_VIRGE_GX 0x0C
90#define CHIP_356_VIRGE_GX2 0x0D
91#define CHIP_357_VIRGE_GX2P 0x0E
92#define CHIP_359_VIRGE_GX2P 0x0F
9966c4fe
OZ		 93#define CHIP_360_TRIO3D_1X 0x10
94#define CHIP_362_TRIO3D_2X 0x11
95#define CHIP_368_TRIO3D_2X 0x12
a268422d
OZ		 96
97#define CHIP_XXX_TRIO 0x80
98#define CHIP_XXX_TRIO64V2_DXGX 0x81
99#define CHIP_XXX_VIRGE_DXGX 0x82
9966c4fe 100#define CHIP_36X_TRIO3D_1X_2X 0x83
a268422d
OZ		 101
102#define CHIP_UNDECIDED_FLAG 0x80
103#define CHIP_MASK 0xFF
104
105/* CRT timing register sets */
106
107static const struct vga_regset s3_h_total_regs[] = {{0x00, 0, 7}, {0x5D, 0, 0}, VGA_REGSET_END};
108static const struct vga_regset s3_h_display_regs[] = {{0x01, 0, 7}, {0x5D, 1, 1}, VGA_REGSET_END};
109static const struct vga_regset s3_h_blank_start_regs[] = {{0x02, 0, 7}, {0x5D, 2, 2}, VGA_REGSET_END};
110static const struct vga_regset s3_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7}, VGA_REGSET_END};
111static const struct vga_regset s3_h_sync_start_regs[] = {{0x04, 0, 7}, {0x5D, 4, 4}, VGA_REGSET_END};
112static const struct vga_regset s3_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END};
113
114static const struct vga_regset s3_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x5E, 0, 0}, VGA_REGSET_END};
115static const struct vga_regset s3_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x5E, 1, 1}, VGA_REGSET_END};
116static const struct vga_regset s3_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x5E, 2, 2}, VGA_REGSET_END};
117static const struct vga_regset s3_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END};
118static const struct vga_regset s3_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x5E, 4, 4}, VGA_REGSET_END};
119static const struct vga_regset s3_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END};
120
121static const struct vga_regset s3_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, {0x5E, 6, 6}, VGA_REGSET_END};
122static const struct vga_regset s3_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x31, 4, 5}, {0x51, 0, 1}, VGA_REGSET_END};
123static const struct vga_regset s3_offset_regs[] = {{0x13, 0, 7}, {0x51, 4, 5}, VGA_REGSET_END}; /* set 0x43 bit 2 to 0 */
124
125static const struct svga_timing_regs s3_timing_regs = {
126 s3_h_total_regs, s3_h_display_regs, s3_h_blank_start_regs,
127 s3_h_blank_end_regs, s3_h_sync_start_regs, s3_h_sync_end_regs,
128 s3_v_total_regs, s3_v_display_regs, s3_v_blank_start_regs,
129 s3_v_blank_end_regs, s3_v_sync_start_regs, s3_v_sync_end_regs,
130};
131
132
133/* ------------------------------------------------------------------------- */
134
135/* Module parameters */
136
137
a8140543 138static char *mode_option __devinitdata = "640x480-8@60";
a268422d
OZ		 139
140#ifdef CONFIG_MTRR
a8140543 141static int mtrr __devinitdata = 1;
a268422d
OZ		 142#endif
143
144static int fasttext = 1;
145
146
147MODULE_AUTHOR("(c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>");
148MODULE_LICENSE("GPL");
149MODULE_DESCRIPTION("fbdev driver for S3 Trio/Virge");
150
a8140543
KH		 151module_param(mode_option, charp, 0444);
152MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)");
153module_param_named(mode, mode_option, charp, 0444);
154MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc) (deprecated)");
a268422d
OZ		 155
156#ifdef CONFIG_MTRR
157module_param(mtrr, int, 0444);
158MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");
159#endif
160
161module_param(fasttext, int, 0644);
162MODULE_PARM_DESC(fasttext, "Enable S3 fast text mode (1=enable, 0=disable, default=1)");
163
164
165/* ------------------------------------------------------------------------- */
166
167/* Set font in S3 fast text mode */
168
169static void s3fb_settile_fast(struct fb_info *info, struct fb_tilemap *map)
170{
171 const u8 *font = map->data;
75814d87 172 u8 __iomem *fb = (u8 __iomem *) info->screen_base;
a268422d
OZ		 173 int i, c;
174
175 if ((map->width != 8) || (map->height != 16) ||
176 (map->depth != 1) || (map->length != 256)) {
177 printk(KERN_ERR "fb%d: unsupported font parameters: width %d, height %d, depth %d, length %d\n",
178 info->node, map->width, map->height, map->depth, map->length);
179 return;
180 }
181
182 fb += 2;
183 for (i = 0; i < map->height; i++) {
184 for (c = 0; c < map->length; c++) {
75814d87 185 fb_writeb(font[c * map->height + i], fb + c * 4);
a268422d
OZ		 186 }
187 fb += 1024;
188 }
189}
190
55db0923
DM		 191static void s3fb_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor)
192{
193 struct s3fb_info *par = info->par;
194
195 svga_tilecursor(par->state.vgabase, info, cursor);
196}
197
a268422d
OZ		 198static struct fb_tile_ops s3fb_tile_ops = {
199 .fb_settile = svga_settile,
200 .fb_tilecopy = svga_tilecopy,
201 .fb_tilefill = svga_tilefill,
202 .fb_tileblit = svga_tileblit,
55db0923 203 .fb_tilecursor = s3fb_tilecursor,
34ed25f5 204 .fb_get_tilemax = svga_get_tilemax,
a268422d
OZ		 205};
206
207static struct fb_tile_ops s3fb_fast_tile_ops = {
208 .fb_settile = s3fb_settile_fast,
209 .fb_tilecopy = svga_tilecopy,
210 .fb_tilefill = svga_tilefill,
211 .fb_tileblit = svga_tileblit,
55db0923 212 .fb_tilecursor = s3fb_tilecursor,
34ed25f5 213 .fb_get_tilemax = svga_get_tilemax,
a268422d
OZ		 214};
215
216
217/* ------------------------------------------------------------------------- */
218
219/* image data is MSB-first, fb structure is MSB-first too */
220static inline u32 expand_color(u32 c)
221{
222 return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF;
223}
224
225/* s3fb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */
226static void s3fb_iplan_imageblit(struct fb_info *info, const struct fb_image *image)
227{
228 u32 fg = expand_color(image->fg_color);
229 u32 bg = expand_color(image->bg_color);
230 const u8 *src1, *src;
231 u8 __iomem *dst1;
232 u32 __iomem *dst;
233 u32 val;
234 int x, y;
235
236 src1 = image->data;
237 dst1 = info->screen_base + (image->dy * info->fix.line_length)
238 + ((image->dx / 8) * 4);
239
240 for (y = 0; y < image->height; y++) {
241 src = src1;
242 dst = (u32 __iomem *) dst1;
243 for (x = 0; x < image->width; x += 8) {
244 val = *(src++) * 0x01010101;
245 val = (val & fg) | (~val & bg);
246 fb_writel(val, dst++);
247 }
248 src1 += image->width / 8;
249 dst1 += info->fix.line_length;
250 }
251
252}
253
254/* s3fb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */
255static void s3fb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
256{
257 u32 fg = expand_color(rect->color);
258 u8 __iomem *dst1;
259 u32 __iomem *dst;
260 int x, y;
261
262 dst1 = info->screen_base + (rect->dy * info->fix.line_length)
263 + ((rect->dx / 8) * 4);
264
265 for (y = 0; y < rect->height; y++) {
266 dst = (u32 __iomem *) dst1;
267 for (x = 0; x < rect->width; x += 8) {
268 fb_writel(fg, dst++);
269 }
270 dst1 += info->fix.line_length;
271 }
272}
273
274
275/* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */
276static inline u32 expand_pixel(u32 c)
277{
278 return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) |
279 ((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF;
280}
281
282/* s3fb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */
283static void s3fb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image)
284{
285 u32 fg = image->fg_color * 0x11111111;
286 u32 bg = image->bg_color * 0x11111111;
287 const u8 *src1, *src;
288 u8 __iomem *dst1;
289 u32 __iomem *dst;
290 u32 val;
291 int x, y;
292
293 src1 = image->data;
294 dst1 = info->screen_base + (image->dy * info->fix.line_length)
295 + ((image->dx / 8) * 4);
296
297 for (y = 0; y < image->height; y++) {
298 src = src1;
299 dst = (u32 __iomem *) dst1;
300 for (x = 0; x < image->width; x += 8) {
301 val = expand_pixel(*(src++));
302 val = (val & fg) | (~val & bg);
303 fb_writel(val, dst++);
304 }
305 src1 += image->width / 8;
306 dst1 += info->fix.line_length;
307 }
308}
309
310static void s3fb_imageblit(struct fb_info *info, const struct fb_image *image)
311{
312 if ((info->var.bits_per_pixel == 4) && (image->depth == 1)
313 && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) {
314 if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)
315 s3fb_iplan_imageblit(info, image);
316 else
317 s3fb_cfb4_imageblit(info, image);
318 } else
319 cfb_imageblit(info, image);
320}
321
322static void s3fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
323{
324 if ((info->var.bits_per_pixel == 4)
325 && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0)
326 && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES))
327 s3fb_iplan_fillrect(info, rect);
328 else
329 cfb_fillrect(info, rect);
330}
331
332
333
334/* ------------------------------------------------------------------------- */
335
336
337static void s3_set_pixclock(struct fb_info *info, u32 pixclock)
338{
9966c4fe 339 struct s3fb_info *par = info->par;
a268422d
OZ		 340 u16 m, n, r;
341 u8 regval;
249bdbbf 342 int rv;
a268422d 343
249bdbbf
OZ		 344 rv = svga_compute_pll(&s3_pll, 1000000000 / pixclock, &m, &n, &r, info->node);
345 if (rv < 0) {
346 printk(KERN_ERR "fb%d: cannot set requested pixclock, keeping old value\n", info->node);
347 return;
348 }
a268422d
OZ		 349
350 /* Set VGA misc register */
351 regval = vga_r(NULL, VGA_MIS_R);
352 vga_w(NULL, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
353
354 /* Set S3 clock registers */
9966c4fe
OZ		 355 if (par->chip == CHIP_360_TRIO3D_1X ||
356 par->chip == CHIP_362_TRIO3D_2X ||
357 par->chip == CHIP_368_TRIO3D_2X) {
358 vga_wseq(NULL, 0x12, (n - 2) | ((r & 3) << 6)); /* n and two bits of r */
359 vga_wseq(NULL, 0x29, r >> 2); /* remaining highest bit of r */
360 } else
361 vga_wseq(NULL, 0x12, (n - 2) | (r << 5));
a268422d
OZ		 362 vga_wseq(NULL, 0x13, m - 2);
363
364 udelay(1000);
365
366 /* Activate clock - write 0, 1, 0 to seq/15 bit 5 */
367 regval = vga_rseq (NULL, 0x15); /* | 0x80; */
368 vga_wseq(NULL, 0x15, regval & ~(1<<5));
369 vga_wseq(NULL, 0x15, regval | (1<<5));
370 vga_wseq(NULL, 0x15, regval & ~(1<<5));
371}
372
373
374/* Open framebuffer */
375
376static int s3fb_open(struct fb_info *info, int user)
377{
378 struct s3fb_info *par = info->par;
379
380 mutex_lock(&(par->open_lock));
381 if (par->ref_count == 0) {
382 memset(&(par->state), 0, sizeof(struct vgastate));
383 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP;
384 par->state.num_crtc = 0x70;
385 par->state.num_seq = 0x20;
386 save_vga(&(par->state));
387 }
388
389 par->ref_count++;
390 mutex_unlock(&(par->open_lock));
391
392 return 0;
393}
394
395/* Close framebuffer */
396
397static int s3fb_release(struct fb_info *info, int user)
398{
399 struct s3fb_info *par = info->par;
400
401 mutex_lock(&(par->open_lock));
402 if (par->ref_count == 0) {
403 mutex_unlock(&(par->open_lock));
404 return -EINVAL;
405 }
406
407 if (par->ref_count == 1)
408 restore_vga(&(par->state));
409
410 par->ref_count--;
411 mutex_unlock(&(par->open_lock));
412
413 return 0;
414}
415
416/* Validate passed in var */
417
418static int s3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
419{
420 struct s3fb_info *par = info->par;
421 int rv, mem, step;
c3ca34f9 422 u16 m, n, r;
a268422d
OZ		 423
424 /* Find appropriate format */
425 rv = svga_match_format (s3fb_formats, var, NULL);
d4b766a0
OZ		 426
427 /* 32bpp mode is not supported on VIRGE VX,
428 24bpp is not supported on others */
429 if ((par->chip == CHIP_988_VIRGE_VX) ? (rv == 7) : (rv == 6))
430 rv = -EINVAL;
431
432 if (rv < 0) {
a268422d
OZ		 433 printk(KERN_ERR "fb%d: unsupported mode requested\n", info->node);
434 return rv;
435 }
436
437 /* Do not allow to have real resoulution larger than virtual */
438 if (var->xres > var->xres_virtual)
439 var->xres_virtual = var->xres;
440
441 if (var->yres > var->yres_virtual)
442 var->yres_virtual = var->yres;
443
444 /* Round up xres_virtual to have proper alignment of lines */
445 step = s3fb_formats[rv].xresstep - 1;
446 var->xres_virtual = (var->xres_virtual+step) & ~step;
447
448 /* Check whether have enough memory */
449 mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual;
c3ca34f9 450 if (mem > info->screen_size) {
a268422d
OZ		 451 printk(KERN_ERR "fb%d: not enough framebuffer memory (%d kB requested , %d kB available)\n",
452 info->node, mem >> 10, (unsigned int) (info->screen_size >> 10));
453 return -EINVAL;
454 }
455
456 rv = svga_check_timings (&s3_timing_regs, var, info->node);
c3ca34f9 457 if (rv < 0) {
a268422d
OZ		 458 printk(KERN_ERR "fb%d: invalid timings requested\n", info->node);
459 return rv;
460 }
461
c3ca34f9
KH		 462 rv = svga_compute_pll(&s3_pll, PICOS2KHZ(var->pixclock), &m, &n, &r,
463 info->node);
464 if (rv < 0) {
465 printk(KERN_ERR "fb%d: invalid pixclock value requested\n",
466 info->node);
467 return rv;
468 }
469
a268422d
OZ		 470 return 0;
471}
472
473/* Set video mode from par */
474
475static int s3fb_set_par(struct fb_info *info)
476{
477 struct s3fb_info *par = info->par;
9966c4fe 478 u32 value, mode, hmul, offset_value, screen_size, multiplex, dbytes;
a268422d
OZ		 479 u32 bpp = info->var.bits_per_pixel;
480
481 if (bpp != 0) {
482 info->fix.ypanstep = 1;
483 info->fix.line_length = (info->var.xres_virtual * bpp) / 8;
484
485 info->flags &= ~FBINFO_MISC_TILEBLITTING;
486 info->tileops = NULL;
487
34ed25f5
OZ		 488 /* in 4bpp supports 8p wide tiles only, any tiles otherwise */
489 info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0);
8db51668 490 info->pixmap.blit_y = ~(u32)0;
34ed25f5 491
a268422d
OZ		 492 offset_value = (info->var.xres_virtual * bpp) / 64;
493 screen_size = info->var.yres_virtual * info->fix.line_length;
494 } else {
495 info->fix.ypanstep = 16;
496 info->fix.line_length = 0;
497
498 info->flags |= FBINFO_MISC_TILEBLITTING;
499 info->tileops = fasttext ? &s3fb_fast_tile_ops : &s3fb_tile_ops;
34ed25f5 500
8db51668
AD		 501 /* supports 8x16 tiles only */
502 info->pixmap.blit_x = 1 << (8 - 1);
503 info->pixmap.blit_y = 1 << (16 - 1);
a268422d
OZ		 504
505 offset_value = info->var.xres_virtual / 16;
506 screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64;
507 }
508
509 info->var.xoffset = 0;
510 info->var.yoffset = 0;
511 info->var.activate = FB_ACTIVATE_NOW;
512
513 /* Unlock registers */
514 vga_wcrt(NULL, 0x38, 0x48);
515 vga_wcrt(NULL, 0x39, 0xA5);
516 vga_wseq(NULL, 0x08, 0x06);
ea770789 517 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80);
a268422d
OZ		 518
519 /* Blank screen and turn off sync */
d907ec04 520 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
ea770789 521 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
a268422d
OZ		 522
523 /* Set default values */
e2fade2c 524 svga_set_default_gfx_regs(par->state.vgabase);
f51a14dd 525 svga_set_default_atc_regs(par->state.vgabase);
a4ade839 526 svga_set_default_seq_regs(par->state.vgabase);
1d28fcad 527 svga_set_default_crt_regs(par->state.vgabase);
21da386d
DM		 528 svga_wcrt_multi(par->state.vgabase, s3_line_compare_regs, 0xFFFFFFFF);
529 svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, 0);
a268422d
OZ		 530
531 /* S3 specific initialization */
ea770789
DM		 532 svga_wcrt_mask(par->state.vgabase, 0x58, 0x10, 0x10); /* enable linear framebuffer */
533 svga_wcrt_mask(par->state.vgabase, 0x31, 0x08, 0x08); /* enable sequencer access to framebuffer above 256 kB */
a268422d 534
ea770789
DM		 535/* svga_wcrt_mask(par->state.vgabase, 0x33, 0x08, 0x08); */ /* DDR ? */
536/* svga_wcrt_mask(par->state.vgabase, 0x43, 0x01, 0x01); */ /* DDR ? */
537 svga_wcrt_mask(par->state.vgabase, 0x33, 0x00, 0x08); /* no DDR ? */
538 svga_wcrt_mask(par->state.vgabase, 0x43, 0x00, 0x01); /* no DDR ? */
a268422d 539
ea770789 540 svga_wcrt_mask(par->state.vgabase, 0x5D, 0x00, 0x28); /* Clear strange HSlen bits */
a268422d 541
ea770789 542/* svga_wcrt_mask(par->state.vgabase, 0x58, 0x03, 0x03); */
a268422d 543
ea770789
DM		 544/* svga_wcrt_mask(par->state.vgabase, 0x53, 0x12, 0x13); */ /* enable MMIO */
545/* svga_wcrt_mask(par->state.vgabase, 0x40, 0x08, 0x08); */ /* enable write buffer */
a268422d
OZ		 546
547
548 /* Set the offset register */
549 pr_debug("fb%d: offset register : %d\n", info->node, offset_value);
21da386d 550 svga_wcrt_multi(par->state.vgabase, s3_offset_regs, offset_value);
a268422d 551
9966c4fe
OZ		 552 if (par->chip != CHIP_360_TRIO3D_1X &&
553 par->chip != CHIP_362_TRIO3D_2X &&
554 par->chip != CHIP_368_TRIO3D_2X) {
555 vga_wcrt(NULL, 0x54, 0x18); /* M parameter */
556 vga_wcrt(NULL, 0x60, 0xff); /* N parameter */
557 vga_wcrt(NULL, 0x61, 0xff); /* L parameter */
558 vga_wcrt(NULL, 0x62, 0xff); /* L parameter */
559 }
a268422d
OZ		 560
561 vga_wcrt(NULL, 0x3A, 0x35);
f6b0cc47 562 svga_wattr(par->state.vgabase, 0x33, 0x00);
a268422d
OZ		 563
564 if (info->var.vmode & FB_VMODE_DOUBLE)
ea770789 565 svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80);
a268422d 566 else
ea770789 567 svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80);
a268422d
OZ		 568
569 if (info->var.vmode & FB_VMODE_INTERLACED)
ea770789 570 svga_wcrt_mask(par->state.vgabase, 0x42, 0x20, 0x20);
a268422d 571 else
ea770789 572 svga_wcrt_mask(par->state.vgabase, 0x42, 0x00, 0x20);
a268422d
OZ		 573
574 /* Disable hardware graphics cursor */
ea770789 575 svga_wcrt_mask(par->state.vgabase, 0x45, 0x00, 0x01);
a268422d 576 /* Disable Streams engine */
ea770789 577 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0x0C);
a268422d
OZ		 578
579 mode = svga_match_format(s3fb_formats, &(info->var), &(info->fix));
580
581 /* S3 virge DX hack */
582 if (par->chip == CHIP_375_VIRGE_DX) {
583 vga_wcrt(NULL, 0x86, 0x80);
584 vga_wcrt(NULL, 0x90, 0x00);
585 }
586
587 /* S3 virge VX hack */
588 if (par->chip == CHIP_988_VIRGE_VX) {
589 vga_wcrt(NULL, 0x50, 0x00);
590 vga_wcrt(NULL, 0x67, 0x50);
591
592 vga_wcrt(NULL, 0x63, (mode <= 2) ? 0x90 : 0x09);
593 vga_wcrt(NULL, 0x66, 0x90);
594 }
595
9966c4fe
OZ		 596 if (par->chip == CHIP_360_TRIO3D_1X ||
597 par->chip == CHIP_362_TRIO3D_2X ||
598 par->chip == CHIP_368_TRIO3D_2X) {
599 dbytes = info->var.xres * ((bpp+7)/8);
600 vga_wcrt(NULL, 0x91, (dbytes + 7) / 8);
601 vga_wcrt(NULL, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80);
602
603 vga_wcrt(NULL, 0x66, 0x81);
604 }
605
ea770789 606 svga_wcrt_mask(par->state.vgabase, 0x31, 0x00, 0x40);
a268422d
OZ		 607 multiplex = 0;
608 hmul = 1;
609
610 /* Set mode-specific register values */
611 switch (mode) {
612 case 0:
613 pr_debug("fb%d: text mode\n", info->node);
9c96394b 614 svga_set_textmode_vga_regs(par->state.vgabase);
a268422d
OZ		 615
616 /* Set additional registers like in 8-bit mode */
ea770789
DM		 617 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
618 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
a268422d
OZ		 619
620 /* Disable enhanced mode */
ea770789 621 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
a268422d
OZ		 622
623 if (fasttext) {
624 pr_debug("fb%d: high speed text mode set\n", info->node);
ea770789 625 svga_wcrt_mask(par->state.vgabase, 0x31, 0x40, 0x40);
a268422d
OZ		 626 }
627 break;
628 case 1:
629 pr_debug("fb%d: 4 bit pseudocolor\n", info->node);
630 vga_wgfx(NULL, VGA_GFX_MODE, 0x40);
631
632 /* Set additional registers like in 8-bit mode */
ea770789
DM		 633 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
634 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
a268422d
OZ		 635
636 /* disable enhanced mode */
ea770789 637 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
a268422d
OZ		 638 break;
639 case 2:
640 pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node);
641
642 /* Set additional registers like in 8-bit mode */
ea770789
DM		 643 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
644 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
a268422d
OZ		 645
646 /* disable enhanced mode */
ea770789 647 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
a268422d
OZ		 648 break;
649 case 3:
650 pr_debug("fb%d: 8 bit pseudocolor\n", info->node);
ea770789 651 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
9966c4fe
OZ		 652 if (info->var.pixclock > 20000 ||
653 par->chip == CHIP_360_TRIO3D_1X ||
654 par->chip == CHIP_362_TRIO3D_2X ||
655 par->chip == CHIP_368_TRIO3D_2X)
ea770789 656 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
9966c4fe 657 else {
ea770789 658 svga_wcrt_mask(par->state.vgabase, 0x67, 0x10, 0xF0);
a268422d
OZ		 659 multiplex = 1;
660 }
661 break;
662 case 4:
663 pr_debug("fb%d: 5/5/5 truecolor\n", info->node);
664 if (par->chip == CHIP_988_VIRGE_VX) {
665 if (info->var.pixclock > 20000)
ea770789 666 svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0);
a268422d 667 else
ea770789 668 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
a268422d 669 } else {
ea770789
DM		 670 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
671 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
9966c4fe
OZ		 672 if (par->chip != CHIP_360_TRIO3D_1X &&
673 par->chip != CHIP_362_TRIO3D_2X &&
674 par->chip != CHIP_368_TRIO3D_2X)
675 hmul = 2;
a268422d
OZ		 676 }
677 break;
678 case 5:
679 pr_debug("fb%d: 5/6/5 truecolor\n", info->node);
680 if (par->chip == CHIP_988_VIRGE_VX) {
681 if (info->var.pixclock > 20000)
ea770789 682 svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0);
a268422d 683 else
ea770789 684 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
a268422d 685 } else {
ea770789
DM		 686 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
687 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
9966c4fe
OZ		 688 if (par->chip != CHIP_360_TRIO3D_1X &&
689 par->chip != CHIP_362_TRIO3D_2X &&
690 par->chip != CHIP_368_TRIO3D_2X)
691 hmul = 2;
a268422d
OZ		 692 }
693 break;
694 case 6:
695 /* VIRGE VX case */
696 pr_debug("fb%d: 8/8/8 truecolor\n", info->node);
ea770789 697 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0);
a268422d
OZ		 698 break;
699 case 7:
700 pr_debug("fb%d: 8/8/8/8 truecolor\n", info->node);
ea770789
DM		 701 svga_wcrt_mask(par->state.vgabase, 0x50, 0x30, 0x30);
702 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0);
a268422d
OZ		 703 break;
704 default:
705 printk(KERN_ERR "fb%d: unsupported mode - bug\n", info->node);
706 return -EINVAL;
707 }
708
709 if (par->chip != CHIP_988_VIRGE_VX) {
d907ec04
DM		 710 svga_wseq_mask(par->state.vgabase, 0x15, multiplex ? 0x10 : 0x00, 0x10);
711 svga_wseq_mask(par->state.vgabase, 0x18, multiplex ? 0x80 : 0x00, 0x80);
a268422d
OZ		 712 }
713
714 s3_set_pixclock(info, info->var.pixclock);
715 svga_set_timings(&s3_timing_regs, &(info->var), hmul, 1,
716 (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1,
717 (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1,
718 hmul, info->node);
719
720 /* Set interlaced mode start/end register */
721 value = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len;
722 value = ((value * hmul) / 8) - 5;
723 vga_wcrt(NULL, 0x3C, (value + 1) / 2);
724
75814d87 725 memset_io(info->screen_base, 0x00, screen_size);
a268422d 726 /* Device and screen back on */
ea770789 727 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
d907ec04 728 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
a268422d
OZ		 729
730 return 0;
731}
732
733/* Set a colour register */
734
735static int s3fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
736 u_int transp, struct fb_info *fb)
737{
738 switch (fb->var.bits_per_pixel) {
739 case 0:
740 case 4:
741 if (regno >= 16)
742 return -EINVAL;
743
744 if ((fb->var.bits_per_pixel == 4) &&
745 (fb->var.nonstd == 0)) {
746 outb(0xF0, VGA_PEL_MSK);
747 outb(regno*16, VGA_PEL_IW);
748 } else {
749 outb(0x0F, VGA_PEL_MSK);
750 outb(regno, VGA_PEL_IW);
751 }
752 outb(red >> 10, VGA_PEL_D);
753 outb(green >> 10, VGA_PEL_D);
754 outb(blue >> 10, VGA_PEL_D);
755 break;
756 case 8:
757 if (regno >= 256)
758 return -EINVAL;
759
760 outb(0xFF, VGA_PEL_MSK);
761 outb(regno, VGA_PEL_IW);
762 outb(red >> 10, VGA_PEL_D);
763 outb(green >> 10, VGA_PEL_D);
764 outb(blue >> 10, VGA_PEL_D);
765 break;
766 case 16:
767 if (regno >= 16)
249bdbbf 768 return 0;
a268422d
OZ		 769
770 if (fb->var.green.length == 5)
771 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) |
772 ((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11);
773 else if (fb->var.green.length == 6)
774 ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) |
775 ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11);
776 else return -EINVAL;
777 break;
778 case 24:
779 case 32:
780 if (regno >= 16)
249bdbbf 781 return 0;
a268422d 782
249bdbbf 783 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) |
a268422d
OZ		 784 (green & 0xFF00) | ((blue & 0xFF00) >> 8);
785 break;
786 default:
787 return -EINVAL;
788 }
789
790 return 0;
791}
792
793
794/* Set the display blanking state */
795
796static int s3fb_blank(int blank_mode, struct fb_info *info)
797{
d907ec04
DM		 798 struct s3fb_info *par = info->par;
799
a268422d
OZ		 800 switch (blank_mode) {
801 case FB_BLANK_UNBLANK:
802 pr_debug("fb%d: unblank\n", info->node);
ea770789 803 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06);
d907ec04 804 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
a268422d
OZ		 805 break;
806 case FB_BLANK_NORMAL:
807 pr_debug("fb%d: blank\n", info->node);
ea770789 808 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06);
d907ec04 809 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
a268422d
OZ		 810 break;
811 case FB_BLANK_HSYNC_SUSPEND:
812 pr_debug("fb%d: hsync\n", info->node);
ea770789 813 svga_wcrt_mask(par->state.vgabase, 0x56, 0x02, 0x06);
d907ec04 814 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
a268422d
OZ		 815 break;
816 case FB_BLANK_VSYNC_SUSPEND:
817 pr_debug("fb%d: vsync\n", info->node);
ea770789 818 svga_wcrt_mask(par->state.vgabase, 0x56, 0x04, 0x06);
d907ec04 819 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
a268422d
OZ		 820 break;
821 case FB_BLANK_POWERDOWN:
822 pr_debug("fb%d: sync down\n", info->node);
ea770789 823 svga_wcrt_mask(par->state.vgabase, 0x56, 0x06, 0x06);
d907ec04 824 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
a268422d
OZ		 825 break;
826 }
827
828 return 0;
829}
830
831
832/* Pan the display */
833
21da386d
DM		 834static int s3fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
835{
836 struct s3fb_info *par = info->par;
a268422d
OZ		 837 unsigned int offset;
838
a268422d
OZ		 839 /* Calculate the offset */
840 if (var->bits_per_pixel == 0) {
841 offset = (var->yoffset / 16) * (var->xres_virtual / 2) + (var->xoffset / 2);
842 offset = offset >> 2;
843 } else {
844 offset = (var->yoffset * info->fix.line_length) +
845 (var->xoffset * var->bits_per_pixel / 8);
846 offset = offset >> 2;
847 }
848
849 /* Set the offset */
21da386d 850 svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, offset);
a268422d
OZ		 851
852 return 0;
853}
854
855/* ------------------------------------------------------------------------- */
856
857/* Frame buffer operations */
858
859static struct fb_ops s3fb_ops = {
860 .owner = THIS_MODULE,
861 .fb_open = s3fb_open,
862 .fb_release = s3fb_release,
863 .fb_check_var = s3fb_check_var,
864 .fb_set_par = s3fb_set_par,
865 .fb_setcolreg = s3fb_setcolreg,
866 .fb_blank = s3fb_blank,
867 .fb_pan_display = s3fb_pan_display,
868 .fb_fillrect = s3fb_fillrect,
869 .fb_copyarea = cfb_copyarea,
870 .fb_imageblit = s3fb_imageblit,
5a87ede9 871 .fb_get_caps = svga_get_caps,
a268422d
OZ		 872};
873
874/* ------------------------------------------------------------------------- */
875
876static int __devinit s3_identification(int chip)
877{
878 if (chip == CHIP_XXX_TRIO) {
879 u8 cr30 = vga_rcrt(NULL, 0x30);
880 u8 cr2e = vga_rcrt(NULL, 0x2e);
881 u8 cr2f = vga_rcrt(NULL, 0x2f);
882
883 if ((cr30 == 0xE0) || (cr30 == 0xE1)) {
884 if (cr2e == 0x10)
885 return CHIP_732_TRIO32;
886 if (cr2e == 0x11) {
887 if (! (cr2f & 0x40))
888 return CHIP_764_TRIO64;
889 else
890 return CHIP_765_TRIO64VP;
891 }
892 }
893 }
894
895 if (chip == CHIP_XXX_TRIO64V2_DXGX) {
896 u8 cr6f = vga_rcrt(NULL, 0x6f);
897
898 if (! (cr6f & 0x01))
899 return CHIP_775_TRIO64V2_DX;
900 else
901 return CHIP_785_TRIO64V2_GX;
902 }
903
904 if (chip == CHIP_XXX_VIRGE_DXGX) {
905 u8 cr6f = vga_rcrt(NULL, 0x6f);
906
907 if (! (cr6f & 0x01))
908 return CHIP_375_VIRGE_DX;
909 else
910 return CHIP_385_VIRGE_GX;
911 }
912
9966c4fe
OZ		 913 if (chip == CHIP_36X_TRIO3D_1X_2X) {
914 switch (vga_rcrt(NULL, 0x2f)) {
915 case 0x00:
916 return CHIP_360_TRIO3D_1X;
917 case 0x01:
918 return CHIP_362_TRIO3D_2X;
919 case 0x02:
920 return CHIP_368_TRIO3D_2X;
921 }
922 }
923
a268422d
OZ		 924 return CHIP_UNKNOWN;
925}
926
927
928/* PCI probe */
929
930static int __devinit s3_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
931{
932 struct fb_info *info;
933 struct s3fb_info *par;
934 int rc;
935 u8 regval, cr38, cr39;
936
937 /* Ignore secondary VGA device because there is no VGA arbitration */
938 if (! svga_primary_device(dev)) {
939 dev_info(&(dev->dev), "ignoring secondary device\n");
940 return -ENODEV;
941 }
942
943 /* Allocate and fill driver data structure */
20e061fb 944 info = framebuffer_alloc(sizeof(struct s3fb_info), &(dev->dev));
a268422d
OZ		 945 if (!info) {
946 dev_err(&(dev->dev), "cannot allocate memory\n");
947 return -ENOMEM;
948 }
949
950 par = info->par;
951 mutex_init(&par->open_lock);
952
953 info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN;
954 info->fbops = &s3fb_ops;
955
956 /* Prepare PCI device */
957 rc = pci_enable_device(dev);
958 if (rc < 0) {
594a8819 959 dev_err(info->device, "cannot enable PCI device\n");
a268422d
OZ		 960 goto err_enable_device;
961 }
962
963 rc = pci_request_regions(dev, "s3fb");
964 if (rc < 0) {
594a8819 965 dev_err(info->device, "cannot reserve framebuffer region\n");
a268422d
OZ		 966 goto err_request_regions;
967 }
968
969
970 info->fix.smem_start = pci_resource_start(dev, 0);
971 info->fix.smem_len = pci_resource_len(dev, 0);
972
973 /* Map physical IO memory address into kernel space */
974 info->screen_base = pci_iomap(dev, 0, 0);
975 if (! info->screen_base) {
976 rc = -ENOMEM;
594a8819 977 dev_err(info->device, "iomap for framebuffer failed\n");
a268422d
OZ		 978 goto err_iomap;
979 }
980
981 /* Unlock regs */
982 cr38 = vga_rcrt(NULL, 0x38);
983 cr39 = vga_rcrt(NULL, 0x39);
984 vga_wseq(NULL, 0x08, 0x06);
985 vga_wcrt(NULL, 0x38, 0x48);
986 vga_wcrt(NULL, 0x39, 0xA5);
987
9966c4fe 988 /* Identify chip type */
a268422d
OZ		 989 par->chip = id->driver_data & CHIP_MASK;
990 par->rev = vga_rcrt(NULL, 0x2f);
991 if (par->chip & CHIP_UNDECIDED_FLAG)
992 par->chip = s3_identification(par->chip);
993
9966c4fe
OZ		 994 /* Find how many physical memory there is on card */
995 /* 0x36 register is accessible even if other registers are locked */
996 regval = vga_rcrt(NULL, 0x36);
997 if (par->chip == CHIP_360_TRIO3D_1X ||
998 par->chip == CHIP_362_TRIO3D_2X ||
999 par->chip == CHIP_368_TRIO3D_2X) {
1000 switch ((regval & 0xE0) >> 5) {
1001 case 0: /* 8MB -- only 4MB usable for display */
1002 case 1: /* 4MB with 32-bit bus */
1003 case 2: /* 4MB */
1004 info->screen_size = 4 << 20;
1005 break;
1006 case 6: /* 2MB */
1007 info->screen_size = 2 << 20;
1008 break;
1009 }
1010 } else
1011 info->screen_size = s3_memsizes[regval >> 5] << 10;
1012 info->fix.smem_len = info->screen_size;
1013
a268422d
OZ		 1014 /* Find MCLK frequency */
1015 regval = vga_rseq(NULL, 0x10);
1016 par->mclk_freq = ((vga_rseq(NULL, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2);
1017 par->mclk_freq = par->mclk_freq >> (regval >> 5);
1018
1019 /* Restore locks */
1020 vga_wcrt(NULL, 0x38, cr38);
1021 vga_wcrt(NULL, 0x39, cr39);
1022
1023 strcpy(info->fix.id, s3_names [par->chip]);
1024 info->fix.mmio_start = 0;
1025 info->fix.mmio_len = 0;
1026 info->fix.type = FB_TYPE_PACKED_PIXELS;
1027 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1028 info->fix.ypanstep = 0;
1029 info->fix.accel = FB_ACCEL_NONE;
1030 info->pseudo_palette = (void*) (par->pseudo_palette);
1031
1032 /* Prepare startup mode */
a8140543 1033 rc = fb_find_mode(&(info->var), info, mode_option, NULL, 0, NULL, 8);
a268422d
OZ		 1034 if (! ((rc == 1) || (rc == 2))) {
1035 rc = -EINVAL;
594a8819 1036 dev_err(info->device, "mode %s not found\n", mode_option);
a268422d
OZ		 1037 goto err_find_mode;
1038 }
1039
1040 rc = fb_alloc_cmap(&info->cmap, 256, 0);
1041 if (rc < 0) {
594a8819 1042 dev_err(info->device, "cannot allocate colormap\n");
a268422d
OZ		 1043 goto err_alloc_cmap;
1044 }
1045
1046 rc = register_framebuffer(info);
1047 if (rc < 0) {
594a8819 1048 dev_err(info->device, "cannot register framebuffer\n");
a268422d
OZ		 1049 goto err_reg_fb;
1050 }
1051
1052 printk(KERN_INFO "fb%d: %s on %s, %d MB RAM, %d MHz MCLK\n", info->node, info->fix.id,
1053 pci_name(dev), info->fix.smem_len >> 20, (par->mclk_freq + 500) / 1000);
1054
1055 if (par->chip == CHIP_UNKNOWN)
1056 printk(KERN_INFO "fb%d: unknown chip, CR2D=%x, CR2E=%x, CRT2F=%x, CRT30=%x\n",
1057 info->node, vga_rcrt(NULL, 0x2d), vga_rcrt(NULL, 0x2e),
1058 vga_rcrt(NULL, 0x2f), vga_rcrt(NULL, 0x30));
1059
1060 /* Record a reference to the driver data */
1061 pci_set_drvdata(dev, info);
1062
1063#ifdef CONFIG_MTRR
1064 if (mtrr) {
1065 par->mtrr_reg = -1;
1066 par->mtrr_reg = mtrr_add(info->fix.smem_start, info->fix.smem_len, MTRR_TYPE_WRCOMB, 1);
1067 }
1068#endif
1069
1070 return 0;
1071
1072 /* Error handling */
1073err_reg_fb:
1074 fb_dealloc_cmap(&info->cmap);
1075err_alloc_cmap:
1076err_find_mode:
1077 pci_iounmap(dev, info->screen_base);
1078err_iomap:
1079 pci_release_regions(dev);
1080err_request_regions:
1081/* pci_disable_device(dev); */
1082err_enable_device:
1083 framebuffer_release(info);
1084 return rc;
1085}
1086
1087
1088/* PCI remove */
1089
1090static void __devexit s3_pci_remove(struct pci_dev *dev)
1091{
1092 struct fb_info *info = pci_get_drvdata(dev);
a268422d
OZ		 1093
1094 if (info) {
1095
1096#ifdef CONFIG_MTRR
47ebea83
AB		 1097 struct s3fb_info *par = info->par;
1098
a268422d
OZ		 1099 if (par->mtrr_reg >= 0) {
1100 mtrr_del(par->mtrr_reg, 0, 0);
1101 par->mtrr_reg = -1;
1102 }
1103#endif
1104
1105 unregister_framebuffer(info);
1106 fb_dealloc_cmap(&info->cmap);
1107
1108 pci_iounmap(dev, info->screen_base);
1109 pci_release_regions(dev);
1110/* pci_disable_device(dev); */
1111
1112 pci_set_drvdata(dev, NULL);
1113 framebuffer_release(info);
1114 }
1115}
1116
1117/* PCI suspend */
1118
1119static int s3_pci_suspend(struct pci_dev* dev, pm_message_t state)
1120{
1121 struct fb_info *info = pci_get_drvdata(dev);
1122 struct s3fb_info *par = info->par;
1123
594a8819 1124 dev_info(info->device, "suspend\n");
a268422d 1125
ac751efa 1126 console_lock();
a268422d
OZ		 1127 mutex_lock(&(par->open_lock));
1128
1129 if ((state.event == PM_EVENT_FREEZE) || (par->ref_count == 0)) {
1130 mutex_unlock(&(par->open_lock));
ac751efa 1131 console_unlock();
a268422d
OZ		 1132 return 0;
1133 }
1134
1135 fb_set_suspend(info, 1);
1136
1137 pci_save_state(dev);
1138 pci_disable_device(dev);
1139 pci_set_power_state(dev, pci_choose_state(dev, state));
1140
1141 mutex_unlock(&(par->open_lock));
ac751efa 1142 console_unlock();
a268422d
OZ		 1143
1144 return 0;
1145}
1146
1147
1148/* PCI resume */
1149
1150static int s3_pci_resume(struct pci_dev* dev)
1151{
1152 struct fb_info *info = pci_get_drvdata(dev);
1153 struct s3fb_info *par = info->par;
6314db41 1154 int err;
a268422d 1155
594a8819 1156 dev_info(info->device, "resume\n");
a268422d 1157
ac751efa 1158 console_lock();
a268422d
OZ		 1159 mutex_lock(&(par->open_lock));
1160
1161 if (par->ref_count == 0) {
1162 mutex_unlock(&(par->open_lock));
ac751efa 1163 console_unlock();
a268422d
OZ		 1164 return 0;
1165 }
1166
1167 pci_set_power_state(dev, PCI_D0);
1168 pci_restore_state(dev);
6314db41
RD		 1169 err = pci_enable_device(dev);
1170 if (err) {
1171 mutex_unlock(&(par->open_lock));
ac751efa 1172 console_unlock();
594a8819 1173 dev_err(info->device, "error %d enabling device for resume\n", err);
6314db41
RD		 1174 return err;
1175 }
a268422d
OZ		 1176 pci_set_master(dev);
1177
1178 s3fb_set_par(info);
1179 fb_set_suspend(info, 0);
1180
1181 mutex_unlock(&(par->open_lock));
ac751efa 1182 console_unlock();
a268422d
OZ		 1183
1184 return 0;
1185}
1186
1187
1188/* List of boards that we are trying to support */
1189
1190static struct pci_device_id s3_devices[] __devinitdata = {
1191 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8810), .driver_data = CHIP_XXX_TRIO},
1192 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8811), .driver_data = CHIP_XXX_TRIO},
1193 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8812), .driver_data = CHIP_M65_AURORA64VP},
1194 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8814), .driver_data = CHIP_767_TRIO64UVP},
1195 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8901), .driver_data = CHIP_XXX_TRIO64V2_DXGX},
1196 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8902), .driver_data = CHIP_551_PLATO_PX},
1197
1198 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x5631), .driver_data = CHIP_325_VIRGE},
1199 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x883D), .driver_data = CHIP_988_VIRGE_VX},
1200 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A01), .driver_data = CHIP_XXX_VIRGE_DXGX},
1201 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A10), .driver_data = CHIP_356_VIRGE_GX2},
1202 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A11), .driver_data = CHIP_357_VIRGE_GX2P},
1203 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A12), .driver_data = CHIP_359_VIRGE_GX2P},
9966c4fe 1204 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A13), .driver_data = CHIP_36X_TRIO3D_1X_2X},
a268422d
OZ		 1205
1206 {0, 0, 0, 0, 0, 0, 0}
1207};
1208
1209
1210MODULE_DEVICE_TABLE(pci, s3_devices);
1211
1212static struct pci_driver s3fb_pci_driver = {
1213 .name = "s3fb",
1214 .id_table = s3_devices,
1215 .probe = s3_pci_probe,
1216 .remove = __devexit_p(s3_pci_remove),
1217 .suspend = s3_pci_suspend,
1218 .resume = s3_pci_resume,
1219};
1220
1221/* Parse user speficied options */
1222
1223#ifndef MODULE
1224static int __init s3fb_setup(char *options)
1225{
1226 char *opt;
1227
1228 if (!options || !*options)
1229 return 0;
1230
1231 while ((opt = strsep(&options, ",")) != NULL) {
1232
1233 if (!*opt)
1234 continue;
1235#ifdef CONFIG_MTRR
62fa4dc7 1236 else if (!strncmp(opt, "mtrr:", 5))
a268422d
OZ		 1237 mtrr = simple_strtoul(opt + 5, NULL, 0);
1238#endif
62fa4dc7
OZ		 1239 else if (!strncmp(opt, "fasttext:", 9))
1240 fasttext = simple_strtoul(opt + 9, NULL, 0);
a268422d 1241 else
a8140543 1242 mode_option = opt;
a268422d
OZ		 1243 }
1244
1245 return 0;
1246}
1247#endif
1248
1249/* Cleanup */
1250
1251static void __exit s3fb_cleanup(void)
1252{
1253 pr_debug("s3fb: cleaning up\n");
1254 pci_unregister_driver(&s3fb_pci_driver);
1255}
1256
1257/* Driver Initialisation */
1258
1259static int __init s3fb_init(void)
1260{
1261
1262#ifndef MODULE
1263 char *option = NULL;
1264
1265 if (fb_get_options("s3fb", &option))
1266 return -ENODEV;
1267 s3fb_setup(option);
1268#endif
1269
1270 pr_debug("s3fb: initializing\n");
1271 return pci_register_driver(&s3fb_pci_driver);
1272}
1273
1274/* ------------------------------------------------------------------------- */
1275
1276/* Modularization */
1277
1278module_init(s3fb_init);
1279module_exit(s3fb_cleanup);
Linux kernel - Deliverables
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