Commit | Line | Data |
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a268422d OZ |
1 | /* |
2 | * linux/drivers/video/s3fb.c -- Frame buffer device driver for S3 Trio/Virge | |
3 | * | |
4 | * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org> | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file COPYING in the main directory of this archive for | |
8 | * more details. | |
9 | * | |
10 | * Code is based on David Boucher's viafb (http://davesdomain.org.uk/viafb/) | |
11 | * which is based on the code of neofb. | |
12 | */ | |
13 | ||
a268422d OZ |
14 | #include <linux/module.h> |
15 | #include <linux/kernel.h> | |
16 | #include <linux/errno.h> | |
17 | #include <linux/string.h> | |
18 | #include <linux/mm.h> | |
19 | #include <linux/tty.h> | |
a268422d OZ |
20 | #include <linux/delay.h> |
21 | #include <linux/fb.h> | |
22 | #include <linux/svga.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/pci.h> | |
ac751efa | 25 | #include <linux/console.h> /* Why should fb driver call console functions? because console_lock() */ |
a268422d OZ |
26 | #include <video/vga.h> |
27 | ||
28 | #ifdef CONFIG_MTRR | |
29 | #include <asm/mtrr.h> | |
30 | #endif | |
31 | ||
32 | struct s3fb_info { | |
33 | int chip, rev, mclk_freq; | |
34 | int mtrr_reg; | |
35 | struct vgastate state; | |
36 | struct mutex open_lock; | |
37 | unsigned int ref_count; | |
38 | u32 pseudo_palette[16]; | |
39 | }; | |
40 | ||
41 | ||
42 | /* ------------------------------------------------------------------------- */ | |
43 | ||
44 | static const struct svga_fb_format s3fb_formats[] = { | |
45 | { 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0, | |
46 | FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4, FB_VISUAL_PSEUDOCOLOR, 8, 16}, | |
c26d7b29 | 47 | { 4, {0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0}, 0, |
a268422d | 48 | FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 16}, |
c26d7b29 | 49 | { 4, {0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0}, 1, |
a268422d | 50 | FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 8, 16}, |
c26d7b29 | 51 | { 8, {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0, |
a268422d OZ |
52 | FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 4, 8}, |
53 | {16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0, | |
54 | FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4}, | |
55 | {16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0, | |
56 | FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4}, | |
57 | {24, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0, | |
58 | FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2}, | |
59 | {32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0, | |
60 | FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2}, | |
61 | SVGA_FORMAT_END | |
62 | }; | |
63 | ||
64 | ||
65 | static const struct svga_pll s3_pll = {3, 129, 3, 33, 0, 3, | |
249bdbbf | 66 | 35000, 240000, 14318}; |
5694f9ce OZ |
67 | static const struct svga_pll s3_trio3d_pll = {3, 129, 3, 31, 0, 4, |
68 | 230000, 460000, 14318}; | |
a268422d OZ |
69 | |
70 | static const int s3_memsizes[] = {4096, 0, 3072, 8192, 2048, 6144, 1024, 512}; | |
71 | ||
72 | static const char * const s3_names[] = {"S3 Unknown", "S3 Trio32", "S3 Trio64", "S3 Trio64V+", | |
73 | "S3 Trio64UV+", "S3 Trio64V2/DX", "S3 Trio64V2/GX", | |
74 | "S3 Plato/PX", "S3 Aurora64VP", "S3 Virge", | |
75 | "S3 Virge/VX", "S3 Virge/DX", "S3 Virge/GX", | |
9966c4fe | 76 | "S3 Virge/GX2", "S3 Virge/GX2P", "S3 Virge/GX2P", |
5694f9ce OZ |
77 | "S3 Trio3D/1X", "S3 Trio3D/2X", "S3 Trio3D/2X", |
78 | "S3 Trio3D"}; | |
a268422d OZ |
79 | |
80 | #define CHIP_UNKNOWN 0x00 | |
81 | #define CHIP_732_TRIO32 0x01 | |
82 | #define CHIP_764_TRIO64 0x02 | |
83 | #define CHIP_765_TRIO64VP 0x03 | |
84 | #define CHIP_767_TRIO64UVP 0x04 | |
85 | #define CHIP_775_TRIO64V2_DX 0x05 | |
86 | #define CHIP_785_TRIO64V2_GX 0x06 | |
87 | #define CHIP_551_PLATO_PX 0x07 | |
88 | #define CHIP_M65_AURORA64VP 0x08 | |
89 | #define CHIP_325_VIRGE 0x09 | |
90 | #define CHIP_988_VIRGE_VX 0x0A | |
91 | #define CHIP_375_VIRGE_DX 0x0B | |
92 | #define CHIP_385_VIRGE_GX 0x0C | |
93 | #define CHIP_356_VIRGE_GX2 0x0D | |
94 | #define CHIP_357_VIRGE_GX2P 0x0E | |
95 | #define CHIP_359_VIRGE_GX2P 0x0F | |
9966c4fe OZ |
96 | #define CHIP_360_TRIO3D_1X 0x10 |
97 | #define CHIP_362_TRIO3D_2X 0x11 | |
98 | #define CHIP_368_TRIO3D_2X 0x12 | |
5694f9ce | 99 | #define CHIP_365_TRIO3D 0x13 |
a268422d OZ |
100 | |
101 | #define CHIP_XXX_TRIO 0x80 | |
102 | #define CHIP_XXX_TRIO64V2_DXGX 0x81 | |
103 | #define CHIP_XXX_VIRGE_DXGX 0x82 | |
9966c4fe | 104 | #define CHIP_36X_TRIO3D_1X_2X 0x83 |
a268422d OZ |
105 | |
106 | #define CHIP_UNDECIDED_FLAG 0x80 | |
107 | #define CHIP_MASK 0xFF | |
108 | ||
109 | /* CRT timing register sets */ | |
110 | ||
111 | static const struct vga_regset s3_h_total_regs[] = {{0x00, 0, 7}, {0x5D, 0, 0}, VGA_REGSET_END}; | |
112 | static const struct vga_regset s3_h_display_regs[] = {{0x01, 0, 7}, {0x5D, 1, 1}, VGA_REGSET_END}; | |
113 | static const struct vga_regset s3_h_blank_start_regs[] = {{0x02, 0, 7}, {0x5D, 2, 2}, VGA_REGSET_END}; | |
114 | static const struct vga_regset s3_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7}, VGA_REGSET_END}; | |
115 | static const struct vga_regset s3_h_sync_start_regs[] = {{0x04, 0, 7}, {0x5D, 4, 4}, VGA_REGSET_END}; | |
116 | static const struct vga_regset s3_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END}; | |
117 | ||
118 | static const struct vga_regset s3_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x5E, 0, 0}, VGA_REGSET_END}; | |
119 | static const struct vga_regset s3_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x5E, 1, 1}, VGA_REGSET_END}; | |
120 | static const struct vga_regset s3_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x5E, 2, 2}, VGA_REGSET_END}; | |
121 | static const struct vga_regset s3_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END}; | |
122 | static const struct vga_regset s3_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x5E, 4, 4}, VGA_REGSET_END}; | |
123 | static const struct vga_regset s3_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END}; | |
124 | ||
125 | static const struct vga_regset s3_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, {0x5E, 6, 6}, VGA_REGSET_END}; | |
126 | static const struct vga_regset s3_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x31, 4, 5}, {0x51, 0, 1}, VGA_REGSET_END}; | |
127 | static const struct vga_regset s3_offset_regs[] = {{0x13, 0, 7}, {0x51, 4, 5}, VGA_REGSET_END}; /* set 0x43 bit 2 to 0 */ | |
128 | ||
cb11c048 OZ |
129 | static const struct vga_regset s3_dtpc_regs[] = {{0x3B, 0, 7}, {0x5D, 6, 6}, VGA_REGSET_END}; |
130 | ||
a268422d OZ |
131 | static const struct svga_timing_regs s3_timing_regs = { |
132 | s3_h_total_regs, s3_h_display_regs, s3_h_blank_start_regs, | |
133 | s3_h_blank_end_regs, s3_h_sync_start_regs, s3_h_sync_end_regs, | |
134 | s3_v_total_regs, s3_v_display_regs, s3_v_blank_start_regs, | |
135 | s3_v_blank_end_regs, s3_v_sync_start_regs, s3_v_sync_end_regs, | |
136 | }; | |
137 | ||
138 | ||
139 | /* ------------------------------------------------------------------------- */ | |
140 | ||
141 | /* Module parameters */ | |
142 | ||
143 | ||
a8140543 | 144 | static char *mode_option __devinitdata = "640x480-8@60"; |
a268422d OZ |
145 | |
146 | #ifdef CONFIG_MTRR | |
a8140543 | 147 | static int mtrr __devinitdata = 1; |
a268422d OZ |
148 | #endif |
149 | ||
150 | static int fasttext = 1; | |
151 | ||
152 | ||
153 | MODULE_AUTHOR("(c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>"); | |
154 | MODULE_LICENSE("GPL"); | |
155 | MODULE_DESCRIPTION("fbdev driver for S3 Trio/Virge"); | |
156 | ||
a8140543 KH |
157 | module_param(mode_option, charp, 0444); |
158 | MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)"); | |
159 | module_param_named(mode, mode_option, charp, 0444); | |
160 | MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc) (deprecated)"); | |
a268422d OZ |
161 | |
162 | #ifdef CONFIG_MTRR | |
163 | module_param(mtrr, int, 0444); | |
164 | MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)"); | |
165 | #endif | |
166 | ||
167 | module_param(fasttext, int, 0644); | |
168 | MODULE_PARM_DESC(fasttext, "Enable S3 fast text mode (1=enable, 0=disable, default=1)"); | |
169 | ||
170 | ||
171 | /* ------------------------------------------------------------------------- */ | |
172 | ||
173 | /* Set font in S3 fast text mode */ | |
174 | ||
175 | static void s3fb_settile_fast(struct fb_info *info, struct fb_tilemap *map) | |
176 | { | |
177 | const u8 *font = map->data; | |
75814d87 | 178 | u8 __iomem *fb = (u8 __iomem *) info->screen_base; |
a268422d OZ |
179 | int i, c; |
180 | ||
181 | if ((map->width != 8) || (map->height != 16) || | |
182 | (map->depth != 1) || (map->length != 256)) { | |
183 | printk(KERN_ERR "fb%d: unsupported font parameters: width %d, height %d, depth %d, length %d\n", | |
184 | info->node, map->width, map->height, map->depth, map->length); | |
185 | return; | |
186 | } | |
187 | ||
188 | fb += 2; | |
189 | for (i = 0; i < map->height; i++) { | |
190 | for (c = 0; c < map->length; c++) { | |
75814d87 | 191 | fb_writeb(font[c * map->height + i], fb + c * 4); |
a268422d OZ |
192 | } |
193 | fb += 1024; | |
194 | } | |
195 | } | |
196 | ||
55db0923 DM |
197 | static void s3fb_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor) |
198 | { | |
199 | struct s3fb_info *par = info->par; | |
200 | ||
201 | svga_tilecursor(par->state.vgabase, info, cursor); | |
202 | } | |
203 | ||
a268422d OZ |
204 | static struct fb_tile_ops s3fb_tile_ops = { |
205 | .fb_settile = svga_settile, | |
206 | .fb_tilecopy = svga_tilecopy, | |
207 | .fb_tilefill = svga_tilefill, | |
208 | .fb_tileblit = svga_tileblit, | |
55db0923 | 209 | .fb_tilecursor = s3fb_tilecursor, |
34ed25f5 | 210 | .fb_get_tilemax = svga_get_tilemax, |
a268422d OZ |
211 | }; |
212 | ||
213 | static struct fb_tile_ops s3fb_fast_tile_ops = { | |
214 | .fb_settile = s3fb_settile_fast, | |
215 | .fb_tilecopy = svga_tilecopy, | |
216 | .fb_tilefill = svga_tilefill, | |
217 | .fb_tileblit = svga_tileblit, | |
55db0923 | 218 | .fb_tilecursor = s3fb_tilecursor, |
34ed25f5 | 219 | .fb_get_tilemax = svga_get_tilemax, |
a268422d OZ |
220 | }; |
221 | ||
222 | ||
223 | /* ------------------------------------------------------------------------- */ | |
224 | ||
225 | /* image data is MSB-first, fb structure is MSB-first too */ | |
226 | static inline u32 expand_color(u32 c) | |
227 | { | |
228 | return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF; | |
229 | } | |
230 | ||
231 | /* s3fb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */ | |
232 | static void s3fb_iplan_imageblit(struct fb_info *info, const struct fb_image *image) | |
233 | { | |
234 | u32 fg = expand_color(image->fg_color); | |
235 | u32 bg = expand_color(image->bg_color); | |
236 | const u8 *src1, *src; | |
237 | u8 __iomem *dst1; | |
238 | u32 __iomem *dst; | |
239 | u32 val; | |
240 | int x, y; | |
241 | ||
242 | src1 = image->data; | |
243 | dst1 = info->screen_base + (image->dy * info->fix.line_length) | |
244 | + ((image->dx / 8) * 4); | |
245 | ||
246 | for (y = 0; y < image->height; y++) { | |
247 | src = src1; | |
248 | dst = (u32 __iomem *) dst1; | |
249 | for (x = 0; x < image->width; x += 8) { | |
250 | val = *(src++) * 0x01010101; | |
251 | val = (val & fg) | (~val & bg); | |
252 | fb_writel(val, dst++); | |
253 | } | |
254 | src1 += image->width / 8; | |
255 | dst1 += info->fix.line_length; | |
256 | } | |
257 | ||
258 | } | |
259 | ||
260 | /* s3fb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */ | |
261 | static void s3fb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect) | |
262 | { | |
263 | u32 fg = expand_color(rect->color); | |
264 | u8 __iomem *dst1; | |
265 | u32 __iomem *dst; | |
266 | int x, y; | |
267 | ||
268 | dst1 = info->screen_base + (rect->dy * info->fix.line_length) | |
269 | + ((rect->dx / 8) * 4); | |
270 | ||
271 | for (y = 0; y < rect->height; y++) { | |
272 | dst = (u32 __iomem *) dst1; | |
273 | for (x = 0; x < rect->width; x += 8) { | |
274 | fb_writel(fg, dst++); | |
275 | } | |
276 | dst1 += info->fix.line_length; | |
277 | } | |
278 | } | |
279 | ||
280 | ||
281 | /* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */ | |
282 | static inline u32 expand_pixel(u32 c) | |
283 | { | |
284 | return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) | | |
285 | ((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF; | |
286 | } | |
287 | ||
288 | /* s3fb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */ | |
289 | static void s3fb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image) | |
290 | { | |
291 | u32 fg = image->fg_color * 0x11111111; | |
292 | u32 bg = image->bg_color * 0x11111111; | |
293 | const u8 *src1, *src; | |
294 | u8 __iomem *dst1; | |
295 | u32 __iomem *dst; | |
296 | u32 val; | |
297 | int x, y; | |
298 | ||
299 | src1 = image->data; | |
300 | dst1 = info->screen_base + (image->dy * info->fix.line_length) | |
301 | + ((image->dx / 8) * 4); | |
302 | ||
303 | for (y = 0; y < image->height; y++) { | |
304 | src = src1; | |
305 | dst = (u32 __iomem *) dst1; | |
306 | for (x = 0; x < image->width; x += 8) { | |
307 | val = expand_pixel(*(src++)); | |
308 | val = (val & fg) | (~val & bg); | |
309 | fb_writel(val, dst++); | |
310 | } | |
311 | src1 += image->width / 8; | |
312 | dst1 += info->fix.line_length; | |
313 | } | |
314 | } | |
315 | ||
316 | static void s3fb_imageblit(struct fb_info *info, const struct fb_image *image) | |
317 | { | |
318 | if ((info->var.bits_per_pixel == 4) && (image->depth == 1) | |
319 | && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) { | |
320 | if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES) | |
321 | s3fb_iplan_imageblit(info, image); | |
322 | else | |
323 | s3fb_cfb4_imageblit(info, image); | |
324 | } else | |
325 | cfb_imageblit(info, image); | |
326 | } | |
327 | ||
328 | static void s3fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) | |
329 | { | |
330 | if ((info->var.bits_per_pixel == 4) | |
331 | && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0) | |
332 | && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)) | |
333 | s3fb_iplan_fillrect(info, rect); | |
334 | else | |
335 | cfb_fillrect(info, rect); | |
336 | } | |
337 | ||
338 | ||
339 | ||
340 | /* ------------------------------------------------------------------------- */ | |
341 | ||
342 | ||
343 | static void s3_set_pixclock(struct fb_info *info, u32 pixclock) | |
344 | { | |
9966c4fe | 345 | struct s3fb_info *par = info->par; |
a268422d OZ |
346 | u16 m, n, r; |
347 | u8 regval; | |
249bdbbf | 348 | int rv; |
a268422d | 349 | |
5694f9ce OZ |
350 | rv = svga_compute_pll((par->chip == CHIP_365_TRIO3D) ? &s3_trio3d_pll : &s3_pll, |
351 | 1000000000 / pixclock, &m, &n, &r, info->node); | |
249bdbbf OZ |
352 | if (rv < 0) { |
353 | printk(KERN_ERR "fb%d: cannot set requested pixclock, keeping old value\n", info->node); | |
354 | return; | |
355 | } | |
a268422d OZ |
356 | |
357 | /* Set VGA misc register */ | |
f8645933 DM |
358 | regval = vga_r(par->state.vgabase, VGA_MIS_R); |
359 | vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); | |
a268422d OZ |
360 | |
361 | /* Set S3 clock registers */ | |
9966c4fe OZ |
362 | if (par->chip == CHIP_360_TRIO3D_1X || |
363 | par->chip == CHIP_362_TRIO3D_2X || | |
364 | par->chip == CHIP_368_TRIO3D_2X) { | |
f8645933 DM |
365 | vga_wseq(par->state.vgabase, 0x12, (n - 2) | ((r & 3) << 6)); /* n and two bits of r */ |
366 | vga_wseq(par->state.vgabase, 0x29, r >> 2); /* remaining highest bit of r */ | |
9966c4fe | 367 | } else |
f8645933 DM |
368 | vga_wseq(par->state.vgabase, 0x12, (n - 2) | (r << 5)); |
369 | vga_wseq(par->state.vgabase, 0x13, m - 2); | |
a268422d OZ |
370 | |
371 | udelay(1000); | |
372 | ||
373 | /* Activate clock - write 0, 1, 0 to seq/15 bit 5 */ | |
f8645933 DM |
374 | regval = vga_rseq (par->state.vgabase, 0x15); /* | 0x80; */ |
375 | vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); | |
376 | vga_wseq(par->state.vgabase, 0x15, regval | (1<<5)); | |
377 | vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); | |
a268422d OZ |
378 | } |
379 | ||
380 | ||
381 | /* Open framebuffer */ | |
382 | ||
383 | static int s3fb_open(struct fb_info *info, int user) | |
384 | { | |
385 | struct s3fb_info *par = info->par; | |
386 | ||
387 | mutex_lock(&(par->open_lock)); | |
388 | if (par->ref_count == 0) { | |
3ff259f2 DM |
389 | void __iomem *vgabase = par->state.vgabase; |
390 | ||
a268422d | 391 | memset(&(par->state), 0, sizeof(struct vgastate)); |
3ff259f2 | 392 | par->state.vgabase = vgabase; |
a268422d OZ |
393 | par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP; |
394 | par->state.num_crtc = 0x70; | |
395 | par->state.num_seq = 0x20; | |
396 | save_vga(&(par->state)); | |
397 | } | |
398 | ||
399 | par->ref_count++; | |
400 | mutex_unlock(&(par->open_lock)); | |
401 | ||
402 | return 0; | |
403 | } | |
404 | ||
405 | /* Close framebuffer */ | |
406 | ||
407 | static int s3fb_release(struct fb_info *info, int user) | |
408 | { | |
409 | struct s3fb_info *par = info->par; | |
410 | ||
411 | mutex_lock(&(par->open_lock)); | |
412 | if (par->ref_count == 0) { | |
413 | mutex_unlock(&(par->open_lock)); | |
414 | return -EINVAL; | |
415 | } | |
416 | ||
417 | if (par->ref_count == 1) | |
418 | restore_vga(&(par->state)); | |
419 | ||
420 | par->ref_count--; | |
421 | mutex_unlock(&(par->open_lock)); | |
422 | ||
423 | return 0; | |
424 | } | |
425 | ||
426 | /* Validate passed in var */ | |
427 | ||
428 | static int s3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) | |
429 | { | |
430 | struct s3fb_info *par = info->par; | |
431 | int rv, mem, step; | |
c3ca34f9 | 432 | u16 m, n, r; |
a268422d OZ |
433 | |
434 | /* Find appropriate format */ | |
435 | rv = svga_match_format (s3fb_formats, var, NULL); | |
d4b766a0 OZ |
436 | |
437 | /* 32bpp mode is not supported on VIRGE VX, | |
438 | 24bpp is not supported on others */ | |
439 | if ((par->chip == CHIP_988_VIRGE_VX) ? (rv == 7) : (rv == 6)) | |
440 | rv = -EINVAL; | |
441 | ||
442 | if (rv < 0) { | |
a268422d OZ |
443 | printk(KERN_ERR "fb%d: unsupported mode requested\n", info->node); |
444 | return rv; | |
445 | } | |
446 | ||
447 | /* Do not allow to have real resoulution larger than virtual */ | |
448 | if (var->xres > var->xres_virtual) | |
449 | var->xres_virtual = var->xres; | |
450 | ||
451 | if (var->yres > var->yres_virtual) | |
452 | var->yres_virtual = var->yres; | |
453 | ||
454 | /* Round up xres_virtual to have proper alignment of lines */ | |
455 | step = s3fb_formats[rv].xresstep - 1; | |
456 | var->xres_virtual = (var->xres_virtual+step) & ~step; | |
457 | ||
458 | /* Check whether have enough memory */ | |
459 | mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual; | |
c3ca34f9 | 460 | if (mem > info->screen_size) { |
a268422d OZ |
461 | printk(KERN_ERR "fb%d: not enough framebuffer memory (%d kB requested , %d kB available)\n", |
462 | info->node, mem >> 10, (unsigned int) (info->screen_size >> 10)); | |
463 | return -EINVAL; | |
464 | } | |
465 | ||
466 | rv = svga_check_timings (&s3_timing_regs, var, info->node); | |
c3ca34f9 | 467 | if (rv < 0) { |
a268422d OZ |
468 | printk(KERN_ERR "fb%d: invalid timings requested\n", info->node); |
469 | return rv; | |
470 | } | |
471 | ||
c3ca34f9 KH |
472 | rv = svga_compute_pll(&s3_pll, PICOS2KHZ(var->pixclock), &m, &n, &r, |
473 | info->node); | |
474 | if (rv < 0) { | |
475 | printk(KERN_ERR "fb%d: invalid pixclock value requested\n", | |
476 | info->node); | |
477 | return rv; | |
478 | } | |
479 | ||
a268422d OZ |
480 | return 0; |
481 | } | |
482 | ||
483 | /* Set video mode from par */ | |
484 | ||
485 | static int s3fb_set_par(struct fb_info *info) | |
486 | { | |
487 | struct s3fb_info *par = info->par; | |
9966c4fe | 488 | u32 value, mode, hmul, offset_value, screen_size, multiplex, dbytes; |
a268422d | 489 | u32 bpp = info->var.bits_per_pixel; |
cb11c048 | 490 | u32 htotal, hsstart; |
a268422d OZ |
491 | |
492 | if (bpp != 0) { | |
493 | info->fix.ypanstep = 1; | |
494 | info->fix.line_length = (info->var.xres_virtual * bpp) / 8; | |
495 | ||
496 | info->flags &= ~FBINFO_MISC_TILEBLITTING; | |
497 | info->tileops = NULL; | |
498 | ||
34ed25f5 OZ |
499 | /* in 4bpp supports 8p wide tiles only, any tiles otherwise */ |
500 | info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0); | |
8db51668 | 501 | info->pixmap.blit_y = ~(u32)0; |
34ed25f5 | 502 | |
a268422d OZ |
503 | offset_value = (info->var.xres_virtual * bpp) / 64; |
504 | screen_size = info->var.yres_virtual * info->fix.line_length; | |
505 | } else { | |
506 | info->fix.ypanstep = 16; | |
507 | info->fix.line_length = 0; | |
508 | ||
509 | info->flags |= FBINFO_MISC_TILEBLITTING; | |
510 | info->tileops = fasttext ? &s3fb_fast_tile_ops : &s3fb_tile_ops; | |
34ed25f5 | 511 | |
8db51668 AD |
512 | /* supports 8x16 tiles only */ |
513 | info->pixmap.blit_x = 1 << (8 - 1); | |
514 | info->pixmap.blit_y = 1 << (16 - 1); | |
a268422d OZ |
515 | |
516 | offset_value = info->var.xres_virtual / 16; | |
517 | screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64; | |
518 | } | |
519 | ||
520 | info->var.xoffset = 0; | |
521 | info->var.yoffset = 0; | |
522 | info->var.activate = FB_ACTIVATE_NOW; | |
523 | ||
524 | /* Unlock registers */ | |
f8645933 DM |
525 | vga_wcrt(par->state.vgabase, 0x38, 0x48); |
526 | vga_wcrt(par->state.vgabase, 0x39, 0xA5); | |
527 | vga_wseq(par->state.vgabase, 0x08, 0x06); | |
ea770789 | 528 | svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80); |
a268422d OZ |
529 | |
530 | /* Blank screen and turn off sync */ | |
d907ec04 | 531 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); |
ea770789 | 532 | svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80); |
a268422d OZ |
533 | |
534 | /* Set default values */ | |
e2fade2c | 535 | svga_set_default_gfx_regs(par->state.vgabase); |
f51a14dd | 536 | svga_set_default_atc_regs(par->state.vgabase); |
a4ade839 | 537 | svga_set_default_seq_regs(par->state.vgabase); |
1d28fcad | 538 | svga_set_default_crt_regs(par->state.vgabase); |
21da386d DM |
539 | svga_wcrt_multi(par->state.vgabase, s3_line_compare_regs, 0xFFFFFFFF); |
540 | svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, 0); | |
a268422d OZ |
541 | |
542 | /* S3 specific initialization */ | |
ea770789 DM |
543 | svga_wcrt_mask(par->state.vgabase, 0x58, 0x10, 0x10); /* enable linear framebuffer */ |
544 | svga_wcrt_mask(par->state.vgabase, 0x31, 0x08, 0x08); /* enable sequencer access to framebuffer above 256 kB */ | |
a268422d | 545 | |
ea770789 DM |
546 | /* svga_wcrt_mask(par->state.vgabase, 0x33, 0x08, 0x08); */ /* DDR ? */ |
547 | /* svga_wcrt_mask(par->state.vgabase, 0x43, 0x01, 0x01); */ /* DDR ? */ | |
548 | svga_wcrt_mask(par->state.vgabase, 0x33, 0x00, 0x08); /* no DDR ? */ | |
549 | svga_wcrt_mask(par->state.vgabase, 0x43, 0x00, 0x01); /* no DDR ? */ | |
a268422d | 550 | |
ea770789 | 551 | svga_wcrt_mask(par->state.vgabase, 0x5D, 0x00, 0x28); /* Clear strange HSlen bits */ |
a268422d | 552 | |
ea770789 | 553 | /* svga_wcrt_mask(par->state.vgabase, 0x58, 0x03, 0x03); */ |
a268422d | 554 | |
ea770789 DM |
555 | /* svga_wcrt_mask(par->state.vgabase, 0x53, 0x12, 0x13); */ /* enable MMIO */ |
556 | /* svga_wcrt_mask(par->state.vgabase, 0x40, 0x08, 0x08); */ /* enable write buffer */ | |
a268422d OZ |
557 | |
558 | ||
559 | /* Set the offset register */ | |
560 | pr_debug("fb%d: offset register : %d\n", info->node, offset_value); | |
21da386d | 561 | svga_wcrt_multi(par->state.vgabase, s3_offset_regs, offset_value); |
a268422d | 562 | |
9966c4fe OZ |
563 | if (par->chip != CHIP_360_TRIO3D_1X && |
564 | par->chip != CHIP_362_TRIO3D_2X && | |
565 | par->chip != CHIP_368_TRIO3D_2X) { | |
f8645933 DM |
566 | vga_wcrt(par->state.vgabase, 0x54, 0x18); /* M parameter */ |
567 | vga_wcrt(par->state.vgabase, 0x60, 0xff); /* N parameter */ | |
568 | vga_wcrt(par->state.vgabase, 0x61, 0xff); /* L parameter */ | |
569 | vga_wcrt(par->state.vgabase, 0x62, 0xff); /* L parameter */ | |
9966c4fe | 570 | } |
a268422d | 571 | |
f8645933 | 572 | vga_wcrt(par->state.vgabase, 0x3A, 0x35); |
f6b0cc47 | 573 | svga_wattr(par->state.vgabase, 0x33, 0x00); |
a268422d OZ |
574 | |
575 | if (info->var.vmode & FB_VMODE_DOUBLE) | |
ea770789 | 576 | svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80); |
a268422d | 577 | else |
ea770789 | 578 | svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80); |
a268422d OZ |
579 | |
580 | if (info->var.vmode & FB_VMODE_INTERLACED) | |
ea770789 | 581 | svga_wcrt_mask(par->state.vgabase, 0x42, 0x20, 0x20); |
a268422d | 582 | else |
ea770789 | 583 | svga_wcrt_mask(par->state.vgabase, 0x42, 0x00, 0x20); |
a268422d OZ |
584 | |
585 | /* Disable hardware graphics cursor */ | |
ea770789 | 586 | svga_wcrt_mask(par->state.vgabase, 0x45, 0x00, 0x01); |
a268422d | 587 | /* Disable Streams engine */ |
ea770789 | 588 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0x0C); |
a268422d OZ |
589 | |
590 | mode = svga_match_format(s3fb_formats, &(info->var), &(info->fix)); | |
591 | ||
592 | /* S3 virge DX hack */ | |
593 | if (par->chip == CHIP_375_VIRGE_DX) { | |
f8645933 DM |
594 | vga_wcrt(par->state.vgabase, 0x86, 0x80); |
595 | vga_wcrt(par->state.vgabase, 0x90, 0x00); | |
a268422d OZ |
596 | } |
597 | ||
598 | /* S3 virge VX hack */ | |
599 | if (par->chip == CHIP_988_VIRGE_VX) { | |
f8645933 DM |
600 | vga_wcrt(par->state.vgabase, 0x50, 0x00); |
601 | vga_wcrt(par->state.vgabase, 0x67, 0x50); | |
a268422d | 602 | |
f8645933 DM |
603 | vga_wcrt(par->state.vgabase, 0x63, (mode <= 2) ? 0x90 : 0x09); |
604 | vga_wcrt(par->state.vgabase, 0x66, 0x90); | |
a268422d OZ |
605 | } |
606 | ||
9966c4fe OZ |
607 | if (par->chip == CHIP_360_TRIO3D_1X || |
608 | par->chip == CHIP_362_TRIO3D_2X || | |
5694f9ce | 609 | par->chip == CHIP_368_TRIO3D_2X || |
cb11c048 OZ |
610 | par->chip == CHIP_365_TRIO3D || |
611 | par->chip == CHIP_375_VIRGE_DX || | |
612 | par->chip == CHIP_385_VIRGE_GX) { | |
9966c4fe | 613 | dbytes = info->var.xres * ((bpp+7)/8); |
f8645933 DM |
614 | vga_wcrt(par->state.vgabase, 0x91, (dbytes + 7) / 8); |
615 | vga_wcrt(par->state.vgabase, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80); | |
9966c4fe | 616 | |
f8645933 | 617 | vga_wcrt(par->state.vgabase, 0x66, 0x81); |
9966c4fe OZ |
618 | } |
619 | ||
cb11c048 OZ |
620 | if (par->chip == CHIP_356_VIRGE_GX2 || |
621 | par->chip == CHIP_357_VIRGE_GX2P || | |
622 | par->chip == CHIP_359_VIRGE_GX2P || | |
623 | par->chip == CHIP_360_TRIO3D_1X || | |
624 | par->chip == CHIP_362_TRIO3D_2X || | |
625 | par->chip == CHIP_368_TRIO3D_2X) | |
626 | vga_wcrt(par->state.vgabase, 0x34, 0x00); | |
627 | else /* enable Data Transfer Position Control (DTPC) */ | |
628 | vga_wcrt(par->state.vgabase, 0x34, 0x10); | |
629 | ||
ea770789 | 630 | svga_wcrt_mask(par->state.vgabase, 0x31, 0x00, 0x40); |
a268422d OZ |
631 | multiplex = 0; |
632 | hmul = 1; | |
633 | ||
634 | /* Set mode-specific register values */ | |
635 | switch (mode) { | |
636 | case 0: | |
637 | pr_debug("fb%d: text mode\n", info->node); | |
9c96394b | 638 | svga_set_textmode_vga_regs(par->state.vgabase); |
a268422d OZ |
639 | |
640 | /* Set additional registers like in 8-bit mode */ | |
ea770789 DM |
641 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); |
642 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); | |
a268422d OZ |
643 | |
644 | /* Disable enhanced mode */ | |
ea770789 | 645 | svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); |
a268422d OZ |
646 | |
647 | if (fasttext) { | |
648 | pr_debug("fb%d: high speed text mode set\n", info->node); | |
ea770789 | 649 | svga_wcrt_mask(par->state.vgabase, 0x31, 0x40, 0x40); |
a268422d OZ |
650 | } |
651 | break; | |
652 | case 1: | |
653 | pr_debug("fb%d: 4 bit pseudocolor\n", info->node); | |
f8645933 | 654 | vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40); |
a268422d OZ |
655 | |
656 | /* Set additional registers like in 8-bit mode */ | |
ea770789 DM |
657 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); |
658 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); | |
a268422d OZ |
659 | |
660 | /* disable enhanced mode */ | |
ea770789 | 661 | svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); |
a268422d OZ |
662 | break; |
663 | case 2: | |
664 | pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node); | |
665 | ||
666 | /* Set additional registers like in 8-bit mode */ | |
ea770789 DM |
667 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); |
668 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); | |
a268422d OZ |
669 | |
670 | /* disable enhanced mode */ | |
ea770789 | 671 | svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); |
a268422d OZ |
672 | break; |
673 | case 3: | |
674 | pr_debug("fb%d: 8 bit pseudocolor\n", info->node); | |
ea770789 | 675 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); |
9966c4fe OZ |
676 | if (info->var.pixclock > 20000 || |
677 | par->chip == CHIP_360_TRIO3D_1X || | |
678 | par->chip == CHIP_362_TRIO3D_2X || | |
679 | par->chip == CHIP_368_TRIO3D_2X) | |
ea770789 | 680 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); |
9966c4fe | 681 | else { |
ea770789 | 682 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x10, 0xF0); |
a268422d OZ |
683 | multiplex = 1; |
684 | } | |
685 | break; | |
686 | case 4: | |
687 | pr_debug("fb%d: 5/5/5 truecolor\n", info->node); | |
688 | if (par->chip == CHIP_988_VIRGE_VX) { | |
689 | if (info->var.pixclock > 20000) | |
ea770789 | 690 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0); |
a268422d | 691 | else |
ea770789 | 692 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); |
3827d10e OZ |
693 | } else if (par->chip == CHIP_365_TRIO3D) { |
694 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); | |
695 | if (info->var.pixclock > 8695) { | |
696 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); | |
697 | hmul = 2; | |
698 | } else { | |
699 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0); | |
700 | multiplex = 1; | |
701 | } | |
a268422d | 702 | } else { |
ea770789 DM |
703 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); |
704 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); | |
9966c4fe OZ |
705 | if (par->chip != CHIP_360_TRIO3D_1X && |
706 | par->chip != CHIP_362_TRIO3D_2X && | |
707 | par->chip != CHIP_368_TRIO3D_2X) | |
708 | hmul = 2; | |
a268422d OZ |
709 | } |
710 | break; | |
711 | case 5: | |
712 | pr_debug("fb%d: 5/6/5 truecolor\n", info->node); | |
713 | if (par->chip == CHIP_988_VIRGE_VX) { | |
714 | if (info->var.pixclock > 20000) | |
ea770789 | 715 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0); |
a268422d | 716 | else |
ea770789 | 717 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); |
3827d10e OZ |
718 | } else if (par->chip == CHIP_365_TRIO3D) { |
719 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); | |
720 | if (info->var.pixclock > 8695) { | |
721 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); | |
722 | hmul = 2; | |
723 | } else { | |
724 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0); | |
725 | multiplex = 1; | |
726 | } | |
a268422d | 727 | } else { |
ea770789 DM |
728 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); |
729 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); | |
9966c4fe OZ |
730 | if (par->chip != CHIP_360_TRIO3D_1X && |
731 | par->chip != CHIP_362_TRIO3D_2X && | |
732 | par->chip != CHIP_368_TRIO3D_2X) | |
733 | hmul = 2; | |
a268422d OZ |
734 | } |
735 | break; | |
736 | case 6: | |
737 | /* VIRGE VX case */ | |
738 | pr_debug("fb%d: 8/8/8 truecolor\n", info->node); | |
ea770789 | 739 | svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0); |
a268422d OZ |
740 | break; |
741 | case 7: | |
742 | pr_debug("fb%d: 8/8/8/8 truecolor\n", info->node); | |
ea770789 DM |
743 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x30, 0x30); |
744 | svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0); | |
a268422d OZ |
745 | break; |
746 | default: | |
747 | printk(KERN_ERR "fb%d: unsupported mode - bug\n", info->node); | |
748 | return -EINVAL; | |
749 | } | |
750 | ||
751 | if (par->chip != CHIP_988_VIRGE_VX) { | |
d907ec04 DM |
752 | svga_wseq_mask(par->state.vgabase, 0x15, multiplex ? 0x10 : 0x00, 0x10); |
753 | svga_wseq_mask(par->state.vgabase, 0x18, multiplex ? 0x80 : 0x00, 0x80); | |
a268422d OZ |
754 | } |
755 | ||
756 | s3_set_pixclock(info, info->var.pixclock); | |
38d2620e | 757 | svga_set_timings(par->state.vgabase, &s3_timing_regs, &(info->var), hmul, 1, |
a268422d OZ |
758 | (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1, |
759 | (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1, | |
760 | hmul, info->node); | |
761 | ||
762 | /* Set interlaced mode start/end register */ | |
cb11c048 OZ |
763 | htotal = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len; |
764 | htotal = ((htotal * hmul) / 8) - 5; | |
765 | vga_wcrt(par->state.vgabase, 0x3C, (htotal + 1) / 2); | |
766 | ||
767 | /* Set Data Transfer Position */ | |
768 | hsstart = ((info->var.xres + info->var.right_margin) * hmul) / 8; | |
769 | value = clamp((htotal + hsstart + 1) / 2, hsstart + 4, htotal + 1); | |
770 | svga_wcrt_multi(par->state.vgabase, s3_dtpc_regs, value); | |
a268422d | 771 | |
75814d87 | 772 | memset_io(info->screen_base, 0x00, screen_size); |
a268422d | 773 | /* Device and screen back on */ |
ea770789 | 774 | svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80); |
d907ec04 | 775 | svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); |
a268422d OZ |
776 | |
777 | return 0; | |
778 | } | |
779 | ||
780 | /* Set a colour register */ | |
781 | ||
782 | static int s3fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, | |
783 | u_int transp, struct fb_info *fb) | |
784 | { | |
785 | switch (fb->var.bits_per_pixel) { | |
786 | case 0: | |
787 | case 4: | |
788 | if (regno >= 16) | |
789 | return -EINVAL; | |
790 | ||
791 | if ((fb->var.bits_per_pixel == 4) && | |
792 | (fb->var.nonstd == 0)) { | |
793 | outb(0xF0, VGA_PEL_MSK); | |
794 | outb(regno*16, VGA_PEL_IW); | |
795 | } else { | |
796 | outb(0x0F, VGA_PEL_MSK); | |
797 | outb(regno, VGA_PEL_IW); | |
798 | } | |
799 | outb(red >> 10, VGA_PEL_D); | |
800 | outb(green >> 10, VGA_PEL_D); | |
801 | outb(blue >> 10, VGA_PEL_D); | |
802 | break; | |
803 | case 8: | |
804 | if (regno >= 256) | |
805 | return -EINVAL; | |
806 | ||
807 | outb(0xFF, VGA_PEL_MSK); | |
808 | outb(regno, VGA_PEL_IW); | |
809 | outb(red >> 10, VGA_PEL_D); | |
810 | outb(green >> 10, VGA_PEL_D); | |
811 | outb(blue >> 10, VGA_PEL_D); | |
812 | break; | |
813 | case 16: | |
814 | if (regno >= 16) | |
249bdbbf | 815 | return 0; |
a268422d OZ |
816 | |
817 | if (fb->var.green.length == 5) | |
818 | ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) | | |
819 | ((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11); | |
820 | else if (fb->var.green.length == 6) | |
821 | ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) | | |
822 | ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11); | |
823 | else return -EINVAL; | |
824 | break; | |
825 | case 24: | |
826 | case 32: | |
827 | if (regno >= 16) | |
249bdbbf | 828 | return 0; |
a268422d | 829 | |
249bdbbf | 830 | ((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) | |
a268422d OZ |
831 | (green & 0xFF00) | ((blue & 0xFF00) >> 8); |
832 | break; | |
833 | default: | |
834 | return -EINVAL; | |
835 | } | |
836 | ||
837 | return 0; | |
838 | } | |
839 | ||
840 | ||
841 | /* Set the display blanking state */ | |
842 | ||
843 | static int s3fb_blank(int blank_mode, struct fb_info *info) | |
844 | { | |
d907ec04 DM |
845 | struct s3fb_info *par = info->par; |
846 | ||
a268422d OZ |
847 | switch (blank_mode) { |
848 | case FB_BLANK_UNBLANK: | |
849 | pr_debug("fb%d: unblank\n", info->node); | |
ea770789 | 850 | svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06); |
d907ec04 | 851 | svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); |
a268422d OZ |
852 | break; |
853 | case FB_BLANK_NORMAL: | |
854 | pr_debug("fb%d: blank\n", info->node); | |
ea770789 | 855 | svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06); |
d907ec04 | 856 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); |
a268422d OZ |
857 | break; |
858 | case FB_BLANK_HSYNC_SUSPEND: | |
859 | pr_debug("fb%d: hsync\n", info->node); | |
ea770789 | 860 | svga_wcrt_mask(par->state.vgabase, 0x56, 0x02, 0x06); |
d907ec04 | 861 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); |
a268422d OZ |
862 | break; |
863 | case FB_BLANK_VSYNC_SUSPEND: | |
864 | pr_debug("fb%d: vsync\n", info->node); | |
ea770789 | 865 | svga_wcrt_mask(par->state.vgabase, 0x56, 0x04, 0x06); |
d907ec04 | 866 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); |
a268422d OZ |
867 | break; |
868 | case FB_BLANK_POWERDOWN: | |
869 | pr_debug("fb%d: sync down\n", info->node); | |
ea770789 | 870 | svga_wcrt_mask(par->state.vgabase, 0x56, 0x06, 0x06); |
d907ec04 | 871 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); |
a268422d OZ |
872 | break; |
873 | } | |
874 | ||
875 | return 0; | |
876 | } | |
877 | ||
878 | ||
879 | /* Pan the display */ | |
880 | ||
21da386d DM |
881 | static int s3fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) |
882 | { | |
883 | struct s3fb_info *par = info->par; | |
a268422d OZ |
884 | unsigned int offset; |
885 | ||
a268422d OZ |
886 | /* Calculate the offset */ |
887 | if (var->bits_per_pixel == 0) { | |
888 | offset = (var->yoffset / 16) * (var->xres_virtual / 2) + (var->xoffset / 2); | |
889 | offset = offset >> 2; | |
890 | } else { | |
891 | offset = (var->yoffset * info->fix.line_length) + | |
892 | (var->xoffset * var->bits_per_pixel / 8); | |
893 | offset = offset >> 2; | |
894 | } | |
895 | ||
896 | /* Set the offset */ | |
21da386d | 897 | svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, offset); |
a268422d OZ |
898 | |
899 | return 0; | |
900 | } | |
901 | ||
902 | /* ------------------------------------------------------------------------- */ | |
903 | ||
904 | /* Frame buffer operations */ | |
905 | ||
906 | static struct fb_ops s3fb_ops = { | |
907 | .owner = THIS_MODULE, | |
908 | .fb_open = s3fb_open, | |
909 | .fb_release = s3fb_release, | |
910 | .fb_check_var = s3fb_check_var, | |
911 | .fb_set_par = s3fb_set_par, | |
912 | .fb_setcolreg = s3fb_setcolreg, | |
913 | .fb_blank = s3fb_blank, | |
914 | .fb_pan_display = s3fb_pan_display, | |
915 | .fb_fillrect = s3fb_fillrect, | |
916 | .fb_copyarea = cfb_copyarea, | |
917 | .fb_imageblit = s3fb_imageblit, | |
5a87ede9 | 918 | .fb_get_caps = svga_get_caps, |
a268422d OZ |
919 | }; |
920 | ||
921 | /* ------------------------------------------------------------------------- */ | |
922 | ||
f8645933 | 923 | static int __devinit s3_identification(struct s3fb_info *par) |
a268422d | 924 | { |
f8645933 DM |
925 | int chip = par->chip; |
926 | ||
a268422d | 927 | if (chip == CHIP_XXX_TRIO) { |
f8645933 DM |
928 | u8 cr30 = vga_rcrt(par->state.vgabase, 0x30); |
929 | u8 cr2e = vga_rcrt(par->state.vgabase, 0x2e); | |
930 | u8 cr2f = vga_rcrt(par->state.vgabase, 0x2f); | |
a268422d OZ |
931 | |
932 | if ((cr30 == 0xE0) || (cr30 == 0xE1)) { | |
933 | if (cr2e == 0x10) | |
934 | return CHIP_732_TRIO32; | |
935 | if (cr2e == 0x11) { | |
936 | if (! (cr2f & 0x40)) | |
937 | return CHIP_764_TRIO64; | |
938 | else | |
939 | return CHIP_765_TRIO64VP; | |
940 | } | |
941 | } | |
942 | } | |
943 | ||
944 | if (chip == CHIP_XXX_TRIO64V2_DXGX) { | |
f8645933 | 945 | u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f); |
a268422d OZ |
946 | |
947 | if (! (cr6f & 0x01)) | |
948 | return CHIP_775_TRIO64V2_DX; | |
949 | else | |
950 | return CHIP_785_TRIO64V2_GX; | |
951 | } | |
952 | ||
953 | if (chip == CHIP_XXX_VIRGE_DXGX) { | |
f8645933 | 954 | u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f); |
a268422d OZ |
955 | |
956 | if (! (cr6f & 0x01)) | |
957 | return CHIP_375_VIRGE_DX; | |
958 | else | |
959 | return CHIP_385_VIRGE_GX; | |
960 | } | |
961 | ||
9966c4fe | 962 | if (chip == CHIP_36X_TRIO3D_1X_2X) { |
f8645933 | 963 | switch (vga_rcrt(par->state.vgabase, 0x2f)) { |
9966c4fe OZ |
964 | case 0x00: |
965 | return CHIP_360_TRIO3D_1X; | |
966 | case 0x01: | |
967 | return CHIP_362_TRIO3D_2X; | |
968 | case 0x02: | |
969 | return CHIP_368_TRIO3D_2X; | |
970 | } | |
971 | } | |
972 | ||
a268422d OZ |
973 | return CHIP_UNKNOWN; |
974 | } | |
975 | ||
976 | ||
977 | /* PCI probe */ | |
978 | ||
979 | static int __devinit s3_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | |
980 | { | |
94c322c3 DM |
981 | struct pci_bus_region bus_reg; |
982 | struct resource vga_res; | |
a268422d OZ |
983 | struct fb_info *info; |
984 | struct s3fb_info *par; | |
985 | int rc; | |
986 | u8 regval, cr38, cr39; | |
987 | ||
988 | /* Ignore secondary VGA device because there is no VGA arbitration */ | |
989 | if (! svga_primary_device(dev)) { | |
990 | dev_info(&(dev->dev), "ignoring secondary device\n"); | |
991 | return -ENODEV; | |
992 | } | |
993 | ||
994 | /* Allocate and fill driver data structure */ | |
20e061fb | 995 | info = framebuffer_alloc(sizeof(struct s3fb_info), &(dev->dev)); |
a268422d OZ |
996 | if (!info) { |
997 | dev_err(&(dev->dev), "cannot allocate memory\n"); | |
998 | return -ENOMEM; | |
999 | } | |
1000 | ||
1001 | par = info->par; | |
1002 | mutex_init(&par->open_lock); | |
1003 | ||
1004 | info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN; | |
1005 | info->fbops = &s3fb_ops; | |
1006 | ||
1007 | /* Prepare PCI device */ | |
1008 | rc = pci_enable_device(dev); | |
1009 | if (rc < 0) { | |
594a8819 | 1010 | dev_err(info->device, "cannot enable PCI device\n"); |
a268422d OZ |
1011 | goto err_enable_device; |
1012 | } | |
1013 | ||
1014 | rc = pci_request_regions(dev, "s3fb"); | |
1015 | if (rc < 0) { | |
594a8819 | 1016 | dev_err(info->device, "cannot reserve framebuffer region\n"); |
a268422d OZ |
1017 | goto err_request_regions; |
1018 | } | |
1019 | ||
1020 | ||
1021 | info->fix.smem_start = pci_resource_start(dev, 0); | |
1022 | info->fix.smem_len = pci_resource_len(dev, 0); | |
1023 | ||
1024 | /* Map physical IO memory address into kernel space */ | |
1025 | info->screen_base = pci_iomap(dev, 0, 0); | |
1026 | if (! info->screen_base) { | |
1027 | rc = -ENOMEM; | |
594a8819 | 1028 | dev_err(info->device, "iomap for framebuffer failed\n"); |
a268422d OZ |
1029 | goto err_iomap; |
1030 | } | |
1031 | ||
94c322c3 DM |
1032 | bus_reg.start = 0; |
1033 | bus_reg.end = 64 * 1024; | |
1034 | ||
1035 | vga_res.flags = IORESOURCE_IO; | |
1036 | ||
1037 | pcibios_bus_to_resource(dev, &vga_res, &bus_reg); | |
1038 | ||
1039 | par->state.vgabase = (void __iomem *) vga_res.start; | |
1040 | ||
a268422d | 1041 | /* Unlock regs */ |
f8645933 DM |
1042 | cr38 = vga_rcrt(par->state.vgabase, 0x38); |
1043 | cr39 = vga_rcrt(par->state.vgabase, 0x39); | |
1044 | vga_wseq(par->state.vgabase, 0x08, 0x06); | |
1045 | vga_wcrt(par->state.vgabase, 0x38, 0x48); | |
1046 | vga_wcrt(par->state.vgabase, 0x39, 0xA5); | |
a268422d | 1047 | |
9966c4fe | 1048 | /* Identify chip type */ |
a268422d | 1049 | par->chip = id->driver_data & CHIP_MASK; |
f8645933 | 1050 | par->rev = vga_rcrt(par->state.vgabase, 0x2f); |
a268422d | 1051 | if (par->chip & CHIP_UNDECIDED_FLAG) |
f8645933 | 1052 | par->chip = s3_identification(par); |
a268422d | 1053 | |
9966c4fe OZ |
1054 | /* Find how many physical memory there is on card */ |
1055 | /* 0x36 register is accessible even if other registers are locked */ | |
f8645933 | 1056 | regval = vga_rcrt(par->state.vgabase, 0x36); |
9966c4fe OZ |
1057 | if (par->chip == CHIP_360_TRIO3D_1X || |
1058 | par->chip == CHIP_362_TRIO3D_2X || | |
5694f9ce OZ |
1059 | par->chip == CHIP_368_TRIO3D_2X || |
1060 | par->chip == CHIP_365_TRIO3D) { | |
9966c4fe OZ |
1061 | switch ((regval & 0xE0) >> 5) { |
1062 | case 0: /* 8MB -- only 4MB usable for display */ | |
1063 | case 1: /* 4MB with 32-bit bus */ | |
1064 | case 2: /* 4MB */ | |
1065 | info->screen_size = 4 << 20; | |
1066 | break; | |
5694f9ce | 1067 | case 4: /* 2MB on 365 Trio3D */ |
9966c4fe OZ |
1068 | case 6: /* 2MB */ |
1069 | info->screen_size = 2 << 20; | |
1070 | break; | |
1071 | } | |
1072 | } else | |
1073 | info->screen_size = s3_memsizes[regval >> 5] << 10; | |
1074 | info->fix.smem_len = info->screen_size; | |
1075 | ||
a268422d | 1076 | /* Find MCLK frequency */ |
f8645933 DM |
1077 | regval = vga_rseq(par->state.vgabase, 0x10); |
1078 | par->mclk_freq = ((vga_rseq(par->state.vgabase, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2); | |
a268422d OZ |
1079 | par->mclk_freq = par->mclk_freq >> (regval >> 5); |
1080 | ||
1081 | /* Restore locks */ | |
f8645933 DM |
1082 | vga_wcrt(par->state.vgabase, 0x38, cr38); |
1083 | vga_wcrt(par->state.vgabase, 0x39, cr39); | |
a268422d OZ |
1084 | |
1085 | strcpy(info->fix.id, s3_names [par->chip]); | |
1086 | info->fix.mmio_start = 0; | |
1087 | info->fix.mmio_len = 0; | |
1088 | info->fix.type = FB_TYPE_PACKED_PIXELS; | |
1089 | info->fix.visual = FB_VISUAL_PSEUDOCOLOR; | |
1090 | info->fix.ypanstep = 0; | |
1091 | info->fix.accel = FB_ACCEL_NONE; | |
1092 | info->pseudo_palette = (void*) (par->pseudo_palette); | |
1093 | ||
1094 | /* Prepare startup mode */ | |
a8140543 | 1095 | rc = fb_find_mode(&(info->var), info, mode_option, NULL, 0, NULL, 8); |
a268422d OZ |
1096 | if (! ((rc == 1) || (rc == 2))) { |
1097 | rc = -EINVAL; | |
594a8819 | 1098 | dev_err(info->device, "mode %s not found\n", mode_option); |
a268422d OZ |
1099 | goto err_find_mode; |
1100 | } | |
1101 | ||
99d054d8 OZ |
1102 | /* maximize virtual vertical size for fast scrolling */ |
1103 | info->var.yres_virtual = info->fix.smem_len * 8 / | |
1104 | (info->var.bits_per_pixel * info->var.xres_virtual); | |
1105 | if (info->var.yres_virtual < info->var.yres) { | |
1106 | dev_err(info->device, "virtual vertical size smaller than real\n"); | |
1107 | goto err_find_mode; | |
1108 | } | |
1109 | ||
a268422d OZ |
1110 | rc = fb_alloc_cmap(&info->cmap, 256, 0); |
1111 | if (rc < 0) { | |
594a8819 | 1112 | dev_err(info->device, "cannot allocate colormap\n"); |
a268422d OZ |
1113 | goto err_alloc_cmap; |
1114 | } | |
1115 | ||
1116 | rc = register_framebuffer(info); | |
1117 | if (rc < 0) { | |
594a8819 | 1118 | dev_err(info->device, "cannot register framebuffer\n"); |
a268422d OZ |
1119 | goto err_reg_fb; |
1120 | } | |
1121 | ||
1122 | printk(KERN_INFO "fb%d: %s on %s, %d MB RAM, %d MHz MCLK\n", info->node, info->fix.id, | |
1123 | pci_name(dev), info->fix.smem_len >> 20, (par->mclk_freq + 500) / 1000); | |
1124 | ||
1125 | if (par->chip == CHIP_UNKNOWN) | |
1126 | printk(KERN_INFO "fb%d: unknown chip, CR2D=%x, CR2E=%x, CRT2F=%x, CRT30=%x\n", | |
f8645933 DM |
1127 | info->node, vga_rcrt(par->state.vgabase, 0x2d), vga_rcrt(par->state.vgabase, 0x2e), |
1128 | vga_rcrt(par->state.vgabase, 0x2f), vga_rcrt(par->state.vgabase, 0x30)); | |
a268422d OZ |
1129 | |
1130 | /* Record a reference to the driver data */ | |
1131 | pci_set_drvdata(dev, info); | |
1132 | ||
1133 | #ifdef CONFIG_MTRR | |
1134 | if (mtrr) { | |
1135 | par->mtrr_reg = -1; | |
1136 | par->mtrr_reg = mtrr_add(info->fix.smem_start, info->fix.smem_len, MTRR_TYPE_WRCOMB, 1); | |
1137 | } | |
1138 | #endif | |
1139 | ||
1140 | return 0; | |
1141 | ||
1142 | /* Error handling */ | |
1143 | err_reg_fb: | |
1144 | fb_dealloc_cmap(&info->cmap); | |
1145 | err_alloc_cmap: | |
1146 | err_find_mode: | |
1147 | pci_iounmap(dev, info->screen_base); | |
1148 | err_iomap: | |
1149 | pci_release_regions(dev); | |
1150 | err_request_regions: | |
1151 | /* pci_disable_device(dev); */ | |
1152 | err_enable_device: | |
1153 | framebuffer_release(info); | |
1154 | return rc; | |
1155 | } | |
1156 | ||
1157 | ||
1158 | /* PCI remove */ | |
1159 | ||
1160 | static void __devexit s3_pci_remove(struct pci_dev *dev) | |
1161 | { | |
1162 | struct fb_info *info = pci_get_drvdata(dev); | |
a268422d OZ |
1163 | |
1164 | if (info) { | |
1165 | ||
1166 | #ifdef CONFIG_MTRR | |
47ebea83 AB |
1167 | struct s3fb_info *par = info->par; |
1168 | ||
a268422d OZ |
1169 | if (par->mtrr_reg >= 0) { |
1170 | mtrr_del(par->mtrr_reg, 0, 0); | |
1171 | par->mtrr_reg = -1; | |
1172 | } | |
1173 | #endif | |
1174 | ||
1175 | unregister_framebuffer(info); | |
1176 | fb_dealloc_cmap(&info->cmap); | |
1177 | ||
1178 | pci_iounmap(dev, info->screen_base); | |
1179 | pci_release_regions(dev); | |
1180 | /* pci_disable_device(dev); */ | |
1181 | ||
1182 | pci_set_drvdata(dev, NULL); | |
1183 | framebuffer_release(info); | |
1184 | } | |
1185 | } | |
1186 | ||
1187 | /* PCI suspend */ | |
1188 | ||
1189 | static int s3_pci_suspend(struct pci_dev* dev, pm_message_t state) | |
1190 | { | |
1191 | struct fb_info *info = pci_get_drvdata(dev); | |
1192 | struct s3fb_info *par = info->par; | |
1193 | ||
594a8819 | 1194 | dev_info(info->device, "suspend\n"); |
a268422d | 1195 | |
ac751efa | 1196 | console_lock(); |
a268422d OZ |
1197 | mutex_lock(&(par->open_lock)); |
1198 | ||
1199 | if ((state.event == PM_EVENT_FREEZE) || (par->ref_count == 0)) { | |
1200 | mutex_unlock(&(par->open_lock)); | |
ac751efa | 1201 | console_unlock(); |
a268422d OZ |
1202 | return 0; |
1203 | } | |
1204 | ||
1205 | fb_set_suspend(info, 1); | |
1206 | ||
1207 | pci_save_state(dev); | |
1208 | pci_disable_device(dev); | |
1209 | pci_set_power_state(dev, pci_choose_state(dev, state)); | |
1210 | ||
1211 | mutex_unlock(&(par->open_lock)); | |
ac751efa | 1212 | console_unlock(); |
a268422d OZ |
1213 | |
1214 | return 0; | |
1215 | } | |
1216 | ||
1217 | ||
1218 | /* PCI resume */ | |
1219 | ||
1220 | static int s3_pci_resume(struct pci_dev* dev) | |
1221 | { | |
1222 | struct fb_info *info = pci_get_drvdata(dev); | |
1223 | struct s3fb_info *par = info->par; | |
6314db41 | 1224 | int err; |
a268422d | 1225 | |
594a8819 | 1226 | dev_info(info->device, "resume\n"); |
a268422d | 1227 | |
ac751efa | 1228 | console_lock(); |
a268422d OZ |
1229 | mutex_lock(&(par->open_lock)); |
1230 | ||
1231 | if (par->ref_count == 0) { | |
1232 | mutex_unlock(&(par->open_lock)); | |
ac751efa | 1233 | console_unlock(); |
a268422d OZ |
1234 | return 0; |
1235 | } | |
1236 | ||
1237 | pci_set_power_state(dev, PCI_D0); | |
1238 | pci_restore_state(dev); | |
6314db41 RD |
1239 | err = pci_enable_device(dev); |
1240 | if (err) { | |
1241 | mutex_unlock(&(par->open_lock)); | |
ac751efa | 1242 | console_unlock(); |
594a8819 | 1243 | dev_err(info->device, "error %d enabling device for resume\n", err); |
6314db41 RD |
1244 | return err; |
1245 | } | |
a268422d OZ |
1246 | pci_set_master(dev); |
1247 | ||
1248 | s3fb_set_par(info); | |
1249 | fb_set_suspend(info, 0); | |
1250 | ||
1251 | mutex_unlock(&(par->open_lock)); | |
ac751efa | 1252 | console_unlock(); |
a268422d OZ |
1253 | |
1254 | return 0; | |
1255 | } | |
1256 | ||
1257 | ||
1258 | /* List of boards that we are trying to support */ | |
1259 | ||
1260 | static struct pci_device_id s3_devices[] __devinitdata = { | |
1261 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8810), .driver_data = CHIP_XXX_TRIO}, | |
1262 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8811), .driver_data = CHIP_XXX_TRIO}, | |
1263 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8812), .driver_data = CHIP_M65_AURORA64VP}, | |
1264 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8814), .driver_data = CHIP_767_TRIO64UVP}, | |
1265 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8901), .driver_data = CHIP_XXX_TRIO64V2_DXGX}, | |
1266 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8902), .driver_data = CHIP_551_PLATO_PX}, | |
1267 | ||
1268 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x5631), .driver_data = CHIP_325_VIRGE}, | |
1269 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x883D), .driver_data = CHIP_988_VIRGE_VX}, | |
1270 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A01), .driver_data = CHIP_XXX_VIRGE_DXGX}, | |
1271 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A10), .driver_data = CHIP_356_VIRGE_GX2}, | |
1272 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A11), .driver_data = CHIP_357_VIRGE_GX2P}, | |
1273 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A12), .driver_data = CHIP_359_VIRGE_GX2P}, | |
9966c4fe | 1274 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A13), .driver_data = CHIP_36X_TRIO3D_1X_2X}, |
5694f9ce | 1275 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8904), .driver_data = CHIP_365_TRIO3D}, |
a268422d OZ |
1276 | |
1277 | {0, 0, 0, 0, 0, 0, 0} | |
1278 | }; | |
1279 | ||
1280 | ||
1281 | MODULE_DEVICE_TABLE(pci, s3_devices); | |
1282 | ||
1283 | static struct pci_driver s3fb_pci_driver = { | |
1284 | .name = "s3fb", | |
1285 | .id_table = s3_devices, | |
1286 | .probe = s3_pci_probe, | |
1287 | .remove = __devexit_p(s3_pci_remove), | |
1288 | .suspend = s3_pci_suspend, | |
1289 | .resume = s3_pci_resume, | |
1290 | }; | |
1291 | ||
1292 | /* Parse user speficied options */ | |
1293 | ||
1294 | #ifndef MODULE | |
1295 | static int __init s3fb_setup(char *options) | |
1296 | { | |
1297 | char *opt; | |
1298 | ||
1299 | if (!options || !*options) | |
1300 | return 0; | |
1301 | ||
1302 | while ((opt = strsep(&options, ",")) != NULL) { | |
1303 | ||
1304 | if (!*opt) | |
1305 | continue; | |
1306 | #ifdef CONFIG_MTRR | |
62fa4dc7 | 1307 | else if (!strncmp(opt, "mtrr:", 5)) |
a268422d OZ |
1308 | mtrr = simple_strtoul(opt + 5, NULL, 0); |
1309 | #endif | |
62fa4dc7 OZ |
1310 | else if (!strncmp(opt, "fasttext:", 9)) |
1311 | fasttext = simple_strtoul(opt + 9, NULL, 0); | |
a268422d | 1312 | else |
a8140543 | 1313 | mode_option = opt; |
a268422d OZ |
1314 | } |
1315 | ||
1316 | return 0; | |
1317 | } | |
1318 | #endif | |
1319 | ||
1320 | /* Cleanup */ | |
1321 | ||
1322 | static void __exit s3fb_cleanup(void) | |
1323 | { | |
1324 | pr_debug("s3fb: cleaning up\n"); | |
1325 | pci_unregister_driver(&s3fb_pci_driver); | |
1326 | } | |
1327 | ||
1328 | /* Driver Initialisation */ | |
1329 | ||
1330 | static int __init s3fb_init(void) | |
1331 | { | |
1332 | ||
1333 | #ifndef MODULE | |
1334 | char *option = NULL; | |
1335 | ||
1336 | if (fb_get_options("s3fb", &option)) | |
1337 | return -ENODEV; | |
1338 | s3fb_setup(option); | |
1339 | #endif | |
1340 | ||
1341 | pr_debug("s3fb: initializing\n"); | |
1342 | return pci_register_driver(&s3fb_pci_driver); | |
1343 | } | |
1344 | ||
1345 | /* ------------------------------------------------------------------------- */ | |
1346 | ||
1347 | /* Modularization */ | |
1348 | ||
1349 | module_init(s3fb_init); | |
1350 | module_exit(s3fb_cleanup); |