[deliverable/linux.git] / drivers / video / savage / savagefb.h

/*
 * linux/drivers/video/savagefb.h -- S3 Savage Framebuffer Driver
 *
 * Copyright (c) 2001  Denis Oliver Kropp <dok@convergence.de>
 *
 * This file is subject to the terms and conditions of the GNU General
 * Public License.  See the file COPYING in the main directory of this
 * archive for more details.
 */


#ifndef __SAVAGEFB_H__
#define __SAVAGEFB_H__

#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
#include <linux/mutex.h>
#include <video/vga.h>
#include "../edid.h"

#ifdef SAVAGEFB_DEBUG
# define DBG(x)		printk (KERN_DEBUG "savagefb: %s\n", (x));
#else
# define DBG(x)
# define SavagePrintRegs(...)
#endif


#define PCI_CHIP_SAVAGE4      0x8a22
#define PCI_CHIP_SAVAGE3D     0x8a20
#define PCI_CHIP_SAVAGE3D_MV  0x8a21
#define PCI_CHIP_SAVAGE2000   0x9102
#define PCI_CHIP_SAVAGE_MX_MV 0x8c10
#define PCI_CHIP_SAVAGE_MX    0x8c11
#define PCI_CHIP_SAVAGE_IX_MV 0x8c12
#define PCI_CHIP_SAVAGE_IX    0x8c13
#define PCI_CHIP_PROSAVAGE_PM 0x8a25
#define PCI_CHIP_PROSAVAGE_KM 0x8a26
#define PCI_CHIP_S3TWISTER_P  0x8d01
#define PCI_CHIP_S3TWISTER_K  0x8d02
#define PCI_CHIP_PROSAVAGE_DDR          0x8d03
#define PCI_CHIP_PROSAVAGE_DDRK         0x8d04
#define PCI_CHIP_SUPSAV_MX128		0x8c22
#define PCI_CHIP_SUPSAV_MX64		0x8c24
#define PCI_CHIP_SUPSAV_MX64C		0x8c26
#define PCI_CHIP_SUPSAV_IX128SDR	0x8c2a
#define PCI_CHIP_SUPSAV_IX128DDR	0x8c2b
#define PCI_CHIP_SUPSAV_IX64SDR		0x8c2c
#define PCI_CHIP_SUPSAV_IX64DDR		0x8c2d
#define PCI_CHIP_SUPSAV_IXCSDR		0x8c2e
#define PCI_CHIP_SUPSAV_IXCDDR		0x8c2f


#define S3_SAVAGE_SERIES(chip)    ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000))

#define S3_SAVAGE3D_SERIES(chip)  ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX))

#define S3_SAVAGE4_SERIES(chip)   ((chip>=S3_SAVAGE4) && (chip<=S3_PROSAVAGEDDR))

#define S3_SAVAGE_MOBILE_SERIES(chip)  ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE))

#define S3_MOBILE_TWISTER_SERIES(chip) ((chip==S3_TWISTER) || (chip==S3_PROSAVAGEDDR))

/* Chip tags.  These are used to group the adapters into
 * related families.
 */

typedef enum {
  S3_UNKNOWN = 0,
  S3_SAVAGE3D,
  S3_SAVAGE_MX,
  S3_SAVAGE4,
  S3_PROSAVAGE,
  S3_TWISTER,
  S3_PROSAVAGEDDR,
  S3_SUPERSAVAGE,
  S3_SAVAGE2000,
  S3_LAST
} savage_chipset;

#define BIOS_BSIZE		     1024
#define BIOS_BASE		     0xc0000

#define SAVAGE_NEWMMIO_REGBASE_S3    0x1000000  /* 16MB */
#define SAVAGE_NEWMMIO_REGBASE_S4    0x0000000
#define SAVAGE_NEWMMIO_REGSIZE	     0x0080000  /* 512kb */
#define SAVAGE_NEWMMIO_VGABASE	     0x8000

#define BASE_FREQ		     14318
#define HALF_BASE_FREQ               7159

#define FIFO_CONTROL_REG	     0x8200
#define MIU_CONTROL_REG		     0x8204
#define STREAMS_TIMEOUT_REG	     0x8208
#define MISC_TIMEOUT_REG	     0x820c

#define MONO_PAT_0                   0xa4e8
#define MONO_PAT_1                   0xa4ec

#define MAXFIFO                      0x7f00

#define BCI_CMD_NOP                  0x40000000
#define BCI_CMD_SETREG               0x96000000
#define BCI_CMD_RECT                 0x48000000
#define BCI_CMD_RECT_XP              0x01000000
#define BCI_CMD_RECT_YP              0x02000000
#define BCI_CMD_SEND_COLOR           0x00008000
#define BCI_CMD_DEST_GBD             0x00000000
#define BCI_CMD_SRC_GBD              0x00000020
#define BCI_CMD_SRC_SOLID            0x00000000
#define BCI_CMD_SRC_MONO             0x00000060
#define BCI_CMD_CLIP_NEW             0x00006000
#define BCI_CMD_CLIP_LR              0x00004000

#define BCI_CLIP_LR(l, r)            ((((r) << 16) | (l)) & 0x0FFF0FFF)
#define BCI_CLIP_TL(t, l)            ((((t) << 16) | (l)) & 0x0FFF0FFF)
#define BCI_CLIP_BR(b, r)            ((((b) << 16) | (r)) & 0x0FFF0FFF)
#define BCI_W_H(w, h)                (((h) << 16) | ((w) & 0xFFF))
#define BCI_X_Y(x, y)                (((y) << 16) | ((x) & 0xFFF))

#define BCI_GBD1                     0xE0
#define BCI_GBD2                     0xE1

#define BCI_BUFFER_OFFSET            0x10000
#define BCI_SIZE                     0x4000

#define BCI_SEND(dw)                 writel(dw, par->bci_base + par->bci_ptr++)

#define BCI_CMD_GET_ROP(cmd)         (((cmd) >> 16) & 0xFF)
#define BCI_CMD_SET_ROP(cmd, rop)    ((cmd) |= ((rop & 0xFF) << 16))
#define BCI_CMD_SEND_COLOR           0x00008000

#define DISP_CRT     1
#define DISP_LCD     2
#define DISP_DFP     3

struct xtimings {
	unsigned int Clock;
	unsigned int HDisplay;
	unsigned int HSyncStart;
	unsigned int HSyncEnd;
	unsigned int HTotal;
	unsigned int HAdjusted;
	unsigned int VDisplay;
	unsigned int VSyncStart;
	unsigned int VSyncEnd;
	unsigned int VTotal;
	unsigned int sync;
	int	       dblscan;
	int	       interlaced;
};

struct savage_reg {
	unsigned char MiscOutReg;     /* Misc */
	unsigned char CRTC[25];       /* Crtc Controller */
	unsigned char Sequencer[5];   /* Video Sequencer */
	unsigned char Graphics[9];    /* Video Graphics */
	unsigned char Attribute[21];  /* Video Attribute */

	unsigned int mode, refresh;
	unsigned char SR08, SR0E, SR0F;
	unsigned char SR10, SR11, SR12, SR13, SR15, SR18, SR29, SR30;
	unsigned char SR54[8];
	unsigned char Clock;
	unsigned char CR31, CR32, CR33, CR34, CR36, CR3A, CR3B, CR3C;
	unsigned char CR40, CR41, CR42, CR43, CR45;
	unsigned char CR50, CR51, CR53, CR55, CR58, CR5B, CR5D, CR5E;
	unsigned char CR60, CR63, CR65, CR66, CR67, CR68, CR69, CR6D, CR6F;
	unsigned char CR86, CR88;
	unsigned char CR90, CR91, CRB0;
	unsigned int  STREAMS[22];	/* yuck, streams regs */
	unsigned int  MMPR0, MMPR1, MMPR2, MMPR3;
};
/* --------------------------------------------------------------------- */

#define NR_PALETTE	256


struct savagefb_par;

struct savagefb_i2c_chan {
	struct savagefb_par *par;
	struct i2c_adapter adapter;
	struct i2c_algo_bit_data algo;
	volatile u8 __iomem *ioaddr;
	u32   reg;
};

struct savagefb_par {
	struct pci_dev *pcidev;
	savage_chipset  chip;
	struct savagefb_i2c_chan chan;
	struct savage_reg state;
	struct savage_reg save;
	struct savage_reg initial;
	struct vgastate vgastate;
	struct mutex open_lock;
	unsigned char   *edid;
	u32 pseudo_palette[16];
	u32 open_count;
	int paletteEnabled;
	int pm_state;
	int display_type;
	int dvi;
	int crtonly;
	int dacSpeedBpp;
	int maxClock;
	int minClock;
	int numClocks;
	int clock[4];
	int MCLK, REFCLK, LCDclk;
	struct {
		void   __iomem *vbase;
		u32    pbase;
		u32    len;
#ifdef CONFIG_MTRR
		int    mtrr;
#endif
	} video;

	struct {
		void  __iomem *vbase;
		u32           pbase;
		u32           len;
	} mmio;

	volatile u32  __iomem *bci_base;
	unsigned int  bci_ptr;
	u32           cob_offset;
	u32           cob_size;
	int           cob_index;

	void (*SavageWaitIdle) (struct savagefb_par *par);
	void (*SavageWaitFifo) (struct savagefb_par *par, int space);

	int HorizScaleFactor;

	/* Panels size */
	int SavagePanelWidth;
	int SavagePanelHeight;

	struct {
		u16 red, green, blue, transp;
	} palette[NR_PALETTE];

	int depth;
	int vwidth;
};

#define BCI_BD_BW_DISABLE            0x10000000
#define BCI_BD_SET_BPP(bd, bpp)      ((bd) |= (((bpp) & 0xFF) << 16))
#define BCI_BD_SET_STRIDE(bd, st)    ((bd) |= ((st) & 0xFFFF))


/* IO functions */
static inline u8 savage_in8(u32 addr, struct savagefb_par *par)
{
	return readb(par->mmio.vbase + addr);
}

static inline u16 savage_in16(u32 addr, struct savagefb_par *par)
{
	return readw(par->mmio.vbase + addr);
}

static inline u32 savage_in32(u32 addr, struct savagefb_par *par)
{
	return readl(par->mmio.vbase + addr);
}

static inline void savage_out8(u32 addr, u8 val, struct savagefb_par *par)
{
	writeb(val, par->mmio.vbase + addr);
}

static inline void savage_out16(u32 addr, u16 val, struct savagefb_par *par)
{
	writew(val, par->mmio.vbase + addr);
}

static inline void savage_out32(u32 addr, u32 val, struct savagefb_par *par)
{
	writel(val, par->mmio.vbase + addr);
}

static inline u8 vga_in8(int addr, struct savagefb_par *par)
{
	return savage_in8(0x8000 + addr, par);
}

static inline u16 vga_in16(int addr, struct savagefb_par *par)
{
	return savage_in16(0x8000 + addr, par);
}

static inline u8 vga_in32(int addr, struct savagefb_par *par)
{
	return savage_in32(0x8000 + addr, par);
}

static inline void vga_out8(int addr, u8 val, struct savagefb_par *par)
{
	savage_out8(0x8000 + addr, val, par);
}

static inline void vga_out16(int addr, u16 val, struct savagefb_par *par)
{
	savage_out16(0x8000 + addr, val, par);
}

static inline void vga_out32(int addr, u32 val, struct savagefb_par *par)
{
	savage_out32(0x8000 + addr, val, par);
}

static inline u8 VGArCR (u8 index, struct savagefb_par *par)
{
	vga_out8(0x3d4, index,  par);
	return vga_in8(0x3d5, par);
}

static inline u8 VGArGR (u8 index, struct savagefb_par *par)
{
	vga_out8(0x3ce, index, par);
	return vga_in8(0x3cf, par);
}

static inline u8 VGArSEQ (u8 index, struct savagefb_par *par)
{
	vga_out8(0x3c4, index, par);
	return vga_in8(0x3c5, par);
}

static inline void VGAwCR(u8 index, u8 val, struct savagefb_par *par)
{
	vga_out8(0x3d4, index, par);
	vga_out8(0x3d5, val, par);
}

static inline void VGAwGR(u8 index, u8 val, struct savagefb_par *par)
{
	vga_out8(0x3ce, index, par);
	vga_out8(0x3cf, val, par);
}

static inline void VGAwSEQ(u8 index, u8 val, struct savagefb_par *par)
{
	vga_out8(0x3c4, index, par);
	vga_out8 (0x3c5, val, par);
}

static inline void VGAenablePalette(struct savagefb_par *par)
{
	u8 tmp;

	tmp = vga_in8(0x3da, par);
	vga_out8(0x3c0, 0x00, par);
	par->paletteEnabled = 1;
}

static inline void VGAdisablePalette(struct savagefb_par *par)
{
	u8 tmp;

	tmp = vga_in8(0x3da, par);
	vga_out8(0x3c0, 0x20, par);
	par->paletteEnabled = 0;
}

static inline void VGAwATTR(u8 index, u8 value, struct savagefb_par *par)
{
	u8 tmp;

	if (par->paletteEnabled)
		index &= ~0x20;
	else
		index |= 0x20;

	tmp = vga_in8(0x3da, par);
	vga_out8(0x3c0, index, par);
	vga_out8 (0x3c0, value, par);
}

static inline void VGAwMISC(u8 value, struct savagefb_par *par)
{
	vga_out8(0x3c2, value, par);
}

#ifndef CONFIG_FB_SAVAGE_ACCEL
#define savagefb_set_clip(x)
#endif

static inline void VerticalRetraceWait(struct savagefb_par *par)
{
	vga_out8(0x3d4, 0x17, par);
	if (vga_in8(0x3d5, par) & 0x80) {
		while ((vga_in8(0x3da, par) & 0x08) == 0x08);
		while ((vga_in8(0x3da, par) & 0x08) == 0x00);
	}
}

extern int savagefb_probe_i2c_connector(struct fb_info *info,
					u8 **out_edid);
extern void savagefb_create_i2c_busses(struct fb_info *info);
extern void savagefb_delete_i2c_busses(struct fb_info *info);
extern int  savagefb_sync(struct fb_info *info);
extern void savagefb_copyarea(struct fb_info *info,
			      const struct fb_copyarea *region);
extern void savagefb_fillrect(struct fb_info *info,
			      const struct fb_fillrect *rect);
extern void savagefb_imageblit(struct fb_info *info,
			       const struct fb_image *image);


#endif /* __SAVAGEFB_H__ */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/drivers/video/savagefb.h -- S3 Savage Framebuffer Driver
	3	*
	4	* Copyright (c) 2001 Denis Oliver Kropp <dok@convergence.de>
	5	*
	6	* This file is subject to the terms and conditions of the GNU General
	7	* Public License. See the file COPYING in the main directory of this
	8	* archive for more details.
	9	*/
	10
	11
	12	#ifndef __SAVAGEFB_H__
	13	#define __SAVAGEFB_H__
	14
	15	#include <linux/i2c.h>
1da177e4	16	#include <linux/i2c-algo-bit.h>
22d832ed AD	17	#include <linux/mutex.h>
22d832ed AD	18	#include <video/vga.h>
1da177e4 LT	19	#include "../edid.h"
	20
	21	#ifdef SAVAGEFB_DEBUG
	22	# define DBG(x) printk (KERN_DEBUG "savagefb: %s\n", (x));
	23	#else
	24	# define DBG(x)
	25	# define SavagePrintRegs(...)
	26	#endif
	27
	28
	29	#define PCI_CHIP_SAVAGE4 0x8a22
	30	#define PCI_CHIP_SAVAGE3D 0x8a20
	31	#define PCI_CHIP_SAVAGE3D_MV 0x8a21
	32	#define PCI_CHIP_SAVAGE2000 0x9102
	33	#define PCI_CHIP_SAVAGE_MX_MV 0x8c10
	34	#define PCI_CHIP_SAVAGE_MX 0x8c11
	35	#define PCI_CHIP_SAVAGE_IX_MV 0x8c12
	36	#define PCI_CHIP_SAVAGE_IX 0x8c13
	37	#define PCI_CHIP_PROSAVAGE_PM 0x8a25
	38	#define PCI_CHIP_PROSAVAGE_KM 0x8a26
1da177e4 LT	39	#define PCI_CHIP_S3TWISTER_P 0x8d01
	40	#define PCI_CHIP_S3TWISTER_K 0x8d02
	41	#define PCI_CHIP_PROSAVAGE_DDR 0x8d03
	42	#define PCI_CHIP_PROSAVAGE_DDRK 0x8d04
	43	#define PCI_CHIP_SUPSAV_MX128 0x8c22
	44	#define PCI_CHIP_SUPSAV_MX64 0x8c24
	45	#define PCI_CHIP_SUPSAV_MX64C 0x8c26
	46	#define PCI_CHIP_SUPSAV_IX128SDR 0x8c2a
	47	#define PCI_CHIP_SUPSAV_IX128DDR 0x8c2b
	48	#define PCI_CHIP_SUPSAV_IX64SDR 0x8c2c
	49	#define PCI_CHIP_SUPSAV_IX64DDR 0x8c2d
	50	#define PCI_CHIP_SUPSAV_IXCSDR 0x8c2e
	51	#define PCI_CHIP_SUPSAV_IXCDDR 0x8c2f
	52
	53
cc406341	54	#define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000))
1da177e4 LT	55
	56	#define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX))
	57
4b00e4b3	58	#define S3_SAVAGE4_SERIES(chip) ((chip>=S3_SAVAGE4) && (chip<=S3_PROSAVAGEDDR))
1da177e4 LT	59
	60	#define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) \|\| (chip==S3_SUPERSAVAGE))
	61
cc406341	62	#define S3_MOBILE_TWISTER_SERIES(chip) ((chip==S3_TWISTER) \|\| (chip==S3_PROSAVAGEDDR))
1da177e4	63
1da177e4 LT	64	/* Chip tags. These are used to group the adapters into
	65	* related families.
	66	*/
	67
	68	typedef enum {
	69	S3_UNKNOWN = 0,
	70	S3_SAVAGE3D,
	71	S3_SAVAGE_MX,
	72	S3_SAVAGE4,
	73	S3_PROSAVAGE,
cc406341 TV	74	S3_TWISTER,
cc406341 TV	75	S3_PROSAVAGEDDR,
1da177e4 LT	76	S3_SUPERSAVAGE,
	77	S3_SAVAGE2000,
	78	S3_LAST
	79	} savage_chipset;
	80
	81	#define BIOS_BSIZE 1024
	82	#define BIOS_BASE 0xc0000
	83
	84	#define SAVAGE_NEWMMIO_REGBASE_S3 0x1000000 /* 16MB */
	85	#define SAVAGE_NEWMMIO_REGBASE_S4 0x0000000
	86	#define SAVAGE_NEWMMIO_REGSIZE 0x0080000 /* 512kb */
	87	#define SAVAGE_NEWMMIO_VGABASE 0x8000
	88
	89	#define BASE_FREQ 14318
	90	#define HALF_BASE_FREQ 7159
	91
	92	#define FIFO_CONTROL_REG 0x8200
	93	#define MIU_CONTROL_REG 0x8204
	94	#define STREAMS_TIMEOUT_REG 0x8208
	95	#define MISC_TIMEOUT_REG 0x820c
	96
	97	#define MONO_PAT_0 0xa4e8
	98	#define MONO_PAT_1 0xa4ec
	99
	100	#define MAXFIFO 0x7f00
	101
	102	#define BCI_CMD_NOP 0x40000000
	103	#define BCI_CMD_SETREG 0x96000000
	104	#define BCI_CMD_RECT 0x48000000
	105	#define BCI_CMD_RECT_XP 0x01000000
	106	#define BCI_CMD_RECT_YP 0x02000000
	107	#define BCI_CMD_SEND_COLOR 0x00008000
	108	#define BCI_CMD_DEST_GBD 0x00000000
	109	#define BCI_CMD_SRC_GBD 0x00000020
	110	#define BCI_CMD_SRC_SOLID 0x00000000
	111	#define BCI_CMD_SRC_MONO 0x00000060
	112	#define BCI_CMD_CLIP_NEW 0x00006000
	113	#define BCI_CMD_CLIP_LR 0x00004000
	114
	115	#define BCI_CLIP_LR(l, r) ((((r) << 16) \| (l)) & 0x0FFF0FFF)
	116	#define BCI_CLIP_TL(t, l) ((((t) << 16) \| (l)) & 0x0FFF0FFF)
	117	#define BCI_CLIP_BR(b, r) ((((b) << 16) \| (r)) & 0x0FFF0FFF)
	118	#define BCI_W_H(w, h) (((h) << 16) \| ((w) & 0xFFF))
	119	#define BCI_X_Y(x, y) (((y) << 16) \| ((x) & 0xFFF))
	120
	121	#define BCI_GBD1 0xE0
	122	#define BCI_GBD2 0xE1
	123
	124	#define BCI_BUFFER_OFFSET 0x10000
	125	#define BCI_SIZE 0x4000
	126
	127	#define BCI_SEND(dw) writel(dw, par->bci_base + par->bci_ptr++)
	128
	129	#define BCI_CMD_GET_ROP(cmd) (((cmd) >> 16) & 0xFF)
	130	#define BCI_CMD_SET_ROP(cmd, rop) ((cmd) \|= ((rop & 0xFF) << 16))
	131	#define BCI_CMD_SEND_COLOR 0x00008000
	132
13776711 AD	133	#define DISP_CRT 1
	134	#define DISP_LCD 2
	135	#define DISP_DFP 3
	136
1da177e4 LT	137	struct xtimings {
	138	unsigned int Clock;
	139	unsigned int HDisplay;
	140	unsigned int HSyncStart;
	141	unsigned int HSyncEnd;
	142	unsigned int HTotal;
	143	unsigned int HAdjusted;
	144	unsigned int VDisplay;
	145	unsigned int VSyncStart;
	146	unsigned int VSyncEnd;
	147	unsigned int VTotal;
	148	unsigned int sync;
	149	int dblscan;
	150	int interlaced;
	151	};
	152
2356614b AD	153	struct savage_reg {
	154	unsigned char MiscOutReg; /* Misc */
	155	unsigned char CRTC[25]; /* Crtc Controller */
	156	unsigned char Sequencer[5]; /* Video Sequencer */
	157	unsigned char Graphics[9]; /* Video Graphics */
25985edc	158	unsigned char Attribute[21]; /* Video Attribute */
1da177e4	159
2356614b AD	160	unsigned int mode, refresh;
	161	unsigned char SR08, SR0E, SR0F;
	162	unsigned char SR10, SR11, SR12, SR13, SR15, SR18, SR29, SR30;
	163	unsigned char SR54[8];
	164	unsigned char Clock;
	165	unsigned char CR31, CR32, CR33, CR34, CR36, CR3A, CR3B, CR3C;
	166	unsigned char CR40, CR41, CR42, CR43, CR45;
	167	unsigned char CR50, CR51, CR53, CR55, CR58, CR5B, CR5D, CR5E;
	168	unsigned char CR60, CR63, CR65, CR66, CR67, CR68, CR69, CR6D, CR6F;
	169	unsigned char CR86, CR88;
	170	unsigned char CR90, CR91, CRB0;
	171	unsigned int STREAMS[22]; /* yuck, streams regs */
	172	unsigned int MMPR0, MMPR1, MMPR2, MMPR3;
	173	};
1da177e4 LT	174	/* --------------------------------------------------------------------- */
	175
	176	#define NR_PALETTE 256
	177
	178
	179	struct savagefb_par;
	180
	181	struct savagefb_i2c_chan {
	182	struct savagefb_par *par;
	183	struct i2c_adapter adapter;
	184	struct i2c_algo_bit_data algo;
	185	volatile u8 __iomem *ioaddr;
	186	u32 reg;
	187	};
	188
	189	struct savagefb_par {
	190	struct pci_dev *pcidev;
	191	savage_chipset chip;
	192	struct savagefb_i2c_chan chan;
2356614b AD	193	struct savage_reg state;
2356614b AD	194	struct savage_reg save;
22d832ed AD	195	struct savage_reg initial;
	196	struct vgastate vgastate;
	197	struct mutex open_lock;
1da177e4 LT	198	unsigned char *edid;
1da177e4 LT	199	u32 pseudo_palette[16];
22d832ed	200	u32 open_count;
1cc650c6	201	int paletteEnabled;
13776711 AD	202	int pm_state;
	203	int display_type;
	204	int dvi;
	205	int crtonly;
1da177e4 LT	206	int dacSpeedBpp;
	207	int maxClock;
	208	int minClock;
	209	int numClocks;
	210	int clock[4];
2356614b	211	int MCLK, REFCLK, LCDclk;
1da177e4	212	struct {
22d832ed	213	void __iomem *vbase;
1da177e4 LT	214	u32 pbase;
	215	u32 len;
	216	#ifdef CONFIG_MTRR
	217	int mtrr;
	218	#endif
	219	} video;
	220
	221	struct {
22d832ed	222	void __iomem *vbase;
1da177e4 LT	223	u32 pbase;
	224	u32 len;
	225	} mmio;
	226
	227	volatile u32 __iomem *bci_base;
	228	unsigned int bci_ptr;
1da177e4 LT	229	u32 cob_offset;
	230	u32 cob_size;
	231	int cob_index;
	232
	233	void (SavageWaitIdle) (struct savagefb_par par);
	234	void (SavageWaitFifo) (struct savagefb_par par, int space);
	235
1da177e4 LT	236	int HorizScaleFactor;
	237
	238	/* Panels size */
	239	int SavagePanelWidth;
	240	int SavagePanelHeight;
	241
	242	struct {
	243	u16 red, green, blue, transp;
	244	} palette[NR_PALETTE];
	245
	246	int depth;
	247	int vwidth;
1da177e4 LT	248	};
	249
	250	#define BCI_BD_BW_DISABLE 0x10000000
	251	#define BCI_BD_SET_BPP(bd, bpp) ((bd) \|= (((bpp) & 0xFF) << 16))
	252	#define BCI_BD_SET_STRIDE(bd, st) ((bd) \|= ((st) & 0xFFFF))
	253
	254
	255	/* IO functions */
1cc650c6 AD	256	static inline u8 savage_in8(u32 addr, struct savagefb_par *par)
	257	{
	258	return readb(par->mmio.vbase + addr);
	259	}
	260
	261	static inline u16 savage_in16(u32 addr, struct savagefb_par *par)
	262	{
	263	return readw(par->mmio.vbase + addr);
	264	}
	265
	266	static inline u32 savage_in32(u32 addr, struct savagefb_par *par)
	267	{
	268	return readl(par->mmio.vbase + addr);
	269	}
	270
	271	static inline void savage_out8(u32 addr, u8 val, struct savagefb_par *par)
	272	{
	273	writeb(val, par->mmio.vbase + addr);
	274	}
	275
	276	static inline void savage_out16(u32 addr, u16 val, struct savagefb_par *par)
	277	{
	278	writew(val, par->mmio.vbase + addr);
	279	}
	280
	281	static inline void savage_out32(u32 addr, u32 val, struct savagefb_par *par)
	282	{
	283	writel(val, par->mmio.vbase + addr);
	284	}
	285
	286	static inline u8 vga_in8(int addr, struct savagefb_par *par)
	287	{
	288	return savage_in8(0x8000 + addr, par);
	289	}
	290
	291	static inline u16 vga_in16(int addr, struct savagefb_par *par)
	292	{
	293	return savage_in16(0x8000 + addr, par);
	294	}
	295
	296	static inline u8 vga_in32(int addr, struct savagefb_par *par)
	297	{
	298	return savage_in32(0x8000 + addr, par);
	299	}
	300
	301	static inline void vga_out8(int addr, u8 val, struct savagefb_par *par)
	302	{
	303	savage_out8(0x8000 + addr, val, par);
	304	}
	305
	306	static inline void vga_out16(int addr, u16 val, struct savagefb_par *par)
	307	{
	308	savage_out16(0x8000 + addr, val, par);
	309	}
	310
	311	static inline void vga_out32(int addr, u32 val, struct savagefb_par *par)
	312	{
	313	savage_out32(0x8000 + addr, val, par);
	314	}
1da177e4	315
1cc650c6 AD	316	static inline u8 VGArCR (u8 index, struct savagefb_par *par)
	317	{
	318	vga_out8(0x3d4, index, par);
	319	return vga_in8(0x3d5, par);
	320	}
	321
	322	static inline u8 VGArGR (u8 index, struct savagefb_par *par)
	323	{
	324	vga_out8(0x3ce, index, par);
	325	return vga_in8(0x3cf, par);
	326	}
	327
	328	static inline u8 VGArSEQ (u8 index, struct savagefb_par *par)
	329	{
	330	vga_out8(0x3c4, index, par);
	331	return vga_in8(0x3c5, par);
	332	}
1da177e4	333
1cc650c6 AD	334	static inline void VGAwCR(u8 index, u8 val, struct savagefb_par *par)
	335	{
	336	vga_out8(0x3d4, index, par);
	337	vga_out8(0x3d5, val, par);
	338	}
1da177e4	339
1cc650c6 AD	340	static inline void VGAwGR(u8 index, u8 val, struct savagefb_par *par)
	341	{
	342	vga_out8(0x3ce, index, par);
	343	vga_out8(0x3cf, val, par);
	344	}
1da177e4	345
1cc650c6 AD	346	static inline void VGAwSEQ(u8 index, u8 val, struct savagefb_par *par)
	347	{
	348	vga_out8(0x3c4, index, par);
	349	vga_out8 (0x3c5, val, par);
	350	}
1da177e4	351
1cc650c6	352	static inline void VGAenablePalette(struct savagefb_par *par)
1da177e4	353	{
1cc650c6 AD	354	u8 tmp;
	355
	356	tmp = vga_in8(0x3da, par);
	357	vga_out8(0x3c0, 0x00, par);
	358	par->paletteEnabled = 1;
1da177e4 LT	359	}
1da177e4 LT	360
1cc650c6	361	static inline void VGAdisablePalette(struct savagefb_par *par)
1da177e4	362	{
1cc650c6 AD	363	u8 tmp;
	364
	365	tmp = vga_in8(0x3da, par);
	366	vga_out8(0x3c0, 0x20, par);
	367	par->paletteEnabled = 0;
1da177e4 LT	368	}
1da177e4 LT	369
1cc650c6	370	static inline void VGAwATTR(u8 index, u8 value, struct savagefb_par *par)
1da177e4	371	{
1cc650c6 AD	372	u8 tmp;
	373
	374	if (par->paletteEnabled)
	375	index &= ~0x20;
	376	else
	377	index \|= 0x20;
	378
	379	tmp = vga_in8(0x3da, par);
	380	vga_out8(0x3c0, index, par);
	381	vga_out8 (0x3c0, value, par);
1da177e4 LT	382	}
1da177e4 LT	383
1cc650c6 AD	384	static inline void VGAwMISC(u8 value, struct savagefb_par *par)
	385	{
	386	vga_out8(0x3c2, value, par);
	387	}
1da177e4 LT	388
	389	#ifndef CONFIG_FB_SAVAGE_ACCEL
	390	#define savagefb_set_clip(x)
	391	#endif
	392
1cc650c6 AD	393	static inline void VerticalRetraceWait(struct savagefb_par *par)
	394	{
	395	vga_out8(0x3d4, 0x17, par);
	396	if (vga_in8(0x3d5, par) & 0x80) {
	397	while ((vga_in8(0x3da, par) & 0x08) == 0x08);
	398	while ((vga_in8(0x3da, par) & 0x08) == 0x00);
	399	}
1da177e4 LT	400	}
1da177e4 LT	401
13776711	402	extern int savagefb_probe_i2c_connector(struct fb_info *info,
1da177e4 LT	403	u8 **out_edid);
	404	extern void savagefb_create_i2c_busses(struct fb_info *info);
	405	extern void savagefb_delete_i2c_busses(struct fb_info *info);
	406	extern int savagefb_sync(struct fb_info *info);
	407	extern void savagefb_copyarea(struct fb_info *info,
	408	const struct fb_copyarea *region);
	409	extern void savagefb_fillrect(struct fb_info *info,
	410	const struct fb_fillrect *rect);
	411	extern void savagefb_imageblit(struct fb_info *info,
	412	const struct fb_image *image);
	413
	414
	415	#endif /* __SAVAGEFB_H__ */