[deliverable/linux.git] / drivers / video / sh_mipi_dsi.c

/*
 * Renesas SH-mobile MIPI DSI support
 *
 * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
 *
 * This is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 */

#include <linux/bitmap.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/types.h>
#include <linux/module.h>

#include <video/mipi_display.h>
#include <video/sh_mipi_dsi.h>
#include <video/sh_mobile_lcdc.h>

#include "sh_mobile_lcdcfb.h"

#define SYSCTRL		0x0000
#define SYSCONF		0x0004
#define TIMSET		0x0008
#define RESREQSET0	0x0018
#define RESREQSET1	0x001c
#define HSTTOVSET	0x0020
#define LPRTOVSET	0x0024
#define TATOVSET	0x0028
#define PRTOVSET	0x002c
#define DSICTRL		0x0030
#define DSIINTE		0x0060
#define PHYCTRL		0x0070

/* relative to linkbase */
#define DTCTR		0x0000
#define VMCTR1		0x0020
#define VMCTR2		0x0024
#define VMLEN1		0x0028
#define VMLEN2		0x002c
#define CMTSRTREQ	0x0070
#define CMTSRTCTR	0x00d0

/* E.g., sh7372 has 2 MIPI-DSIs - one for each LCDC */
#define MAX_SH_MIPI_DSI 2

struct sh_mipi {
	struct sh_mobile_lcdc_entity entity;

	void __iomem	*base;
	void __iomem	*linkbase;
	struct clk	*dsit_clk;
	struct platform_device *pdev;
};

#define to_sh_mipi(e)	container_of(e, struct sh_mipi, entity)

static struct sh_mipi *mipi_dsi[MAX_SH_MIPI_DSI];

/* Protect the above array */
static DEFINE_MUTEX(array_lock);

static struct sh_mipi *sh_mipi_by_handle(int handle)
{
	if (handle >= ARRAY_SIZE(mipi_dsi) || handle < 0)
		return NULL;

	return mipi_dsi[handle];
}

static int sh_mipi_send_short(struct sh_mipi *mipi, u8 dsi_cmd,
			      u8 cmd, u8 param)
{
	u32 data = (dsi_cmd << 24) | (cmd << 16) | (param << 8);
	int cnt = 100;

	/* transmit a short packet to LCD panel */
	iowrite32(1 | data, mipi->linkbase + CMTSRTCTR);
	iowrite32(1, mipi->linkbase + CMTSRTREQ);

	while ((ioread32(mipi->linkbase + CMTSRTREQ) & 1) && --cnt)
		udelay(1);

	return cnt ? 0 : -ETIMEDOUT;
}

#define LCD_CHAN2MIPI(c) ((c) < LCDC_CHAN_MAINLCD || (c) > LCDC_CHAN_SUBLCD ? \
				-EINVAL : (c) - 1)

static int sh_mipi_dcs(int handle, u8 cmd)
{
	struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
	if (!mipi)
		return -ENODEV;
	return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE, cmd, 0);
}

static int sh_mipi_dcs_param(int handle, u8 cmd, u8 param)
{
	struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
	if (!mipi)
		return -ENODEV;
	return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE_PARAM, cmd,
				  param);
}

static void sh_mipi_dsi_enable(struct sh_mipi *mipi, bool enable)
{
	/*
	 * enable LCDC data tx, transition to LPS after completion of each HS
	 * packet
	 */
	iowrite32(0x00000002 | enable, mipi->linkbase + DTCTR);
}

static void sh_mipi_shutdown(struct platform_device *pdev)
{
	struct sh_mipi *mipi = to_sh_mipi(platform_get_drvdata(pdev));

	sh_mipi_dsi_enable(mipi, false);
}

static int __init sh_mipi_setup(struct sh_mipi *mipi,
				struct sh_mipi_dsi_info *pdata)
{
	void __iomem *base = mipi->base;
	struct sh_mobile_lcdc_chan_cfg *ch = pdata->lcd_chan;
	u32 pctype, datatype, pixfmt, linelength, vmctr2;
	u32 tmp, top, bottom, delay, div;
	bool yuv;
	int bpp;

	/*
	 * Select data format. MIPI DSI is not hot-pluggable, so, we just use
	 * the default videomode. If this ever becomes a problem, We'll have to
	 * move this to mipi_display_on() above and use info->var.xres
	 */
	switch (pdata->data_format) {
	case MIPI_RGB888:
		pctype = 0;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
		pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
		linelength = ch->lcd_modes[0].xres * 3;
		yuv = false;
		break;
	case MIPI_RGB565:
		pctype = 1;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
		pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
		linelength = ch->lcd_modes[0].xres * 2;
		yuv = false;
		break;
	case MIPI_RGB666_LP:
		pctype = 2;
		datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
		pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
		linelength = ch->lcd_modes[0].xres * 3;
		yuv = false;
		break;
	case MIPI_RGB666:
		pctype = 3;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
		pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
		linelength = (ch->lcd_modes[0].xres * 18 + 7) / 8;
		yuv = false;
		break;
	case MIPI_BGR888:
		pctype = 8;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
		pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
		linelength = ch->lcd_modes[0].xres * 3;
		yuv = false;
		break;
	case MIPI_BGR565:
		pctype = 9;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
		pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
		linelength = ch->lcd_modes[0].xres * 2;
		yuv = false;
		break;
	case MIPI_BGR666_LP:
		pctype = 0xa;
		datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
		pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
		linelength = ch->lcd_modes[0].xres * 3;
		yuv = false;
		break;
	case MIPI_BGR666:
		pctype = 0xb;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
		pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
		linelength = (ch->lcd_modes[0].xres * 18 + 7) / 8;
		yuv = false;
		break;
	case MIPI_YUYV:
		pctype = 4;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
		pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
		linelength = ch->lcd_modes[0].xres * 2;
		yuv = true;
		break;
	case MIPI_UYVY:
		pctype = 5;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
		pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
		linelength = ch->lcd_modes[0].xres * 2;
		yuv = true;
		break;
	case MIPI_YUV420_L:
		pctype = 6;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
		pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
		linelength = (ch->lcd_modes[0].xres * 12 + 7) / 8;
		yuv = true;
		break;
	case MIPI_YUV420:
		pctype = 7;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
		pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
		/* Length of U/V line */
		linelength = (ch->lcd_modes[0].xres + 1) / 2;
		yuv = true;
		break;
	default:
		return -EINVAL;
	}

	if ((yuv && ch->interface_type != YUV422) ||
	    (!yuv && ch->interface_type != RGB24))
		return -EINVAL;

	if (!pdata->lane)
		return -EINVAL;

	/* reset DSI link */
	iowrite32(0x00000001, base + SYSCTRL);
	/* Hold reset for 100 cycles of the slowest of bus, HS byte and LP clock */
	udelay(50);
	iowrite32(0x00000000, base + SYSCTRL);

	/* setup DSI link */

	/*
	 * T_wakeup = 0x7000
	 * T_hs-trail = 3
	 * T_hs-prepare = 3
	 * T_clk-trail = 3
	 * T_clk-prepare = 2
	 */
	iowrite32(0x70003332, base + TIMSET);
	/* no responses requested */
	iowrite32(0x00000000, base + RESREQSET0);
	/* request response to packets of type 0x28 */
	iowrite32(0x00000100, base + RESREQSET1);
	/* High-speed transmission timeout, default 0xffffffff */
	iowrite32(0x0fffffff, base + HSTTOVSET);
	/* LP reception timeout, default 0xffffffff */
	iowrite32(0x0fffffff, base + LPRTOVSET);
	/* Turn-around timeout, default 0xffffffff */
	iowrite32(0x0fffffff, base + TATOVSET);
	/* Peripheral reset timeout, default 0xffffffff */
	iowrite32(0x0fffffff, base + PRTOVSET);
	/* Interrupts not used, disable all */
	iowrite32(0, base + DSIINTE);
	/* DSI-Tx bias on */
	iowrite32(0x00000001, base + PHYCTRL);
	udelay(200);
	/* Deassert resets, power on */
	iowrite32(0x03070001 | pdata->phyctrl, base + PHYCTRL);

	/*
	 * Default = ULPS enable |
	 *	Contention detection enabled |
	 *	EoT packet transmission enable |
	 *	CRC check enable |
	 *	ECC check enable
	 */
	bitmap_fill((unsigned long *)&tmp, pdata->lane);
	tmp |= 0x00003700;
	iowrite32(tmp, base + SYSCONF);

	/* setup l-bridge */

	/*
	 * Enable transmission of all packets,
	 * transmit LPS after each HS packet completion
	 */
	iowrite32(0x00000006, mipi->linkbase + DTCTR);
	/* VSYNC width = 2 (<< 17) */
	iowrite32((ch->lcd_modes[0].vsync_len << pdata->vsynw_offset) |
		  (pdata->clksrc << 16) | (pctype << 12) | datatype,
		  mipi->linkbase + VMCTR1);

	/*
	 * Non-burst mode with sync pulses: VSE and HSE are output,
	 * HSA period allowed, no commands in LP
	 */
	vmctr2 = 0;
	if (pdata->flags & SH_MIPI_DSI_VSEE)
		vmctr2 |= 1 << 23;
	if (pdata->flags & SH_MIPI_DSI_HSEE)
		vmctr2 |= 1 << 22;
	if (pdata->flags & SH_MIPI_DSI_HSAE)
		vmctr2 |= 1 << 21;
	if (pdata->flags & SH_MIPI_DSI_BL2E)
		vmctr2 |= 1 << 17;
	if (pdata->flags & SH_MIPI_DSI_HSABM)
		vmctr2 |= 1 << 5;
	if (pdata->flags & SH_MIPI_DSI_HBPBM)
		vmctr2 |= 1 << 4;
	if (pdata->flags & SH_MIPI_DSI_HFPBM)
		vmctr2 |= 1 << 3;
	iowrite32(vmctr2, mipi->linkbase + VMCTR2);

	/*
	 * VMLEN1 = RGBLEN | HSALEN
	 *
	 * see
	 *  Video mode - Blanking Packet setting
	 */
	top = linelength << 16; /* RGBLEN */
	bottom = 0x00000001;
	if (pdata->flags & SH_MIPI_DSI_HSABM) /* HSALEN */
		bottom = (pdata->lane * ch->lcd_modes[0].hsync_len) - 10;
	iowrite32(top | bottom , mipi->linkbase + VMLEN1);

	/*
	 * VMLEN2 = HBPLEN | HFPLEN
	 *
	 * see
	 *  Video mode - Blanking Packet setting
	 */
	top	= 0x00010000;
	bottom	= 0x00000001;
	delay	= 0;

	div = 1;	/* HSbyteCLK is calculation base
			 * HS4divCLK = HSbyteCLK/2
			 * HS6divCLK is not supported for now */
	if (pdata->flags & SH_MIPI_DSI_HS4divCLK)
		div = 2;

	if (pdata->flags & SH_MIPI_DSI_HFPBM) {	/* HBPLEN */
		top = ch->lcd_modes[0].hsync_len + ch->lcd_modes[0].left_margin;
		top = ((pdata->lane * top / div) - 10) << 16;
	}
	if (pdata->flags & SH_MIPI_DSI_HBPBM) { /* HFPLEN */
		bottom = ch->lcd_modes[0].right_margin;
		bottom = (pdata->lane * bottom / div) - 12;
	}

	bpp = linelength / ch->lcd_modes[0].xres; /* byte / pixel */
	if ((pdata->lane / div) > bpp) {
		tmp = ch->lcd_modes[0].xres / bpp; /* output cycle */
		tmp = ch->lcd_modes[0].xres - tmp; /* (input - output) cycle */
		delay = (pdata->lane * tmp);
	}

	iowrite32(top | (bottom + delay) , mipi->linkbase + VMLEN2);

	msleep(5);

	/* setup LCD panel */

	/* cf. drivers/video/omap/lcd_mipid.c */
	sh_mipi_dcs(ch->chan, MIPI_DCS_EXIT_SLEEP_MODE);
	msleep(120);
	/*
	 * [7] - Page Address Mode
	 * [6] - Column Address Mode
	 * [5] - Page / Column Address Mode
	 * [4] - Display Device Line Refresh Order
	 * [3] - RGB/BGR Order
	 * [2] - Display Data Latch Data Order
	 * [1] - Flip Horizontal
	 * [0] - Flip Vertical
	 */
	sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
	/* cf. set_data_lines() */
	sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_PIXEL_FORMAT,
			  pixfmt << 4);
	sh_mipi_dcs(ch->chan, MIPI_DCS_SET_DISPLAY_ON);

	/* Enable timeout counters */
	iowrite32(0x00000f00, base + DSICTRL);

	return 0;
}

static int mipi_display_on(struct sh_mobile_lcdc_entity *entity)
{
	struct sh_mipi *mipi = to_sh_mipi(entity);
	struct sh_mipi_dsi_info *pdata = mipi->pdev->dev.platform_data;
	int ret;

	pm_runtime_get_sync(&mipi->pdev->dev);

	ret = pdata->set_dot_clock(mipi->pdev, mipi->base, 1);
	if (ret < 0)
		goto mipi_display_on_fail1;

	ret = sh_mipi_setup(mipi, pdata);
	if (ret < 0)
		goto mipi_display_on_fail2;

	sh_mipi_dsi_enable(mipi, true);

	return SH_MOBILE_LCDC_DISPLAY_CONNECTED;

mipi_display_on_fail1:
	pm_runtime_put_sync(&mipi->pdev->dev);
mipi_display_on_fail2:
	pdata->set_dot_clock(mipi->pdev, mipi->base, 0);

	return ret;
}

static void mipi_display_off(struct sh_mobile_lcdc_entity *entity)
{
	struct sh_mipi *mipi = to_sh_mipi(entity);
	struct sh_mipi_dsi_info *pdata = mipi->pdev->dev.platform_data;

	sh_mipi_dsi_enable(mipi, false);

	pdata->set_dot_clock(mipi->pdev, mipi->base, 0);

	pm_runtime_put_sync(&mipi->pdev->dev);
}

static const struct sh_mobile_lcdc_entity_ops mipi_ops = {
	.display_on = mipi_display_on,
	.display_off = mipi_display_off,
};

static int __init sh_mipi_probe(struct platform_device *pdev)
{
	struct sh_mipi *mipi;
	struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	unsigned long rate, f_current;
	int idx = pdev->id, ret;

	if (!res || !res2 || idx >= ARRAY_SIZE(mipi_dsi) || !pdata)
		return -ENODEV;

	if (!pdata->set_dot_clock)
		return -EINVAL;

	mutex_lock(&array_lock);
	if (idx < 0)
		for (idx = 0; idx < ARRAY_SIZE(mipi_dsi) && mipi_dsi[idx]; idx++)
			;

	if (idx == ARRAY_SIZE(mipi_dsi)) {
		ret = -EBUSY;
		goto efindslot;
	}

	mipi = kzalloc(sizeof(*mipi), GFP_KERNEL);
	if (!mipi) {
		ret = -ENOMEM;
		goto ealloc;
	}

	mipi->entity.owner = THIS_MODULE;
	mipi->entity.ops = &mipi_ops;

	if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
		dev_err(&pdev->dev, "MIPI register region already claimed\n");
		ret = -EBUSY;
		goto ereqreg;
	}

	mipi->base = ioremap(res->start, resource_size(res));
	if (!mipi->base) {
		ret = -ENOMEM;
		goto emap;
	}

	if (!request_mem_region(res2->start, resource_size(res2), pdev->name)) {
		dev_err(&pdev->dev, "MIPI register region 2 already claimed\n");
		ret = -EBUSY;
		goto ereqreg2;
	}

	mipi->linkbase = ioremap(res2->start, resource_size(res2));
	if (!mipi->linkbase) {
		ret = -ENOMEM;
		goto emap2;
	}

	mipi->pdev = pdev;

	mipi->dsit_clk = clk_get(&pdev->dev, "dsit_clk");
	if (IS_ERR(mipi->dsit_clk)) {
		ret = PTR_ERR(mipi->dsit_clk);
		goto eclktget;
	}

	f_current = clk_get_rate(mipi->dsit_clk);
	/* 80MHz required by the datasheet */
	rate = clk_round_rate(mipi->dsit_clk, 80000000);
	if (rate > 0 && rate != f_current)
		ret = clk_set_rate(mipi->dsit_clk, rate);
	else
		ret = rate;
	if (ret < 0)
		goto esettrate;

	dev_dbg(&pdev->dev, "DSI-T clk %lu -> %lu\n", f_current, rate);

	ret = clk_enable(mipi->dsit_clk);
	if (ret < 0)
		goto eclkton;

	mipi_dsi[idx] = mipi;

	pm_runtime_enable(&pdev->dev);
	pm_runtime_resume(&pdev->dev);

	mutex_unlock(&array_lock);
	platform_set_drvdata(pdev, &mipi->entity);

	return 0;

eclkton:
esettrate:
	clk_put(mipi->dsit_clk);
eclktget:
	iounmap(mipi->linkbase);
emap2:
	release_mem_region(res2->start, resource_size(res2));
ereqreg2:
	iounmap(mipi->base);
emap:
	release_mem_region(res->start, resource_size(res));
ereqreg:
	kfree(mipi);
ealloc:
efindslot:
	mutex_unlock(&array_lock);

	return ret;
}

static int __exit sh_mipi_remove(struct platform_device *pdev)
{
	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	struct sh_mipi *mipi = to_sh_mipi(platform_get_drvdata(pdev));
	int i, ret;

	mutex_lock(&array_lock);

	for (i = 0; i < ARRAY_SIZE(mipi_dsi) && mipi_dsi[i] != mipi; i++)
		;

	if (i == ARRAY_SIZE(mipi_dsi)) {
		ret = -EINVAL;
	} else {
		ret = 0;
		mipi_dsi[i] = NULL;
	}

	mutex_unlock(&array_lock);

	if (ret < 0)
		return ret;

	pm_runtime_disable(&pdev->dev);
	clk_disable(mipi->dsit_clk);
	clk_put(mipi->dsit_clk);

	iounmap(mipi->linkbase);
	if (res2)
		release_mem_region(res2->start, resource_size(res2));
	iounmap(mipi->base);
	if (res)
		release_mem_region(res->start, resource_size(res));
	platform_set_drvdata(pdev, NULL);
	kfree(mipi);

	return 0;
}

static struct platform_driver sh_mipi_driver = {
	.remove		= __exit_p(sh_mipi_remove),
	.shutdown	= sh_mipi_shutdown,
	.driver = {
		.name	= "sh-mipi-dsi",
	},
};

static int __init sh_mipi_init(void)
{
	return platform_driver_probe(&sh_mipi_driver, sh_mipi_probe);
}
module_init(sh_mipi_init);

static void __exit sh_mipi_exit(void)
{
	platform_driver_unregister(&sh_mipi_driver);
}
module_exit(sh_mipi_exit);

MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
MODULE_DESCRIPTION("SuperH / ARM-shmobile MIPI DSI driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
9fd04fe3 GL	1	/*
	2	* Renesas SH-mobile MIPI DSI support
	3	*
	4	* Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
	5	*
	6	* This is free software; you can redistribute it and/or modify
	7	* it under the terms of version 2 of the GNU General Public License as
	8	* published by the Free Software Foundation.
	9	*/
	10
26c3d7ac	11	#include <linux/bitmap.h>
9fd04fe3 GL	12	#include <linux/clk.h>
	13	#include <linux/delay.h>
	14	#include <linux/init.h>
	15	#include <linux/io.h>
	16	#include <linux/platform_device.h>
236782a5	17	#include <linux/pm_runtime.h>
9fd04fe3 GL	18	#include <linux/slab.h>
	19	#include <linux/string.h>
	20	#include <linux/types.h>
355b200b	21	#include <linux/module.h>
9fd04fe3 GL	22
	23	#include <video/mipi_display.h>
	24	#include <video/sh_mipi_dsi.h>
	25	#include <video/sh_mobile_lcdc.h>
	26
732bbcc4 LP	27	#include "sh_mobile_lcdcfb.h"
732bbcc4 LP	28
71b146c8 MD	29	#define SYSCTRL 0x0000
	30	#define SYSCONF 0x0004
	31	#define TIMSET 0x0008
	32	#define RESREQSET0 0x0018
	33	#define RESREQSET1 0x001c
	34	#define HSTTOVSET 0x0020
	35	#define LPRTOVSET 0x0024
	36	#define TATOVSET 0x0028
	37	#define PRTOVSET 0x002c
	38	#define DSICTRL 0x0030
	39	#define DSIINTE 0x0060
	40	#define PHYCTRL 0x0070
	41
deaba190 MD	42	/* relative to linkbase */
	43	#define DTCTR 0x0000
	44	#define VMCTR1 0x0020
	45	#define VMCTR2 0x0024
	46	#define VMLEN1 0x0028
08750617	47	#define VMLEN2 0x002c
deaba190 MD	48	#define CMTSRTREQ 0x0070
deaba190 MD	49	#define CMTSRTCTR 0x00d0
9fd04fe3 GL	50
	51	/* E.g., sh7372 has 2 MIPI-DSIs - one for each LCDC */
	52	#define MAX_SH_MIPI_DSI 2
	53
	54	struct sh_mipi {
732bbcc4 LP	55	struct sh_mobile_lcdc_entity entity;
732bbcc4 LP	56
9fd04fe3	57	void __iomem *base;
deaba190	58	void __iomem *linkbase;
9fd04fe3	59	struct clk *dsit_clk;
7d9f88b4	60	struct platform_device *pdev;
9fd04fe3 GL	61	};
9fd04fe3 GL	62
732bbcc4 LP	63	#define to_sh_mipi(e) container_of(e, struct sh_mipi, entity)
732bbcc4 LP	64
9fd04fe3 GL	65	static struct sh_mipi *mipi_dsi[MAX_SH_MIPI_DSI];
	66
	67	/* Protect the above array */
	68	static DEFINE_MUTEX(array_lock);
	69
	70	static struct sh_mipi *sh_mipi_by_handle(int handle)
	71	{
	72	if (handle >= ARRAY_SIZE(mipi_dsi) \|\| handle < 0)
	73	return NULL;
	74
	75	return mipi_dsi[handle];
	76	}
	77
	78	static int sh_mipi_send_short(struct sh_mipi *mipi, u8 dsi_cmd,
	79	u8 cmd, u8 param)
	80	{
	81	u32 data = (dsi_cmd << 24) \| (cmd << 16) \| (param << 8);
	82	int cnt = 100;
	83
	84	/* transmit a short packet to LCD panel */
deaba190 MD	85	iowrite32(1 \| data, mipi->linkbase + CMTSRTCTR);
deaba190 MD	86	iowrite32(1, mipi->linkbase + CMTSRTREQ);
9fd04fe3	87
deaba190	88	while ((ioread32(mipi->linkbase + CMTSRTREQ) & 1) && --cnt)
9fd04fe3 GL	89	udelay(1);
	90
	91	return cnt ? 0 : -ETIMEDOUT;
	92	}
	93
	94	#define LCD_CHAN2MIPI(c) ((c) < LCDC_CHAN_MAINLCD \|\| (c) > LCDC_CHAN_SUBLCD ? \
	95	-EINVAL : (c) - 1)
	96
	97	static int sh_mipi_dcs(int handle, u8 cmd)
	98	{
	99	struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
	100	if (!mipi)
	101	return -ENODEV;
	102	return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE, cmd, 0);
	103	}
	104
	105	static int sh_mipi_dcs_param(int handle, u8 cmd, u8 param)
	106	{
	107	struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
	108	if (!mipi)
	109	return -ENODEV;
	110	return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE_PARAM, cmd,
	111	param);
	112	}
	113
	114	static void sh_mipi_dsi_enable(struct sh_mipi *mipi, bool enable)
	115	{
	116	/*
	117	* enable LCDC data tx, transition to LPS after completion of each HS
	118	* packet
	119	*/
deaba190	120	iowrite32(0x00000002 \| enable, mipi->linkbase + DTCTR);
9fd04fe3 GL	121	}
	122
	123	static void sh_mipi_shutdown(struct platform_device *pdev)
	124	{
732bbcc4	125	struct sh_mipi *mipi = to_sh_mipi(platform_get_drvdata(pdev));
9fd04fe3 GL	126
	127	sh_mipi_dsi_enable(mipi, false);
	128	}
	129
9fd04fe3 GL	130	static int __init sh_mipi_setup(struct sh_mipi *mipi,
	131	struct sh_mipi_dsi_info *pdata)
	132	{
	133	void __iomem *base = mipi->base;
	134	struct sh_mobile_lcdc_chan_cfg *ch = pdata->lcd_chan;
f832906a	135	u32 pctype, datatype, pixfmt, linelength, vmctr2;
a2e62971	136	u32 tmp, top, bottom, delay, div;
9fd04fe3	137	bool yuv;
08750617	138	int bpp;
9fd04fe3	139
44432407 GL	140	/*
	141	* Select data format. MIPI DSI is not hot-pluggable, so, we just use
	142	* the default videomode. If this ever becomes a problem, We'll have to
	143	* move this to mipi_display_on() above and use info->var.xres
	144	*/
9fd04fe3 GL	145	switch (pdata->data_format) {
	146	case MIPI_RGB888:
	147	pctype = 0;
	148	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
	149	pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
93ff2598	150	linelength = ch->lcd_modes[0].xres * 3;
9fd04fe3 GL	151	yuv = false;
	152	break;
	153	case MIPI_RGB565:
	154	pctype = 1;
	155	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
	156	pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
93ff2598	157	linelength = ch->lcd_modes[0].xres * 2;
9fd04fe3 GL	158	yuv = false;
	159	break;
	160	case MIPI_RGB666_LP:
	161	pctype = 2;
	162	datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
	163	pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
93ff2598	164	linelength = ch->lcd_modes[0].xres * 3;
9fd04fe3 GL	165	yuv = false;
	166	break;
	167	case MIPI_RGB666:
	168	pctype = 3;
	169	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
	170	pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
93ff2598	171	linelength = (ch->lcd_modes[0].xres * 18 + 7) / 8;
9fd04fe3 GL	172	yuv = false;
	173	break;
	174	case MIPI_BGR888:
	175	pctype = 8;
	176	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
	177	pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
93ff2598	178	linelength = ch->lcd_modes[0].xres * 3;
9fd04fe3 GL	179	yuv = false;
	180	break;
	181	case MIPI_BGR565:
	182	pctype = 9;
	183	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
	184	pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
93ff2598	185	linelength = ch->lcd_modes[0].xres * 2;
9fd04fe3 GL	186	yuv = false;
	187	break;
	188	case MIPI_BGR666_LP:
	189	pctype = 0xa;
	190	datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
	191	pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
93ff2598	192	linelength = ch->lcd_modes[0].xres * 3;
9fd04fe3 GL	193	yuv = false;
	194	break;
	195	case MIPI_BGR666:
	196	pctype = 0xb;
	197	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
	198	pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
93ff2598	199	linelength = (ch->lcd_modes[0].xres * 18 + 7) / 8;
9fd04fe3 GL	200	yuv = false;
	201	break;
	202	case MIPI_YUYV:
	203	pctype = 4;
	204	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
	205	pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
93ff2598	206	linelength = ch->lcd_modes[0].xres * 2;
9fd04fe3 GL	207	yuv = true;
	208	break;
	209	case MIPI_UYVY:
	210	pctype = 5;
	211	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
	212	pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
93ff2598	213	linelength = ch->lcd_modes[0].xres * 2;
9fd04fe3 GL	214	yuv = true;
	215	break;
	216	case MIPI_YUV420_L:
	217	pctype = 6;
	218	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
	219	pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
93ff2598	220	linelength = (ch->lcd_modes[0].xres * 12 + 7) / 8;
9fd04fe3 GL	221	yuv = true;
	222	break;
	223	case MIPI_YUV420:
	224	pctype = 7;
	225	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
	226	pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
	227	/* Length of U/V line */
93ff2598	228	linelength = (ch->lcd_modes[0].xres + 1) / 2;
9fd04fe3 GL	229	yuv = true;
	230	break;
	231	default:
	232	return -EINVAL;
	233	}
	234
	235	if ((yuv && ch->interface_type != YUV422) \|\|
	236	(!yuv && ch->interface_type != RGB24))
	237	return -EINVAL;
	238
26c3d7ac KM	239	if (!pdata->lane)
	240	return -EINVAL;
	241
9fd04fe3	242	/* reset DSI link */
71b146c8	243	iowrite32(0x00000001, base + SYSCTRL);
9fd04fe3 GL	244	/* Hold reset for 100 cycles of the slowest of bus, HS byte and LP clock */
9fd04fe3 GL	245	udelay(50);
71b146c8	246	iowrite32(0x00000000, base + SYSCTRL);
9fd04fe3 GL	247
	248	/* setup DSI link */
	249
9fd04fe3 GL	250	/*
	251	* T_wakeup = 0x7000
	252	* T_hs-trail = 3
	253	* T_hs-prepare = 3
	254	* T_clk-trail = 3
	255	* T_clk-prepare = 2
	256	*/
71b146c8	257	iowrite32(0x70003332, base + TIMSET);
9fd04fe3	258	/* no responses requested */
71b146c8	259	iowrite32(0x00000000, base + RESREQSET0);
9fd04fe3	260	/* request response to packets of type 0x28 */
71b146c8	261	iowrite32(0x00000100, base + RESREQSET1);
9fd04fe3	262	/* High-speed transmission timeout, default 0xffffffff */
71b146c8	263	iowrite32(0x0fffffff, base + HSTTOVSET);
9fd04fe3	264	/* LP reception timeout, default 0xffffffff */
71b146c8	265	iowrite32(0x0fffffff, base + LPRTOVSET);
9fd04fe3	266	/* Turn-around timeout, default 0xffffffff */
71b146c8	267	iowrite32(0x0fffffff, base + TATOVSET);
9fd04fe3	268	/* Peripheral reset timeout, default 0xffffffff */
71b146c8	269	iowrite32(0x0fffffff, base + PRTOVSET);
9fd04fe3 GL	270	/* Interrupts not used, disable all */
	271	iowrite32(0, base + DSIINTE);
	272	/* DSI-Tx bias on */
71b146c8	273	iowrite32(0x00000001, base + PHYCTRL);
9fd04fe3	274	udelay(200);
5e47431a	275	/* Deassert resets, power on */
8f9c60f2	276	iowrite32(0x03070001 \| pdata->phyctrl, base + PHYCTRL);
9fd04fe3	277
a2065a36 KM	278	/*
	279	* Default = ULPS enable \|
	280	* Contention detection enabled \|
	281	* EoT packet transmission enable \|
	282	* CRC check enable \|
	283	* ECC check enable
	284	*/
	285	bitmap_fill((unsigned long *)&tmp, pdata->lane);
	286	tmp \|= 0x00003700;
	287	iowrite32(tmp, base + SYSCONF);
	288
9fd04fe3 GL	289	/* setup l-bridge */
	290
	291	/*
	292	* Enable transmission of all packets,
	293	* transmit LPS after each HS packet completion
	294	*/
deaba190	295	iowrite32(0x00000006, mipi->linkbase + DTCTR);
9fd04fe3	296	/* VSYNC width = 2 (<< 17) */
93ff2598	297	iowrite32((ch->lcd_modes[0].vsync_len << pdata->vsynw_offset) \|
14bbb7c6	298	(pdata->clksrc << 16) \| (pctype << 12) \| datatype,
deaba190	299	mipi->linkbase + VMCTR1);
14bbb7c6	300
9fd04fe3 GL	301	/*
	302	* Non-burst mode with sync pulses: VSE and HSE are output,
	303	* HSA period allowed, no commands in LP
	304	*/
f832906a KM	305	vmctr2 = 0;
	306	if (pdata->flags & SH_MIPI_DSI_VSEE)
	307	vmctr2 \|= 1 << 23;
	308	if (pdata->flags & SH_MIPI_DSI_HSEE)
	309	vmctr2 \|= 1 << 22;
	310	if (pdata->flags & SH_MIPI_DSI_HSAE)
	311	vmctr2 \|= 1 << 21;
d07a9d2a KM	312	if (pdata->flags & SH_MIPI_DSI_BL2E)
d07a9d2a KM	313	vmctr2 \|= 1 << 17;
14bbb7c6	314	if (pdata->flags & SH_MIPI_DSI_HSABM)
3c2a6599	315	vmctr2 \|= 1 << 5;
32ba95c6	316	if (pdata->flags & SH_MIPI_DSI_HBPBM)
3c2a6599	317	vmctr2 \|= 1 << 4;
f7b0af68 KM	318	if (pdata->flags & SH_MIPI_DSI_HFPBM)
f7b0af68 KM	319	vmctr2 \|= 1 << 3;
14bbb7c6 GL	320	iowrite32(vmctr2, mipi->linkbase + VMCTR2);
14bbb7c6 GL	321
9fd04fe3	322	/*
08750617 KM	323	* VMLEN1 = RGBLEN \| HSALEN
	324	*
	325	* see
	326	* Video mode - Blanking Packet setting
9fd04fe3	327	*/
08750617 KM	328	top = linelength << 16; /* RGBLEN */
	329	bottom = 0x00000001;
	330	if (pdata->flags & SH_MIPI_DSI_HSABM) /* HSALEN */
93ff2598	331	bottom = (pdata->lane * ch->lcd_modes[0].hsync_len) - 10;
08750617 KM	332	iowrite32(top \| bottom , mipi->linkbase + VMLEN1);
	333
	334	/*
	335	* VMLEN2 = HBPLEN \| HFPLEN
	336	*
	337	* see
	338	* Video mode - Blanking Packet setting
	339	*/
	340	top = 0x00010000;
	341	bottom = 0x00000001;
	342	delay = 0;
	343
a2e62971 KM	344	div = 1; /* HSbyteCLK is calculation base
	345	* HS4divCLK = HSbyteCLK/2
	346	* HS6divCLK is not supported for now */
	347	if (pdata->flags & SH_MIPI_DSI_HS4divCLK)
	348	div = 2;
	349
08750617	350	if (pdata->flags & SH_MIPI_DSI_HFPBM) { /* HBPLEN */
93ff2598	351	top = ch->lcd_modes[0].hsync_len + ch->lcd_modes[0].left_margin;
a2e62971	352	top = ((pdata->lane * top / div) - 10) << 16;
08750617 KM	353	}
08750617 KM	354	if (pdata->flags & SH_MIPI_DSI_HBPBM) { /* HFPLEN */
93ff2598	355	bottom = ch->lcd_modes[0].right_margin;
a2e62971	356	bottom = (pdata->lane * bottom / div) - 12;
08750617 KM	357	}
08750617 KM	358
93ff2598	359	bpp = linelength / ch->lcd_modes[0].xres; /* byte / pixel */
a2e62971	360	if ((pdata->lane / div) > bpp) {
93ff2598 LP	361	tmp = ch->lcd_modes[0].xres / bpp; /* output cycle */
93ff2598 LP	362	tmp = ch->lcd_modes[0].xres - tmp; /* (input - output) cycle */
08750617 KM	363	delay = (pdata->lane * tmp);
	364	}
	365
	366	iowrite32(top \| (bottom + delay) , mipi->linkbase + VMLEN2);
9fd04fe3 GL	367
	368	msleep(5);
	369
	370	/* setup LCD panel */
	371
	372	/* cf. drivers/video/omap/lcd_mipid.c */
	373	sh_mipi_dcs(ch->chan, MIPI_DCS_EXIT_SLEEP_MODE);
	374	msleep(120);
	375	/*
	376	* [7] - Page Address Mode
	377	* [6] - Column Address Mode
	378	* [5] - Page / Column Address Mode
	379	* [4] - Display Device Line Refresh Order
	380	* [3] - RGB/BGR Order
	381	* [2] - Display Data Latch Data Order
	382	* [1] - Flip Horizontal
	383	* [0] - Flip Vertical
	384	*/
	385	sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
	386	/* cf. set_data_lines() */
	387	sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_PIXEL_FORMAT,
	388	pixfmt << 4);
	389	sh_mipi_dcs(ch->chan, MIPI_DCS_SET_DISPLAY_ON);
	390
97cab455 KM	391	/* Enable timeout counters */
	392	iowrite32(0x00000f00, base + DSICTRL);
	393
9fd04fe3 GL	394	return 0;
	395	}
	396
5864ace1	397	static int mipi_display_on(struct sh_mobile_lcdc_entity *entity)
c2658b70	398	{
732bbcc4	399	struct sh_mipi *mipi = to_sh_mipi(entity);
c2658b70 KM	400	struct sh_mipi_dsi_info *pdata = mipi->pdev->dev.platform_data;
	401	int ret;
	402
	403	pm_runtime_get_sync(&mipi->pdev->dev);
	404
	405	ret = pdata->set_dot_clock(mipi->pdev, mipi->base, 1);
	406	if (ret < 0)
	407	goto mipi_display_on_fail1;
	408
	409	ret = sh_mipi_setup(mipi, pdata);
	410	if (ret < 0)
	411	goto mipi_display_on_fail2;
	412
	413	sh_mipi_dsi_enable(mipi, true);
	414
458981c3	415	return SH_MOBILE_LCDC_DISPLAY_CONNECTED;
c2658b70 KM	416
	417	mipi_display_on_fail1:
	418	pm_runtime_put_sync(&mipi->pdev->dev);
	419	mipi_display_on_fail2:
	420	pdata->set_dot_clock(mipi->pdev, mipi->base, 0);
732bbcc4 LP	421
732bbcc4 LP	422	return ret;
c2658b70 KM	423	}
c2658b70 KM	424
d2c594a0	425	static void mipi_display_off(struct sh_mobile_lcdc_entity *entity)
732bbcc4 LP	426	{
	427	struct sh_mipi *mipi = to_sh_mipi(entity);
	428	struct sh_mipi_dsi_info *pdata = mipi->pdev->dev.platform_data;
c2658b70 KM	429
	430	sh_mipi_dsi_enable(mipi, false);
	431
	432	pdata->set_dot_clock(mipi->pdev, mipi->base, 0);
	433
	434	pm_runtime_put_sync(&mipi->pdev->dev);
	435	}
	436
732bbcc4	437	static const struct sh_mobile_lcdc_entity_ops mipi_ops = {
d2c594a0 LP	438	.display_on = mipi_display_on,
d2c594a0 LP	439	.display_off = mipi_display_off,
732bbcc4 LP	440	};
732bbcc4 LP	441
9fd04fe3 GL	442	static int __init sh_mipi_probe(struct platform_device *pdev)
	443	{
	444	struct sh_mipi *mipi;
	445	struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
	446	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
deaba190	447	struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
9fd04fe3 GL	448	unsigned long rate, f_current;
9fd04fe3 GL	449	int idx = pdev->id, ret;
9fd04fe3	450
deaba190	451	if (!res \|\| !res2 \|\| idx >= ARRAY_SIZE(mipi_dsi) \|\| !pdata)
9fd04fe3 GL	452	return -ENODEV;
9fd04fe3 GL	453
5e47431a KM	454	if (!pdata->set_dot_clock)
	455	return -EINVAL;
	456
9fd04fe3 GL	457	mutex_lock(&array_lock);
	458	if (idx < 0)
	459	for (idx = 0; idx < ARRAY_SIZE(mipi_dsi) && mipi_dsi[idx]; idx++)
	460	;
	461
	462	if (idx == ARRAY_SIZE(mipi_dsi)) {
	463	ret = -EBUSY;
	464	goto efindslot;
	465	}
	466
	467	mipi = kzalloc(sizeof(*mipi), GFP_KERNEL);
	468	if (!mipi) {
	469	ret = -ENOMEM;
	470	goto ealloc;
	471	}
	472
732bbcc4 LP	473	mipi->entity.owner = THIS_MODULE;
	474	mipi->entity.ops = &mipi_ops;
	475
9fd04fe3 GL	476	if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
	477	dev_err(&pdev->dev, "MIPI register region already claimed\n");
	478	ret = -EBUSY;
	479	goto ereqreg;
	480	}
	481
	482	mipi->base = ioremap(res->start, resource_size(res));
	483	if (!mipi->base) {
	484	ret = -ENOMEM;
	485	goto emap;
	486	}
	487
deaba190 MD	488	if (!request_mem_region(res2->start, resource_size(res2), pdev->name)) {
	489	dev_err(&pdev->dev, "MIPI register region 2 already claimed\n");
	490	ret = -EBUSY;
	491	goto ereqreg2;
	492	}
	493
	494	mipi->linkbase = ioremap(res2->start, resource_size(res2));
	495	if (!mipi->linkbase) {
	496	ret = -ENOMEM;
	497	goto emap2;
	498	}
	499
7d9f88b4	500	mipi->pdev = pdev;
236782a5	501
9fd04fe3 GL	502	mipi->dsit_clk = clk_get(&pdev->dev, "dsit_clk");
	503	if (IS_ERR(mipi->dsit_clk)) {
	504	ret = PTR_ERR(mipi->dsit_clk);
	505	goto eclktget;
	506	}
	507
	508	f_current = clk_get_rate(mipi->dsit_clk);
	509	/* 80MHz required by the datasheet */
	510	rate = clk_round_rate(mipi->dsit_clk, 80000000);
	511	if (rate > 0 && rate != f_current)
	512	ret = clk_set_rate(mipi->dsit_clk, rate);
	513	else
	514	ret = rate;
	515	if (ret < 0)
	516	goto esettrate;
	517
	518	dev_dbg(&pdev->dev, "DSI-T clk %lu -> %lu\n", f_current, rate);
	519
9fd04fe3 GL	520	ret = clk_enable(mipi->dsit_clk);
	521	if (ret < 0)
	522	goto eclkton;
	523
9fd04fe3 GL	524	mipi_dsi[idx] = mipi;
9fd04fe3 GL	525
236782a5 GL	526	pm_runtime_enable(&pdev->dev);
	527	pm_runtime_resume(&pdev->dev);
	528
9fd04fe3	529	mutex_unlock(&array_lock);
732bbcc4	530	platform_set_drvdata(pdev, &mipi->entity);
9fd04fe3	531
9fd04fe3 GL	532	return 0;
9fd04fe3 GL	533
9fd04fe3	534	eclkton:
9fd04fe3 GL	535	esettrate:
	536	clk_put(mipi->dsit_clk);
	537	eclktget:
deaba190 MD	538	iounmap(mipi->linkbase);
	539	emap2:
	540	release_mem_region(res2->start, resource_size(res2));
	541	ereqreg2:
9fd04fe3 GL	542	iounmap(mipi->base);
	543	emap:
	544	release_mem_region(res->start, resource_size(res));
	545	ereqreg:
	546	kfree(mipi);
	547	ealloc:
	548	efindslot:
	549	mutex_unlock(&array_lock);
	550
	551	return ret;
	552	}
	553
	554	static int __exit sh_mipi_remove(struct platform_device *pdev)
	555	{
9fd04fe3	556	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
deaba190	557	struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
732bbcc4	558	struct sh_mipi *mipi = to_sh_mipi(platform_get_drvdata(pdev));
9fd04fe3 GL	559	int i, ret;
	560
	561	mutex_lock(&array_lock);
	562
	563	for (i = 0; i < ARRAY_SIZE(mipi_dsi) && mipi_dsi[i] != mipi; i++)
	564	;
	565
	566	if (i == ARRAY_SIZE(mipi_dsi)) {
	567	ret = -EINVAL;
	568	} else {
	569	ret = 0;
	570	mipi_dsi[i] = NULL;
	571	}
	572
	573	mutex_unlock(&array_lock);
	574
	575	if (ret < 0)
	576	return ret;
	577
236782a5	578	pm_runtime_disable(&pdev->dev);
9fd04fe3 GL	579	clk_disable(mipi->dsit_clk);
9fd04fe3 GL	580	clk_put(mipi->dsit_clk);
5e47431a	581
deaba190 MD	582	iounmap(mipi->linkbase);
	583	if (res2)
	584	release_mem_region(res2->start, resource_size(res2));
9fd04fe3 GL	585	iounmap(mipi->base);
	586	if (res)
	587	release_mem_region(res->start, resource_size(res));
	588	platform_set_drvdata(pdev, NULL);
	589	kfree(mipi);
	590
	591	return 0;
	592	}
	593
	594	static struct platform_driver sh_mipi_driver = {
	595	.remove = __exit_p(sh_mipi_remove),
	596	.shutdown = sh_mipi_shutdown,
	597	.driver = {
	598	.name = "sh-mipi-dsi",
	599	},
	600	};
	601
	602	static int __init sh_mipi_init(void)
	603	{
	604	return platform_driver_probe(&sh_mipi_driver, sh_mipi_probe);
	605	}
	606	module_init(sh_mipi_init);
	607
	608	static void __exit sh_mipi_exit(void)
	609	{
	610	platform_driver_unregister(&sh_mipi_driver);
	611	}
	612	module_exit(sh_mipi_exit);
	613
	614	MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
	615	MODULE_DESCRIPTION("SuperH / ARM-shmobile MIPI DSI driver");
	616	MODULE_LICENSE("GPL v2");