[deliverable/linux.git] / drivers / video / sh_mipi_dsi.c

/*
 * Renesas SH-mobile MIPI DSI support
 *
 * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
 *
 * This is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 */

#include <linux/bitmap.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/types.h>
#include <linux/module.h>

#include <video/mipi_display.h>
#include <video/sh_mipi_dsi.h>
#include <video/sh_mobile_lcdc.h>

#define SYSCTRL		0x0000
#define SYSCONF		0x0004
#define TIMSET		0x0008
#define RESREQSET0	0x0018
#define RESREQSET1	0x001c
#define HSTTOVSET	0x0020
#define LPRTOVSET	0x0024
#define TATOVSET	0x0028
#define PRTOVSET	0x002c
#define DSICTRL		0x0030
#define DSIINTE		0x0060
#define PHYCTRL		0x0070

/* relative to linkbase */
#define DTCTR		0x0000
#define VMCTR1		0x0020
#define VMCTR2		0x0024
#define VMLEN1		0x0028
#define VMLEN2		0x002c
#define CMTSRTREQ	0x0070
#define CMTSRTCTR	0x00d0

/* E.g., sh7372 has 2 MIPI-DSIs - one for each LCDC */
#define MAX_SH_MIPI_DSI 2

struct sh_mipi {
	void __iomem	*base;
	void __iomem	*linkbase;
	struct clk	*dsit_clk;
	struct device	*dev;

	void	*next_board_data;
	void	(*next_display_on)(void *board_data, struct fb_info *info);
	void	(*next_display_off)(void *board_data);
};

static struct sh_mipi *mipi_dsi[MAX_SH_MIPI_DSI];

/* Protect the above array */
static DEFINE_MUTEX(array_lock);

static struct sh_mipi *sh_mipi_by_handle(int handle)
{
	if (handle >= ARRAY_SIZE(mipi_dsi) || handle < 0)
		return NULL;

	return mipi_dsi[handle];
}

static int sh_mipi_send_short(struct sh_mipi *mipi, u8 dsi_cmd,
			      u8 cmd, u8 param)
{
	u32 data = (dsi_cmd << 24) | (cmd << 16) | (param << 8);
	int cnt = 100;

	/* transmit a short packet to LCD panel */
	iowrite32(1 | data, mipi->linkbase + CMTSRTCTR);
	iowrite32(1, mipi->linkbase + CMTSRTREQ);

	while ((ioread32(mipi->linkbase + CMTSRTREQ) & 1) && --cnt)
		udelay(1);

	return cnt ? 0 : -ETIMEDOUT;
}

#define LCD_CHAN2MIPI(c) ((c) < LCDC_CHAN_MAINLCD || (c) > LCDC_CHAN_SUBLCD ? \
				-EINVAL : (c) - 1)

static int sh_mipi_dcs(int handle, u8 cmd)
{
	struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
	if (!mipi)
		return -ENODEV;
	return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE, cmd, 0);
}

static int sh_mipi_dcs_param(int handle, u8 cmd, u8 param)
{
	struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
	if (!mipi)
		return -ENODEV;
	return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE_PARAM, cmd,
				  param);
}

static void sh_mipi_dsi_enable(struct sh_mipi *mipi, bool enable)
{
	/*
	 * enable LCDC data tx, transition to LPS after completion of each HS
	 * packet
	 */
	iowrite32(0x00000002 | enable, mipi->linkbase + DTCTR);
}

static void sh_mipi_shutdown(struct platform_device *pdev)
{
	struct sh_mipi *mipi = platform_get_drvdata(pdev);

	sh_mipi_dsi_enable(mipi, false);
}

static void mipi_display_on(void *arg, struct fb_info *info)
{
	struct sh_mipi *mipi = arg;

	pm_runtime_get_sync(mipi->dev);
	sh_mipi_dsi_enable(mipi, true);

	if (mipi->next_display_on)
		mipi->next_display_on(mipi->next_board_data, info);
}

static void mipi_display_off(void *arg)
{
	struct sh_mipi *mipi = arg;

	if (mipi->next_display_off)
		mipi->next_display_off(mipi->next_board_data);

	sh_mipi_dsi_enable(mipi, false);
	pm_runtime_put(mipi->dev);
}

static int __init sh_mipi_setup(struct sh_mipi *mipi,
				struct sh_mipi_dsi_info *pdata)
{
	void __iomem *base = mipi->base;
	struct sh_mobile_lcdc_chan_cfg *ch = pdata->lcd_chan;
	u32 pctype, datatype, pixfmt, linelength, vmctr2;
	u32 tmp, top, bottom, delay;
	bool yuv;
	int bpp;

	/*
	 * Select data format. MIPI DSI is not hot-pluggable, so, we just use
	 * the default videomode. If this ever becomes a problem, We'll have to
	 * move this to mipi_display_on() above and use info->var.xres
	 */
	switch (pdata->data_format) {
	case MIPI_RGB888:
		pctype = 0;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
		pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
		linelength = ch->lcd_cfg[0].xres * 3;
		yuv = false;
		break;
	case MIPI_RGB565:
		pctype = 1;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
		pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
		linelength = ch->lcd_cfg[0].xres * 2;
		yuv = false;
		break;
	case MIPI_RGB666_LP:
		pctype = 2;
		datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
		pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
		linelength = ch->lcd_cfg[0].xres * 3;
		yuv = false;
		break;
	case MIPI_RGB666:
		pctype = 3;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
		pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
		linelength = (ch->lcd_cfg[0].xres * 18 + 7) / 8;
		yuv = false;
		break;
	case MIPI_BGR888:
		pctype = 8;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
		pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
		linelength = ch->lcd_cfg[0].xres * 3;
		yuv = false;
		break;
	case MIPI_BGR565:
		pctype = 9;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
		pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
		linelength = ch->lcd_cfg[0].xres * 2;
		yuv = false;
		break;
	case MIPI_BGR666_LP:
		pctype = 0xa;
		datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
		pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
		linelength = ch->lcd_cfg[0].xres * 3;
		yuv = false;
		break;
	case MIPI_BGR666:
		pctype = 0xb;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
		pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
		linelength = (ch->lcd_cfg[0].xres * 18 + 7) / 8;
		yuv = false;
		break;
	case MIPI_YUYV:
		pctype = 4;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
		pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
		linelength = ch->lcd_cfg[0].xres * 2;
		yuv = true;
		break;
	case MIPI_UYVY:
		pctype = 5;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
		pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
		linelength = ch->lcd_cfg[0].xres * 2;
		yuv = true;
		break;
	case MIPI_YUV420_L:
		pctype = 6;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
		pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
		linelength = (ch->lcd_cfg[0].xres * 12 + 7) / 8;
		yuv = true;
		break;
	case MIPI_YUV420:
		pctype = 7;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
		pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
		/* Length of U/V line */
		linelength = (ch->lcd_cfg[0].xres + 1) / 2;
		yuv = true;
		break;
	default:
		return -EINVAL;
	}

	if ((yuv && ch->interface_type != YUV422) ||
	    (!yuv && ch->interface_type != RGB24))
		return -EINVAL;

	if (!pdata->lane)
		return -EINVAL;

	/* reset DSI link */
	iowrite32(0x00000001, base + SYSCTRL);
	/* Hold reset for 100 cycles of the slowest of bus, HS byte and LP clock */
	udelay(50);
	iowrite32(0x00000000, base + SYSCTRL);

	/* setup DSI link */

	/*
	 * Default = ULPS enable |
	 *	Contention detection enabled |
	 *	EoT packet transmission enable |
	 *	CRC check enable |
	 *	ECC check enable
	 * additionally enable first two lanes
	 */
	bitmap_fill((unsigned long *)&tmp, pdata->lane);
	tmp |= 0x00003700;
	iowrite32(tmp, base + SYSCONF);

	/*
	 * T_wakeup = 0x7000
	 * T_hs-trail = 3
	 * T_hs-prepare = 3
	 * T_clk-trail = 3
	 * T_clk-prepare = 2
	 */
	iowrite32(0x70003332, base + TIMSET);
	/* no responses requested */
	iowrite32(0x00000000, base + RESREQSET0);
	/* request response to packets of type 0x28 */
	iowrite32(0x00000100, base + RESREQSET1);
	/* High-speed transmission timeout, default 0xffffffff */
	iowrite32(0x0fffffff, base + HSTTOVSET);
	/* LP reception timeout, default 0xffffffff */
	iowrite32(0x0fffffff, base + LPRTOVSET);
	/* Turn-around timeout, default 0xffffffff */
	iowrite32(0x0fffffff, base + TATOVSET);
	/* Peripheral reset timeout, default 0xffffffff */
	iowrite32(0x0fffffff, base + PRTOVSET);
	/* Enable timeout counters */
	iowrite32(0x00000f00, base + DSICTRL);
	/* Interrupts not used, disable all */
	iowrite32(0, base + DSIINTE);
	/* DSI-Tx bias on */
	iowrite32(0x00000001, base + PHYCTRL);
	udelay(200);
	/* Deassert resets, power on */
	iowrite32(0x03070001, base + PHYCTRL);

	/* setup l-bridge */

	/*
	 * Enable transmission of all packets,
	 * transmit LPS after each HS packet completion
	 */
	iowrite32(0x00000006, mipi->linkbase + DTCTR);
	/* VSYNC width = 2 (<< 17) */
	iowrite32((ch->lcd_cfg[0].vsync_len << pdata->vsynw_offset) |
		  (pdata->clksrc << 16) | (pctype << 12) | datatype,
		  mipi->linkbase + VMCTR1);

	/*
	 * Non-burst mode with sync pulses: VSE and HSE are output,
	 * HSA period allowed, no commands in LP
	 */
	vmctr2 = 0;
	if (pdata->flags & SH_MIPI_DSI_VSEE)
		vmctr2 |= 1 << 23;
	if (pdata->flags & SH_MIPI_DSI_HSEE)
		vmctr2 |= 1 << 22;
	if (pdata->flags & SH_MIPI_DSI_HSAE)
		vmctr2 |= 1 << 21;
	if (pdata->flags & SH_MIPI_DSI_BL2E)
		vmctr2 |= 1 << 17;
	if (pdata->flags & SH_MIPI_DSI_HSABM)
		vmctr2 |= 1 << 5;
	if (pdata->flags & SH_MIPI_DSI_HBPBM)
		vmctr2 |= 1 << 4;
	if (pdata->flags & SH_MIPI_DSI_HFPBM)
		vmctr2 |= 1 << 3;
	iowrite32(vmctr2, mipi->linkbase + VMCTR2);

	/*
	 * VMLEN1 = RGBLEN | HSALEN
	 *
	 * see
	 *  Video mode - Blanking Packet setting
	 */
	top = linelength << 16; /* RGBLEN */
	bottom = 0x00000001;
	if (pdata->flags & SH_MIPI_DSI_HSABM) /* HSALEN */
		bottom = (pdata->lane * ch->lcd_cfg[0].hsync_len) - 10;
	iowrite32(top | bottom , mipi->linkbase + VMLEN1);

	/*
	 * VMLEN2 = HBPLEN | HFPLEN
	 *
	 * see
	 *  Video mode - Blanking Packet setting
	 */
	top	= 0x00010000;
	bottom	= 0x00000001;
	delay	= 0;

	if (pdata->flags & SH_MIPI_DSI_HFPBM) {	/* HBPLEN */
		top = ch->lcd_cfg[0].hsync_len + ch->lcd_cfg[0].left_margin;
		top = ((pdata->lane * top) - 10) << 16;
	}
	if (pdata->flags & SH_MIPI_DSI_HBPBM) { /* HFPLEN */
		bottom = ch->lcd_cfg[0].right_margin;
		bottom = (pdata->lane * bottom) - 12;
	}

	bpp = linelength / ch->lcd_cfg[0].xres; /* byte / pixel */
	if (pdata->lane > bpp) {
		tmp = ch->lcd_cfg[0].xres / bpp; /* output cycle */
		tmp = ch->lcd_cfg[0].xres - tmp; /* (input - output) cycle */
		delay = (pdata->lane * tmp);
	}

	iowrite32(top | (bottom + delay) , mipi->linkbase + VMLEN2);

	msleep(5);

	/* setup LCD panel */

	/* cf. drivers/video/omap/lcd_mipid.c */
	sh_mipi_dcs(ch->chan, MIPI_DCS_EXIT_SLEEP_MODE);
	msleep(120);
	/*
	 * [7] - Page Address Mode
	 * [6] - Column Address Mode
	 * [5] - Page / Column Address Mode
	 * [4] - Display Device Line Refresh Order
	 * [3] - RGB/BGR Order
	 * [2] - Display Data Latch Data Order
	 * [1] - Flip Horizontal
	 * [0] - Flip Vertical
	 */
	sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
	/* cf. set_data_lines() */
	sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_PIXEL_FORMAT,
			  pixfmt << 4);
	sh_mipi_dcs(ch->chan, MIPI_DCS_SET_DISPLAY_ON);

	return 0;
}

static int __init sh_mipi_probe(struct platform_device *pdev)
{
	struct sh_mipi *mipi;
	struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	unsigned long rate, f_current;
	int idx = pdev->id, ret;

	if (!res || !res2 || idx >= ARRAY_SIZE(mipi_dsi) || !pdata)
		return -ENODEV;

	if (!pdata->set_dot_clock)
		return -EINVAL;

	mutex_lock(&array_lock);
	if (idx < 0)
		for (idx = 0; idx < ARRAY_SIZE(mipi_dsi) && mipi_dsi[idx]; idx++)
			;

	if (idx == ARRAY_SIZE(mipi_dsi)) {
		ret = -EBUSY;
		goto efindslot;
	}

	mipi = kzalloc(sizeof(*mipi), GFP_KERNEL);
	if (!mipi) {
		ret = -ENOMEM;
		goto ealloc;
	}

	if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
		dev_err(&pdev->dev, "MIPI register region already claimed\n");
		ret = -EBUSY;
		goto ereqreg;
	}

	mipi->base = ioremap(res->start, resource_size(res));
	if (!mipi->base) {
		ret = -ENOMEM;
		goto emap;
	}

	if (!request_mem_region(res2->start, resource_size(res2), pdev->name)) {
		dev_err(&pdev->dev, "MIPI register region 2 already claimed\n");
		ret = -EBUSY;
		goto ereqreg2;
	}

	mipi->linkbase = ioremap(res2->start, resource_size(res2));
	if (!mipi->linkbase) {
		ret = -ENOMEM;
		goto emap2;
	}

	mipi->dev = &pdev->dev;

	mipi->dsit_clk = clk_get(&pdev->dev, "dsit_clk");
	if (IS_ERR(mipi->dsit_clk)) {
		ret = PTR_ERR(mipi->dsit_clk);
		goto eclktget;
	}

	f_current = clk_get_rate(mipi->dsit_clk);
	/* 80MHz required by the datasheet */
	rate = clk_round_rate(mipi->dsit_clk, 80000000);
	if (rate > 0 && rate != f_current)
		ret = clk_set_rate(mipi->dsit_clk, rate);
	else
		ret = rate;
	if (ret < 0)
		goto esettrate;

	dev_dbg(&pdev->dev, "DSI-T clk %lu -> %lu\n", f_current, rate);

	ret = clk_enable(mipi->dsit_clk);
	if (ret < 0)
		goto eclkton;

	mipi_dsi[idx] = mipi;

	pm_runtime_enable(&pdev->dev);
	pm_runtime_resume(&pdev->dev);

	ret = sh_mipi_setup(mipi, pdata);
	if (ret < 0)
		goto emipisetup;

	ret = pdata->set_dot_clock(pdev, mipi->base, 1);
	if (ret < 0)
		goto emipisetup;

	mutex_unlock(&array_lock);
	platform_set_drvdata(pdev, mipi);

	/* Save original LCDC callbacks */
	mipi->next_board_data = pdata->lcd_chan->board_cfg.board_data;
	mipi->next_display_on = pdata->lcd_chan->board_cfg.display_on;
	mipi->next_display_off = pdata->lcd_chan->board_cfg.display_off;

	/* Set up LCDC callbacks */
	pdata->lcd_chan->board_cfg.board_data = mipi;
	pdata->lcd_chan->board_cfg.display_on = mipi_display_on;
	pdata->lcd_chan->board_cfg.display_off = mipi_display_off;
	pdata->lcd_chan->board_cfg.owner = THIS_MODULE;

	return 0;

emipisetup:
	mipi_dsi[idx] = NULL;
	pm_runtime_disable(&pdev->dev);
	clk_disable(mipi->dsit_clk);
eclkton:
esettrate:
	clk_put(mipi->dsit_clk);
eclktget:
	iounmap(mipi->linkbase);
emap2:
	release_mem_region(res2->start, resource_size(res2));
ereqreg2:
	iounmap(mipi->base);
emap:
	release_mem_region(res->start, resource_size(res));
ereqreg:
	kfree(mipi);
ealloc:
efindslot:
	mutex_unlock(&array_lock);

	return ret;
}

static int __exit sh_mipi_remove(struct platform_device *pdev)
{
	struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	struct sh_mipi *mipi = platform_get_drvdata(pdev);
	int i, ret;

	mutex_lock(&array_lock);

	for (i = 0; i < ARRAY_SIZE(mipi_dsi) && mipi_dsi[i] != mipi; i++)
		;

	if (i == ARRAY_SIZE(mipi_dsi)) {
		ret = -EINVAL;
	} else {
		ret = 0;
		mipi_dsi[i] = NULL;
	}

	mutex_unlock(&array_lock);

	if (ret < 0)
		return ret;

	pdata->lcd_chan->board_cfg.owner = NULL;
	pdata->lcd_chan->board_cfg.display_on = NULL;
	pdata->lcd_chan->board_cfg.display_off = NULL;
	pdata->lcd_chan->board_cfg.board_data = NULL;

	pm_runtime_disable(&pdev->dev);
	clk_disable(mipi->dsit_clk);
	clk_put(mipi->dsit_clk);
	pdata->set_dot_clock(pdev, mipi->base, 0);

	iounmap(mipi->linkbase);
	if (res2)
		release_mem_region(res2->start, resource_size(res2));
	iounmap(mipi->base);
	if (res)
		release_mem_region(res->start, resource_size(res));
	platform_set_drvdata(pdev, NULL);
	kfree(mipi);

	return 0;
}

static struct platform_driver sh_mipi_driver = {
	.remove		= __exit_p(sh_mipi_remove),
	.shutdown	= sh_mipi_shutdown,
	.driver = {
		.name	= "sh-mipi-dsi",
	},
};

static int __init sh_mipi_init(void)
{
	return platform_driver_probe(&sh_mipi_driver, sh_mipi_probe);
}
module_init(sh_mipi_init);

static void __exit sh_mipi_exit(void)
{
	platform_driver_unregister(&sh_mipi_driver);
}
module_exit(sh_mipi_exit);

MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
MODULE_DESCRIPTION("SuperH / ARM-shmobile MIPI DSI driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
9fd04fe3 GL	1	/*
	2	* Renesas SH-mobile MIPI DSI support
	3	*
	4	* Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
	5	*
	6	* This is free software; you can redistribute it and/or modify
	7	* it under the terms of version 2 of the GNU General Public License as
	8	* published by the Free Software Foundation.
	9	*/
	10
26c3d7ac	11	#include <linux/bitmap.h>
9fd04fe3 GL	12	#include <linux/clk.h>
	13	#include <linux/delay.h>
	14	#include <linux/init.h>
	15	#include <linux/io.h>
	16	#include <linux/platform_device.h>
236782a5	17	#include <linux/pm_runtime.h>
9fd04fe3 GL	18	#include <linux/slab.h>
	19	#include <linux/string.h>
	20	#include <linux/types.h>
355b200b	21	#include <linux/module.h>
9fd04fe3 GL	22
	23	#include <video/mipi_display.h>
	24	#include <video/sh_mipi_dsi.h>
	25	#include <video/sh_mobile_lcdc.h>
	26
71b146c8 MD	27	#define SYSCTRL 0x0000
	28	#define SYSCONF 0x0004
	29	#define TIMSET 0x0008
	30	#define RESREQSET0 0x0018
	31	#define RESREQSET1 0x001c
	32	#define HSTTOVSET 0x0020
	33	#define LPRTOVSET 0x0024
	34	#define TATOVSET 0x0028
	35	#define PRTOVSET 0x002c
	36	#define DSICTRL 0x0030
	37	#define DSIINTE 0x0060
	38	#define PHYCTRL 0x0070
	39
deaba190 MD	40	/* relative to linkbase */
	41	#define DTCTR 0x0000
	42	#define VMCTR1 0x0020
	43	#define VMCTR2 0x0024
	44	#define VMLEN1 0x0028
08750617	45	#define VMLEN2 0x002c
deaba190 MD	46	#define CMTSRTREQ 0x0070
deaba190 MD	47	#define CMTSRTCTR 0x00d0
9fd04fe3 GL	48
	49	/* E.g., sh7372 has 2 MIPI-DSIs - one for each LCDC */
	50	#define MAX_SH_MIPI_DSI 2
	51
	52	struct sh_mipi {
	53	void __iomem *base;
deaba190	54	void __iomem *linkbase;
9fd04fe3	55	struct clk *dsit_clk;
236782a5 GL	56	struct device *dev;
	57
	58	void *next_board_data;
	59	void (next_display_on)(void board_data, struct fb_info *info);
	60	void (next_display_off)(void board_data);
9fd04fe3 GL	61	};
	62
	63	static struct sh_mipi *mipi_dsi[MAX_SH_MIPI_DSI];
	64
	65	/* Protect the above array */
	66	static DEFINE_MUTEX(array_lock);
	67
	68	static struct sh_mipi *sh_mipi_by_handle(int handle)
	69	{
	70	if (handle >= ARRAY_SIZE(mipi_dsi) \|\| handle < 0)
	71	return NULL;
	72
	73	return mipi_dsi[handle];
	74	}
	75
	76	static int sh_mipi_send_short(struct sh_mipi *mipi, u8 dsi_cmd,
	77	u8 cmd, u8 param)
	78	{
	79	u32 data = (dsi_cmd << 24) \| (cmd << 16) \| (param << 8);
	80	int cnt = 100;
	81
	82	/* transmit a short packet to LCD panel */
deaba190 MD	83	iowrite32(1 \| data, mipi->linkbase + CMTSRTCTR);
deaba190 MD	84	iowrite32(1, mipi->linkbase + CMTSRTREQ);
9fd04fe3	85
deaba190	86	while ((ioread32(mipi->linkbase + CMTSRTREQ) & 1) && --cnt)
9fd04fe3 GL	87	udelay(1);
	88
	89	return cnt ? 0 : -ETIMEDOUT;
	90	}
	91
	92	#define LCD_CHAN2MIPI(c) ((c) < LCDC_CHAN_MAINLCD \|\| (c) > LCDC_CHAN_SUBLCD ? \
	93	-EINVAL : (c) - 1)
	94
	95	static int sh_mipi_dcs(int handle, u8 cmd)
	96	{
	97	struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
	98	if (!mipi)
	99	return -ENODEV;
	100	return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE, cmd, 0);
	101	}
	102
	103	static int sh_mipi_dcs_param(int handle, u8 cmd, u8 param)
	104	{
	105	struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
	106	if (!mipi)
	107	return -ENODEV;
	108	return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE_PARAM, cmd,
	109	param);
	110	}
	111
	112	static void sh_mipi_dsi_enable(struct sh_mipi *mipi, bool enable)
	113	{
	114	/*
	115	* enable LCDC data tx, transition to LPS after completion of each HS
	116	* packet
	117	*/
deaba190	118	iowrite32(0x00000002 \| enable, mipi->linkbase + DTCTR);
9fd04fe3 GL	119	}
	120
	121	static void sh_mipi_shutdown(struct platform_device *pdev)
	122	{
	123	struct sh_mipi *mipi = platform_get_drvdata(pdev);
	124
	125	sh_mipi_dsi_enable(mipi, false);
	126	}
	127
c2439398	128	static void mipi_display_on(void arg, struct fb_info info)
9fd04fe3 GL	129	{
	130	struct sh_mipi *mipi = arg;
	131
236782a5	132	pm_runtime_get_sync(mipi->dev);
9fd04fe3	133	sh_mipi_dsi_enable(mipi, true);
6722a401 MD	134
	135	if (mipi->next_display_on)
	136	mipi->next_display_on(mipi->next_board_data, info);
9fd04fe3 GL	137	}
	138
	139	static void mipi_display_off(void *arg)
	140	{
	141	struct sh_mipi *mipi = arg;
	142
6722a401 MD	143	if (mipi->next_display_off)
	144	mipi->next_display_off(mipi->next_board_data);
	145
9fd04fe3	146	sh_mipi_dsi_enable(mipi, false);
236782a5	147	pm_runtime_put(mipi->dev);
9fd04fe3 GL	148	}
	149
	150	static int __init sh_mipi_setup(struct sh_mipi *mipi,
	151	struct sh_mipi_dsi_info *pdata)
	152	{
	153	void __iomem *base = mipi->base;
	154	struct sh_mobile_lcdc_chan_cfg *ch = pdata->lcd_chan;
f832906a	155	u32 pctype, datatype, pixfmt, linelength, vmctr2;
08750617	156	u32 tmp, top, bottom, delay;
9fd04fe3	157	bool yuv;
08750617	158	int bpp;
9fd04fe3	159
44432407 GL	160	/*
	161	* Select data format. MIPI DSI is not hot-pluggable, so, we just use
	162	* the default videomode. If this ever becomes a problem, We'll have to
	163	* move this to mipi_display_on() above and use info->var.xres
	164	*/
9fd04fe3 GL	165	switch (pdata->data_format) {
	166	case MIPI_RGB888:
	167	pctype = 0;
	168	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
	169	pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
44432407	170	linelength = ch->lcd_cfg[0].xres * 3;
9fd04fe3 GL	171	yuv = false;
	172	break;
	173	case MIPI_RGB565:
	174	pctype = 1;
	175	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
	176	pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
44432407	177	linelength = ch->lcd_cfg[0].xres * 2;
9fd04fe3 GL	178	yuv = false;
	179	break;
	180	case MIPI_RGB666_LP:
	181	pctype = 2;
	182	datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
	183	pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
44432407	184	linelength = ch->lcd_cfg[0].xres * 3;
9fd04fe3 GL	185	yuv = false;
	186	break;
	187	case MIPI_RGB666:
	188	pctype = 3;
	189	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
	190	pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
44432407	191	linelength = (ch->lcd_cfg[0].xres * 18 + 7) / 8;
9fd04fe3 GL	192	yuv = false;
	193	break;
	194	case MIPI_BGR888:
	195	pctype = 8;
	196	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
	197	pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
44432407	198	linelength = ch->lcd_cfg[0].xres * 3;
9fd04fe3 GL	199	yuv = false;
	200	break;
	201	case MIPI_BGR565:
	202	pctype = 9;
	203	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
	204	pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
44432407	205	linelength = ch->lcd_cfg[0].xres * 2;
9fd04fe3 GL	206	yuv = false;
	207	break;
	208	case MIPI_BGR666_LP:
	209	pctype = 0xa;
	210	datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
	211	pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
44432407	212	linelength = ch->lcd_cfg[0].xres * 3;
9fd04fe3 GL	213	yuv = false;
	214	break;
	215	case MIPI_BGR666:
	216	pctype = 0xb;
	217	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
	218	pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
44432407	219	linelength = (ch->lcd_cfg[0].xres * 18 + 7) / 8;
9fd04fe3 GL	220	yuv = false;
	221	break;
	222	case MIPI_YUYV:
	223	pctype = 4;
	224	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
	225	pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
44432407	226	linelength = ch->lcd_cfg[0].xres * 2;
9fd04fe3 GL	227	yuv = true;
	228	break;
	229	case MIPI_UYVY:
	230	pctype = 5;
	231	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
	232	pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
44432407	233	linelength = ch->lcd_cfg[0].xres * 2;
9fd04fe3 GL	234	yuv = true;
	235	break;
	236	case MIPI_YUV420_L:
	237	pctype = 6;
	238	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
	239	pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
44432407	240	linelength = (ch->lcd_cfg[0].xres * 12 + 7) / 8;
9fd04fe3 GL	241	yuv = true;
	242	break;
	243	case MIPI_YUV420:
	244	pctype = 7;
	245	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
	246	pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
	247	/* Length of U/V line */
44432407	248	linelength = (ch->lcd_cfg[0].xres + 1) / 2;
9fd04fe3 GL	249	yuv = true;
	250	break;
	251	default:
	252	return -EINVAL;
	253	}
	254
	255	if ((yuv && ch->interface_type != YUV422) \|\|
	256	(!yuv && ch->interface_type != RGB24))
	257	return -EINVAL;
	258
26c3d7ac KM	259	if (!pdata->lane)
	260	return -EINVAL;
	261
9fd04fe3	262	/* reset DSI link */
71b146c8	263	iowrite32(0x00000001, base + SYSCTRL);
9fd04fe3 GL	264	/* Hold reset for 100 cycles of the slowest of bus, HS byte and LP clock */
9fd04fe3 GL	265	udelay(50);
71b146c8	266	iowrite32(0x00000000, base + SYSCTRL);
9fd04fe3 GL	267
	268	/* setup DSI link */
	269
	270	/*
	271	* Default = ULPS enable \|
	272	* Contention detection enabled \|
	273	* EoT packet transmission enable \|
	274	* CRC check enable \|
	275	* ECC check enable
	276	* additionally enable first two lanes
	277	*/
26c3d7ac KM	278	bitmap_fill((unsigned long *)&tmp, pdata->lane);
	279	tmp \|= 0x00003700;
	280	iowrite32(tmp, base + SYSCONF);
	281
9fd04fe3 GL	282	/*
	283	* T_wakeup = 0x7000
	284	* T_hs-trail = 3
	285	* T_hs-prepare = 3
	286	* T_clk-trail = 3
	287	* T_clk-prepare = 2
	288	*/
71b146c8	289	iowrite32(0x70003332, base + TIMSET);
9fd04fe3	290	/* no responses requested */
71b146c8	291	iowrite32(0x00000000, base + RESREQSET0);
9fd04fe3	292	/* request response to packets of type 0x28 */
71b146c8	293	iowrite32(0x00000100, base + RESREQSET1);
9fd04fe3	294	/* High-speed transmission timeout, default 0xffffffff */
71b146c8	295	iowrite32(0x0fffffff, base + HSTTOVSET);
9fd04fe3	296	/* LP reception timeout, default 0xffffffff */
71b146c8	297	iowrite32(0x0fffffff, base + LPRTOVSET);
9fd04fe3	298	/* Turn-around timeout, default 0xffffffff */
71b146c8	299	iowrite32(0x0fffffff, base + TATOVSET);
9fd04fe3	300	/* Peripheral reset timeout, default 0xffffffff */
71b146c8	301	iowrite32(0x0fffffff, base + PRTOVSET);
9fd04fe3	302	/* Enable timeout counters */
71b146c8	303	iowrite32(0x00000f00, base + DSICTRL);
9fd04fe3 GL	304	/* Interrupts not used, disable all */
	305	iowrite32(0, base + DSIINTE);
	306	/* DSI-Tx bias on */
71b146c8	307	iowrite32(0x00000001, base + PHYCTRL);
9fd04fe3	308	udelay(200);
5e47431a KM	309	/* Deassert resets, power on */
5e47431a KM	310	iowrite32(0x03070001, base + PHYCTRL);
9fd04fe3 GL	311
	312	/* setup l-bridge */
	313
	314	/*
	315	* Enable transmission of all packets,
	316	* transmit LPS after each HS packet completion
	317	*/
deaba190	318	iowrite32(0x00000006, mipi->linkbase + DTCTR);
9fd04fe3	319	/* VSYNC width = 2 (<< 17) */
14bbb7c6 GL	320	iowrite32((ch->lcd_cfg[0].vsync_len << pdata->vsynw_offset) \|
14bbb7c6 GL	321	(pdata->clksrc << 16) \| (pctype << 12) \| datatype,
deaba190	322	mipi->linkbase + VMCTR1);
14bbb7c6	323
9fd04fe3 GL	324	/*
	325	* Non-burst mode with sync pulses: VSE and HSE are output,
	326	* HSA period allowed, no commands in LP
	327	*/
f832906a KM	328	vmctr2 = 0;
	329	if (pdata->flags & SH_MIPI_DSI_VSEE)
	330	vmctr2 \|= 1 << 23;
	331	if (pdata->flags & SH_MIPI_DSI_HSEE)
	332	vmctr2 \|= 1 << 22;
	333	if (pdata->flags & SH_MIPI_DSI_HSAE)
	334	vmctr2 \|= 1 << 21;
d07a9d2a KM	335	if (pdata->flags & SH_MIPI_DSI_BL2E)
d07a9d2a KM	336	vmctr2 \|= 1 << 17;
14bbb7c6	337	if (pdata->flags & SH_MIPI_DSI_HSABM)
3c2a6599	338	vmctr2 \|= 1 << 5;
32ba95c6	339	if (pdata->flags & SH_MIPI_DSI_HBPBM)
3c2a6599	340	vmctr2 \|= 1 << 4;
f7b0af68 KM	341	if (pdata->flags & SH_MIPI_DSI_HFPBM)
f7b0af68 KM	342	vmctr2 \|= 1 << 3;
14bbb7c6 GL	343	iowrite32(vmctr2, mipi->linkbase + VMCTR2);
14bbb7c6 GL	344
9fd04fe3	345	/*
08750617 KM	346	* VMLEN1 = RGBLEN \| HSALEN
	347	*
	348	* see
	349	* Video mode - Blanking Packet setting
9fd04fe3	350	*/
08750617 KM	351	top = linelength << 16; /* RGBLEN */
	352	bottom = 0x00000001;
	353	if (pdata->flags & SH_MIPI_DSI_HSABM) /* HSALEN */
	354	bottom = (pdata->lane * ch->lcd_cfg[0].hsync_len) - 10;
	355	iowrite32(top \| bottom , mipi->linkbase + VMLEN1);
	356
	357	/*
	358	* VMLEN2 = HBPLEN \| HFPLEN
	359	*
	360	* see
	361	* Video mode - Blanking Packet setting
	362	*/
	363	top = 0x00010000;
	364	bottom = 0x00000001;
	365	delay = 0;
	366
	367	if (pdata->flags & SH_MIPI_DSI_HFPBM) { /* HBPLEN */
	368	top = ch->lcd_cfg[0].hsync_len + ch->lcd_cfg[0].left_margin;
	369	top = ((pdata->lane * top) - 10) << 16;
	370	}
	371	if (pdata->flags & SH_MIPI_DSI_HBPBM) { /* HFPLEN */
	372	bottom = ch->lcd_cfg[0].right_margin;
	373	bottom = (pdata->lane * bottom) - 12;
	374	}
	375
	376	bpp = linelength / ch->lcd_cfg[0].xres; /* byte / pixel */
	377	if (pdata->lane > bpp) {
	378	tmp = ch->lcd_cfg[0].xres / bpp; /* output cycle */
	379	tmp = ch->lcd_cfg[0].xres - tmp; /* (input - output) cycle */
	380	delay = (pdata->lane * tmp);
	381	}
	382
	383	iowrite32(top \| (bottom + delay) , mipi->linkbase + VMLEN2);
9fd04fe3 GL	384
	385	msleep(5);
	386
	387	/* setup LCD panel */
	388
	389	/* cf. drivers/video/omap/lcd_mipid.c */
	390	sh_mipi_dcs(ch->chan, MIPI_DCS_EXIT_SLEEP_MODE);
	391	msleep(120);
	392	/*
	393	* [7] - Page Address Mode
	394	* [6] - Column Address Mode
	395	* [5] - Page / Column Address Mode
	396	* [4] - Display Device Line Refresh Order
	397	* [3] - RGB/BGR Order
	398	* [2] - Display Data Latch Data Order
	399	* [1] - Flip Horizontal
	400	* [0] - Flip Vertical
	401	*/
	402	sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
	403	/* cf. set_data_lines() */
	404	sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_PIXEL_FORMAT,
	405	pixfmt << 4);
	406	sh_mipi_dcs(ch->chan, MIPI_DCS_SET_DISPLAY_ON);
	407
	408	return 0;
	409	}
	410
	411	static int __init sh_mipi_probe(struct platform_device *pdev)
	412	{
	413	struct sh_mipi *mipi;
	414	struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
	415	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
deaba190	416	struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
9fd04fe3 GL	417	unsigned long rate, f_current;
9fd04fe3 GL	418	int idx = pdev->id, ret;
9fd04fe3	419
deaba190	420	if (!res \|\| !res2 \|\| idx >= ARRAY_SIZE(mipi_dsi) \|\| !pdata)
9fd04fe3 GL	421	return -ENODEV;
9fd04fe3 GL	422
5e47431a KM	423	if (!pdata->set_dot_clock)
	424	return -EINVAL;
	425
9fd04fe3 GL	426	mutex_lock(&array_lock);
	427	if (idx < 0)
	428	for (idx = 0; idx < ARRAY_SIZE(mipi_dsi) && mipi_dsi[idx]; idx++)
	429	;
	430
	431	if (idx == ARRAY_SIZE(mipi_dsi)) {
	432	ret = -EBUSY;
	433	goto efindslot;
	434	}
	435
	436	mipi = kzalloc(sizeof(*mipi), GFP_KERNEL);
	437	if (!mipi) {
	438	ret = -ENOMEM;
	439	goto ealloc;
	440	}
	441
	442	if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
	443	dev_err(&pdev->dev, "MIPI register region already claimed\n");
	444	ret = -EBUSY;
	445	goto ereqreg;
	446	}
	447
	448	mipi->base = ioremap(res->start, resource_size(res));
	449	if (!mipi->base) {
	450	ret = -ENOMEM;
	451	goto emap;
	452	}
	453
deaba190 MD	454	if (!request_mem_region(res2->start, resource_size(res2), pdev->name)) {
	455	dev_err(&pdev->dev, "MIPI register region 2 already claimed\n");
	456	ret = -EBUSY;
	457	goto ereqreg2;
	458	}
	459
	460	mipi->linkbase = ioremap(res2->start, resource_size(res2));
	461	if (!mipi->linkbase) {
	462	ret = -ENOMEM;
	463	goto emap2;
	464	}
	465
236782a5 GL	466	mipi->dev = &pdev->dev;
236782a5 GL	467
9fd04fe3 GL	468	mipi->dsit_clk = clk_get(&pdev->dev, "dsit_clk");
	469	if (IS_ERR(mipi->dsit_clk)) {
	470	ret = PTR_ERR(mipi->dsit_clk);
	471	goto eclktget;
	472	}
	473
	474	f_current = clk_get_rate(mipi->dsit_clk);
	475	/* 80MHz required by the datasheet */
	476	rate = clk_round_rate(mipi->dsit_clk, 80000000);
	477	if (rate > 0 && rate != f_current)
	478	ret = clk_set_rate(mipi->dsit_clk, rate);
	479	else
	480	ret = rate;
	481	if (ret < 0)
	482	goto esettrate;
	483
	484	dev_dbg(&pdev->dev, "DSI-T clk %lu -> %lu\n", f_current, rate);
	485
9fd04fe3 GL	486	ret = clk_enable(mipi->dsit_clk);
	487	if (ret < 0)
	488	goto eclkton;
	489
9fd04fe3 GL	490	mipi_dsi[idx] = mipi;
9fd04fe3 GL	491
236782a5 GL	492	pm_runtime_enable(&pdev->dev);
	493	pm_runtime_resume(&pdev->dev);
	494
9fd04fe3 GL	495	ret = sh_mipi_setup(mipi, pdata);
	496	if (ret < 0)
	497	goto emipisetup;
	498
5e47431a KM	499	ret = pdata->set_dot_clock(pdev, mipi->base, 1);
	500	if (ret < 0)
	501	goto emipisetup;
	502
9fd04fe3 GL	503	mutex_unlock(&array_lock);
	504	platform_set_drvdata(pdev, mipi);
	505
6722a401 MD	506	/* Save original LCDC callbacks */
	507	mipi->next_board_data = pdata->lcd_chan->board_cfg.board_data;
	508	mipi->next_display_on = pdata->lcd_chan->board_cfg.display_on;
	509	mipi->next_display_off = pdata->lcd_chan->board_cfg.display_off;
	510
9fd04fe3 GL	511	/* Set up LCDC callbacks */
	512	pdata->lcd_chan->board_cfg.board_data = mipi;
	513	pdata->lcd_chan->board_cfg.display_on = mipi_display_on;
	514	pdata->lcd_chan->board_cfg.display_off = mipi_display_off;
236782a5	515	pdata->lcd_chan->board_cfg.owner = THIS_MODULE;
9fd04fe3 GL	516
	517	return 0;
	518
	519	emipisetup:
	520	mipi_dsi[idx] = NULL;
236782a5	521	pm_runtime_disable(&pdev->dev);
9fd04fe3 GL	522	clk_disable(mipi->dsit_clk);
9fd04fe3 GL	523	eclkton:
9fd04fe3 GL	524	esettrate:
	525	clk_put(mipi->dsit_clk);
	526	eclktget:
deaba190 MD	527	iounmap(mipi->linkbase);
	528	emap2:
	529	release_mem_region(res2->start, resource_size(res2));
	530	ereqreg2:
9fd04fe3 GL	531	iounmap(mipi->base);
	532	emap:
	533	release_mem_region(res->start, resource_size(res));
	534	ereqreg:
	535	kfree(mipi);
	536	ealloc:
	537	efindslot:
	538	mutex_unlock(&array_lock);
	539
	540	return ret;
	541	}
	542
	543	static int __exit sh_mipi_remove(struct platform_device *pdev)
	544	{
	545	struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
	546	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
deaba190	547	struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
9fd04fe3 GL	548	struct sh_mipi *mipi = platform_get_drvdata(pdev);
	549	int i, ret;
	550
	551	mutex_lock(&array_lock);
	552
	553	for (i = 0; i < ARRAY_SIZE(mipi_dsi) && mipi_dsi[i] != mipi; i++)
	554	;
	555
	556	if (i == ARRAY_SIZE(mipi_dsi)) {
	557	ret = -EINVAL;
	558	} else {
	559	ret = 0;
	560	mipi_dsi[i] = NULL;
	561	}
	562
	563	mutex_unlock(&array_lock);
	564
	565	if (ret < 0)
	566	return ret;
	567
236782a5	568	pdata->lcd_chan->board_cfg.owner = NULL;
9fd04fe3 GL	569	pdata->lcd_chan->board_cfg.display_on = NULL;
	570	pdata->lcd_chan->board_cfg.display_off = NULL;
	571	pdata->lcd_chan->board_cfg.board_data = NULL;
	572
236782a5	573	pm_runtime_disable(&pdev->dev);
9fd04fe3 GL	574	clk_disable(mipi->dsit_clk);
9fd04fe3 GL	575	clk_put(mipi->dsit_clk);
5e47431a KM	576	pdata->set_dot_clock(pdev, mipi->base, 0);
5e47431a KM	577
deaba190 MD	578	iounmap(mipi->linkbase);
	579	if (res2)
	580	release_mem_region(res2->start, resource_size(res2));
9fd04fe3 GL	581	iounmap(mipi->base);
	582	if (res)
	583	release_mem_region(res->start, resource_size(res));
	584	platform_set_drvdata(pdev, NULL);
	585	kfree(mipi);
	586
	587	return 0;
	588	}
	589
	590	static struct platform_driver sh_mipi_driver = {
	591	.remove = __exit_p(sh_mipi_remove),
	592	.shutdown = sh_mipi_shutdown,
	593	.driver = {
	594	.name = "sh-mipi-dsi",
	595	},
	596	};
	597
	598	static int __init sh_mipi_init(void)
	599	{
	600	return platform_driver_probe(&sh_mipi_driver, sh_mipi_probe);
	601	}
	602	module_init(sh_mipi_init);
	603
	604	static void __exit sh_mipi_exit(void)
	605	{
	606	platform_driver_unregister(&sh_mipi_driver);
	607	}
	608	module_exit(sh_mipi_exit);
	609
	610	MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
	611	MODULE_DESCRIPTION("SuperH / ARM-shmobile MIPI DSI driver");
	612	MODULE_LICENSE("GPL v2");