Commit | Line | Data |
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9fd04fe3 GL |
1 | /* |
2 | * Renesas SH-mobile MIPI DSI support | |
3 | * | |
4 | * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de> | |
5 | * | |
6 | * This is free software; you can redistribute it and/or modify | |
7 | * it under the terms of version 2 of the GNU General Public License as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/clk.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/platform_device.h> | |
236782a5 | 16 | #include <linux/pm_runtime.h> |
9fd04fe3 GL |
17 | #include <linux/slab.h> |
18 | #include <linux/string.h> | |
19 | #include <linux/types.h> | |
355b200b | 20 | #include <linux/module.h> |
9fd04fe3 GL |
21 | |
22 | #include <video/mipi_display.h> | |
23 | #include <video/sh_mipi_dsi.h> | |
24 | #include <video/sh_mobile_lcdc.h> | |
25 | ||
71b146c8 MD |
26 | #define SYSCTRL 0x0000 |
27 | #define SYSCONF 0x0004 | |
28 | #define TIMSET 0x0008 | |
29 | #define RESREQSET0 0x0018 | |
30 | #define RESREQSET1 0x001c | |
31 | #define HSTTOVSET 0x0020 | |
32 | #define LPRTOVSET 0x0024 | |
33 | #define TATOVSET 0x0028 | |
34 | #define PRTOVSET 0x002c | |
35 | #define DSICTRL 0x0030 | |
36 | #define DSIINTE 0x0060 | |
37 | #define PHYCTRL 0x0070 | |
38 | ||
deaba190 MD |
39 | /* relative to linkbase */ |
40 | #define DTCTR 0x0000 | |
41 | #define VMCTR1 0x0020 | |
42 | #define VMCTR2 0x0024 | |
43 | #define VMLEN1 0x0028 | |
44 | #define CMTSRTREQ 0x0070 | |
45 | #define CMTSRTCTR 0x00d0 | |
9fd04fe3 GL |
46 | |
47 | /* E.g., sh7372 has 2 MIPI-DSIs - one for each LCDC */ | |
48 | #define MAX_SH_MIPI_DSI 2 | |
49 | ||
50 | struct sh_mipi { | |
51 | void __iomem *base; | |
deaba190 | 52 | void __iomem *linkbase; |
9fd04fe3 GL |
53 | struct clk *dsit_clk; |
54 | struct clk *dsip_clk; | |
236782a5 GL |
55 | struct device *dev; |
56 | ||
57 | void *next_board_data; | |
58 | void (*next_display_on)(void *board_data, struct fb_info *info); | |
59 | void (*next_display_off)(void *board_data); | |
9fd04fe3 GL |
60 | }; |
61 | ||
62 | static struct sh_mipi *mipi_dsi[MAX_SH_MIPI_DSI]; | |
63 | ||
64 | /* Protect the above array */ | |
65 | static DEFINE_MUTEX(array_lock); | |
66 | ||
67 | static struct sh_mipi *sh_mipi_by_handle(int handle) | |
68 | { | |
69 | if (handle >= ARRAY_SIZE(mipi_dsi) || handle < 0) | |
70 | return NULL; | |
71 | ||
72 | return mipi_dsi[handle]; | |
73 | } | |
74 | ||
75 | static int sh_mipi_send_short(struct sh_mipi *mipi, u8 dsi_cmd, | |
76 | u8 cmd, u8 param) | |
77 | { | |
78 | u32 data = (dsi_cmd << 24) | (cmd << 16) | (param << 8); | |
79 | int cnt = 100; | |
80 | ||
81 | /* transmit a short packet to LCD panel */ | |
deaba190 MD |
82 | iowrite32(1 | data, mipi->linkbase + CMTSRTCTR); |
83 | iowrite32(1, mipi->linkbase + CMTSRTREQ); | |
9fd04fe3 | 84 | |
deaba190 | 85 | while ((ioread32(mipi->linkbase + CMTSRTREQ) & 1) && --cnt) |
9fd04fe3 GL |
86 | udelay(1); |
87 | ||
88 | return cnt ? 0 : -ETIMEDOUT; | |
89 | } | |
90 | ||
91 | #define LCD_CHAN2MIPI(c) ((c) < LCDC_CHAN_MAINLCD || (c) > LCDC_CHAN_SUBLCD ? \ | |
92 | -EINVAL : (c) - 1) | |
93 | ||
94 | static int sh_mipi_dcs(int handle, u8 cmd) | |
95 | { | |
96 | struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle)); | |
97 | if (!mipi) | |
98 | return -ENODEV; | |
99 | return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE, cmd, 0); | |
100 | } | |
101 | ||
102 | static int sh_mipi_dcs_param(int handle, u8 cmd, u8 param) | |
103 | { | |
104 | struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle)); | |
105 | if (!mipi) | |
106 | return -ENODEV; | |
107 | return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE_PARAM, cmd, | |
108 | param); | |
109 | } | |
110 | ||
111 | static void sh_mipi_dsi_enable(struct sh_mipi *mipi, bool enable) | |
112 | { | |
113 | /* | |
114 | * enable LCDC data tx, transition to LPS after completion of each HS | |
115 | * packet | |
116 | */ | |
deaba190 | 117 | iowrite32(0x00000002 | enable, mipi->linkbase + DTCTR); |
9fd04fe3 GL |
118 | } |
119 | ||
120 | static void sh_mipi_shutdown(struct platform_device *pdev) | |
121 | { | |
122 | struct sh_mipi *mipi = platform_get_drvdata(pdev); | |
123 | ||
124 | sh_mipi_dsi_enable(mipi, false); | |
125 | } | |
126 | ||
c2439398 | 127 | static void mipi_display_on(void *arg, struct fb_info *info) |
9fd04fe3 GL |
128 | { |
129 | struct sh_mipi *mipi = arg; | |
130 | ||
236782a5 | 131 | pm_runtime_get_sync(mipi->dev); |
9fd04fe3 | 132 | sh_mipi_dsi_enable(mipi, true); |
6722a401 MD |
133 | |
134 | if (mipi->next_display_on) | |
135 | mipi->next_display_on(mipi->next_board_data, info); | |
9fd04fe3 GL |
136 | } |
137 | ||
138 | static void mipi_display_off(void *arg) | |
139 | { | |
140 | struct sh_mipi *mipi = arg; | |
141 | ||
6722a401 MD |
142 | if (mipi->next_display_off) |
143 | mipi->next_display_off(mipi->next_board_data); | |
144 | ||
9fd04fe3 | 145 | sh_mipi_dsi_enable(mipi, false); |
236782a5 | 146 | pm_runtime_put(mipi->dev); |
9fd04fe3 GL |
147 | } |
148 | ||
149 | static int __init sh_mipi_setup(struct sh_mipi *mipi, | |
150 | struct sh_mipi_dsi_info *pdata) | |
151 | { | |
152 | void __iomem *base = mipi->base; | |
153 | struct sh_mobile_lcdc_chan_cfg *ch = pdata->lcd_chan; | |
14bbb7c6 | 154 | u32 pctype, datatype, pixfmt, linelength, vmctr2 = 0x00e00000; |
9fd04fe3 GL |
155 | bool yuv; |
156 | ||
44432407 GL |
157 | /* |
158 | * Select data format. MIPI DSI is not hot-pluggable, so, we just use | |
159 | * the default videomode. If this ever becomes a problem, We'll have to | |
160 | * move this to mipi_display_on() above and use info->var.xres | |
161 | */ | |
9fd04fe3 GL |
162 | switch (pdata->data_format) { |
163 | case MIPI_RGB888: | |
164 | pctype = 0; | |
165 | datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24; | |
166 | pixfmt = MIPI_DCS_PIXEL_FMT_24BIT; | |
44432407 | 167 | linelength = ch->lcd_cfg[0].xres * 3; |
9fd04fe3 GL |
168 | yuv = false; |
169 | break; | |
170 | case MIPI_RGB565: | |
171 | pctype = 1; | |
172 | datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16; | |
173 | pixfmt = MIPI_DCS_PIXEL_FMT_16BIT; | |
44432407 | 174 | linelength = ch->lcd_cfg[0].xres * 2; |
9fd04fe3 GL |
175 | yuv = false; |
176 | break; | |
177 | case MIPI_RGB666_LP: | |
178 | pctype = 2; | |
179 | datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18; | |
180 | pixfmt = MIPI_DCS_PIXEL_FMT_24BIT; | |
44432407 | 181 | linelength = ch->lcd_cfg[0].xres * 3; |
9fd04fe3 GL |
182 | yuv = false; |
183 | break; | |
184 | case MIPI_RGB666: | |
185 | pctype = 3; | |
186 | datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18; | |
187 | pixfmt = MIPI_DCS_PIXEL_FMT_18BIT; | |
44432407 | 188 | linelength = (ch->lcd_cfg[0].xres * 18 + 7) / 8; |
9fd04fe3 GL |
189 | yuv = false; |
190 | break; | |
191 | case MIPI_BGR888: | |
192 | pctype = 8; | |
193 | datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24; | |
194 | pixfmt = MIPI_DCS_PIXEL_FMT_24BIT; | |
44432407 | 195 | linelength = ch->lcd_cfg[0].xres * 3; |
9fd04fe3 GL |
196 | yuv = false; |
197 | break; | |
198 | case MIPI_BGR565: | |
199 | pctype = 9; | |
200 | datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16; | |
201 | pixfmt = MIPI_DCS_PIXEL_FMT_16BIT; | |
44432407 | 202 | linelength = ch->lcd_cfg[0].xres * 2; |
9fd04fe3 GL |
203 | yuv = false; |
204 | break; | |
205 | case MIPI_BGR666_LP: | |
206 | pctype = 0xa; | |
207 | datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18; | |
208 | pixfmt = MIPI_DCS_PIXEL_FMT_24BIT; | |
44432407 | 209 | linelength = ch->lcd_cfg[0].xres * 3; |
9fd04fe3 GL |
210 | yuv = false; |
211 | break; | |
212 | case MIPI_BGR666: | |
213 | pctype = 0xb; | |
214 | datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18; | |
215 | pixfmt = MIPI_DCS_PIXEL_FMT_18BIT; | |
44432407 | 216 | linelength = (ch->lcd_cfg[0].xres * 18 + 7) / 8; |
9fd04fe3 GL |
217 | yuv = false; |
218 | break; | |
219 | case MIPI_YUYV: | |
220 | pctype = 4; | |
221 | datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16; | |
222 | pixfmt = MIPI_DCS_PIXEL_FMT_16BIT; | |
44432407 | 223 | linelength = ch->lcd_cfg[0].xres * 2; |
9fd04fe3 GL |
224 | yuv = true; |
225 | break; | |
226 | case MIPI_UYVY: | |
227 | pctype = 5; | |
228 | datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16; | |
229 | pixfmt = MIPI_DCS_PIXEL_FMT_16BIT; | |
44432407 | 230 | linelength = ch->lcd_cfg[0].xres * 2; |
9fd04fe3 GL |
231 | yuv = true; |
232 | break; | |
233 | case MIPI_YUV420_L: | |
234 | pctype = 6; | |
235 | datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12; | |
236 | pixfmt = MIPI_DCS_PIXEL_FMT_12BIT; | |
44432407 | 237 | linelength = (ch->lcd_cfg[0].xres * 12 + 7) / 8; |
9fd04fe3 GL |
238 | yuv = true; |
239 | break; | |
240 | case MIPI_YUV420: | |
241 | pctype = 7; | |
242 | datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12; | |
243 | pixfmt = MIPI_DCS_PIXEL_FMT_12BIT; | |
244 | /* Length of U/V line */ | |
44432407 | 245 | linelength = (ch->lcd_cfg[0].xres + 1) / 2; |
9fd04fe3 GL |
246 | yuv = true; |
247 | break; | |
248 | default: | |
249 | return -EINVAL; | |
250 | } | |
251 | ||
252 | if ((yuv && ch->interface_type != YUV422) || | |
253 | (!yuv && ch->interface_type != RGB24)) | |
254 | return -EINVAL; | |
255 | ||
256 | /* reset DSI link */ | |
71b146c8 | 257 | iowrite32(0x00000001, base + SYSCTRL); |
9fd04fe3 GL |
258 | /* Hold reset for 100 cycles of the slowest of bus, HS byte and LP clock */ |
259 | udelay(50); | |
71b146c8 | 260 | iowrite32(0x00000000, base + SYSCTRL); |
9fd04fe3 GL |
261 | |
262 | /* setup DSI link */ | |
263 | ||
264 | /* | |
265 | * Default = ULPS enable | | |
266 | * Contention detection enabled | | |
267 | * EoT packet transmission enable | | |
268 | * CRC check enable | | |
269 | * ECC check enable | |
270 | * additionally enable first two lanes | |
271 | */ | |
71b146c8 | 272 | iowrite32(0x00003703, base + SYSCONF); |
9fd04fe3 GL |
273 | /* |
274 | * T_wakeup = 0x7000 | |
275 | * T_hs-trail = 3 | |
276 | * T_hs-prepare = 3 | |
277 | * T_clk-trail = 3 | |
278 | * T_clk-prepare = 2 | |
279 | */ | |
71b146c8 | 280 | iowrite32(0x70003332, base + TIMSET); |
9fd04fe3 | 281 | /* no responses requested */ |
71b146c8 | 282 | iowrite32(0x00000000, base + RESREQSET0); |
9fd04fe3 | 283 | /* request response to packets of type 0x28 */ |
71b146c8 | 284 | iowrite32(0x00000100, base + RESREQSET1); |
9fd04fe3 | 285 | /* High-speed transmission timeout, default 0xffffffff */ |
71b146c8 | 286 | iowrite32(0x0fffffff, base + HSTTOVSET); |
9fd04fe3 | 287 | /* LP reception timeout, default 0xffffffff */ |
71b146c8 | 288 | iowrite32(0x0fffffff, base + LPRTOVSET); |
9fd04fe3 | 289 | /* Turn-around timeout, default 0xffffffff */ |
71b146c8 | 290 | iowrite32(0x0fffffff, base + TATOVSET); |
9fd04fe3 | 291 | /* Peripheral reset timeout, default 0xffffffff */ |
71b146c8 | 292 | iowrite32(0x0fffffff, base + PRTOVSET); |
9fd04fe3 | 293 | /* Enable timeout counters */ |
71b146c8 | 294 | iowrite32(0x00000f00, base + DSICTRL); |
9fd04fe3 GL |
295 | /* Interrupts not used, disable all */ |
296 | iowrite32(0, base + DSIINTE); | |
297 | /* DSI-Tx bias on */ | |
71b146c8 | 298 | iowrite32(0x00000001, base + PHYCTRL); |
9fd04fe3 GL |
299 | udelay(200); |
300 | /* Deassert resets, power on, set multiplier */ | |
71b146c8 | 301 | iowrite32(0x03070b01, base + PHYCTRL); |
9fd04fe3 GL |
302 | |
303 | /* setup l-bridge */ | |
304 | ||
305 | /* | |
306 | * Enable transmission of all packets, | |
307 | * transmit LPS after each HS packet completion | |
308 | */ | |
deaba190 | 309 | iowrite32(0x00000006, mipi->linkbase + DTCTR); |
9fd04fe3 | 310 | /* VSYNC width = 2 (<< 17) */ |
14bbb7c6 GL |
311 | iowrite32((ch->lcd_cfg[0].vsync_len << pdata->vsynw_offset) | |
312 | (pdata->clksrc << 16) | (pctype << 12) | datatype, | |
deaba190 | 313 | mipi->linkbase + VMCTR1); |
14bbb7c6 | 314 | |
9fd04fe3 GL |
315 | /* |
316 | * Non-burst mode with sync pulses: VSE and HSE are output, | |
317 | * HSA period allowed, no commands in LP | |
318 | */ | |
d07a9d2a KM |
319 | if (pdata->flags & SH_MIPI_DSI_BL2E) |
320 | vmctr2 |= 1 << 17; | |
14bbb7c6 | 321 | if (pdata->flags & SH_MIPI_DSI_HSABM) |
3c2a6599 | 322 | vmctr2 |= 1 << 5; |
32ba95c6 | 323 | if (pdata->flags & SH_MIPI_DSI_HBPBM) |
3c2a6599 | 324 | vmctr2 |= 1 << 4; |
f7b0af68 KM |
325 | if (pdata->flags & SH_MIPI_DSI_HFPBM) |
326 | vmctr2 |= 1 << 3; | |
14bbb7c6 GL |
327 | iowrite32(vmctr2, mipi->linkbase + VMCTR2); |
328 | ||
9fd04fe3 GL |
329 | /* |
330 | * 0x660 = 1632 bytes per line (RGB24, 544 pixels: see | |
44432407 | 331 | * sh_mobile_lcdc_info.ch[0].lcd_cfg[0].xres), HSALEN = 1 - default |
14bbb7c6 | 332 | * (unused if VMCTR2[HSABM] = 0) |
9fd04fe3 | 333 | */ |
deaba190 | 334 | iowrite32(1 | (linelength << 16), mipi->linkbase + VMLEN1); |
9fd04fe3 GL |
335 | |
336 | msleep(5); | |
337 | ||
338 | /* setup LCD panel */ | |
339 | ||
340 | /* cf. drivers/video/omap/lcd_mipid.c */ | |
341 | sh_mipi_dcs(ch->chan, MIPI_DCS_EXIT_SLEEP_MODE); | |
342 | msleep(120); | |
343 | /* | |
344 | * [7] - Page Address Mode | |
345 | * [6] - Column Address Mode | |
346 | * [5] - Page / Column Address Mode | |
347 | * [4] - Display Device Line Refresh Order | |
348 | * [3] - RGB/BGR Order | |
349 | * [2] - Display Data Latch Data Order | |
350 | * [1] - Flip Horizontal | |
351 | * [0] - Flip Vertical | |
352 | */ | |
353 | sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_ADDRESS_MODE, 0x00); | |
354 | /* cf. set_data_lines() */ | |
355 | sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_PIXEL_FORMAT, | |
356 | pixfmt << 4); | |
357 | sh_mipi_dcs(ch->chan, MIPI_DCS_SET_DISPLAY_ON); | |
358 | ||
359 | return 0; | |
360 | } | |
361 | ||
362 | static int __init sh_mipi_probe(struct platform_device *pdev) | |
363 | { | |
364 | struct sh_mipi *mipi; | |
365 | struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data; | |
366 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
deaba190 | 367 | struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
9fd04fe3 GL |
368 | unsigned long rate, f_current; |
369 | int idx = pdev->id, ret; | |
9fd04fe3 | 370 | |
deaba190 | 371 | if (!res || !res2 || idx >= ARRAY_SIZE(mipi_dsi) || !pdata) |
9fd04fe3 GL |
372 | return -ENODEV; |
373 | ||
374 | mutex_lock(&array_lock); | |
375 | if (idx < 0) | |
376 | for (idx = 0; idx < ARRAY_SIZE(mipi_dsi) && mipi_dsi[idx]; idx++) | |
377 | ; | |
378 | ||
379 | if (idx == ARRAY_SIZE(mipi_dsi)) { | |
380 | ret = -EBUSY; | |
381 | goto efindslot; | |
382 | } | |
383 | ||
384 | mipi = kzalloc(sizeof(*mipi), GFP_KERNEL); | |
385 | if (!mipi) { | |
386 | ret = -ENOMEM; | |
387 | goto ealloc; | |
388 | } | |
389 | ||
390 | if (!request_mem_region(res->start, resource_size(res), pdev->name)) { | |
391 | dev_err(&pdev->dev, "MIPI register region already claimed\n"); | |
392 | ret = -EBUSY; | |
393 | goto ereqreg; | |
394 | } | |
395 | ||
396 | mipi->base = ioremap(res->start, resource_size(res)); | |
397 | if (!mipi->base) { | |
398 | ret = -ENOMEM; | |
399 | goto emap; | |
400 | } | |
401 | ||
deaba190 MD |
402 | if (!request_mem_region(res2->start, resource_size(res2), pdev->name)) { |
403 | dev_err(&pdev->dev, "MIPI register region 2 already claimed\n"); | |
404 | ret = -EBUSY; | |
405 | goto ereqreg2; | |
406 | } | |
407 | ||
408 | mipi->linkbase = ioremap(res2->start, resource_size(res2)); | |
409 | if (!mipi->linkbase) { | |
410 | ret = -ENOMEM; | |
411 | goto emap2; | |
412 | } | |
413 | ||
236782a5 GL |
414 | mipi->dev = &pdev->dev; |
415 | ||
9fd04fe3 GL |
416 | mipi->dsit_clk = clk_get(&pdev->dev, "dsit_clk"); |
417 | if (IS_ERR(mipi->dsit_clk)) { | |
418 | ret = PTR_ERR(mipi->dsit_clk); | |
419 | goto eclktget; | |
420 | } | |
421 | ||
422 | f_current = clk_get_rate(mipi->dsit_clk); | |
423 | /* 80MHz required by the datasheet */ | |
424 | rate = clk_round_rate(mipi->dsit_clk, 80000000); | |
425 | if (rate > 0 && rate != f_current) | |
426 | ret = clk_set_rate(mipi->dsit_clk, rate); | |
427 | else | |
428 | ret = rate; | |
429 | if (ret < 0) | |
430 | goto esettrate; | |
431 | ||
432 | dev_dbg(&pdev->dev, "DSI-T clk %lu -> %lu\n", f_current, rate); | |
433 | ||
9250741e | 434 | mipi->dsip_clk = clk_get(&pdev->dev, "dsip_clk"); |
9fd04fe3 GL |
435 | if (IS_ERR(mipi->dsip_clk)) { |
436 | ret = PTR_ERR(mipi->dsip_clk); | |
437 | goto eclkpget; | |
438 | } | |
439 | ||
440 | f_current = clk_get_rate(mipi->dsip_clk); | |
441 | /* Between 10 and 50MHz */ | |
442 | rate = clk_round_rate(mipi->dsip_clk, 24000000); | |
443 | if (rate > 0 && rate != f_current) | |
444 | ret = clk_set_rate(mipi->dsip_clk, rate); | |
445 | else | |
446 | ret = rate; | |
447 | if (ret < 0) | |
448 | goto esetprate; | |
449 | ||
450 | dev_dbg(&pdev->dev, "DSI-P clk %lu -> %lu\n", f_current, rate); | |
451 | ||
452 | msleep(10); | |
453 | ||
454 | ret = clk_enable(mipi->dsit_clk); | |
455 | if (ret < 0) | |
456 | goto eclkton; | |
457 | ||
458 | ret = clk_enable(mipi->dsip_clk); | |
459 | if (ret < 0) | |
460 | goto eclkpon; | |
461 | ||
462 | mipi_dsi[idx] = mipi; | |
463 | ||
236782a5 GL |
464 | pm_runtime_enable(&pdev->dev); |
465 | pm_runtime_resume(&pdev->dev); | |
466 | ||
9fd04fe3 GL |
467 | ret = sh_mipi_setup(mipi, pdata); |
468 | if (ret < 0) | |
469 | goto emipisetup; | |
470 | ||
471 | mutex_unlock(&array_lock); | |
472 | platform_set_drvdata(pdev, mipi); | |
473 | ||
6722a401 MD |
474 | /* Save original LCDC callbacks */ |
475 | mipi->next_board_data = pdata->lcd_chan->board_cfg.board_data; | |
476 | mipi->next_display_on = pdata->lcd_chan->board_cfg.display_on; | |
477 | mipi->next_display_off = pdata->lcd_chan->board_cfg.display_off; | |
478 | ||
9fd04fe3 GL |
479 | /* Set up LCDC callbacks */ |
480 | pdata->lcd_chan->board_cfg.board_data = mipi; | |
481 | pdata->lcd_chan->board_cfg.display_on = mipi_display_on; | |
482 | pdata->lcd_chan->board_cfg.display_off = mipi_display_off; | |
236782a5 | 483 | pdata->lcd_chan->board_cfg.owner = THIS_MODULE; |
9fd04fe3 GL |
484 | |
485 | return 0; | |
486 | ||
487 | emipisetup: | |
488 | mipi_dsi[idx] = NULL; | |
236782a5 | 489 | pm_runtime_disable(&pdev->dev); |
9fd04fe3 GL |
490 | clk_disable(mipi->dsip_clk); |
491 | eclkpon: | |
492 | clk_disable(mipi->dsit_clk); | |
493 | eclkton: | |
494 | esetprate: | |
495 | clk_put(mipi->dsip_clk); | |
496 | eclkpget: | |
497 | esettrate: | |
498 | clk_put(mipi->dsit_clk); | |
499 | eclktget: | |
deaba190 MD |
500 | iounmap(mipi->linkbase); |
501 | emap2: | |
502 | release_mem_region(res2->start, resource_size(res2)); | |
503 | ereqreg2: | |
9fd04fe3 GL |
504 | iounmap(mipi->base); |
505 | emap: | |
506 | release_mem_region(res->start, resource_size(res)); | |
507 | ereqreg: | |
508 | kfree(mipi); | |
509 | ealloc: | |
510 | efindslot: | |
511 | mutex_unlock(&array_lock); | |
512 | ||
513 | return ret; | |
514 | } | |
515 | ||
516 | static int __exit sh_mipi_remove(struct platform_device *pdev) | |
517 | { | |
518 | struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data; | |
519 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
deaba190 | 520 | struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
9fd04fe3 GL |
521 | struct sh_mipi *mipi = platform_get_drvdata(pdev); |
522 | int i, ret; | |
523 | ||
524 | mutex_lock(&array_lock); | |
525 | ||
526 | for (i = 0; i < ARRAY_SIZE(mipi_dsi) && mipi_dsi[i] != mipi; i++) | |
527 | ; | |
528 | ||
529 | if (i == ARRAY_SIZE(mipi_dsi)) { | |
530 | ret = -EINVAL; | |
531 | } else { | |
532 | ret = 0; | |
533 | mipi_dsi[i] = NULL; | |
534 | } | |
535 | ||
536 | mutex_unlock(&array_lock); | |
537 | ||
538 | if (ret < 0) | |
539 | return ret; | |
540 | ||
236782a5 | 541 | pdata->lcd_chan->board_cfg.owner = NULL; |
9fd04fe3 GL |
542 | pdata->lcd_chan->board_cfg.display_on = NULL; |
543 | pdata->lcd_chan->board_cfg.display_off = NULL; | |
544 | pdata->lcd_chan->board_cfg.board_data = NULL; | |
545 | ||
236782a5 | 546 | pm_runtime_disable(&pdev->dev); |
9fd04fe3 GL |
547 | clk_disable(mipi->dsip_clk); |
548 | clk_disable(mipi->dsit_clk); | |
549 | clk_put(mipi->dsit_clk); | |
550 | clk_put(mipi->dsip_clk); | |
deaba190 MD |
551 | iounmap(mipi->linkbase); |
552 | if (res2) | |
553 | release_mem_region(res2->start, resource_size(res2)); | |
9fd04fe3 GL |
554 | iounmap(mipi->base); |
555 | if (res) | |
556 | release_mem_region(res->start, resource_size(res)); | |
557 | platform_set_drvdata(pdev, NULL); | |
558 | kfree(mipi); | |
559 | ||
560 | return 0; | |
561 | } | |
562 | ||
563 | static struct platform_driver sh_mipi_driver = { | |
564 | .remove = __exit_p(sh_mipi_remove), | |
565 | .shutdown = sh_mipi_shutdown, | |
566 | .driver = { | |
567 | .name = "sh-mipi-dsi", | |
568 | }, | |
569 | }; | |
570 | ||
571 | static int __init sh_mipi_init(void) | |
572 | { | |
573 | return platform_driver_probe(&sh_mipi_driver, sh_mipi_probe); | |
574 | } | |
575 | module_init(sh_mipi_init); | |
576 | ||
577 | static void __exit sh_mipi_exit(void) | |
578 | { | |
579 | platform_driver_unregister(&sh_mipi_driver); | |
580 | } | |
581 | module_exit(sh_mipi_exit); | |
582 | ||
583 | MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>"); | |
584 | MODULE_DESCRIPTION("SuperH / ARM-shmobile MIPI DSI driver"); | |
585 | MODULE_LICENSE("GPL v2"); |