projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
fbdev: sh_mobile_lcdc: Remove fb_info parameter to display_on operation
[deliverable/linux.git] / drivers / video / sh_mobile_hdmi.c
CommitLineData
6011bdea
GL		 1/*
2 * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
3 * for SLISHDMI13T and SLIPHDMIT IP cores
4 *
5 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/clk.h>
13#include <linux/console.h>
14#include <linux/delay.h>
15#include <linux/err.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/module.h>
20#include <linux/platform_device.h>
21#include <linux/pm_runtime.h>
22#include <linux/slab.h>
23#include <linux/types.h>
24#include <linux/workqueue.h>
644a9845 25#include <sound/soc.h>
1d6be338
KM		 26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
6011bdea
GL		 28
29#include <video/sh_mobile_hdmi.h>
30#include <video/sh_mobile_lcdc.h>
31
6de9edd5
GL		 32#include "sh_mobile_lcdcfb.h"
33
6011bdea
GL		 34#define HDMI_SYSTEM_CTRL 0x00 /* System control */
35#define HDMI_L_R_DATA_SWAP_CTRL_RPKT 0x01 /* L/R data swap control,
36 bits 19..16 of 20-bit N for Audio Clock Regeneration packet */
37#define HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8 0x02 /* bits 15..8 of 20-bit N for Audio Clock Regeneration packet */
38#define HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0 0x03 /* bits 7..0 of 20-bit N for Audio Clock Regeneration packet */
39#define HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS 0x04 /* SPDIF audio sampling frequency,
40 bits 19..16 of Internal CTS */
41#define HDMI_INTERNAL_CTS_15_8 0x05 /* bits 15..8 of Internal CTS */
42#define HDMI_INTERNAL_CTS_7_0 0x06 /* bits 7..0 of Internal CTS */
43#define HDMI_EXTERNAL_CTS_19_16 0x07 /* External CTS */
44#define HDMI_EXTERNAL_CTS_15_8 0x08 /* External CTS */
45#define HDMI_EXTERNAL_CTS_7_0 0x09 /* External CTS */
46#define HDMI_AUDIO_SETTING_1 0x0A /* Audio setting.1 */
47#define HDMI_AUDIO_SETTING_2 0x0B /* Audio setting.2 */
48#define HDMI_I2S_AUDIO_SET 0x0C /* I2S audio setting */
49#define HDMI_DSD_AUDIO_SET 0x0D /* DSD audio setting */
50#define HDMI_DEBUG_MONITOR_1 0x0E /* Debug monitor.1 */
51#define HDMI_DEBUG_MONITOR_2 0x0F /* Debug monitor.2 */
52#define HDMI_I2S_INPUT_PIN_SWAP 0x10 /* I2S input pin swap */
53#define HDMI_AUDIO_STATUS_BITS_SETTING_1 0x11 /* Audio status bits setting.1 */
54#define HDMI_AUDIO_STATUS_BITS_SETTING_2 0x12 /* Audio status bits setting.2 */
55#define HDMI_CATEGORY_CODE 0x13 /* Category code */
56#define HDMI_SOURCE_NUM_AUDIO_WORD_LEN 0x14 /* Source number/Audio word length */
57#define HDMI_AUDIO_VIDEO_SETTING_1 0x15 /* Audio/Video setting.1 */
58#define HDMI_VIDEO_SETTING_1 0x16 /* Video setting.1 */
59#define HDMI_DEEP_COLOR_MODES 0x17 /* Deep Color Modes */
60
61/* 12 16- and 10-bit Color space conversion parameters: 0x18..0x2f */
62#define HDMI_COLOR_SPACE_CONVERSION_PARAMETERS 0x18
63
64#define HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS 0x30 /* External video parameter settings */
65#define HDMI_EXTERNAL_H_TOTAL_7_0 0x31 /* External horizontal total (LSB) */
66#define HDMI_EXTERNAL_H_TOTAL_11_8 0x32 /* External horizontal total (MSB) */
67#define HDMI_EXTERNAL_H_BLANK_7_0 0x33 /* External horizontal blank (LSB) */
68#define HDMI_EXTERNAL_H_BLANK_9_8 0x34 /* External horizontal blank (MSB) */
69#define HDMI_EXTERNAL_H_DELAY_7_0 0x35 /* External horizontal delay (LSB) */
70#define HDMI_EXTERNAL_H_DELAY_9_8 0x36 /* External horizontal delay (MSB) */
71#define HDMI_EXTERNAL_H_DURATION_7_0 0x37 /* External horizontal duration (LSB) */
72#define HDMI_EXTERNAL_H_DURATION_9_8 0x38 /* External horizontal duration (MSB) */
73#define HDMI_EXTERNAL_V_TOTAL_7_0 0x39 /* External vertical total (LSB) */
74#define HDMI_EXTERNAL_V_TOTAL_9_8 0x3A /* External vertical total (MSB) */
75#define HDMI_AUDIO_VIDEO_SETTING_2 0x3B /* Audio/Video setting.2 */
76#define HDMI_EXTERNAL_V_BLANK 0x3D /* External vertical blank */
77#define HDMI_EXTERNAL_V_DELAY 0x3E /* External vertical delay */
78#define HDMI_EXTERNAL_V_DURATION 0x3F /* External vertical duration */
79#define HDMI_CTRL_PKT_MANUAL_SEND_CONTROL 0x40 /* Control packet manual send control */
80#define HDMI_CTRL_PKT_AUTO_SEND 0x41 /* Control packet auto send with VSYNC control */
81#define HDMI_AUTO_CHECKSUM_OPTION 0x42 /* Auto checksum option */
82#define HDMI_VIDEO_SETTING_2 0x45 /* Video setting.2 */
83#define HDMI_OUTPUT_OPTION 0x46 /* Output option */
84#define HDMI_SLIPHDMIT_PARAM_OPTION 0x51 /* SLIPHDMIT parameter option */
85#define HDMI_HSYNC_PMENT_AT_EMB_7_0 0x52 /* HSYNC placement at embedded sync (LSB) */
86#define HDMI_HSYNC_PMENT_AT_EMB_15_8 0x53 /* HSYNC placement at embedded sync (MSB) */
87#define HDMI_VSYNC_PMENT_AT_EMB_7_0 0x54 /* VSYNC placement at embedded sync (LSB) */
88#define HDMI_VSYNC_PMENT_AT_EMB_14_8 0x55 /* VSYNC placement at embedded sync (MSB) */
89#define HDMI_SLIPHDMIT_PARAM_SETTINGS_1 0x56 /* SLIPHDMIT parameter settings.1 */
90#define HDMI_SLIPHDMIT_PARAM_SETTINGS_2 0x57 /* SLIPHDMIT parameter settings.2 */
91#define HDMI_SLIPHDMIT_PARAM_SETTINGS_3 0x58 /* SLIPHDMIT parameter settings.3 */
92#define HDMI_SLIPHDMIT_PARAM_SETTINGS_5 0x59 /* SLIPHDMIT parameter settings.5 */
93#define HDMI_SLIPHDMIT_PARAM_SETTINGS_6 0x5A /* SLIPHDMIT parameter settings.6 */
94#define HDMI_SLIPHDMIT_PARAM_SETTINGS_7 0x5B /* SLIPHDMIT parameter settings.7 */
95#define HDMI_SLIPHDMIT_PARAM_SETTINGS_8 0x5C /* SLIPHDMIT parameter settings.8 */
96#define HDMI_SLIPHDMIT_PARAM_SETTINGS_9 0x5D /* SLIPHDMIT parameter settings.9 */
97#define HDMI_SLIPHDMIT_PARAM_SETTINGS_10 0x5E /* SLIPHDMIT parameter settings.10 */
98#define HDMI_CTRL_PKT_BUF_INDEX 0x5F /* Control packet buffer index */
99#define HDMI_CTRL_PKT_BUF_ACCESS_HB0 0x60 /* Control packet data buffer access window - HB0 */
100#define HDMI_CTRL_PKT_BUF_ACCESS_HB1 0x61 /* Control packet data buffer access window - HB1 */
101#define HDMI_CTRL_PKT_BUF_ACCESS_HB2 0x62 /* Control packet data buffer access window - HB2 */
102#define HDMI_CTRL_PKT_BUF_ACCESS_PB0 0x63 /* Control packet data buffer access window - PB0 */
103#define HDMI_CTRL_PKT_BUF_ACCESS_PB1 0x64 /* Control packet data buffer access window - PB1 */
104#define HDMI_CTRL_PKT_BUF_ACCESS_PB2 0x65 /* Control packet data buffer access window - PB2 */
105#define HDMI_CTRL_PKT_BUF_ACCESS_PB3 0x66 /* Control packet data buffer access window - PB3 */
106#define HDMI_CTRL_PKT_BUF_ACCESS_PB4 0x67 /* Control packet data buffer access window - PB4 */
107#define HDMI_CTRL_PKT_BUF_ACCESS_PB5 0x68 /* Control packet data buffer access window - PB5 */
108#define HDMI_CTRL_PKT_BUF_ACCESS_PB6 0x69 /* Control packet data buffer access window - PB6 */
109#define HDMI_CTRL_PKT_BUF_ACCESS_PB7 0x6A /* Control packet data buffer access window - PB7 */
110#define HDMI_CTRL_PKT_BUF_ACCESS_PB8 0x6B /* Control packet data buffer access window - PB8 */
111#define HDMI_CTRL_PKT_BUF_ACCESS_PB9 0x6C /* Control packet data buffer access window - PB9 */
112#define HDMI_CTRL_PKT_BUF_ACCESS_PB10 0x6D /* Control packet data buffer access window - PB10 */
113#define HDMI_CTRL_PKT_BUF_ACCESS_PB11 0x6E /* Control packet data buffer access window - PB11 */
114#define HDMI_CTRL_PKT_BUF_ACCESS_PB12 0x6F /* Control packet data buffer access window - PB12 */
115#define HDMI_CTRL_PKT_BUF_ACCESS_PB13 0x70 /* Control packet data buffer access window - PB13 */
116#define HDMI_CTRL_PKT_BUF_ACCESS_PB14 0x71 /* Control packet data buffer access window - PB14 */
117#define HDMI_CTRL_PKT_BUF_ACCESS_PB15 0x72 /* Control packet data buffer access window - PB15 */
118#define HDMI_CTRL_PKT_BUF_ACCESS_PB16 0x73 /* Control packet data buffer access window - PB16 */
119#define HDMI_CTRL_PKT_BUF_ACCESS_PB17 0x74 /* Control packet data buffer access window - PB17 */
120#define HDMI_CTRL_PKT_BUF_ACCESS_PB18 0x75 /* Control packet data buffer access window - PB18 */
121#define HDMI_CTRL_PKT_BUF_ACCESS_PB19 0x76 /* Control packet data buffer access window - PB19 */
122#define HDMI_CTRL_PKT_BUF_ACCESS_PB20 0x77 /* Control packet data buffer access window - PB20 */
123#define HDMI_CTRL_PKT_BUF_ACCESS_PB21 0x78 /* Control packet data buffer access window - PB21 */
124#define HDMI_CTRL_PKT_BUF_ACCESS_PB22 0x79 /* Control packet data buffer access window - PB22 */
125#define HDMI_CTRL_PKT_BUF_ACCESS_PB23 0x7A /* Control packet data buffer access window - PB23 */
126#define HDMI_CTRL_PKT_BUF_ACCESS_PB24 0x7B /* Control packet data buffer access window - PB24 */
127#define HDMI_CTRL_PKT_BUF_ACCESS_PB25 0x7C /* Control packet data buffer access window - PB25 */
128#define HDMI_CTRL_PKT_BUF_ACCESS_PB26 0x7D /* Control packet data buffer access window - PB26 */
129#define HDMI_CTRL_PKT_BUF_ACCESS_PB27 0x7E /* Control packet data buffer access window - PB27 */
130#define HDMI_EDID_KSV_FIFO_ACCESS_WINDOW 0x80 /* EDID/KSV FIFO access window */
131#define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_7_0 0x81 /* DDC bus access frequency control (LSB) */
132#define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_15_8 0x82 /* DDC bus access frequency control (MSB) */
133#define HDMI_INTERRUPT_MASK_1 0x92 /* Interrupt mask.1 */
134#define HDMI_INTERRUPT_MASK_2 0x93 /* Interrupt mask.2 */
135#define HDMI_INTERRUPT_STATUS_1 0x94 /* Interrupt status.1 */
136#define HDMI_INTERRUPT_STATUS_2 0x95 /* Interrupt status.2 */
137#define HDMI_INTERRUPT_MASK_3 0x96 /* Interrupt mask.3 */
138#define HDMI_INTERRUPT_MASK_4 0x97 /* Interrupt mask.4 */
139#define HDMI_INTERRUPT_STATUS_3 0x98 /* Interrupt status.3 */
140#define HDMI_INTERRUPT_STATUS_4 0x99 /* Interrupt status.4 */
141#define HDMI_SOFTWARE_HDCP_CONTROL_1 0x9A /* Software HDCP control.1 */
142#define HDMI_FRAME_COUNTER 0x9C /* Frame counter */
143#define HDMI_FRAME_COUNTER_FOR_RI_CHECK 0x9D /* Frame counter for Ri check */
144#define HDMI_HDCP_CONTROL 0xAF /* HDCP control */
145#define HDMI_RI_FRAME_COUNT_REGISTER 0xB2 /* Ri frame count register */
146#define HDMI_DDC_BUS_CONTROL 0xB7 /* DDC bus control */
147#define HDMI_HDCP_STATUS 0xB8 /* HDCP status */
148#define HDMI_SHA0 0xB9 /* sha0 */
149#define HDMI_SHA1 0xBA /* sha1 */
150#define HDMI_SHA2 0xBB /* sha2 */
151#define HDMI_SHA3 0xBC /* sha3 */
152#define HDMI_SHA4 0xBD /* sha4 */
153#define HDMI_BCAPS_READ 0xBE /* BCAPS read / debug */
154#define HDMI_AKSV_BKSV_7_0_MONITOR 0xBF /* AKSV/BKSV[7:0] monitor */
155#define HDMI_AKSV_BKSV_15_8_MONITOR 0xC0 /* AKSV/BKSV[15:8] monitor */
156#define HDMI_AKSV_BKSV_23_16_MONITOR 0xC1 /* AKSV/BKSV[23:16] monitor */
157#define HDMI_AKSV_BKSV_31_24_MONITOR 0xC2 /* AKSV/BKSV[31:24] monitor */
158#define HDMI_AKSV_BKSV_39_32_MONITOR 0xC3 /* AKSV/BKSV[39:32] monitor */
159#define HDMI_EDID_SEGMENT_POINTER 0xC4 /* EDID segment pointer */
160#define HDMI_EDID_WORD_ADDRESS 0xC5 /* EDID word address */
161#define HDMI_EDID_DATA_FIFO_ADDRESS 0xC6 /* EDID data FIFO address */
162#define HDMI_NUM_OF_HDMI_DEVICES 0xC7 /* Number of HDMI devices */
163#define HDMI_HDCP_ERROR_CODE 0xC8 /* HDCP error code */
164#define HDMI_100MS_TIMER_SET 0xC9 /* 100ms timer setting */
165#define HDMI_5SEC_TIMER_SET 0xCA /* 5sec timer setting */
166#define HDMI_RI_READ_COUNT 0xCB /* Ri read count */
167#define HDMI_AN_SEED 0xCC /* An seed */
168#define HDMI_MAX_NUM_OF_RCIVRS_ALLOWED 0xCD /* Maximum number of receivers allowed */
169#define HDMI_HDCP_MEMORY_ACCESS_CONTROL_1 0xCE /* HDCP memory access control.1 */
170#define HDMI_HDCP_MEMORY_ACCESS_CONTROL_2 0xCF /* HDCP memory access control.2 */
171#define HDMI_HDCP_CONTROL_2 0xD0 /* HDCP Control 2 */
172#define HDMI_HDCP_KEY_MEMORY_CONTROL 0xD2 /* HDCP Key Memory Control */
173#define HDMI_COLOR_SPACE_CONV_CONFIG_1 0xD3 /* Color space conversion configuration.1 */
174#define HDMI_VIDEO_SETTING_3 0xD4 /* Video setting.3 */
175#define HDMI_RI_7_0 0xD5 /* Ri[7:0] */
176#define HDMI_RI_15_8 0xD6 /* Ri[15:8] */
177#define HDMI_PJ 0xD7 /* Pj */
178#define HDMI_SHA_RD 0xD8 /* sha_rd */
179#define HDMI_RI_7_0_SAVED 0xD9 /* Ri[7:0] saved */
180#define HDMI_RI_15_8_SAVED 0xDA /* Ri[15:8] saved */
181#define HDMI_PJ_SAVED 0xDB /* Pj saved */
182#define HDMI_NUM_OF_DEVICES 0xDC /* Number of devices */
183#define HDMI_HOT_PLUG_MSENS_STATUS 0xDF /* Hot plug/MSENS status */
184#define HDMI_BCAPS_WRITE 0xE0 /* bcaps */
185#define HDMI_BSTAT_7_0 0xE1 /* bstat[7:0] */
186#define HDMI_BSTAT_15_8 0xE2 /* bstat[15:8] */
187#define HDMI_BKSV_7_0 0xE3 /* bksv[7:0] */
188#define HDMI_BKSV_15_8 0xE4 /* bksv[15:8] */
189#define HDMI_BKSV_23_16 0xE5 /* bksv[23:16] */
190#define HDMI_BKSV_31_24 0xE6 /* bksv[31:24] */
191#define HDMI_BKSV_39_32 0xE7 /* bksv[39:32] */
192#define HDMI_AN_7_0 0xE8 /* An[7:0] */
193#define HDMI_AN_15_8 0xE9 /* An [15:8] */
194#define HDMI_AN_23_16 0xEA /* An [23:16] */
195#define HDMI_AN_31_24 0xEB /* An [31:24] */
196#define HDMI_AN_39_32 0xEC /* An [39:32] */
197#define HDMI_AN_47_40 0xED /* An [47:40] */
198#define HDMI_AN_55_48 0xEE /* An [55:48] */
199#define HDMI_AN_63_56 0xEF /* An [63:56] */
200#define HDMI_PRODUCT_ID 0xF0 /* Product ID */
201#define HDMI_REVISION_ID 0xF1 /* Revision ID */
202#define HDMI_TEST_MODE 0xFE /* Test mode */
203
204enum hotplug_state {
205 HDMI_HOTPLUG_DISCONNECTED,
206 HDMI_HOTPLUG_CONNECTED,
207 HDMI_HOTPLUG_EDID_DONE,
208};
209
210struct sh_hdmi {
8511ea4a
LP		 211 struct sh_mobile_lcdc_entity entity;
212
6011bdea 213 void __iomem *base;
6aa966e6 214 enum hotplug_state hp_state; /* hot-plug status */
0ea2af1c
GL		 215 u8 preprogrammed_vic; /* use a pre-programmed VIC or
216 the external mode */
4232f607
GL		 217 u8 edid_block_addr;
218 u8 edid_segment_nr;
219 u8 edid_blocks;
6011bdea
GL		 220 struct clk *hdmi_clk;
221 struct device *dev;
6011bdea
GL		 222 struct delayed_work edid_work;
223 struct fb_var_screeninfo var;
afe417c0 224 struct fb_monspecs monspec;
6011bdea
GL		 225};
226
8511ea4a 227#define entity_to_sh_hdmi(e) container_of(e, struct sh_hdmi, entity)
12ee2502 228
6011bdea
GL		 229static void hdmi_write(struct sh_hdmi *hdmi, u8 data, u8 reg)
230{
231 iowrite8(data, hdmi->base + reg);
232}
233
234static u8 hdmi_read(struct sh_hdmi *hdmi, u8 reg)
235{
236 return ioread8(hdmi->base + reg);
237}
238
f4363b7d
KM		 239/*
240 * HDMI sound
241 */
1d6be338
KM		 242static unsigned int sh_hdmi_snd_read(struct snd_soc_codec *codec,
243 unsigned int reg)
244{
245 struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec);
246
247 return hdmi_read(hdmi, reg);
248}
249
250static int sh_hdmi_snd_write(struct snd_soc_codec *codec,
251 unsigned int reg,
252 unsigned int value)
253{
254 struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec);
255
256 hdmi_write(hdmi, value, reg);
257 return 0;
258}
259
260static struct snd_soc_dai_driver sh_hdmi_dai = {
261 .name = "sh_mobile_hdmi-hifi",
262 .playback = {
263 .stream_name = "Playback",
17731f8d
KM		 264 .channels_min = 2,
265 .channels_max = 8,
266 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
267 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
268 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
269 SNDRV_PCM_RATE_192000,
1d6be338
KM		 270 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
271 },
272};
273
274static int sh_hdmi_snd_probe(struct snd_soc_codec *codec)
275{
276 dev_info(codec->dev, "SH Mobile HDMI Audio Codec");
277
278 return 0;
279}
280
281static struct snd_soc_codec_driver soc_codec_dev_sh_hdmi = {
282 .probe = sh_hdmi_snd_probe,
283 .read = sh_hdmi_snd_read,
284 .write = sh_hdmi_snd_write,
285};
286
f4363b7d
KM		 287/*
288 * HDMI video
289 */
1d6be338 290
6011bdea 291/* External video parameter settings */
6aa966e6 292static void sh_hdmi_external_video_param(struct sh_hdmi *hdmi)
6011bdea
GL		 293{
294 struct fb_var_screeninfo *var = &hdmi->var;
295 u16 htotal, hblank, hdelay, vtotal, vblank, vdelay, voffset;
296 u8 sync = 0;
297
298 htotal = var->xres + var->right_margin + var->left_margin + var->hsync_len;
299
300 hdelay = var->hsync_len + var->left_margin;
301 hblank = var->right_margin + hdelay;
302
303 /*
304 * Vertical timing looks a bit different in Figure 18,
305 * but let's try the same first by setting offset = 0
306 */
307 vtotal = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
308
309 vdelay = var->vsync_len + var->upper_margin;
310 vblank = var->lower_margin + vdelay;
311 voffset = min(var->upper_margin / 2, 6U);
312
313 /*
314 * [3]: VSYNC polarity: Positive
315 * [2]: HSYNC polarity: Positive
316 * [1]: Interlace/Progressive: Progressive
317 * [0]: External video settings enable: used.
318 */
319 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
320 sync |= 4;
321 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
322 sync |= 8;
323
6aa966e6
GL		 324 dev_dbg(hdmi->dev, "H: %u, %u, %u, %u; V: %u, %u, %u, %u; sync 0x%x\n",
325 htotal, hblank, hdelay, var->hsync_len,
326 vtotal, vblank, vdelay, var->vsync_len, sync);
6011bdea
GL		 327
328 hdmi_write(hdmi, sync | (voffset << 4), HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
329
330 hdmi_write(hdmi, htotal, HDMI_EXTERNAL_H_TOTAL_7_0);
331 hdmi_write(hdmi, htotal >> 8, HDMI_EXTERNAL_H_TOTAL_11_8);
332
333 hdmi_write(hdmi, hblank, HDMI_EXTERNAL_H_BLANK_7_0);
334 hdmi_write(hdmi, hblank >> 8, HDMI_EXTERNAL_H_BLANK_9_8);
335
336 hdmi_write(hdmi, hdelay, HDMI_EXTERNAL_H_DELAY_7_0);
337 hdmi_write(hdmi, hdelay >> 8, HDMI_EXTERNAL_H_DELAY_9_8);
338
339 hdmi_write(hdmi, var->hsync_len, HDMI_EXTERNAL_H_DURATION_7_0);
340 hdmi_write(hdmi, var->hsync_len >> 8, HDMI_EXTERNAL_H_DURATION_9_8);
341
342 hdmi_write(hdmi, vtotal, HDMI_EXTERNAL_V_TOTAL_7_0);
343 hdmi_write(hdmi, vtotal >> 8, HDMI_EXTERNAL_V_TOTAL_9_8);
344
345 hdmi_write(hdmi, vblank, HDMI_EXTERNAL_V_BLANK);
346
347 hdmi_write(hdmi, vdelay, HDMI_EXTERNAL_V_DELAY);
348
349 hdmi_write(hdmi, var->vsync_len, HDMI_EXTERNAL_V_DURATION);
350
89712699 351 /* Set bit 0 of HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS here for external mode */
0ea2af1c 352 if (!hdmi->preprogrammed_vic)
89712699
GL		 353 hdmi_write(hdmi, sync | 1 | (voffset << 4),
354 HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
6011bdea
GL		 355}
356
357/**
358 * sh_hdmi_video_config()
359 */
360static void sh_hdmi_video_config(struct sh_hdmi *hdmi)
361{
362 /*
363 * [7:4]: Audio sampling frequency: 48kHz
364 * [3:1]: Input video format: RGB and YCbCr 4:4:4 (Y on Green)
365 * [0]: Internal/External DE select: internal
366 */
367 hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
368
369 /*
370 * [7:6]: Video output format: RGB 4:4:4
371 * [5:4]: Input video data width: 8 bit
372 * [3:1]: EAV/SAV location: channel 1
373 * [0]: Video input color space: RGB
374 */
375 hdmi_write(hdmi, 0x34, HDMI_VIDEO_SETTING_1);
376
377 /*
378 * [7:6]: Together with bit [6] of HDMI_AUDIO_VIDEO_SETTING_2, which is
379 * left at 0 by default, this configures 24bpp and sets the Color Depth
380 * (CD) field in the General Control Packet
381 */
382 hdmi_write(hdmi, 0x20, HDMI_DEEP_COLOR_MODES);
383}
384
385/**
386 * sh_hdmi_audio_config()
387 */
388static void sh_hdmi_audio_config(struct sh_hdmi *hdmi)
389{
6d865771
KM		 390 u8 data;
391 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
392
6011bdea
GL		 393 /*
394 * [7:4] L/R data swap control
395 * [3:0] appropriate N[19:16]
396 */
397 hdmi_write(hdmi, 0x00, HDMI_L_R_DATA_SWAP_CTRL_RPKT);
398 /* appropriate N[15:8] */
399 hdmi_write(hdmi, 0x18, HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8);
400 /* appropriate N[7:0] */
401 hdmi_write(hdmi, 0x00, HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0);
402
403 /* [7:4] 48 kHz SPDIF not used */
404 hdmi_write(hdmi, 0x20, HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS);
405
406 /*
407 * [6:5] set required down sampling rate if required
408 * [4:3] set required audio source
409 */
dec6aa49 410 switch (pdata->flags & HDMI_SND_SRC_MASK) {
6d865771 411 default:
f4363b7d 412 /* fall through */
dec6aa49
KM		 413 case HDMI_SND_SRC_I2S:
414 data = 0x0 << 3;
6d865771 415 break;
dec6aa49
KM		 416 case HDMI_SND_SRC_SPDIF:
417 data = 0x1 << 3;
6d865771 418 break;
dec6aa49
KM		 419 case HDMI_SND_SRC_DSD:
420 data = 0x2 << 3;
6d865771 421 break;
dec6aa49
KM		 422 case HDMI_SND_SRC_HBR:
423 data = 0x3 << 3;
6d865771
KM		 424 break;
425 }
426 hdmi_write(hdmi, data, HDMI_AUDIO_SETTING_1);
6011bdea
GL		 427
428 /* [3:0] set sending channel number for channel status */
429 hdmi_write(hdmi, 0x40, HDMI_AUDIO_SETTING_2);
430
431 /*
432 * [5:2] set valid I2S source input pin
433 * [1:0] set input I2S source mode
434 */
435 hdmi_write(hdmi, 0x04, HDMI_I2S_AUDIO_SET);
436
437 /* [7:4] set valid DSD source input pin */
438 hdmi_write(hdmi, 0x00, HDMI_DSD_AUDIO_SET);
439
440 /* [7:0] set appropriate I2S input pin swap settings if required */
441 hdmi_write(hdmi, 0x00, HDMI_I2S_INPUT_PIN_SWAP);
442
443 /*
444 * [7] set validity bit for channel status
445 * [3:0] set original sample frequency for channel status
446 */
447 hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_1);
448
449 /*
450 * [7] set value for channel status
451 * [6] set value for channel status
452 * [5] set copyright bit for channel status
453 * [4:2] set additional information for channel status
454 * [1:0] set clock accuracy for channel status
455 */
456 hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_2);
457
458 /* [7:0] set category code for channel status */
459 hdmi_write(hdmi, 0x00, HDMI_CATEGORY_CODE);
460
461 /*
462 * [7:4] set source number for channel status
463 * [3:0] set word length for channel status
464 */
465 hdmi_write(hdmi, 0x00, HDMI_SOURCE_NUM_AUDIO_WORD_LEN);
466
467 /* [7:4] set sample frequency for channel status */
468 hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
469}
470
471/**
6e45746c 472 * sh_hdmi_phy_config() - configure the HDMI PHY for the used video mode
6011bdea
GL		 473 */
474static void sh_hdmi_phy_config(struct sh_hdmi *hdmi)
475{
0ea2af1c
GL		 476 if (hdmi->var.pixclock < 10000) {
477 /* for 1080p8bit 148MHz */
478 hdmi_write(hdmi, 0x1d, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
479 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
480 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
481 hdmi_write(hdmi, 0x4c, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
482 hdmi_write(hdmi, 0x1e, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
483 hdmi_write(hdmi, 0x48, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
484 hdmi_write(hdmi, 0x0e, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
485 hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
486 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
487 } else if (hdmi->var.pixclock < 30000) {
6e45746c
GL		 488 /* 720p, 8bit, 74.25MHz. Might need to be adjusted for other formats */
489 /*
490 * [1:0] Speed_A
491 * [3:2] Speed_B
492 * [4] PLLA_Bypass
493 * [6] DRV_TEST_EN
494 * [7] DRV_TEST_IN
495 */
9289c475 496 hdmi_write(hdmi, 0x0f, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
6e45746c
GL		 497 /* PLLB_CONFIG[17], PLLA_CONFIG[17] - not in PHY datasheet */
498 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
499 /*
500 * [2:0] BGR_I_OFFSET
501 * [6:4] BGR_V_OFFSET
502 */
503 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
504 /* PLLA_CONFIG[7:0]: VCO gain, VCO offset, LPF resistance[0] */
505 hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
506 /*
507 * PLLA_CONFIG[15:8]: regulator voltage[0], CP current,
508 * LPF capacitance, LPF resistance[1]
509 */
510 hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
511 /* PLLB_CONFIG[7:0]: LPF resistance[0], VCO offset, VCO gain */
512 hdmi_write(hdmi, 0x4A, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
513 /*
514 * PLLB_CONFIG[15:8]: regulator voltage[0], CP current,
515 * LPF capacitance, LPF resistance[1]
516 */
9289c475 517 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
6e45746c
GL		 518 /* DRV_CONFIG, PE_CONFIG */
519 hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
520 /*
521 * [2:0] AMON_SEL (4 == LPF voltage)
522 * [4] PLLA_CONFIG[16]
523 * [5] PLLB_CONFIG[16]
524 */
525 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
526 } else {
527 /* for 480p8bit 27MHz */
528 hdmi_write(hdmi, 0x19, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
529 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
530 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
531 hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
532 hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
533 hdmi_write(hdmi, 0x48, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
534 hdmi_write(hdmi, 0x0F, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
535 hdmi_write(hdmi, 0x20, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
536 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
537 }
6011bdea
GL		 538}
539
540/**
541 * sh_hdmi_avi_infoframe_setup() - Auxiliary Video Information InfoFrame CONTROL PACKET
542 */
543static void sh_hdmi_avi_infoframe_setup(struct sh_hdmi *hdmi)
544{
6e45746c
GL		 545 u8 vic;
546
6011bdea
GL		 547 /* AVI InfoFrame */
548 hdmi_write(hdmi, 0x06, HDMI_CTRL_PKT_BUF_INDEX);
549
550 /* Packet Type = 0x82 */
551 hdmi_write(hdmi, 0x82, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
552
553 /* Version = 0x02 */
554 hdmi_write(hdmi, 0x02, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
555
556 /* Length = 13 (0x0D) */
557 hdmi_write(hdmi, 0x0D, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
558
559 /* N. A. Checksum */
560 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
561
562 /*
563 * Y = RGB
564 * A0 = No Data
565 * B = Bar Data not valid
566 * S = No Data
567 */
568 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
569
570 /*
6aa966e6
GL		 571 * [7:6] C = Colorimetry: no data
572 * [5:4] M = 2: 16:9, 1: 4:3 Picture Aspect Ratio
573 * [3:0] R = 8: Active Frame Aspect Ratio: same as picture aspect ratio
6011bdea
GL		 574 */
575 hdmi_write(hdmi, 0x28, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
576
577 /*
578 * ITC = No Data
579 * EC = xvYCC601
580 * Q = Default (depends on video format)
581 * SC = No Known non_uniform Scaling
582 */
583 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
584
585 /*
0ea2af1c
GL		 586 * VIC should be ignored if external config is used, so, we could just use 0,
587 * but play safe and use a valid value in any case just in case
6011bdea 588 */
0ea2af1c
GL		 589 if (hdmi->preprogrammed_vic)
590 vic = hdmi->preprogrammed_vic;
6e45746c
GL		 591 else
592 vic = 4;
593 hdmi_write(hdmi, vic, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
6011bdea
GL		 594
595 /* PR = No Repetition */
596 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
597
598 /* Line Number of End of Top Bar (lower 8 bits) */
599 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
600
601 /* Line Number of End of Top Bar (upper 8 bits) */
602 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
603
604 /* Line Number of Start of Bottom Bar (lower 8 bits) */
605 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
606
607 /* Line Number of Start of Bottom Bar (upper 8 bits) */
608 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
609
610 /* Pixel Number of End of Left Bar (lower 8 bits) */
611 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
612
613 /* Pixel Number of End of Left Bar (upper 8 bits) */
614 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB11);
615
616 /* Pixel Number of Start of Right Bar (lower 8 bits) */
617 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB12);
618
619 /* Pixel Number of Start of Right Bar (upper 8 bits) */
620 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB13);
621}
622
623/**
624 * sh_hdmi_audio_infoframe_setup() - Audio InfoFrame of CONTROL PACKET
625 */
626static void sh_hdmi_audio_infoframe_setup(struct sh_hdmi *hdmi)
627{
628 /* Audio InfoFrame */
629 hdmi_write(hdmi, 0x08, HDMI_CTRL_PKT_BUF_INDEX);
630
631 /* Packet Type = 0x84 */
632 hdmi_write(hdmi, 0x84, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
633
634 /* Version Number = 0x01 */
635 hdmi_write(hdmi, 0x01, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
636
637 /* 0 Length = 10 (0x0A) */
638 hdmi_write(hdmi, 0x0A, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
639
640 /* n. a. Checksum */
641 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
642
643 /* Audio Channel Count = Refer to Stream Header */
644 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
645
646 /* Refer to Stream Header */
647 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
648
649 /* Format depends on coding type (i.e. CT0...CT3) */
650 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
651
652 /* Speaker Channel Allocation = Front Right + Front Left */
653 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
654
655 /* Level Shift Value = 0 dB, Down - mix is permitted or no information */
656 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
657
658 /* Reserved (0) */
659 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
660 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
661 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
662 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
663 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
664}
665
6011bdea
GL		 666/**
667 * sh_hdmi_configure() - Initialise HDMI for output
668 */
669static void sh_hdmi_configure(struct sh_hdmi *hdmi)
670{
671 /* Configure video format */
672 sh_hdmi_video_config(hdmi);
673
674 /* Configure audio format */
675 sh_hdmi_audio_config(hdmi);
676
677 /* Configure PHY */
678 sh_hdmi_phy_config(hdmi);
679
680 /* Auxiliary Video Information (AVI) InfoFrame */
681 sh_hdmi_avi_infoframe_setup(hdmi);
682
683 /* Audio InfoFrame */
684 sh_hdmi_audio_infoframe_setup(hdmi);
685
6011bdea
GL		 686 /*
687 * Control packet auto send with VSYNC control: auto send
688 * General control, Gamut metadata, ISRC, and ACP packets
689 */
690 hdmi_write(hdmi, 0x8E, HDMI_CTRL_PKT_AUTO_SEND);
691
692 /* FIXME */
693 msleep(10);
694
695 /* PS mode b->d, reset PLLA and PLLB */
696 hdmi_write(hdmi, 0x4C, HDMI_SYSTEM_CTRL);
697
698 udelay(10);
699
700 hdmi_write(hdmi, 0x40, HDMI_SYSTEM_CTRL);
701}
702
f1198d1e 703static unsigned long sh_hdmi_rate_error(struct sh_hdmi *hdmi,
c36940e6
GL		 704 const struct fb_videomode *mode,
705 unsigned long *hdmi_rate, unsigned long *parent_rate)
6011bdea 706{
c36940e6
GL		 707 unsigned long target = PICOS2KHZ(mode->pixclock) * 1000, rate_error;
708 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
709
710 *hdmi_rate = clk_round_rate(hdmi->hdmi_clk, target);
711 if ((long)*hdmi_rate < 0)
712 *hdmi_rate = clk_get_rate(hdmi->hdmi_clk);
713
714 rate_error = (long)*hdmi_rate > 0 ? abs(*hdmi_rate - target) : ULONG_MAX;
715 if (rate_error && pdata->clk_optimize_parent)
716 rate_error = pdata->clk_optimize_parent(target, hdmi_rate, parent_rate);
717 else if (clk_get_parent(hdmi->hdmi_clk))
718 *parent_rate = clk_get_rate(clk_get_parent(hdmi->hdmi_clk));
f1198d1e
GL		 719
720 dev_dbg(hdmi->dev, "%u-%u-%u-%u x %u-%u-%u-%u\n",
721 mode->left_margin, mode->xres,
722 mode->right_margin, mode->hsync_len,
723 mode->upper_margin, mode->yres,
724 mode->lower_margin, mode->vsync_len);
725
c36940e6
GL		 726 dev_dbg(hdmi->dev, "\t@%lu(+/-%lu)Hz, e=%lu / 1000, r=%uHz, p=%luHz\n", target,
727 rate_error, rate_error ? 10000 / (10 * target / rate_error) : 0,
728 mode->refresh, *parent_rate);
f1198d1e
GL		 729
730 return rate_error;
731}
732
c36940e6
GL		 733static int sh_hdmi_read_edid(struct sh_hdmi *hdmi, unsigned long *hdmi_rate,
734 unsigned long *parent_rate)
6011bdea 735{
bce95fe8
LP		 736 struct fb_info *info = hdmi->entity.lcdc
737 ? hdmi->entity.lcdc->info : NULL;
6ee48452 738 struct fb_var_screeninfo tmpvar;
6ee48452 739 struct fb_var_screeninfo *var = &tmpvar;
afe417c0 740 const struct fb_videomode *mode, *found = NULL;
f1198d1e
GL		 741 struct fb_modelist *modelist = NULL;
742 unsigned int f_width = 0, f_height = 0, f_refresh = 0;
743 unsigned long found_rate_error = ULONG_MAX; /* silly compiler... */
c7321d6f 744 bool scanning = false, preferred_bad = false;
6011bdea 745 u8 edid[128];
f1198d1e
GL		 746 char *forced;
747 int i;
6011bdea
GL		 748
749 /* Read EDID */
6aa966e6 750 dev_dbg(hdmi->dev, "Read back EDID code:");
6011bdea
GL		 751 for (i = 0; i < 128; i++) {
752 edid[i] = hdmi_read(hdmi, HDMI_EDID_KSV_FIFO_ACCESS_WINDOW);
753#ifdef DEBUG
754 if ((i % 16) == 0) {
755 printk(KERN_CONT "\n");
756 printk(KERN_DEBUG "%02X | %02X", i, edid[i]);
757 } else {
758 printk(KERN_CONT " %02X", edid[i]);
759 }
760#endif
761 }
762#ifdef DEBUG
763 printk(KERN_CONT "\n");
764#endif
afe417c0 765
4232f607
GL		 766 if (!hdmi->edid_blocks) {
767 fb_edid_to_monspecs(edid, &hdmi->monspec);
768 hdmi->edid_blocks = edid[126] + 1;
769
770 dev_dbg(hdmi->dev, "%d main modes, %d extension blocks\n",
771 hdmi->monspec.modedb_len, hdmi->edid_blocks - 1);
772 } else {
773 dev_dbg(hdmi->dev, "Extension %u detected, DTD start %u\n",
774 edid[0], edid[2]);
775 fb_edid_add_monspecs(edid, &hdmi->monspec);
776 }
777
778 if (hdmi->edid_blocks > hdmi->edid_segment_nr * 2 +
779 (hdmi->edid_block_addr >> 7) + 1) {
780 /* More blocks to read */
781 if (hdmi->edid_block_addr) {
782 hdmi->edid_block_addr = 0;
783 hdmi->edid_segment_nr++;
784 } else {
785 hdmi->edid_block_addr = 0x80;
786 }
787 /* Set EDID word address */
788 hdmi_write(hdmi, hdmi->edid_block_addr, HDMI_EDID_WORD_ADDRESS);
789 /* Enable EDID interrupt */
790 hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
791 /* Set EDID segment pointer - starts reading EDID */
792 hdmi_write(hdmi, hdmi->edid_segment_nr, HDMI_EDID_SEGMENT_POINTER);
793 return -EAGAIN;
794 }
795
796 /* All E-EDID blocks ready */
797 dev_dbg(hdmi->dev, "%d main and extended modes\n", hdmi->monspec.modedb_len);
afe417c0 798
f1198d1e
GL		 799 fb_get_options("sh_mobile_lcdc", &forced);
800 if (forced && *forced) {
801 /* Only primitive parsing so far */
802 i = sscanf(forced, "%ux%u@%u",
803 &f_width, &f_height, &f_refresh);
804 if (i < 2) {
805 f_width = 0;
806 f_height = 0;
c7321d6f
GL		 807 } else {
808 /* The user wants us to use the EDID data */
809 scanning = true;
f1198d1e
GL		 810 }
811 dev_dbg(hdmi->dev, "Forced mode %ux%u@%uHz\n",
812 f_width, f_height, f_refresh);
813 }
814
815 /* Walk monitor modes to find the best or the exact match */
816 for (i = 0, mode = hdmi->monspec.modedb;
c7321d6f 817 i < hdmi->monspec.modedb_len && scanning;
afe417c0 818 i++, mode++) {
c36940e6 819 unsigned long rate_error;
f1198d1e 820
c7321d6f
GL		 821 if (!f_width && !f_height) {
822 /*
823 * A parameter string "video=sh_mobile_lcdc:0x0" means
824 * use the preferred EDID mode. If it is rejected by
825 * .fb_check_var(), keep looking, until an acceptable
826 * one is found.
827 */
828 if ((mode->flag & FB_MODE_IS_FIRST) || preferred_bad)
829 scanning = false;
830 else
831 continue;
832 } else if (f_width != mode->xres || f_height != mode->yres) {
833 /* No interest in unmatching modes */
f1198d1e 834 continue;
c7321d6f 835 }
c36940e6
GL		 836
837 rate_error = sh_hdmi_rate_error(hdmi, mode, hdmi_rate, parent_rate);
838
c7321d6f
GL		 839 if (scanning) {
840 if (f_refresh == mode->refresh || (!f_refresh && !rate_error))
841 /*
842 * Exact match if either the refresh rate
843 * matches or it hasn't been specified and we've
844 * found a mode, for which we can configure the
845 * clock precisely
846 */
847 scanning = false;
848 else if (found && found_rate_error <= rate_error)
849 /*
850 * We otherwise search for the closest matching
851 * clock rate - either if no refresh rate has
852 * been specified or we cannot find an exactly
853 * matching one
854 */
855 continue;
856 }
f1198d1e
GL		 857
858 /* Check if supported: sufficient fb memory, supported clock-rate */
859 fb_videomode_to_var(var, mode);
860
c7321d6f
GL		 861 var->bits_per_pixel = info->var.bits_per_pixel;
862
f1198d1e
GL		 863 if (info && info->fbops->fb_check_var &&
864 info->fbops->fb_check_var(var, info)) {
c7321d6f
GL		 865 scanning = true;
866 preferred_bad = true;
f1198d1e 867 continue;
afe417c0 868 }
f1198d1e
GL		 869
870 found = mode;
871 found_rate_error = rate_error;
afe417c0
GL		 872 }
873
8c1ac08b
GL		 874 hdmi->var.width = hdmi->monspec.max_x * 10;
875 hdmi->var.height = hdmi->monspec.max_y * 10;
876
afe417c0 877 /*
f1198d1e
GL		 878 * TODO 1: if no ->info is present, postpone running the config until
879 * after ->info first gets registered.
880 * TODO 2: consider registering the HDMI platform device from the LCDC
881 * driver, and passing ->info with HDMI platform data.
afe417c0 882 */
f1198d1e 883 if (info && !found) {
0d7fa180
GL		 884 modelist = info->modelist.next &&
885 !list_empty(&info->modelist) ?
886 list_entry(info->modelist.next,
f1198d1e
GL		 887 struct fb_modelist, list) :
888 NULL;
889
890 if (modelist) {
891 found = &modelist->mode;
c36940e6 892 found_rate_error = sh_hdmi_rate_error(hdmi, found, hdmi_rate, parent_rate);
afe417c0
GL		 893 }
894 }
895
afe417c0
GL		 896 /* No cookie today */
897 if (!found)
898 return -ENXIO;
899
0ea2af1c
GL		 900 if (found->xres == 640 && found->yres == 480 && found->refresh == 60)
901 hdmi->preprogrammed_vic = 1;
902 else if (found->xres == 720 && found->yres == 480 && found->refresh == 60)
903 hdmi->preprogrammed_vic = 2;
904 else if (found->xres == 720 && found->yres == 576 && found->refresh == 50)
905 hdmi->preprogrammed_vic = 17;
906 else if (found->xres == 1280 && found->yres == 720 && found->refresh == 60)
907 hdmi->preprogrammed_vic = 4;
908 else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 24)
909 hdmi->preprogrammed_vic = 32;
910 else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 50)
911 hdmi->preprogrammed_vic = 31;
912 else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 60)
913 hdmi->preprogrammed_vic = 16;
89712699 914 else
0ea2af1c 915 hdmi->preprogrammed_vic = 0;
89712699 916
c36940e6 917 dev_dbg(hdmi->dev, "Using %s %s mode %ux%u@%uHz (%luHz), clock error %luHz\n",
0ea2af1c 918 modelist ? "default" : "EDID", hdmi->preprogrammed_vic ? "VIC" : "external",
c36940e6
GL		 919 found->xres, found->yres, found->refresh,
920 PICOS2KHZ(found->pixclock) * 1000, found_rate_error);
921
afe417c0 922 fb_videomode_to_var(&hdmi->var, found);
6aa966e6 923 sh_hdmi_external_video_param(hdmi);
afe417c0
GL		 924
925 return 0;
6011bdea
GL		 926}
927
928static irqreturn_t sh_hdmi_hotplug(int irq, void *dev_id)
929{
930 struct sh_hdmi *hdmi = dev_id;
931 u8 status1, status2, mask1, mask2;
932
933 /* mode_b and PLLA and PLLB reset */
934 hdmi_write(hdmi, 0x2C, HDMI_SYSTEM_CTRL);
935
936 /* How long shall reset be held? */
937 udelay(10);
938
939 /* mode_b and PLLA and PLLB reset release */
940 hdmi_write(hdmi, 0x20, HDMI_SYSTEM_CTRL);
941
942 status1 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_1);
943 status2 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_2);
944
945 mask1 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_1);
946 mask2 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_2);
947
948 /* Correct would be to ack only set bits, but the datasheet requires 0xff */
949 hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_1);
950 hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_2);
951
952 if (printk_ratelimit())
6aa966e6
GL		 953 dev_dbg(hdmi->dev, "IRQ #%d: Status #1: 0x%x & 0x%x, #2: 0x%x & 0x%x\n",
954 irq, status1, mask1, status2, mask2);
6011bdea
GL		 955
956 if (!((status1 & mask1) | (status2 & mask2))) {
957 return IRQ_NONE;
958 } else if (status1 & 0xc0) {
959 u8 msens;
960
961 /* Datasheet specifies 10ms... */
962 udelay(500);
963
964 msens = hdmi_read(hdmi, HDMI_HOT_PLUG_MSENS_STATUS);
6aa966e6 965 dev_dbg(hdmi->dev, "MSENS 0x%x\n", msens);
6011bdea
GL		 966 /* Check, if hot plug & MSENS pin status are both high */
967 if ((msens & 0xC0) == 0xC0) {
968 /* Display plug in */
4232f607
GL		 969 hdmi->edid_segment_nr = 0;
970 hdmi->edid_block_addr = 0;
971 hdmi->edid_blocks = 0;
6011bdea
GL		 972 hdmi->hp_state = HDMI_HOTPLUG_CONNECTED;
973
974 /* Set EDID word address */
975 hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
6011bdea
GL		 976 /* Enable EDID interrupt */
977 hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
4232f607
GL		 978 /* Set EDID segment pointer - starts reading EDID */
979 hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
6011bdea
GL		 980 } else if (!(status1 & 0x80)) {
981 /* Display unplug, beware multiple interrupts */
4232f607
GL		 982 if (hdmi->hp_state != HDMI_HOTPLUG_DISCONNECTED) {
983 hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
6011bdea 984 schedule_delayed_work(&hdmi->edid_work, 0);
4232f607 985 }
6011bdea
GL		 986 /* display_off will switch back to mode_a */
987 }
988 } else if (status1 & 2) {
989 /* EDID error interrupt: retry */
990 /* Set EDID word address */
4232f607 991 hdmi_write(hdmi, hdmi->edid_block_addr, HDMI_EDID_WORD_ADDRESS);
6011bdea 992 /* Set EDID segment pointer */
4232f607 993 hdmi_write(hdmi, hdmi->edid_segment_nr, HDMI_EDID_SEGMENT_POINTER);
6011bdea
GL		 994 } else if (status1 & 4) {
995 /* Disable EDID interrupt */
996 hdmi_write(hdmi, 0xC0, HDMI_INTERRUPT_MASK_1);
6011bdea
GL		 997 schedule_delayed_work(&hdmi->edid_work, msecs_to_jiffies(10));
998 }
999
1000 return IRQ_HANDLED;
1001}
1002
5864ace1 1003static int sh_hdmi_display_on(struct sh_mobile_lcdc_entity *entity)
6011bdea 1004{
8511ea4a 1005 struct sh_hdmi *hdmi = entity_to_sh_hdmi(entity);
bce95fe8 1006 struct sh_mobile_lcdc_chan *ch = entity->lcdc;
5864ace1 1007 struct fb_info *info = ch->info;
6011bdea 1008
134d22eb 1009 dev_dbg(hdmi->dev, "%s(%p): state %x\n", __func__, hdmi, info->state);
6de9edd5 1010
6011bdea 1011 /*
6aa966e6
GL		 1012 * hp_state can be set to
1013 * HDMI_HOTPLUG_DISCONNECTED: on monitor unplug
1014 * HDMI_HOTPLUG_CONNECTED: on monitor plug-in
1015 * HDMI_HOTPLUG_EDID_DONE: on EDID read completion
6011bdea 1016 */
6011bdea
GL		 1017 switch (hdmi->hp_state) {
1018 case HDMI_HOTPLUG_EDID_DONE:
1019 /* PS mode d->e. All functions are active */
1020 hdmi_write(hdmi, 0x80, HDMI_SYSTEM_CTRL);
6aa966e6 1021 dev_dbg(hdmi->dev, "HDMI running\n");
6011bdea
GL		 1022 break;
1023 case HDMI_HOTPLUG_DISCONNECTED:
1024 info->state = FBINFO_STATE_SUSPENDED;
1025 default:
1c120deb 1026 hdmi->var = ch->display_var;
6011bdea 1027 }
8511ea4a
LP		 1028
1029 return 0;
1030}
1031
db85905a 1032static void sh_hdmi_display_off(struct sh_mobile_lcdc_entity *entity)
6011bdea 1033{
8511ea4a 1034 struct sh_hdmi *hdmi = entity_to_sh_hdmi(entity);
6011bdea 1035
134d22eb 1036 dev_dbg(hdmi->dev, "%s(%p)\n", __func__, hdmi);
6011bdea
GL		 1037 /* PS mode e->a */
1038 hdmi_write(hdmi, 0x10, HDMI_SYSTEM_CTRL);
1039}
1040
8511ea4a 1041static const struct sh_mobile_lcdc_entity_ops sh_hdmi_ops = {
db85905a
LP		 1042 .display_on = sh_hdmi_display_on,
1043 .display_off = sh_hdmi_display_off,
8511ea4a
LP		 1044};
1045
afe417c0
GL		 1046static bool sh_hdmi_must_reconfigure(struct sh_hdmi *hdmi)
1047{
bce95fe8 1048 struct sh_mobile_lcdc_chan *ch = hdmi->entity.lcdc;
afe417c0
GL		 1049 struct fb_var_screeninfo *new_var = &hdmi->var, *old_var = &ch->display_var;
1050 struct fb_videomode mode1, mode2;
1051
1052 fb_var_to_videomode(&mode1, old_var);
1053 fb_var_to_videomode(&mode2, new_var);
1054
bce95fe8 1055 dev_dbg(hdmi->dev, "Old %ux%u, new %ux%u\n",
afe417c0
GL		 1056 mode1.xres, mode1.yres, mode2.xres, mode2.yres);
1057
8c1ac08b
GL		 1058 if (fb_mode_is_equal(&mode1, &mode2)) {
1059 /* It can be a different monitor with an equal video-mode */
1060 old_var->width = new_var->width;
1061 old_var->height = new_var->height;
afe417c0 1062 return false;
8c1ac08b 1063 }
afe417c0 1064
bce95fe8 1065 dev_dbg(hdmi->dev, "Switching %u -> %u lines\n",
afe417c0
GL		 1066 mode1.yres, mode2.yres);
1067 *old_var = *new_var;
1068
1069 return true;
1070}
1071
1072/**
1073 * sh_hdmi_clk_configure() - set HDMI clock frequency and enable the clock
c36940e6
GL		 1074 * @hdmi: driver context
1075 * @hdmi_rate: HDMI clock frequency in Hz
1076 * @parent_rate: if != 0 - set parent clock rate for optimal precision
1077 * return: configured positive rate if successful
1078 * 0 if couldn't set the rate, but managed to enable the
1079 * clock, negative error, if couldn't enable the clock
afe417c0 1080 */
c36940e6
GL		 1081static long sh_hdmi_clk_configure(struct sh_hdmi *hdmi, unsigned long hdmi_rate,
1082 unsigned long parent_rate)
afe417c0 1083{
afe417c0
GL		 1084 int ret;
1085
c36940e6
GL		 1086 if (parent_rate && clk_get_parent(hdmi->hdmi_clk)) {
1087 ret = clk_set_rate(clk_get_parent(hdmi->hdmi_clk), parent_rate);
afe417c0 1088 if (ret < 0) {
c36940e6
GL		 1089 dev_warn(hdmi->dev, "Cannot set parent rate %ld: %d\n", parent_rate, ret);
1090 hdmi_rate = clk_round_rate(hdmi->hdmi_clk, hdmi_rate);
afe417c0 1091 } else {
c36940e6 1092 dev_dbg(hdmi->dev, "HDMI set parent frequency %lu\n", parent_rate);
afe417c0 1093 }
afe417c0
GL		 1094 }
1095
c36940e6 1096 ret = clk_set_rate(hdmi->hdmi_clk, hdmi_rate);
afe417c0 1097 if (ret < 0) {
c36940e6
GL		 1098 dev_warn(hdmi->dev, "Cannot set rate %ld: %d\n", hdmi_rate, ret);
1099 hdmi_rate = 0;
1100 } else {
1101 dev_dbg(hdmi->dev, "HDMI set frequency %lu\n", hdmi_rate);
afe417c0
GL		 1102 }
1103
c36940e6 1104 return hdmi_rate;
afe417c0
GL		 1105}
1106
6011bdea 1107/* Hotplug interrupt occurred, read EDID */
6aa966e6 1108static void sh_hdmi_edid_work_fn(struct work_struct *work)
6011bdea
GL		 1109{
1110 struct sh_hdmi *hdmi = container_of(work, struct sh_hdmi, edid_work.work);
bce95fe8 1111 struct sh_mobile_lcdc_chan *ch = hdmi->entity.lcdc;
4a47a0e0 1112 struct fb_info *info;
afe417c0 1113 int ret;
6011bdea 1114
134d22eb
LP		 1115 dev_dbg(hdmi->dev, "%s(%p): begin, hotplug status %d\n", __func__, hdmi,
1116 hdmi->hp_state);
6011bdea 1117
4232f607 1118 if (hdmi->hp_state == HDMI_HOTPLUG_CONNECTED) {
c36940e6
GL		 1119 unsigned long parent_rate = 0, hdmi_rate;
1120
c36940e6 1121 ret = sh_hdmi_read_edid(hdmi, &hdmi_rate, &parent_rate);
d521dd94 1122 if (ret < 0)
afe417c0
GL		 1123 goto out;
1124
4232f607
GL		 1125 hdmi->hp_state = HDMI_HOTPLUG_EDID_DONE;
1126
afe417c0 1127 /* Reconfigure the clock */
c36940e6 1128 ret = sh_hdmi_clk_configure(hdmi, hdmi_rate, parent_rate);
d521dd94 1129 if (ret < 0)
afe417c0
GL		 1130 goto out;
1131
6011bdea
GL		 1132 msleep(10);
1133 sh_hdmi_configure(hdmi);
1134 /* Switched to another (d) power-save mode */
1135 msleep(10);
1136
bce95fe8 1137 if (ch == NULL)
6de9edd5 1138 goto out;
6011bdea 1139
bce95fe8 1140 info = ch->info;
6011bdea 1141
4a47a0e0
BP		 1142 if (lock_fb_info(info)) {
1143 console_lock();
6011bdea 1144
4a47a0e0
BP		 1145 /* HDMI plug in */
1146 if (!sh_hdmi_must_reconfigure(hdmi) &&
1147 info->state == FBINFO_STATE_RUNNING) {
1148 /*
1149 * First activation with the default monitor - just turn
1150 * on, if we run a resume here, the logo disappears
1151 */
8c1ac08b
GL		 1152 info->var.width = hdmi->var.width;
1153 info->var.height = hdmi->var.height;
5864ace1 1154 sh_hdmi_display_on(&hdmi->entity);
4a47a0e0
BP		 1155 } else {
1156 /* New monitor or have to wake up */
1157 fb_set_suspend(info, 0);
6de9edd5 1158 }
6011bdea 1159
4a47a0e0
BP		 1160 console_unlock();
1161 unlock_fb_info(info);
1162 }
6011bdea 1163 } else {
afe417c0 1164 ret = 0;
bce95fe8 1165 if (ch == NULL)
6de9edd5 1166 goto out;
6011bdea 1167
bce95fe8
LP		 1168 info = ch->info;
1169
91d63f8a
GL		 1170 hdmi->monspec.modedb_len = 0;
1171 fb_destroy_modedb(hdmi->monspec.modedb);
1172 hdmi->monspec.modedb = NULL;
1173
4a47a0e0
BP		 1174 if (lock_fb_info(info)) {
1175 console_lock();
6011bdea 1176
4a47a0e0
BP		 1177 /* HDMI disconnect */
1178 fb_set_suspend(info, 1);
6011bdea 1179
4a47a0e0
BP		 1180 console_unlock();
1181 unlock_fb_info(info);
1182 }
6011bdea
GL		 1183 }
1184
6de9edd5 1185out:
4232f607 1186 if (ret < 0 && ret != -EAGAIN)
afe417c0 1187 hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
6de9edd5 1188
134d22eb 1189 dev_dbg(hdmi->dev, "%s(%p): end\n", __func__, hdmi);
6011bdea
GL		 1190}
1191
1192static int __init sh_hdmi_probe(struct platform_device *pdev)
1193{
1194 struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
1195 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1196 int irq = platform_get_irq(pdev, 0), ret;
1197 struct sh_hdmi *hdmi;
1198 long rate;
1199
1200 if (!res || !pdata || irq < 0)
1201 return -ENODEV;
1202
1203 hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
1204 if (!hdmi) {
1205 dev_err(&pdev->dev, "Cannot allocate device data\n");
1206 return -ENOMEM;
1207 }
1208
1209 hdmi->dev = &pdev->dev;
8511ea4a
LP		 1210 hdmi->entity.owner = THIS_MODULE;
1211 hdmi->entity.ops = &sh_hdmi_ops;
6011bdea
GL		 1212
1213 hdmi->hdmi_clk = clk_get(&pdev->dev, "ick");
1214 if (IS_ERR(hdmi->hdmi_clk)) {
1215 ret = PTR_ERR(hdmi->hdmi_clk);
1216 dev_err(&pdev->dev, "Unable to get clock: %d\n", ret);
1217 goto egetclk;
1218 }
1219
c36940e6
GL		 1220 /* An arbitrary relaxed pixclock just to get things started: from standard 480p */
1221 rate = clk_round_rate(hdmi->hdmi_clk, PICOS2KHZ(37037));
1222 if (rate > 0)
1223 rate = sh_hdmi_clk_configure(hdmi, rate, 0);
1224
6011bdea
GL		 1225 if (rate < 0) {
1226 ret = rate;
6011bdea
GL		 1227 goto erate;
1228 }
1229
c36940e6
GL		 1230 ret = clk_enable(hdmi->hdmi_clk);
1231 if (ret < 0) {
1232 dev_err(hdmi->dev, "Cannot enable clock: %d\n", ret);
1233 goto erate;
1234 }
1235
afe417c0 1236 dev_dbg(&pdev->dev, "Enabled HDMI clock at %luHz\n", rate);
6011bdea
GL		 1237
1238 if (!request_mem_region(res->start, resource_size(res), dev_name(&pdev->dev))) {
1239 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1240 ret = -EBUSY;
1241 goto ereqreg;
1242 }
1243
1244 hdmi->base = ioremap(res->start, resource_size(res));
1245 if (!hdmi->base) {
1246 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1247 ret = -ENOMEM;
1248 goto emap;
1249 }
1250
8511ea4a 1251 platform_set_drvdata(pdev, &hdmi->entity);
6011bdea 1252
6aa966e6 1253 INIT_DELAYED_WORK(&hdmi->edid_work, sh_hdmi_edid_work_fn);
6011bdea
GL		 1254
1255 pm_runtime_enable(&pdev->dev);
d521dd94 1256 pm_runtime_get_sync(&pdev->dev);
6011bdea 1257
c36940e6
GL		 1258 /* Product and revision IDs are 0 in sh-mobile version */
1259 dev_info(&pdev->dev, "Detected HDMI controller 0x%x:0x%x\n",
1260 hdmi_read(hdmi, HDMI_PRODUCT_ID), hdmi_read(hdmi, HDMI_REVISION_ID));
1261
6011bdea
GL		 1262 ret = request_irq(irq, sh_hdmi_hotplug, 0,
1263 dev_name(&pdev->dev), hdmi);
1264 if (ret < 0) {
1265 dev_err(&pdev->dev, "Unable to request irq: %d\n", ret);
1266 goto ereqirq;
1267 }
1268
b3773301
RK		 1269 ret = snd_soc_register_codec(&pdev->dev,
1270 &soc_codec_dev_sh_hdmi, &sh_hdmi_dai, 1);
1271 if (ret < 0) {
1272 dev_err(&pdev->dev, "codec registration failed\n");
1273 goto ecodec;
1274 }
1275
6011bdea
GL		 1276 return 0;
1277
b3773301
RK		 1278ecodec:
1279 free_irq(irq, hdmi);
6011bdea 1280ereqirq:
d521dd94 1281 pm_runtime_put(&pdev->dev);
6011bdea
GL		 1282 pm_runtime_disable(&pdev->dev);
1283 iounmap(hdmi->base);
1284emap:
1285 release_mem_region(res->start, resource_size(res));
1286ereqreg:
1287 clk_disable(hdmi->hdmi_clk);
6011bdea
GL		 1288erate:
1289 clk_put(hdmi->hdmi_clk);
1290egetclk:
1291 kfree(hdmi);
1292
1293 return ret;
1294}
1295
1296static int __exit sh_hdmi_remove(struct platform_device *pdev)
1297{
8511ea4a 1298 struct sh_hdmi *hdmi = entity_to_sh_hdmi(platform_get_drvdata(pdev));
6011bdea
GL		 1299 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1300 int irq = platform_get_irq(pdev, 0);
1301
1d6be338
KM		 1302 snd_soc_unregister_codec(&pdev->dev);
1303
6de9edd5 1304 /* No new work will be scheduled, wait for running ISR */
6011bdea 1305 free_irq(irq, hdmi);
6de9edd5 1306 /* Wait for already scheduled work */
6011bdea 1307 cancel_delayed_work_sync(&hdmi->edid_work);
d521dd94 1308 pm_runtime_put(&pdev->dev);
6de9edd5 1309 pm_runtime_disable(&pdev->dev);
6011bdea
GL		 1310 clk_disable(hdmi->hdmi_clk);
1311 clk_put(hdmi->hdmi_clk);
1312 iounmap(hdmi->base);
1313 release_mem_region(res->start, resource_size(res));
1314 kfree(hdmi);
1315
1316 return 0;
1317}
1318
1319static struct platform_driver sh_hdmi_driver = {
1320 .remove = __exit_p(sh_hdmi_remove),
1321 .driver = {
1322 .name = "sh-mobile-hdmi",
1323 },
1324};
1325
1326static int __init sh_hdmi_init(void)
1327{
1328 return platform_driver_probe(&sh_hdmi_driver, sh_hdmi_probe);
1329}
1330module_init(sh_hdmi_init);
1331
1332static void __exit sh_hdmi_exit(void)
1333{
1334 platform_driver_unregister(&sh_hdmi_driver);
1335}
1336module_exit(sh_hdmi_exit);
1337
1338MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
1339MODULE_DESCRIPTION("SuperH / ARM-shmobile HDMI driver");
1340MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
This page took 0.165626 seconds and 5 git commands to generate.