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fbdev: sh_mobile_lcdc: Compute clock pattern using divider denominator
[deliverable/linux.git] / drivers / video / sh_mobile_lcdcfb.c
CommitLineData
cfb4f5d1
MD		 1/*
2 * SuperH Mobile LCDC Framebuffer
3 *
4 * Copyright (c) 2008 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/delay.h>
14#include <linux/mm.h>
cfb4f5d1 15#include <linux/clk.h>
0246c471 16#include <linux/pm_runtime.h>
cfb4f5d1
MD		 17#include <linux/platform_device.h>
18#include <linux/dma-mapping.h>
8564557a 19#include <linux/interrupt.h>
1c6a307a 20#include <linux/vmalloc.h>
40331b21 21#include <linux/ioctl.h>
5a0e3ad6 22#include <linux/slab.h>
dd210503 23#include <linux/console.h>
3b0fd9d7
AC		 24#include <linux/backlight.h>
25#include <linux/gpio.h>
225c9a8d 26#include <video/sh_mobile_lcdc.h>
60063497 27#include <linux/atomic.h>
cfb4f5d1 28
6de9edd5 29#include "sh_mobile_lcdcfb.h"
7caa4342 30#include "sh_mobile_meram.h"
6de9edd5 31
a6f15ade
PE		 32#define SIDE_B_OFFSET 0x1000
33#define MIRROR_OFFSET 0x2000
cfb4f5d1 34
0246c471
MD		 35/* shared registers and their order for context save/restore */
36static int lcdc_shared_regs[] = {
37 _LDDCKR,
38 _LDDCKSTPR,
39 _LDINTR,
40 _LDDDSR,
41 _LDCNT1R,
42 _LDCNT2R,
43};
44#define NR_SHARED_REGS ARRAY_SIZE(lcdc_shared_regs)
45
d2ecbab5
GL		 46#define MAX_XRES 1920
47#define MAX_YRES 1080
cfb4f5d1 48
0246c471 49static unsigned long lcdc_offs_mainlcd[NR_CH_REGS] = {
cfb4f5d1
MD		 50 [LDDCKPAT1R] = 0x400,
51 [LDDCKPAT2R] = 0x404,
52 [LDMT1R] = 0x418,
53 [LDMT2R] = 0x41c,
54 [LDMT3R] = 0x420,
55 [LDDFR] = 0x424,
56 [LDSM1R] = 0x428,
8564557a 57 [LDSM2R] = 0x42c,
cfb4f5d1 58 [LDSA1R] = 0x430,
53b50314 59 [LDSA2R] = 0x434,
cfb4f5d1
MD		 60 [LDMLSR] = 0x438,
61 [LDHCNR] = 0x448,
62 [LDHSYNR] = 0x44c,
63 [LDVLNR] = 0x450,
64 [LDVSYNR] = 0x454,
65 [LDPMR] = 0x460,
6011bdea 66 [LDHAJR] = 0x4a0,
cfb4f5d1
MD		 67};
68
0246c471 69static unsigned long lcdc_offs_sublcd[NR_CH_REGS] = {
cfb4f5d1
MD		 70 [LDDCKPAT1R] = 0x408,
71 [LDDCKPAT2R] = 0x40c,
72 [LDMT1R] = 0x600,
73 [LDMT2R] = 0x604,
74 [LDMT3R] = 0x608,
75 [LDDFR] = 0x60c,
76 [LDSM1R] = 0x610,
8564557a 77 [LDSM2R] = 0x614,
cfb4f5d1
MD		 78 [LDSA1R] = 0x618,
79 [LDMLSR] = 0x620,
80 [LDHCNR] = 0x624,
81 [LDHSYNR] = 0x628,
82 [LDVLNR] = 0x62c,
83 [LDVSYNR] = 0x630,
84 [LDPMR] = 0x63c,
85};
86
c44f9f76
GL		 87static const struct fb_videomode default_720p = {
88 .name = "HDMI 720p",
89 .xres = 1280,
90 .yres = 720,
91
5ae0cf82
GL		 92 .left_margin = 220,
93 .right_margin = 110,
94 .hsync_len = 40,
c44f9f76
GL		 95
96 .upper_margin = 20,
97 .lower_margin = 5,
98 .vsync_len = 5,
99
100 .pixclock = 13468,
5ae0cf82 101 .refresh = 60,
c44f9f76 102 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
0246c471
MD		 103};
104
105struct sh_mobile_lcdc_priv {
106 void __iomem *base;
107 int irq;
108 atomic_t hw_usecnt;
109 struct device *dev;
110 struct clk *dot_clk;
111 unsigned long lddckr;
112 struct sh_mobile_lcdc_chan ch[2];
6011bdea 113 struct notifier_block notifier;
0246c471
MD		 114 unsigned long saved_shared_regs[NR_SHARED_REGS];
115 int started;
417d4827 116 int forced_bpp; /* 2 channel LCDC must share bpp setting */
7caa4342 117 struct sh_mobile_meram_info *meram_dev;
0246c471
MD		 118};
119
a6f15ade
PE		 120static bool banked(int reg_nr)
121{
122 switch (reg_nr) {
123 case LDMT1R:
124 case LDMT2R:
125 case LDMT3R:
126 case LDDFR:
127 case LDSM1R:
128 case LDSA1R:
53b50314 129 case LDSA2R:
a6f15ade
PE		 130 case LDMLSR:
131 case LDHCNR:
132 case LDHSYNR:
133 case LDVLNR:
134 case LDVSYNR:
135 return true;
136 }
137 return false;
138}
139
cfb4f5d1
MD		 140static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan,
141 int reg_nr, unsigned long data)
142{
143 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]);
a6f15ade
PE		 144 if (banked(reg_nr))
145 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
146 SIDE_B_OFFSET);
147}
148
149static void lcdc_write_chan_mirror(struct sh_mobile_lcdc_chan *chan,
150 int reg_nr, unsigned long data)
151{
152 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
153 MIRROR_OFFSET);
cfb4f5d1
MD		 154}
155
156static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan,
157 int reg_nr)
158{
159 return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]);
160}
161
162static void lcdc_write(struct sh_mobile_lcdc_priv *priv,
163 unsigned long reg_offs, unsigned long data)
164{
165 iowrite32(data, priv->base + reg_offs);
166}
167
168static unsigned long lcdc_read(struct sh_mobile_lcdc_priv *priv,
169 unsigned long reg_offs)
170{
171 return ioread32(priv->base + reg_offs);
172}
173
174static void lcdc_wait_bit(struct sh_mobile_lcdc_priv *priv,
175 unsigned long reg_offs,
176 unsigned long mask, unsigned long until)
177{
178 while ((lcdc_read(priv, reg_offs) & mask) != until)
179 cpu_relax();
180}
181
182static int lcdc_chan_is_sublcd(struct sh_mobile_lcdc_chan *chan)
183{
184 return chan->cfg.chan == LCDC_CHAN_SUBLCD;
185}
186
187static void lcdc_sys_write_index(void *handle, unsigned long data)
188{
189 struct sh_mobile_lcdc_chan *ch = handle;
190
ce1c0b08
LP		 191 lcdc_write(ch->lcdc, _LDDWD0R, data | LDDWDxR_WDACT);
192 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
193 lcdc_write(ch->lcdc, _LDDWAR, LDDWAR_WA |
194 (lcdc_chan_is_sublcd(ch) ? 2 : 0));
195 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
cfb4f5d1
MD		 196}
197
198static void lcdc_sys_write_data(void *handle, unsigned long data)
199{
200 struct sh_mobile_lcdc_chan *ch = handle;
201
ce1c0b08
LP		 202 lcdc_write(ch->lcdc, _LDDWD0R, data | LDDWDxR_WDACT | LDDWDxR_RSW);
203 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
204 lcdc_write(ch->lcdc, _LDDWAR, LDDWAR_WA |
205 (lcdc_chan_is_sublcd(ch) ? 2 : 0));
206 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
cfb4f5d1
MD		 207}
208
209static unsigned long lcdc_sys_read_data(void *handle)
210{
211 struct sh_mobile_lcdc_chan *ch = handle;
212
ce1c0b08
LP		 213 lcdc_write(ch->lcdc, _LDDRDR, LDDRDR_RSR);
214 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
215 lcdc_write(ch->lcdc, _LDDRAR, LDDRAR_RA |
216 (lcdc_chan_is_sublcd(ch) ? 2 : 0));
cfb4f5d1 217 udelay(1);
ce1c0b08 218 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
cfb4f5d1 219
ce1c0b08 220 return lcdc_read(ch->lcdc, _LDDRDR) & LDDRDR_DRD_MASK;
cfb4f5d1
MD		 221}
222
223struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = {
224 lcdc_sys_write_index,
225 lcdc_sys_write_data,
226 lcdc_sys_read_data,
227};
228
8564557a
MD		 229static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv)
230{
0246c471 231 if (atomic_inc_and_test(&priv->hw_usecnt)) {
8564557a
MD		 232 if (priv->dot_clk)
233 clk_enable(priv->dot_clk);
f1ad90da 234 pm_runtime_get_sync(priv->dev);
ec19b9e0
DHG		 235 if (priv->meram_dev && priv->meram_dev->pdev)
236 pm_runtime_get_sync(&priv->meram_dev->pdev->dev);
8564557a
MD		 237 }
238}
239
240static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv)
241{
0246c471 242 if (atomic_sub_return(1, &priv->hw_usecnt) == -1) {
ec19b9e0
DHG		 243 if (priv->meram_dev && priv->meram_dev->pdev)
244 pm_runtime_put_sync(&priv->meram_dev->pdev->dev);
0246c471 245 pm_runtime_put(priv->dev);
f1ad90da
LP		 246 if (priv->dot_clk)
247 clk_disable(priv->dot_clk);
8564557a
MD		 248 }
249}
8564557a 250
1c6a307a
PM		 251static int sh_mobile_lcdc_sginit(struct fb_info *info,
252 struct list_head *pagelist)
253{
254 struct sh_mobile_lcdc_chan *ch = info->par;
255 unsigned int nr_pages_max = info->fix.smem_len >> PAGE_SHIFT;
256 struct page *page;
257 int nr_pages = 0;
258
259 sg_init_table(ch->sglist, nr_pages_max);
260
261 list_for_each_entry(page, pagelist, lru)
262 sg_set_page(&ch->sglist[nr_pages++], page, PAGE_SIZE, 0);
263
264 return nr_pages;
265}
266
8564557a
MD		 267static void sh_mobile_lcdc_deferred_io(struct fb_info *info,
268 struct list_head *pagelist)
269{
270 struct sh_mobile_lcdc_chan *ch = info->par;
ef61aae4 271 struct sh_mobile_lcdc_board_cfg *bcfg = &ch->cfg.board_cfg;
8564557a
MD		 272
273 /* enable clocks before accessing hardware */
274 sh_mobile_lcdc_clk_on(ch->lcdc);
275
5c1a56b5
PM		 276 /*
277 * It's possible to get here without anything on the pagelist via
278 * sh_mobile_lcdc_deferred_io_touch() or via a userspace fsync()
279 * invocation. In the former case, the acceleration routines are
280 * stepped in to when using the framebuffer console causing the
281 * workqueue to be scheduled without any dirty pages on the list.
282 *
283 * Despite this, a panel update is still needed given that the
284 * acceleration routines have their own methods for writing in
285 * that still need to be updated.
286 *
287 * The fsync() and empty pagelist case could be optimized for,
288 * but we don't bother, as any application exhibiting such
289 * behaviour is fundamentally broken anyways.
290 */
291 if (!list_empty(pagelist)) {
292 unsigned int nr_pages = sh_mobile_lcdc_sginit(info, pagelist);
293
294 /* trigger panel update */
295 dma_map_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
ef61aae4
MD		 296 if (bcfg->start_transfer)
297 bcfg->start_transfer(bcfg->board_data, ch,
298 &sh_mobile_lcdc_sys_bus_ops);
ce1c0b08 299 lcdc_write_chan(ch, LDSM2R, LDSM2R_OSTRG);
5c1a56b5 300 dma_unmap_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
ef61aae4
MD		 301 } else {
302 if (bcfg->start_transfer)
303 bcfg->start_transfer(bcfg->board_data, ch,
304 &sh_mobile_lcdc_sys_bus_ops);
ce1c0b08 305 lcdc_write_chan(ch, LDSM2R, LDSM2R_OSTRG);
ef61aae4 306 }
8564557a
MD		 307}
308
309static void sh_mobile_lcdc_deferred_io_touch(struct fb_info *info)
310{
311 struct fb_deferred_io *fbdefio = info->fbdefio;
312
313 if (fbdefio)
314 schedule_delayed_work(&info->deferred_work, fbdefio->delay);
315}
316
317static irqreturn_t sh_mobile_lcdc_irq(int irq, void *data)
318{
319 struct sh_mobile_lcdc_priv *priv = data;
2feb075a 320 struct sh_mobile_lcdc_chan *ch;
9dd38819 321 unsigned long ldintr;
2feb075a
MD		 322 int is_sub;
323 int k;
8564557a 324
dc48665f
LP		 325 /* Acknowledge interrupts and disable further VSYNC End IRQs. */
326 ldintr = lcdc_read(priv, _LDINTR);
327 lcdc_write(priv, _LDINTR, (ldintr ^ LDINTR_STATUS_MASK) & ~LDINTR_VEE);
8564557a 328
2feb075a 329 /* figure out if this interrupt is for main or sub lcd */
ce1c0b08 330 is_sub = (lcdc_read(priv, _LDSR) & LDSR_MSS) ? 1 : 0;
2feb075a 331
9dd38819 332 /* wake up channel and disable clocks */
2feb075a
MD		 333 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
334 ch = &priv->ch[k];
335
336 if (!ch->enabled)
337 continue;
338
dc48665f 339 /* Frame End */
9dd38819
PE		 340 if (ldintr & LDINTR_FS) {
341 if (is_sub == lcdc_chan_is_sublcd(ch)) {
342 ch->frame_end = 1;
343 wake_up(&ch->frame_end_wait);
2feb075a 344
9dd38819
PE		 345 sh_mobile_lcdc_clk_off(priv);
346 }
347 }
348
349 /* VSYNC End */
40331b21
PE		 350 if (ldintr & LDINTR_VES)
351 complete(&ch->vsync_completion);
2feb075a
MD		 352 }
353
8564557a
MD		 354 return IRQ_HANDLED;
355}
356
cfb4f5d1
MD		 357static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv *priv,
358 int start)
359{
360 unsigned long tmp = lcdc_read(priv, _LDCNT2R);
361 int k;
362
363 /* start or stop the lcdc */
364 if (start)
ce1c0b08 365 lcdc_write(priv, _LDCNT2R, tmp | LDCNT2R_DO);
cfb4f5d1 366 else
ce1c0b08 367 lcdc_write(priv, _LDCNT2R, tmp & ~LDCNT2R_DO);
cfb4f5d1
MD		 368
369 /* wait until power is applied/stopped on all channels */
370 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
371 if (lcdc_read(priv, _LDCNT2R) & priv->ch[k].enabled)
372 while (1) {
ce1c0b08
LP		 373 tmp = lcdc_read_chan(&priv->ch[k], LDPMR)
374 & LDPMR_LPS;
375 if (start && tmp == LDPMR_LPS)
cfb4f5d1
MD		 376 break;
377 if (!start && tmp == 0)
378 break;
379 cpu_relax();
380 }
381
382 if (!start)
383 lcdc_write(priv, _LDDCKSTPR, 1); /* stop dotclock */
384}
385
6011bdea
GL		 386static void sh_mobile_lcdc_geometry(struct sh_mobile_lcdc_chan *ch)
387{
1c120deb
GL		 388 struct fb_var_screeninfo *var = &ch->info->var, *display_var = &ch->display_var;
389 unsigned long h_total, hsync_pos, display_h_total;
6011bdea
GL		 390 u32 tmp;
391
392 tmp = ch->ldmt1r_value;
ce1c0b08
LP		 393 tmp |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : LDMT1R_VPOL;
394 tmp |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : LDMT1R_HPOL;
395 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWPOL) ? LDMT1R_DWPOL : 0;
396 tmp |= (ch->cfg.flags & LCDC_FLAGS_DIPOL) ? LDMT1R_DIPOL : 0;
397 tmp |= (ch->cfg.flags & LCDC_FLAGS_DAPOL) ? LDMT1R_DAPOL : 0;
398 tmp |= (ch->cfg.flags & LCDC_FLAGS_HSCNT) ? LDMT1R_HSCNT : 0;
399 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWCNT) ? LDMT1R_DWCNT : 0;
6011bdea
GL		 400 lcdc_write_chan(ch, LDMT1R, tmp);
401
402 /* setup SYS bus */
403 lcdc_write_chan(ch, LDMT2R, ch->cfg.sys_bus_cfg.ldmt2r);
404 lcdc_write_chan(ch, LDMT3R, ch->cfg.sys_bus_cfg.ldmt3r);
405
406 /* horizontal configuration */
1c120deb
GL		 407 h_total = display_var->xres + display_var->hsync_len +
408 display_var->left_margin + display_var->right_margin;
6011bdea 409 tmp = h_total / 8; /* HTCN */
1c120deb 410 tmp |= (min(display_var->xres, var->xres) / 8) << 16; /* HDCN */
6011bdea
GL		 411 lcdc_write_chan(ch, LDHCNR, tmp);
412
1c120deb 413 hsync_pos = display_var->xres + display_var->right_margin;
6011bdea 414 tmp = hsync_pos / 8; /* HSYNP */
1c120deb 415 tmp |= (display_var->hsync_len / 8) << 16; /* HSYNW */
6011bdea
GL		 416 lcdc_write_chan(ch, LDHSYNR, tmp);
417
418 /* vertical configuration */
1c120deb
GL		 419 tmp = display_var->yres + display_var->vsync_len +
420 display_var->upper_margin + display_var->lower_margin; /* VTLN */
421 tmp |= min(display_var->yres, var->yres) << 16; /* VDLN */
6011bdea
GL		 422 lcdc_write_chan(ch, LDVLNR, tmp);
423
1c120deb
GL		 424 tmp = display_var->yres + display_var->lower_margin; /* VSYNP */
425 tmp |= display_var->vsync_len << 16; /* VSYNW */
6011bdea
GL		 426 lcdc_write_chan(ch, LDVSYNR, tmp);
427
428 /* Adjust horizontal synchronisation for HDMI */
1c120deb
GL		 429 display_h_total = display_var->xres + display_var->hsync_len +
430 display_var->left_margin + display_var->right_margin;
431 tmp = ((display_var->xres & 7) << 24) |
432 ((display_h_total & 7) << 16) |
433 ((display_var->hsync_len & 7) << 8) |
6011bdea
GL		 434 hsync_pos;
435 lcdc_write_chan(ch, LDHAJR, tmp);
436}
437
cfb4f5d1
MD		 438static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
439{
440 struct sh_mobile_lcdc_chan *ch;
cfb4f5d1
MD		 441 struct sh_mobile_lcdc_board_cfg *board_cfg;
442 unsigned long tmp;
417d4827 443 int bpp = 0;
53b50314 444 unsigned long ldddsr;
554cc102 445 int k, m, ret;
cfb4f5d1 446
8564557a 447 /* enable clocks before accessing the hardware */
417d4827
MD		 448 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
449 if (priv->ch[k].enabled) {
8564557a 450 sh_mobile_lcdc_clk_on(priv);
417d4827
MD		 451 if (!bpp)
452 bpp = priv->ch[k].info->var.bits_per_pixel;
453 }
454 }
8564557a 455
cfb4f5d1 456 /* reset */
ce1c0b08
LP		 457 lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LDCNT2R_BR);
458 lcdc_wait_bit(priv, _LDCNT2R, LDCNT2R_BR, 0);
cfb4f5d1
MD		 459
460 /* enable LCDC channels */
461 tmp = lcdc_read(priv, _LDCNT2R);
462 tmp |= priv->ch[0].enabled;
463 tmp |= priv->ch[1].enabled;
464 lcdc_write(priv, _LDCNT2R, tmp);
465
466 /* read data from external memory, avoid using the BEU for now */
ce1c0b08 467 lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) & ~LDCNT2R_MD);
cfb4f5d1
MD		 468
469 /* stop the lcdc first */
470 sh_mobile_lcdc_start_stop(priv, 0);
471
472 /* configure clocks */
473 tmp = priv->lddckr;
474 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
475 ch = &priv->ch[k];
476
477 if (!priv->ch[k].enabled)
478 continue;
479
480 m = ch->cfg.clock_divider;
481 if (!m)
482 continue;
483
505c7de5
LP		 484 /* FIXME: sh7724 can only use 42, 48, 54 and 60 for the divider
485 * denominator.
486 */
487 lcdc_write_chan(ch, LDDCKPAT1R, 0);
488 lcdc_write_chan(ch, LDDCKPAT2R, (1 << (m/2)) - 1);
489
cfb4f5d1 490 if (m == 1)
ce1c0b08 491 m = LDDCKR_MOSEL;
cfb4f5d1 492 tmp |= m << (lcdc_chan_is_sublcd(ch) ? 8 : 0);
cfb4f5d1
MD		 493 }
494
495 lcdc_write(priv, _LDDCKR, tmp);
496
497 /* start dotclock again */
498 lcdc_write(priv, _LDDCKSTPR, 0);
499 lcdc_wait_bit(priv, _LDDCKSTPR, ~0, 0);
500
8564557a 501 /* interrupts are disabled to begin with */
cfb4f5d1
MD		 502 lcdc_write(priv, _LDINTR, 0);
503
504 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
505 ch = &priv->ch[k];
cfb4f5d1
MD		 506
507 if (!ch->enabled)
508 continue;
509
6011bdea 510 sh_mobile_lcdc_geometry(ch);
cfb4f5d1
MD		 511
512 /* power supply */
513 lcdc_write_chan(ch, LDPMR, 0);
514
cfb4f5d1 515 board_cfg = &ch->cfg.board_cfg;
69843ba7 516 if (board_cfg->setup_sys) {
554cc102 517 ret = board_cfg->setup_sys(board_cfg->board_data,
69843ba7
GL		 518 ch, &sh_mobile_lcdc_sys_bus_ops);
519 if (ret)
520 return ret;
521 }
cfb4f5d1
MD		 522 }
523
cfb4f5d1 524 /* word and long word swap */
53b50314
DHG		 525 ldddsr = lcdc_read(priv, _LDDDSR);
526 if (priv->ch[0].info->var.nonstd)
ce1c0b08 527 ldddsr |= LDDDSR_LS | LDDDSR_WS | LDDDSR_BS;
53b50314
DHG		 528 else {
529 switch (bpp) {
530 case 16:
ce1c0b08 531 ldddsr |= LDDDSR_LS | LDDDSR_WS;
53b50314
DHG		 532 break;
533 case 24:
ce1c0b08 534 ldddsr |= LDDDSR_LS | LDDDSR_WS | LDDDSR_BS;
53b50314
DHG		 535 break;
536 case 32:
ce1c0b08 537 ldddsr |= LDDDSR_LS;
53b50314
DHG		 538 break;
539 }
417d4827 540 }
ce1c0b08 541 lcdc_write(priv, _LDDDSR, ldddsr);
cfb4f5d1
MD		 542
543 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
7caa4342
D		 544 unsigned long base_addr_y;
545 unsigned long base_addr_c = 0;
546 int pitch;
cfb4f5d1
MD		 547 ch = &priv->ch[k];
548
549 if (!priv->ch[k].enabled)
550 continue;
551
552 /* set bpp format in PKF[4:0] */
553 tmp = lcdc_read_chan(ch, LDDFR);
ce1c0b08 554 tmp &= ~(LDDFR_CF0 | LDDFR_CC | LDDFR_YF_MASK | LDDFR_PKF_MASK);
53b50314
DHG		 555 if (ch->info->var.nonstd) {
556 tmp |= (ch->info->var.nonstd << 16);
557 switch (ch->info->var.bits_per_pixel) {
558 case 12:
559 break;
560 case 16:
ce1c0b08 561 tmp |= LDDFR_YF_422;
53b50314
DHG		 562 break;
563 case 24:
ce1c0b08 564 tmp |= LDDFR_YF_444;
53b50314
DHG		 565 break;
566 }
567 } else {
568 switch (ch->info->var.bits_per_pixel) {
569 case 16:
ce1c0b08 570 tmp |= LDDFR_PKF_RGB16;
53b50314
DHG		 571 break;
572 case 24:
ce1c0b08 573 tmp |= LDDFR_PKF_RGB24;
53b50314
DHG		 574 break;
575 case 32:
ce1c0b08 576 tmp |= LDDFR_PKF_ARGB32;
53b50314
DHG		 577 break;
578 }
417d4827 579 }
cfb4f5d1
MD		 580 lcdc_write_chan(ch, LDDFR, tmp);
581
7caa4342
D		 582 base_addr_y = ch->info->fix.smem_start;
583 base_addr_c = base_addr_y +
584 ch->info->var.xres *
585 ch->info->var.yres_virtual;
586 pitch = ch->info->fix.line_length;
587
588 /* test if we can enable meram */
eae9b85b
D		 589 if (ch->cfg.meram_cfg && priv->meram_dev &&
590 priv->meram_dev->ops) {
7caa4342
D		 591 struct sh_mobile_meram_cfg *cfg;
592 struct sh_mobile_meram_info *mdev;
593 unsigned long icb_addr_y, icb_addr_c;
594 int icb_pitch;
595 int pf;
596
597 cfg = ch->cfg.meram_cfg;
598 mdev = priv->meram_dev;
599 /* we need to de-init configured ICBs before we
600 * we can re-initialize them.
601 */
602 if (ch->meram_enabled)
603 mdev->ops->meram_unregister(mdev, cfg);
604
605 ch->meram_enabled = 0;
606
3fedd2ac
D		 607 if (ch->info->var.nonstd) {
608 if (ch->info->var.bits_per_pixel == 24)
609 pf = SH_MOBILE_MERAM_PF_NV24;
610 else
611 pf = SH_MOBILE_MERAM_PF_NV;
612 } else {
7caa4342 613 pf = SH_MOBILE_MERAM_PF_RGB;
3fedd2ac 614 }
7caa4342
D		 615
616 ret = mdev->ops->meram_register(mdev, cfg, pitch,
617 ch->info->var.yres,
618 pf,
619 base_addr_y,
620 base_addr_c,
621 &icb_addr_y,
622 &icb_addr_c,
623 &icb_pitch);
624 if (!ret) {
625 /* set LDSA1R value */
626 base_addr_y = icb_addr_y;
627 pitch = icb_pitch;
628
629 /* set LDSA2R value if required */
630 if (base_addr_c)
631 base_addr_c = icb_addr_c;
632
633 ch->meram_enabled = 1;
634 }
635 }
636
cfb4f5d1 637 /* point out our frame buffer */
7caa4342 638 lcdc_write_chan(ch, LDSA1R, base_addr_y);
53b50314 639 if (ch->info->var.nonstd)
7caa4342 640 lcdc_write_chan(ch, LDSA2R, base_addr_c);
cfb4f5d1
MD		 641
642 /* set line size */
7caa4342 643 lcdc_write_chan(ch, LDMLSR, pitch);
cfb4f5d1 644
8564557a
MD		 645 /* setup deferred io if SYS bus */
646 tmp = ch->cfg.sys_bus_cfg.deferred_io_msec;
ce1c0b08 647 if (ch->ldmt1r_value & LDMT1R_IFM && tmp) {
8564557a
MD		 648 ch->defio.deferred_io = sh_mobile_lcdc_deferred_io;
649 ch->defio.delay = msecs_to_jiffies(tmp);
e33afddc
PM		 650 ch->info->fbdefio = &ch->defio;
651 fb_deferred_io_init(ch->info);
8564557a
MD		 652
653 /* one-shot mode */
ce1c0b08 654 lcdc_write_chan(ch, LDSM1R, LDSM1R_OS);
8564557a
MD		 655
656 /* enable "Frame End Interrupt Enable" bit */
657 lcdc_write(priv, _LDINTR, LDINTR_FE);
658
659 } else {
660 /* continuous read mode */
661 lcdc_write_chan(ch, LDSM1R, 0);
662 }
cfb4f5d1
MD		 663 }
664
665 /* display output */
ce1c0b08 666 lcdc_write(priv, _LDCNT1R, LDCNT1R_DE);
cfb4f5d1
MD		 667
668 /* start the lcdc */
669 sh_mobile_lcdc_start_stop(priv, 1);
8e9bb19e 670 priv->started = 1;
cfb4f5d1
MD		 671
672 /* tell the board code to enable the panel */
673 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
674 ch = &priv->ch[k];
21bc1f02
MD		 675 if (!ch->enabled)
676 continue;
677
cfb4f5d1 678 board_cfg = &ch->cfg.board_cfg;
247f9938 679 if (board_cfg->display_on && try_module_get(board_cfg->owner)) {
c2439398 680 board_cfg->display_on(board_cfg->board_data, ch->info);
6de9edd5
GL		 681 module_put(board_cfg->owner);
682 }
3b0fd9d7
AC		 683
684 if (ch->bl) {
685 ch->bl->props.power = FB_BLANK_UNBLANK;
686 backlight_update_status(ch->bl);
687 }
cfb4f5d1
MD		 688 }
689
690 return 0;
691}
692
693static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
694{
695 struct sh_mobile_lcdc_chan *ch;
696 struct sh_mobile_lcdc_board_cfg *board_cfg;
697 int k;
698
2feb075a 699 /* clean up deferred io and ask board code to disable panel */
cfb4f5d1
MD		 700 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
701 ch = &priv->ch[k];
21bc1f02
MD		 702 if (!ch->enabled)
703 continue;
8564557a 704
2feb075a
MD		 705 /* deferred io mode:
706 * flush frame, and wait for frame end interrupt
707 * clean up deferred io and enable clock
708 */
5ef6b505 709 if (ch->info && ch->info->fbdefio) {
2feb075a 710 ch->frame_end = 0;
e33afddc 711 schedule_delayed_work(&ch->info->deferred_work, 0);
2feb075a 712 wait_event(ch->frame_end_wait, ch->frame_end);
e33afddc
PM		 713 fb_deferred_io_cleanup(ch->info);
714 ch->info->fbdefio = NULL;
2feb075a 715 sh_mobile_lcdc_clk_on(priv);
8564557a 716 }
2feb075a 717
3b0fd9d7
AC		 718 if (ch->bl) {
719 ch->bl->props.power = FB_BLANK_POWERDOWN;
720 backlight_update_status(ch->bl);
721 }
722
2feb075a 723 board_cfg = &ch->cfg.board_cfg;
247f9938 724 if (board_cfg->display_off && try_module_get(board_cfg->owner)) {
2feb075a 725 board_cfg->display_off(board_cfg->board_data);
6de9edd5
GL		 726 module_put(board_cfg->owner);
727 }
7caa4342
D		 728
729 /* disable the meram */
730 if (ch->meram_enabled) {
731 struct sh_mobile_meram_cfg *cfg;
732 struct sh_mobile_meram_info *mdev;
733 cfg = ch->cfg.meram_cfg;
734 mdev = priv->meram_dev;
735 mdev->ops->meram_unregister(mdev, cfg);
736 ch->meram_enabled = 0;
737 }
738
cfb4f5d1
MD		 739 }
740
741 /* stop the lcdc */
8e9bb19e
MD		 742 if (priv->started) {
743 sh_mobile_lcdc_start_stop(priv, 0);
744 priv->started = 0;
745 }
b51339ff 746
8564557a
MD		 747 /* stop clocks */
748 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
749 if (priv->ch[k].enabled)
750 sh_mobile_lcdc_clk_off(priv);
cfb4f5d1
MD		 751}
752
753static int sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan *ch)
754{
ce1c0b08
LP		 755 int interface_type = ch->cfg.interface_type;
756
757 switch (interface_type) {
758 case RGB8:
759 case RGB9:
760 case RGB12A:
761 case RGB12B:
762 case RGB16:
763 case RGB18:
764 case RGB24:
765 case SYS8A:
766 case SYS8B:
767 case SYS8C:
768 case SYS8D:
769 case SYS9:
770 case SYS12:
771 case SYS16A:
772 case SYS16B:
773 case SYS16C:
774 case SYS18:
775 case SYS24:
776 break;
777 default:
778 return -EINVAL;
cfb4f5d1
MD		 779 }
780
781 /* SUBLCD only supports SYS interface */
782 if (lcdc_chan_is_sublcd(ch)) {
ce1c0b08
LP		 783 if (!(interface_type & LDMT1R_IFM))
784 return -EINVAL;
785
786 interface_type &= ~LDMT1R_IFM;
cfb4f5d1
MD		 787 }
788
ce1c0b08 789 ch->ldmt1r_value = interface_type;
cfb4f5d1 790 return 0;
cfb4f5d1
MD		 791}
792
b51339ff
MD		 793static int sh_mobile_lcdc_setup_clocks(struct platform_device *pdev,
794 int clock_source,
cfb4f5d1
MD		 795 struct sh_mobile_lcdc_priv *priv)
796{
797 char *str;
cfb4f5d1
MD		 798
799 switch (clock_source) {
ce1c0b08
LP		 800 case LCDC_CLK_BUS:
801 str = "bus_clk";
802 priv->lddckr = LDDCKR_ICKSEL_BUS;
803 break;
804 case LCDC_CLK_PERIPHERAL:
805 str = "peripheral_clk";
806 priv->lddckr = LDDCKR_ICKSEL_MIPI;
807 break;
808 case LCDC_CLK_EXTERNAL:
809 str = NULL;
810 priv->lddckr = LDDCKR_ICKSEL_HDMI;
811 break;
cfb4f5d1
MD		 812 default:
813 return -EINVAL;
814 }
815
cfb4f5d1 816 if (str) {
b51339ff
MD		 817 priv->dot_clk = clk_get(&pdev->dev, str);
818 if (IS_ERR(priv->dot_clk)) {
819 dev_err(&pdev->dev, "cannot get dot clock %s\n", str);
b51339ff 820 return PTR_ERR(priv->dot_clk);
cfb4f5d1 821 }
cfb4f5d1 822 }
0246c471
MD		 823
824 /* Runtime PM support involves two step for this driver:
825 * 1) Enable Runtime PM
826 * 2) Force Runtime PM Resume since hardware is accessed from probe()
827 */
8bed9055 828 priv->dev = &pdev->dev;
0246c471
MD		 829 pm_runtime_enable(priv->dev);
830 pm_runtime_resume(priv->dev);
cfb4f5d1
MD		 831 return 0;
832}
833
834static int sh_mobile_lcdc_setcolreg(u_int regno,
835 u_int red, u_int green, u_int blue,
836 u_int transp, struct fb_info *info)
837{
838 u32 *palette = info->pseudo_palette;
839
840 if (regno >= PALETTE_NR)
841 return -EINVAL;
842
843 /* only FB_VISUAL_TRUECOLOR supported */
844
845 red >>= 16 - info->var.red.length;
846 green >>= 16 - info->var.green.length;
847 blue >>= 16 - info->var.blue.length;
848 transp >>= 16 - info->var.transp.length;
849
850 palette[regno] = (red << info->var.red.offset) |
851 (green << info->var.green.offset) |
852 (blue << info->var.blue.offset) |
853 (transp << info->var.transp.offset);
854
855 return 0;
856}
857
858static struct fb_fix_screeninfo sh_mobile_lcdc_fix = {
859 .id = "SH Mobile LCDC",
860 .type = FB_TYPE_PACKED_PIXELS,
861 .visual = FB_VISUAL_TRUECOLOR,
862 .accel = FB_ACCEL_NONE,
9dd38819
PE		 863 .xpanstep = 0,
864 .ypanstep = 1,
865 .ywrapstep = 0,
cfb4f5d1
MD		 866};
867
8564557a
MD		 868static void sh_mobile_lcdc_fillrect(struct fb_info *info,
869 const struct fb_fillrect *rect)
870{
871 sys_fillrect(info, rect);
872 sh_mobile_lcdc_deferred_io_touch(info);
873}
874
875static void sh_mobile_lcdc_copyarea(struct fb_info *info,
876 const struct fb_copyarea *area)
877{
878 sys_copyarea(info, area);
879 sh_mobile_lcdc_deferred_io_touch(info);
880}
881
882static void sh_mobile_lcdc_imageblit(struct fb_info *info,
883 const struct fb_image *image)
884{
885 sys_imageblit(info, image);
886 sh_mobile_lcdc_deferred_io_touch(info);
887}
888
9dd38819
PE		 889static int sh_mobile_fb_pan_display(struct fb_var_screeninfo *var,
890 struct fb_info *info)
891{
892 struct sh_mobile_lcdc_chan *ch = info->par;
92e1f9a7
PE		 893 struct sh_mobile_lcdc_priv *priv = ch->lcdc;
894 unsigned long ldrcntr;
895 unsigned long new_pan_offset;
53b50314
DHG		 896 unsigned long base_addr_y, base_addr_c;
897 unsigned long c_offset;
92e1f9a7 898
53b50314
DHG		 899 if (!var->nonstd)
900 new_pan_offset = (var->yoffset * info->fix.line_length) +
901 (var->xoffset * (info->var.bits_per_pixel / 8));
902 else
903 new_pan_offset = (var->yoffset * info->fix.line_length) +
904 (var->xoffset);
9dd38819 905
92e1f9a7 906 if (new_pan_offset == ch->pan_offset)
9dd38819
PE		 907 return 0; /* No change, do nothing */
908
92e1f9a7 909 ldrcntr = lcdc_read(priv, _LDRCNTR);
9dd38819 910
92e1f9a7 911 /* Set the source address for the next refresh */
53b50314
DHG		 912 base_addr_y = ch->dma_handle + new_pan_offset;
913 if (var->nonstd) {
914 /* Set y offset */
915 c_offset = (var->yoffset *
916 info->fix.line_length *
917 (info->var.bits_per_pixel - 8)) / 8;
918 base_addr_c = ch->dma_handle + var->xres * var->yres_virtual +
919 c_offset;
920 /* Set x offset */
921 if (info->var.bits_per_pixel == 24)
922 base_addr_c += 2 * var->xoffset;
923 else
924 base_addr_c += var->xoffset;
925 } else
926 base_addr_c = 0;
927
7caa4342
D		 928 if (!ch->meram_enabled) {
929 lcdc_write_chan_mirror(ch, LDSA1R, base_addr_y);
930 if (base_addr_c)
931 lcdc_write_chan_mirror(ch, LDSA2R, base_addr_c);
932 } else {
933 struct sh_mobile_meram_cfg *cfg;
934 struct sh_mobile_meram_info *mdev;
935 unsigned long icb_addr_y, icb_addr_c;
936 int ret;
937
938 cfg = ch->cfg.meram_cfg;
939 mdev = priv->meram_dev;
940 ret = mdev->ops->meram_update(mdev, cfg,
941 base_addr_y, base_addr_c,
942 &icb_addr_y, &icb_addr_c);
943 if (ret)
944 return ret;
945
946 lcdc_write_chan_mirror(ch, LDSA1R, icb_addr_y);
947 if (icb_addr_c)
948 lcdc_write_chan_mirror(ch, LDSA2R, icb_addr_c);
949
950 }
53b50314 951
92e1f9a7
PE		 952 if (lcdc_chan_is_sublcd(ch))
953 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_SRS);
954 else
955 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_MRS);
956
957 ch->pan_offset = new_pan_offset;
958
959 sh_mobile_lcdc_deferred_io_touch(info);
9dd38819
PE		 960
961 return 0;
962}
963
40331b21
PE		 964static int sh_mobile_wait_for_vsync(struct fb_info *info)
965{
966 struct sh_mobile_lcdc_chan *ch = info->par;
967 unsigned long ldintr;
968 int ret;
969
dc48665f
LP		 970 /* Enable VSync End interrupt and be careful not to acknowledge any
971 * pending interrupt.
972 */
40331b21 973 ldintr = lcdc_read(ch->lcdc, _LDINTR);
dc48665f 974 ldintr |= LDINTR_VEE | LDINTR_STATUS_MASK;
40331b21
PE		 975 lcdc_write(ch->lcdc, _LDINTR, ldintr);
976
977 ret = wait_for_completion_interruptible_timeout(&ch->vsync_completion,
978 msecs_to_jiffies(100));
979 if (!ret)
980 return -ETIMEDOUT;
981
982 return 0;
983}
984
985static int sh_mobile_ioctl(struct fb_info *info, unsigned int cmd,
986 unsigned long arg)
987{
988 int retval;
989
990 switch (cmd) {
991 case FBIO_WAITFORVSYNC:
992 retval = sh_mobile_wait_for_vsync(info);
993 break;
994
995 default:
996 retval = -ENOIOCTLCMD;
997 break;
998 }
999 return retval;
1000}
1001
dd210503
GL		 1002static void sh_mobile_fb_reconfig(struct fb_info *info)
1003{
1004 struct sh_mobile_lcdc_chan *ch = info->par;
1005 struct fb_videomode mode1, mode2;
1006 struct fb_event event;
1007 int evnt = FB_EVENT_MODE_CHANGE_ALL;
1008
1009 if (ch->use_count > 1 || (ch->use_count == 1 && !info->fbcon_par))
1010 /* More framebuffer users are active */
1011 return;
1012
1013 fb_var_to_videomode(&mode1, &ch->display_var);
1014 fb_var_to_videomode(&mode2, &info->var);
1015
1016 if (fb_mode_is_equal(&mode1, &mode2))
1017 return;
1018
1019 /* Display has been re-plugged, framebuffer is free now, reconfigure */
1020 if (fb_set_var(info, &ch->display_var) < 0)
1021 /* Couldn't reconfigure, hopefully, can continue as before */
1022 return;
1023
53b50314
DHG		 1024 if (info->var.nonstd)
1025 info->fix.line_length = mode1.xres;
1026 else
1027 info->fix.line_length = mode1.xres * (ch->cfg.bpp / 8);
dd210503
GL		 1028
1029 /*
1030 * fb_set_var() calls the notifier change internally, only if
1031 * FBINFO_MISC_USEREVENT flag is set. Since we do not want to fake a
1032 * user event, we have to call the chain ourselves.
1033 */
1034 event.info = info;
cc267ec5 1035 event.data = &mode1;
dd210503
GL		 1036 fb_notifier_call_chain(evnt, &event);
1037}
1038
1039/*
1040 * Locking: both .fb_release() and .fb_open() are called with info->lock held if
1041 * user == 1, or with console sem held, if user == 0.
1042 */
1043static int sh_mobile_release(struct fb_info *info, int user)
1044{
1045 struct sh_mobile_lcdc_chan *ch = info->par;
1046
1047 mutex_lock(&ch->open_lock);
1048 dev_dbg(info->dev, "%s(): %d users\n", __func__, ch->use_count);
1049
1050 ch->use_count--;
1051
1052 /* Nothing to reconfigure, when called from fbcon */
1053 if (user) {
ac751efa 1054 console_lock();
dd210503 1055 sh_mobile_fb_reconfig(info);
ac751efa 1056 console_unlock();
dd210503
GL		 1057 }
1058
1059 mutex_unlock(&ch->open_lock);
1060
1061 return 0;
1062}
1063
1064static int sh_mobile_open(struct fb_info *info, int user)
1065{
1066 struct sh_mobile_lcdc_chan *ch = info->par;
1067
1068 mutex_lock(&ch->open_lock);
1069 ch->use_count++;
1070
1071 dev_dbg(info->dev, "%s(): %d users\n", __func__, ch->use_count);
1072 mutex_unlock(&ch->open_lock);
1073
1074 return 0;
1075}
1076
1077static int sh_mobile_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1078{
1079 struct sh_mobile_lcdc_chan *ch = info->par;
417d4827 1080 struct sh_mobile_lcdc_priv *p = ch->lcdc;
dd210503 1081
d2ecbab5 1082 if (var->xres > MAX_XRES || var->yres > MAX_YRES ||
dd210503 1083 var->xres * var->yres * (ch->cfg.bpp / 8) * 2 > info->fix.smem_len) {
830539d1 1084 dev_warn(info->dev, "Invalid info: %u-%u-%u-%u x %u-%u-%u-%u @ %lukHz!\n",
d2ecbab5
GL		 1085 var->left_margin, var->xres, var->right_margin, var->hsync_len,
1086 var->upper_margin, var->yres, var->lower_margin, var->vsync_len,
1087 PICOS2KHZ(var->pixclock));
dd210503
GL		 1088 return -EINVAL;
1089 }
417d4827
MD		 1090
1091 /* only accept the forced_bpp for dual channel configurations */
1092 if (p->forced_bpp && p->forced_bpp != var->bits_per_pixel)
1093 return -EINVAL;
1094
1095 switch (var->bits_per_pixel) {
1096 case 16: /* PKF[4:0] = 00011 - RGB 565 */
1097 case 24: /* PKF[4:0] = 01011 - RGB 888 */
1098 case 32: /* PKF[4:0] = 00000 - RGBA 888 */
1099 break;
1100 default:
1101 return -EINVAL;
1102 }
1103
dd210503
GL		 1104 return 0;
1105}
40331b21 1106
8857b9aa
AC		 1107/*
1108 * Screen blanking. Behavior is as follows:
1109 * FB_BLANK_UNBLANK: screen unblanked, clocks enabled
1110 * FB_BLANK_NORMAL: screen blanked, clocks enabled
1111 * FB_BLANK_VSYNC,
1112 * FB_BLANK_HSYNC,
1113 * FB_BLANK_POWEROFF: screen blanked, clocks disabled
1114 */
1115static int sh_mobile_lcdc_blank(int blank, struct fb_info *info)
1116{
1117 struct sh_mobile_lcdc_chan *ch = info->par;
1118 struct sh_mobile_lcdc_priv *p = ch->lcdc;
1119
1120 /* blank the screen? */
1121 if (blank > FB_BLANK_UNBLANK && ch->blank_status == FB_BLANK_UNBLANK) {
1122 struct fb_fillrect rect = {
1123 .width = info->var.xres,
1124 .height = info->var.yres,
1125 };
1126 sh_mobile_lcdc_fillrect(info, &rect);
1127 }
1128 /* turn clocks on? */
1129 if (blank <= FB_BLANK_NORMAL && ch->blank_status > FB_BLANK_NORMAL) {
1130 sh_mobile_lcdc_clk_on(p);
1131 }
1132 /* turn clocks off? */
1133 if (blank > FB_BLANK_NORMAL && ch->blank_status <= FB_BLANK_NORMAL) {
1134 /* make sure the screen is updated with the black fill before
1135 * switching the clocks off. one vsync is not enough since
1136 * blanking may occur in the middle of a refresh. deferred io
1137 * mode will reenable the clocks and update the screen in time,
1138 * so it does not need this. */
1139 if (!info->fbdefio) {
1140 sh_mobile_wait_for_vsync(info);
1141 sh_mobile_wait_for_vsync(info);
1142 }
1143 sh_mobile_lcdc_clk_off(p);
1144 }
1145
1146 ch->blank_status = blank;
1147 return 0;
1148}
1149
cfb4f5d1 1150static struct fb_ops sh_mobile_lcdc_ops = {
9dd38819 1151 .owner = THIS_MODULE,
cfb4f5d1 1152 .fb_setcolreg = sh_mobile_lcdc_setcolreg,
2540c111
MD		 1153 .fb_read = fb_sys_read,
1154 .fb_write = fb_sys_write,
8564557a
MD		 1155 .fb_fillrect = sh_mobile_lcdc_fillrect,
1156 .fb_copyarea = sh_mobile_lcdc_copyarea,
1157 .fb_imageblit = sh_mobile_lcdc_imageblit,
8857b9aa 1158 .fb_blank = sh_mobile_lcdc_blank,
9dd38819 1159 .fb_pan_display = sh_mobile_fb_pan_display,
40331b21 1160 .fb_ioctl = sh_mobile_ioctl,
dd210503
GL		 1161 .fb_open = sh_mobile_open,
1162 .fb_release = sh_mobile_release,
1163 .fb_check_var = sh_mobile_check_var,
cfb4f5d1
MD		 1164};
1165
3b0fd9d7
AC		 1166static int sh_mobile_lcdc_update_bl(struct backlight_device *bdev)
1167{
1168 struct sh_mobile_lcdc_chan *ch = bl_get_data(bdev);
1169 struct sh_mobile_lcdc_board_cfg *cfg = &ch->cfg.board_cfg;
1170 int brightness = bdev->props.brightness;
1171
1172 if (bdev->props.power != FB_BLANK_UNBLANK ||
1173 bdev->props.state & (BL_CORE_SUSPENDED | BL_CORE_FBBLANK))
1174 brightness = 0;
1175
1176 return cfg->set_brightness(cfg->board_data, brightness);
1177}
1178
1179static int sh_mobile_lcdc_get_brightness(struct backlight_device *bdev)
1180{
1181 struct sh_mobile_lcdc_chan *ch = bl_get_data(bdev);
1182 struct sh_mobile_lcdc_board_cfg *cfg = &ch->cfg.board_cfg;
1183
1184 return cfg->get_brightness(cfg->board_data);
1185}
1186
1187static int sh_mobile_lcdc_check_fb(struct backlight_device *bdev,
1188 struct fb_info *info)
1189{
1190 return (info->bl_dev == bdev);
1191}
1192
1193static struct backlight_ops sh_mobile_lcdc_bl_ops = {
1194 .options = BL_CORE_SUSPENDRESUME,
1195 .update_status = sh_mobile_lcdc_update_bl,
1196 .get_brightness = sh_mobile_lcdc_get_brightness,
1197 .check_fb = sh_mobile_lcdc_check_fb,
1198};
1199
1200static struct backlight_device *sh_mobile_lcdc_bl_probe(struct device *parent,
1201 struct sh_mobile_lcdc_chan *ch)
1202{
1203 struct backlight_device *bl;
1204
1205 bl = backlight_device_register(ch->cfg.bl_info.name, parent, ch,
1206 &sh_mobile_lcdc_bl_ops, NULL);
beee1f20
DC		 1207 if (IS_ERR(bl)) {
1208 dev_err(parent, "unable to register backlight device: %ld\n",
1209 PTR_ERR(bl));
3b0fd9d7
AC		 1210 return NULL;
1211 }
1212
1213 bl->props.max_brightness = ch->cfg.bl_info.max_brightness;
1214 bl->props.brightness = bl->props.max_brightness;
1215 backlight_update_status(bl);
1216
1217 return bl;
1218}
1219
1220static void sh_mobile_lcdc_bl_remove(struct backlight_device *bdev)
1221{
1222 backlight_device_unregister(bdev);
1223}
1224
53b50314
DHG		 1225static int sh_mobile_lcdc_set_bpp(struct fb_var_screeninfo *var, int bpp,
1226 int nonstd)
cfb4f5d1 1227{
53b50314
DHG		 1228 if (nonstd) {
1229 switch (bpp) {
1230 case 12:
1231 case 16:
1232 case 24:
1233 var->bits_per_pixel = bpp;
1234 var->nonstd = nonstd;
1235 return 0;
1236 default:
1237 return -EINVAL;
1238 }
1239 }
1240
cfb4f5d1
MD		 1241 switch (bpp) {
1242 case 16: /* PKF[4:0] = 00011 - RGB 565 */
1243 var->red.offset = 11;
1244 var->red.length = 5;
1245 var->green.offset = 5;
1246 var->green.length = 6;
1247 var->blue.offset = 0;
1248 var->blue.length = 5;
1249 var->transp.offset = 0;
1250 var->transp.length = 0;
1251 break;
1252
417d4827
MD		 1253 case 24: /* PKF[4:0] = 01011 - RGB 888 */
1254 var->red.offset = 16;
cfb4f5d1 1255 var->red.length = 8;
417d4827 1256 var->green.offset = 8;
cfb4f5d1 1257 var->green.length = 8;
417d4827 1258 var->blue.offset = 0;
cfb4f5d1
MD		 1259 var->blue.length = 8;
1260 var->transp.offset = 0;
1261 var->transp.length = 0;
1262 break;
417d4827
MD		 1263
1264 case 32: /* PKF[4:0] = 00000 - RGBA 888 */
1265 var->red.offset = 16;
1266 var->red.length = 8;
1267 var->green.offset = 8;
1268 var->green.length = 8;
1269 var->blue.offset = 0;
1270 var->blue.length = 8;
1271 var->transp.offset = 24;
1272 var->transp.length = 8;
1273 break;
cfb4f5d1
MD		 1274 default:
1275 return -EINVAL;
1276 }
1277 var->bits_per_pixel = bpp;
1278 var->red.msb_right = 0;
1279 var->green.msb_right = 0;
1280 var->blue.msb_right = 0;
1281 var->transp.msb_right = 0;
1282 return 0;
1283}
1284
2feb075a
MD		 1285static int sh_mobile_lcdc_suspend(struct device *dev)
1286{
1287 struct platform_device *pdev = to_platform_device(dev);
1288
1289 sh_mobile_lcdc_stop(platform_get_drvdata(pdev));
1290 return 0;
1291}
1292
1293static int sh_mobile_lcdc_resume(struct device *dev)
1294{
1295 struct platform_device *pdev = to_platform_device(dev);
1296
1297 return sh_mobile_lcdc_start(platform_get_drvdata(pdev));
1298}
1299
0246c471
MD		 1300static int sh_mobile_lcdc_runtime_suspend(struct device *dev)
1301{
1302 struct platform_device *pdev = to_platform_device(dev);
1303 struct sh_mobile_lcdc_priv *p = platform_get_drvdata(pdev);
1304 struct sh_mobile_lcdc_chan *ch;
1305 int k, n;
1306
1307 /* save per-channel registers */
1308 for (k = 0; k < ARRAY_SIZE(p->ch); k++) {
1309 ch = &p->ch[k];
1310 if (!ch->enabled)
1311 continue;
1312 for (n = 0; n < NR_CH_REGS; n++)
1313 ch->saved_ch_regs[n] = lcdc_read_chan(ch, n);
1314 }
1315
1316 /* save shared registers */
1317 for (n = 0; n < NR_SHARED_REGS; n++)
1318 p->saved_shared_regs[n] = lcdc_read(p, lcdc_shared_regs[n]);
1319
1320 /* turn off LCDC hardware */
1321 lcdc_write(p, _LDCNT1R, 0);
1322 return 0;
1323}
1324
1325static int sh_mobile_lcdc_runtime_resume(struct device *dev)
1326{
1327 struct platform_device *pdev = to_platform_device(dev);
1328 struct sh_mobile_lcdc_priv *p = platform_get_drvdata(pdev);
1329 struct sh_mobile_lcdc_chan *ch;
1330 int k, n;
1331
1332 /* restore per-channel registers */
1333 for (k = 0; k < ARRAY_SIZE(p->ch); k++) {
1334 ch = &p->ch[k];
1335 if (!ch->enabled)
1336 continue;
1337 for (n = 0; n < NR_CH_REGS; n++)
1338 lcdc_write_chan(ch, n, ch->saved_ch_regs[n]);
1339 }
1340
1341 /* restore shared registers */
1342 for (n = 0; n < NR_SHARED_REGS; n++)
1343 lcdc_write(p, lcdc_shared_regs[n], p->saved_shared_regs[n]);
1344
1345 return 0;
1346}
1347
47145210 1348static const struct dev_pm_ops sh_mobile_lcdc_dev_pm_ops = {
2feb075a
MD		 1349 .suspend = sh_mobile_lcdc_suspend,
1350 .resume = sh_mobile_lcdc_resume,
0246c471
MD		 1351 .runtime_suspend = sh_mobile_lcdc_runtime_suspend,
1352 .runtime_resume = sh_mobile_lcdc_runtime_resume,
2feb075a
MD		 1353};
1354
6de9edd5 1355/* locking: called with info->lock held */
6011bdea
GL		 1356static int sh_mobile_lcdc_notify(struct notifier_block *nb,
1357 unsigned long action, void *data)
1358{
1359 struct fb_event *event = data;
1360 struct fb_info *info = event->info;
1361 struct sh_mobile_lcdc_chan *ch = info->par;
1362 struct sh_mobile_lcdc_board_cfg *board_cfg = &ch->cfg.board_cfg;
6011bdea
GL		 1363
1364 if (&ch->lcdc->notifier != nb)
baf16374 1365 return NOTIFY_DONE;
6011bdea
GL		 1366
1367 dev_dbg(info->dev, "%s(): action = %lu, data = %p\n",
1368 __func__, action, event->data);
1369
1370 switch(action) {
1371 case FB_EVENT_SUSPEND:
247f9938 1372 if (board_cfg->display_off && try_module_get(board_cfg->owner)) {
6011bdea 1373 board_cfg->display_off(board_cfg->board_data);
6de9edd5
GL		 1374 module_put(board_cfg->owner);
1375 }
afe417c0 1376 sh_mobile_lcdc_stop(ch->lcdc);
6011bdea
GL		 1377 break;
1378 case FB_EVENT_RESUME:
dd210503
GL		 1379 mutex_lock(&ch->open_lock);
1380 sh_mobile_fb_reconfig(info);
1381 mutex_unlock(&ch->open_lock);
6011bdea
GL		 1382
1383 /* HDMI must be enabled before LCDC configuration */
247f9938 1384 if (board_cfg->display_on && try_module_get(board_cfg->owner)) {
dd210503 1385 board_cfg->display_on(board_cfg->board_data, info);
6de9edd5 1386 module_put(board_cfg->owner);
6011bdea
GL		 1387 }
1388
ebe5e12d 1389 sh_mobile_lcdc_start(ch->lcdc);
6011bdea
GL		 1390 }
1391
baf16374 1392 return NOTIFY_OK;
6011bdea
GL		 1393}
1394
cfb4f5d1
MD		 1395static int sh_mobile_lcdc_remove(struct platform_device *pdev);
1396
c2e13037 1397static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev)
cfb4f5d1
MD		 1398{
1399 struct fb_info *info;
1400 struct sh_mobile_lcdc_priv *priv;
01ac25b5 1401 struct sh_mobile_lcdc_info *pdata = pdev->dev.platform_data;
cfb4f5d1
MD		 1402 struct resource *res;
1403 int error;
1404 void *buf;
1405 int i, j;
1406
01ac25b5 1407 if (!pdata) {
cfb4f5d1 1408 dev_err(&pdev->dev, "no platform data defined\n");
8bed9055 1409 return -EINVAL;
cfb4f5d1
MD		 1410 }
1411
1412 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8564557a
MD		 1413 i = platform_get_irq(pdev, 0);
1414 if (!res || i < 0) {
1415 dev_err(&pdev->dev, "cannot get platform resources\n");
8bed9055 1416 return -ENOENT;
cfb4f5d1
MD		 1417 }
1418
1419 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1420 if (!priv) {
1421 dev_err(&pdev->dev, "cannot allocate device data\n");
8bed9055 1422 return -ENOMEM;
cfb4f5d1
MD		 1423 }
1424
8bed9055
GL		 1425 platform_set_drvdata(pdev, priv);
1426
8564557a 1427 error = request_irq(i, sh_mobile_lcdc_irq, IRQF_DISABLED,
7ad33e74 1428 dev_name(&pdev->dev), priv);
8564557a
MD		 1429 if (error) {
1430 dev_err(&pdev->dev, "unable to request irq\n");
1431 goto err1;
1432 }
1433
1434 priv->irq = i;
5ef6b505 1435 atomic_set(&priv->hw_usecnt, -1);
cfb4f5d1
MD		 1436
1437 j = 0;
1438 for (i = 0; i < ARRAY_SIZE(pdata->ch); i++) {
01ac25b5 1439 struct sh_mobile_lcdc_chan *ch = priv->ch + j;
cfb4f5d1 1440
01ac25b5
GL		 1441 ch->lcdc = priv;
1442 memcpy(&ch->cfg, &pdata->ch[i], sizeof(pdata->ch[i]));
cfb4f5d1 1443
01ac25b5 1444 error = sh_mobile_lcdc_check_interface(ch);
cfb4f5d1
MD		 1445 if (error) {
1446 dev_err(&pdev->dev, "unsupported interface type\n");
1447 goto err1;
1448 }
01ac25b5
GL		 1449 init_waitqueue_head(&ch->frame_end_wait);
1450 init_completion(&ch->vsync_completion);
1451 ch->pan_offset = 0;
cfb4f5d1 1452
3b0fd9d7
AC		 1453 /* probe the backlight is there is one defined */
1454 if (ch->cfg.bl_info.max_brightness)
1455 ch->bl = sh_mobile_lcdc_bl_probe(&pdev->dev, ch);
1456
cfb4f5d1
MD		 1457 switch (pdata->ch[i].chan) {
1458 case LCDC_CHAN_MAINLCD:
ce1c0b08 1459 ch->enabled = LDCNT2R_ME;
01ac25b5 1460 ch->reg_offs = lcdc_offs_mainlcd;
cfb4f5d1
MD		 1461 j++;
1462 break;
1463 case LCDC_CHAN_SUBLCD:
ce1c0b08 1464 ch->enabled = LDCNT2R_SE;
01ac25b5 1465 ch->reg_offs = lcdc_offs_sublcd;
cfb4f5d1
MD		 1466 j++;
1467 break;
1468 }
1469 }
1470
1471 if (!j) {
1472 dev_err(&pdev->dev, "no channels defined\n");
1473 error = -EINVAL;
1474 goto err1;
1475 }
1476
417d4827
MD		 1477 /* for dual channel LCDC (MAIN + SUB) force shared bpp setting */
1478 if (j == 2)
1479 priv->forced_bpp = pdata->ch[0].bpp;
1480
dba6f385
GL		 1481 priv->base = ioremap_nocache(res->start, resource_size(res));
1482 if (!priv->base)
1483 goto err1;
1484
b51339ff 1485 error = sh_mobile_lcdc_setup_clocks(pdev, pdata->clock_source, priv);
cfb4f5d1
MD		 1486 if (error) {
1487 dev_err(&pdev->dev, "unable to setup clocks\n");
1488 goto err1;
1489 }
1490
7caa4342
D		 1491 priv->meram_dev = pdata->meram_dev;
1492
cfb4f5d1 1493 for (i = 0; i < j; i++) {
6011bdea 1494 struct fb_var_screeninfo *var;
71d3b0fc 1495 const struct fb_videomode *lcd_cfg, *max_cfg = NULL;
01ac25b5 1496 struct sh_mobile_lcdc_chan *ch = priv->ch + i;
c44f9f76
GL		 1497 struct sh_mobile_lcdc_chan_cfg *cfg = &ch->cfg;
1498 const struct fb_videomode *mode = cfg->lcd_cfg;
71d3b0fc
GL		 1499 unsigned long max_size = 0;
1500 int k;
5fd284e6 1501 int num_cfg;
cfb4f5d1 1502
01ac25b5
GL		 1503 ch->info = framebuffer_alloc(0, &pdev->dev);
1504 if (!ch->info) {
e33afddc
PM		 1505 dev_err(&pdev->dev, "unable to allocate fb_info\n");
1506 error = -ENOMEM;
1507 break;
1508 }
1509
01ac25b5 1510 info = ch->info;
6011bdea 1511 var = &info->var;
cfb4f5d1 1512 info->fbops = &sh_mobile_lcdc_ops;
c44f9f76 1513 info->par = ch;
dd210503
GL		 1514
1515 mutex_init(&ch->open_lock);
1516
c44f9f76
GL		 1517 for (k = 0, lcd_cfg = mode;
1518 k < cfg->num_cfg && lcd_cfg;
71d3b0fc
GL		 1519 k++, lcd_cfg++) {
1520 unsigned long size = lcd_cfg->yres * lcd_cfg->xres;
53b50314
DHG		 1521 /* NV12 buffers must have even number of lines */
1522 if ((cfg->nonstd) && cfg->bpp == 12 &&
1523 (lcd_cfg->yres & 0x1)) {
1524 dev_err(&pdev->dev, "yres must be multiple of 2"
1525 " for YCbCr420 mode.\n");
1526 error = -EINVAL;
1527 goto err1;
1528 }
71d3b0fc
GL		 1529
1530 if (size > max_size) {
1531 max_cfg = lcd_cfg;
1532 max_size = size;
1533 }
1534 }
1535
c44f9f76 1536 if (!mode)
d2ecbab5 1537 max_size = MAX_XRES * MAX_YRES;
c44f9f76
GL		 1538 else if (max_cfg)
1539 dev_dbg(&pdev->dev, "Found largest videomode %ux%u\n",
1540 max_cfg->xres, max_cfg->yres);
71d3b0fc 1541
cfb4f5d1 1542 info->fix = sh_mobile_lcdc_fix;
53b50314
DHG		 1543 info->fix.smem_len = max_size * 2 * cfg->bpp / 8;
1544
1545 /* Only pan in 2 line steps for NV12 */
1546 if (cfg->nonstd && cfg->bpp == 12)
1547 info->fix.ypanstep = 2;
cfb4f5d1 1548
5fd284e6 1549 if (!mode) {
c44f9f76 1550 mode = &default_720p;
5fd284e6
GL		 1551 num_cfg = 1;
1552 } else {
e0b9fb26 1553 num_cfg = cfg->num_cfg;
5fd284e6
GL		 1554 }
1555
1556 fb_videomode_to_modelist(mode, num_cfg, &info->modelist);
c44f9f76
GL		 1557
1558 fb_videomode_to_var(var, mode);
e0b9fb26
GL		 1559 var->width = cfg->lcd_size_cfg.width;
1560 var->height = cfg->lcd_size_cfg.height;
9dd38819 1561 /* Default Y virtual resolution is 2x panel size */
6011bdea 1562 var->yres_virtual = var->yres * 2;
6011bdea 1563 var->activate = FB_ACTIVATE_NOW;
6011bdea 1564
53b50314 1565 error = sh_mobile_lcdc_set_bpp(var, cfg->bpp, cfg->nonstd);
cfb4f5d1
MD		 1566 if (error)
1567 break;
1568
cfb4f5d1 1569 buf = dma_alloc_coherent(&pdev->dev, info->fix.smem_len,
01ac25b5 1570 &ch->dma_handle, GFP_KERNEL);
cfb4f5d1
MD		 1571 if (!buf) {
1572 dev_err(&pdev->dev, "unable to allocate buffer\n");
1573 error = -ENOMEM;
1574 break;
1575 }
1576
01ac25b5 1577 info->pseudo_palette = &ch->pseudo_palette;
cfb4f5d1
MD		 1578 info->flags = FBINFO_FLAG_DEFAULT;
1579
1580 error = fb_alloc_cmap(&info->cmap, PALETTE_NR, 0);
1581 if (error < 0) {
1582 dev_err(&pdev->dev, "unable to allocate cmap\n");
1583 dma_free_coherent(&pdev->dev, info->fix.smem_len,
01ac25b5 1584 buf, ch->dma_handle);
cfb4f5d1
MD		 1585 break;
1586 }
1587
01ac25b5 1588 info->fix.smem_start = ch->dma_handle;
53b50314
DHG		 1589 if (var->nonstd)
1590 info->fix.line_length = var->xres;
1591 else
1592 info->fix.line_length = var->xres * (cfg->bpp / 8);
1593
cfb4f5d1
MD		 1594 info->screen_base = buf;
1595 info->device = &pdev->dev;
1c120deb 1596 ch->display_var = *var;
cfb4f5d1
MD		 1597 }
1598
1599 if (error)
1600 goto err1;
1601
1602 error = sh_mobile_lcdc_start(priv);
1603 if (error) {
1604 dev_err(&pdev->dev, "unable to start hardware\n");
1605 goto err1;
1606 }
1607
1608 for (i = 0; i < j; i++) {
1c6a307a
PM		 1609 struct sh_mobile_lcdc_chan *ch = priv->ch + i;
1610
e33afddc 1611 info = ch->info;
1c6a307a
PM		 1612
1613 if (info->fbdefio) {
8bed9055 1614 ch->sglist = vmalloc(sizeof(struct scatterlist) *
1c6a307a 1615 info->fix.smem_len >> PAGE_SHIFT);
8bed9055 1616 if (!ch->sglist) {
1c6a307a
PM		 1617 dev_err(&pdev->dev, "cannot allocate sglist\n");
1618 goto err1;
1619 }
1620 }
1621
3b0fd9d7
AC		 1622 info->bl_dev = ch->bl;
1623
1c6a307a 1624 error = register_framebuffer(info);
cfb4f5d1
MD		 1625 if (error < 0)
1626 goto err1;
cfb4f5d1 1627
cfb4f5d1
MD		 1628 dev_info(info->dev,
1629 "registered %s/%s as %dx%d %dbpp.\n",
1630 pdev->name,
1c6a307a 1631 (ch->cfg.chan == LCDC_CHAN_MAINLCD) ?
cfb4f5d1 1632 "mainlcd" : "sublcd",
c44f9f76 1633 info->var.xres, info->var.yres,
1c6a307a 1634 ch->cfg.bpp);
8564557a
MD		 1635
1636 /* deferred io mode: disable clock to save power */
6011bdea 1637 if (info->fbdefio || info->state == FBINFO_STATE_SUSPENDED)
8564557a 1638 sh_mobile_lcdc_clk_off(priv);
cfb4f5d1
MD		 1639 }
1640
6011bdea
GL		 1641 /* Failure ignored */
1642 priv->notifier.notifier_call = sh_mobile_lcdc_notify;
1643 fb_register_client(&priv->notifier);
1644
cfb4f5d1 1645 return 0;
8bed9055 1646err1:
cfb4f5d1 1647 sh_mobile_lcdc_remove(pdev);
8bed9055 1648
cfb4f5d1
MD		 1649 return error;
1650}
1651
1652static int sh_mobile_lcdc_remove(struct platform_device *pdev)
1653{
1654 struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
1655 struct fb_info *info;
1656 int i;
1657
6011bdea
GL		 1658 fb_unregister_client(&priv->notifier);
1659
cfb4f5d1 1660 for (i = 0; i < ARRAY_SIZE(priv->ch); i++)
8bed9055 1661 if (priv->ch[i].info && priv->ch[i].info->dev)
e33afddc 1662 unregister_framebuffer(priv->ch[i].info);
cfb4f5d1
MD		 1663
1664 sh_mobile_lcdc_stop(priv);
1665
1666 for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
e33afddc 1667 info = priv->ch[i].info;
cfb4f5d1 1668
e33afddc 1669 if (!info || !info->device)
cfb4f5d1
MD		 1670 continue;
1671
1c6a307a
PM		 1672 if (priv->ch[i].sglist)
1673 vfree(priv->ch[i].sglist);
1674
1ffbb037
MD		 1675 if (info->screen_base)
1676 dma_free_coherent(&pdev->dev, info->fix.smem_len,
1677 info->screen_base,
1678 priv->ch[i].dma_handle);
cfb4f5d1 1679 fb_dealloc_cmap(&info->cmap);
e33afddc 1680 framebuffer_release(info);
cfb4f5d1
MD		 1681 }
1682
3b0fd9d7
AC		 1683 for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
1684 if (priv->ch[i].bl)
1685 sh_mobile_lcdc_bl_remove(priv->ch[i].bl);
1686 }
1687
b51339ff
MD		 1688 if (priv->dot_clk)
1689 clk_put(priv->dot_clk);
0246c471 1690
8bed9055
GL		 1691 if (priv->dev)
1692 pm_runtime_disable(priv->dev);
cfb4f5d1
MD		 1693
1694 if (priv->base)
1695 iounmap(priv->base);
1696
8564557a
MD		 1697 if (priv->irq)
1698 free_irq(priv->irq, priv);
cfb4f5d1
MD		 1699 kfree(priv);
1700 return 0;
1701}
1702
1703static struct platform_driver sh_mobile_lcdc_driver = {
1704 .driver = {
1705 .name = "sh_mobile_lcdc_fb",
1706 .owner = THIS_MODULE,
2feb075a 1707 .pm = &sh_mobile_lcdc_dev_pm_ops,
cfb4f5d1
MD		 1708 },
1709 .probe = sh_mobile_lcdc_probe,
1710 .remove = sh_mobile_lcdc_remove,
1711};
1712
1713static int __init sh_mobile_lcdc_init(void)
1714{
1715 return platform_driver_register(&sh_mobile_lcdc_driver);
1716}
1717
1718static void __exit sh_mobile_lcdc_exit(void)
1719{
1720 platform_driver_unregister(&sh_mobile_lcdc_driver);
1721}
1722
1723module_init(sh_mobile_lcdc_init);
1724module_exit(sh_mobile_lcdc_exit);
1725
1726MODULE_DESCRIPTION("SuperH Mobile LCDC Framebuffer driver");
1727MODULE_AUTHOR("Magnus Damm <damm@opensource.se>");
1728MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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