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fbdev: sh_mobile_lcdcfb: fix more error paths
[deliverable/linux.git] / drivers / video / sh_mobile_lcdcfb.c
CommitLineData
cfb4f5d1
MD		 1/*
2 * SuperH Mobile LCDC Framebuffer
3 *
4 * Copyright (c) 2008 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/delay.h>
14#include <linux/mm.h>
15#include <linux/fb.h>
16#include <linux/clk.h>
0246c471 17#include <linux/pm_runtime.h>
cfb4f5d1
MD		 18#include <linux/platform_device.h>
19#include <linux/dma-mapping.h>
8564557a 20#include <linux/interrupt.h>
1c6a307a 21#include <linux/vmalloc.h>
40331b21 22#include <linux/ioctl.h>
5a0e3ad6 23#include <linux/slab.h>
225c9a8d 24#include <video/sh_mobile_lcdc.h>
8564557a 25#include <asm/atomic.h>
cfb4f5d1
MD		 26
27#define PALETTE_NR 16
a6f15ade
PE		 28#define SIDE_B_OFFSET 0x1000
29#define MIRROR_OFFSET 0x2000
cfb4f5d1 30
cfb4f5d1
MD		 31/* shared registers */
32#define _LDDCKR 0x410
33#define _LDDCKSTPR 0x414
34#define _LDINTR 0x468
35#define _LDSR 0x46c
36#define _LDCNT1R 0x470
37#define _LDCNT2R 0x474
9dd38819 38#define _LDRCNTR 0x478
cfb4f5d1
MD		 39#define _LDDDSR 0x47c
40#define _LDDWD0R 0x800
41#define _LDDRDR 0x840
42#define _LDDWAR 0x900
43#define _LDDRAR 0x904
44
0246c471
MD		 45/* shared registers and their order for context save/restore */
46static int lcdc_shared_regs[] = {
47 _LDDCKR,
48 _LDDCKSTPR,
49 _LDINTR,
50 _LDDDSR,
51 _LDCNT1R,
52 _LDCNT2R,
53};
54#define NR_SHARED_REGS ARRAY_SIZE(lcdc_shared_regs)
55
cfb4f5d1
MD		 56/* per-channel registers */
57enum { LDDCKPAT1R, LDDCKPAT2R, LDMT1R, LDMT2R, LDMT3R, LDDFR, LDSM1R,
0246c471 58 LDSM2R, LDSA1R, LDMLSR, LDHCNR, LDHSYNR, LDVLNR, LDVSYNR, LDPMR,
6011bdea 59 LDHAJR,
0246c471 60 NR_CH_REGS };
cfb4f5d1 61
0246c471 62static unsigned long lcdc_offs_mainlcd[NR_CH_REGS] = {
cfb4f5d1
MD		 63 [LDDCKPAT1R] = 0x400,
64 [LDDCKPAT2R] = 0x404,
65 [LDMT1R] = 0x418,
66 [LDMT2R] = 0x41c,
67 [LDMT3R] = 0x420,
68 [LDDFR] = 0x424,
69 [LDSM1R] = 0x428,
8564557a 70 [LDSM2R] = 0x42c,
cfb4f5d1
MD		 71 [LDSA1R] = 0x430,
72 [LDMLSR] = 0x438,
73 [LDHCNR] = 0x448,
74 [LDHSYNR] = 0x44c,
75 [LDVLNR] = 0x450,
76 [LDVSYNR] = 0x454,
77 [LDPMR] = 0x460,
6011bdea 78 [LDHAJR] = 0x4a0,
cfb4f5d1
MD		 79};
80
0246c471 81static unsigned long lcdc_offs_sublcd[NR_CH_REGS] = {
cfb4f5d1
MD		 82 [LDDCKPAT1R] = 0x408,
83 [LDDCKPAT2R] = 0x40c,
84 [LDMT1R] = 0x600,
85 [LDMT2R] = 0x604,
86 [LDMT3R] = 0x608,
87 [LDDFR] = 0x60c,
88 [LDSM1R] = 0x610,
8564557a 89 [LDSM2R] = 0x614,
cfb4f5d1
MD		 90 [LDSA1R] = 0x618,
91 [LDMLSR] = 0x620,
92 [LDHCNR] = 0x624,
93 [LDHSYNR] = 0x628,
94 [LDVLNR] = 0x62c,
95 [LDVSYNR] = 0x630,
96 [LDPMR] = 0x63c,
97};
98
99#define START_LCDC 0x00000001
100#define LCDC_RESET 0x00000100
101#define DISPLAY_BEU 0x00000008
102#define LCDC_ENABLE 0x00000001
8564557a 103#define LDINTR_FE 0x00000400
9dd38819
PE		 104#define LDINTR_VSE 0x00000200
105#define LDINTR_VEE 0x00000100
8564557a 106#define LDINTR_FS 0x00000004
9dd38819
PE		 107#define LDINTR_VSS 0x00000002
108#define LDINTR_VES 0x00000001
a6f15ade
PE		 109#define LDRCNTR_SRS 0x00020000
110#define LDRCNTR_SRC 0x00010000
111#define LDRCNTR_MRS 0x00000002
112#define LDRCNTR_MRC 0x00000001
40331b21 113#define LDSR_MRS 0x00000100
cfb4f5d1 114
0246c471
MD		 115struct sh_mobile_lcdc_priv;
116struct sh_mobile_lcdc_chan {
117 struct sh_mobile_lcdc_priv *lcdc;
118 unsigned long *reg_offs;
119 unsigned long ldmt1r_value;
120 unsigned long enabled; /* ME and SE in LDCNT2R */
121 struct sh_mobile_lcdc_chan_cfg cfg;
122 u32 pseudo_palette[PALETTE_NR];
123 unsigned long saved_ch_regs[NR_CH_REGS];
124 struct fb_info *info;
125 dma_addr_t dma_handle;
126 struct fb_deferred_io defio;
127 struct scatterlist *sglist;
128 unsigned long frame_end;
9dd38819 129 unsigned long pan_offset;
0246c471 130 wait_queue_head_t frame_end_wait;
40331b21 131 struct completion vsync_completion;
0246c471
MD		 132};
133
134struct sh_mobile_lcdc_priv {
135 void __iomem *base;
136 int irq;
137 atomic_t hw_usecnt;
138 struct device *dev;
139 struct clk *dot_clk;
140 unsigned long lddckr;
141 struct sh_mobile_lcdc_chan ch[2];
6011bdea 142 struct notifier_block notifier;
0246c471
MD		 143 unsigned long saved_shared_regs[NR_SHARED_REGS];
144 int started;
145};
146
a6f15ade
PE		 147static bool banked(int reg_nr)
148{
149 switch (reg_nr) {
150 case LDMT1R:
151 case LDMT2R:
152 case LDMT3R:
153 case LDDFR:
154 case LDSM1R:
155 case LDSA1R:
156 case LDMLSR:
157 case LDHCNR:
158 case LDHSYNR:
159 case LDVLNR:
160 case LDVSYNR:
161 return true;
162 }
163 return false;
164}
165
cfb4f5d1
MD		 166static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan,
167 int reg_nr, unsigned long data)
168{
169 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]);
a6f15ade
PE		 170 if (banked(reg_nr))
171 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
172 SIDE_B_OFFSET);
173}
174
175static void lcdc_write_chan_mirror(struct sh_mobile_lcdc_chan *chan,
176 int reg_nr, unsigned long data)
177{
178 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
179 MIRROR_OFFSET);
cfb4f5d1
MD		 180}
181
182static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan,
183 int reg_nr)
184{
185 return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]);
186}
187
188static void lcdc_write(struct sh_mobile_lcdc_priv *priv,
189 unsigned long reg_offs, unsigned long data)
190{
191 iowrite32(data, priv->base + reg_offs);
192}
193
194static unsigned long lcdc_read(struct sh_mobile_lcdc_priv *priv,
195 unsigned long reg_offs)
196{
197 return ioread32(priv->base + reg_offs);
198}
199
200static void lcdc_wait_bit(struct sh_mobile_lcdc_priv *priv,
201 unsigned long reg_offs,
202 unsigned long mask, unsigned long until)
203{
204 while ((lcdc_read(priv, reg_offs) & mask) != until)
205 cpu_relax();
206}
207
208static int lcdc_chan_is_sublcd(struct sh_mobile_lcdc_chan *chan)
209{
210 return chan->cfg.chan == LCDC_CHAN_SUBLCD;
211}
212
213static void lcdc_sys_write_index(void *handle, unsigned long data)
214{
215 struct sh_mobile_lcdc_chan *ch = handle;
216
217 lcdc_write(ch->lcdc, _LDDWD0R, data | 0x10000000);
218 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
219 lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
909f10de 220 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
cfb4f5d1
MD		 221}
222
223static void lcdc_sys_write_data(void *handle, unsigned long data)
224{
225 struct sh_mobile_lcdc_chan *ch = handle;
226
227 lcdc_write(ch->lcdc, _LDDWD0R, data | 0x11000000);
228 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
229 lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
909f10de 230 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
cfb4f5d1
MD		 231}
232
233static unsigned long lcdc_sys_read_data(void *handle)
234{
235 struct sh_mobile_lcdc_chan *ch = handle;
236
237 lcdc_write(ch->lcdc, _LDDRDR, 0x01000000);
238 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
239 lcdc_write(ch->lcdc, _LDDRAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
240 udelay(1);
909f10de 241 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
cfb4f5d1 242
ec56b66f 243 return lcdc_read(ch->lcdc, _LDDRDR) & 0x3ffff;
cfb4f5d1
MD		 244}
245
246struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = {
247 lcdc_sys_write_index,
248 lcdc_sys_write_data,
249 lcdc_sys_read_data,
250};
251
8564557a
MD		 252static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv)
253{
0246c471
MD		 254 if (atomic_inc_and_test(&priv->hw_usecnt)) {
255 pm_runtime_get_sync(priv->dev);
8564557a
MD		 256 if (priv->dot_clk)
257 clk_enable(priv->dot_clk);
258 }
259}
260
261static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv)
262{
0246c471 263 if (atomic_sub_return(1, &priv->hw_usecnt) == -1) {
8564557a
MD		 264 if (priv->dot_clk)
265 clk_disable(priv->dot_clk);
0246c471 266 pm_runtime_put(priv->dev);
8564557a
MD		 267 }
268}
8564557a 269
1c6a307a
PM		 270static int sh_mobile_lcdc_sginit(struct fb_info *info,
271 struct list_head *pagelist)
272{
273 struct sh_mobile_lcdc_chan *ch = info->par;
274 unsigned int nr_pages_max = info->fix.smem_len >> PAGE_SHIFT;
275 struct page *page;
276 int nr_pages = 0;
277
278 sg_init_table(ch->sglist, nr_pages_max);
279
280 list_for_each_entry(page, pagelist, lru)
281 sg_set_page(&ch->sglist[nr_pages++], page, PAGE_SIZE, 0);
282
283 return nr_pages;
284}
285
8564557a
MD		 286static void sh_mobile_lcdc_deferred_io(struct fb_info *info,
287 struct list_head *pagelist)
288{
289 struct sh_mobile_lcdc_chan *ch = info->par;
ef61aae4 290 struct sh_mobile_lcdc_board_cfg *bcfg = &ch->cfg.board_cfg;
8564557a
MD		 291
292 /* enable clocks before accessing hardware */
293 sh_mobile_lcdc_clk_on(ch->lcdc);
294
5c1a56b5
PM		 295 /*
296 * It's possible to get here without anything on the pagelist via
297 * sh_mobile_lcdc_deferred_io_touch() or via a userspace fsync()
298 * invocation. In the former case, the acceleration routines are
299 * stepped in to when using the framebuffer console causing the
300 * workqueue to be scheduled without any dirty pages on the list.
301 *
302 * Despite this, a panel update is still needed given that the
303 * acceleration routines have their own methods for writing in
304 * that still need to be updated.
305 *
306 * The fsync() and empty pagelist case could be optimized for,
307 * but we don't bother, as any application exhibiting such
308 * behaviour is fundamentally broken anyways.
309 */
310 if (!list_empty(pagelist)) {
311 unsigned int nr_pages = sh_mobile_lcdc_sginit(info, pagelist);
312
313 /* trigger panel update */
314 dma_map_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
ef61aae4
MD		 315 if (bcfg->start_transfer)
316 bcfg->start_transfer(bcfg->board_data, ch,
317 &sh_mobile_lcdc_sys_bus_ops);
5c1a56b5
PM		 318 lcdc_write_chan(ch, LDSM2R, 1);
319 dma_unmap_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
ef61aae4
MD		 320 } else {
321 if (bcfg->start_transfer)
322 bcfg->start_transfer(bcfg->board_data, ch,
323 &sh_mobile_lcdc_sys_bus_ops);
5c1a56b5 324 lcdc_write_chan(ch, LDSM2R, 1);
ef61aae4 325 }
8564557a
MD		 326}
327
328static void sh_mobile_lcdc_deferred_io_touch(struct fb_info *info)
329{
330 struct fb_deferred_io *fbdefio = info->fbdefio;
331
332 if (fbdefio)
333 schedule_delayed_work(&info->deferred_work, fbdefio->delay);
334}
335
336static irqreturn_t sh_mobile_lcdc_irq(int irq, void *data)
337{
338 struct sh_mobile_lcdc_priv *priv = data;
2feb075a 339 struct sh_mobile_lcdc_chan *ch;
8564557a 340 unsigned long tmp;
9dd38819 341 unsigned long ldintr;
2feb075a
MD		 342 int is_sub;
343 int k;
8564557a
MD		 344
345 /* acknowledge interrupt */
9dd38819
PE		 346 ldintr = tmp = lcdc_read(priv, _LDINTR);
347 /*
348 * disable further VSYNC End IRQs, preserve all other enabled IRQs,
349 * write 0 to bits 0-6 to ack all triggered IRQs.
350 */
351 tmp &= 0xffffff00 & ~LDINTR_VEE;
8564557a
MD		 352 lcdc_write(priv, _LDINTR, tmp);
353
2feb075a
MD		 354 /* figure out if this interrupt is for main or sub lcd */
355 is_sub = (lcdc_read(priv, _LDSR) & (1 << 10)) ? 1 : 0;
356
9dd38819 357 /* wake up channel and disable clocks */
2feb075a
MD		 358 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
359 ch = &priv->ch[k];
360
361 if (!ch->enabled)
362 continue;
363
9dd38819
PE		 364 /* Frame Start */
365 if (ldintr & LDINTR_FS) {
366 if (is_sub == lcdc_chan_is_sublcd(ch)) {
367 ch->frame_end = 1;
368 wake_up(&ch->frame_end_wait);
2feb075a 369
9dd38819
PE		 370 sh_mobile_lcdc_clk_off(priv);
371 }
372 }
373
374 /* VSYNC End */
40331b21
PE		 375 if (ldintr & LDINTR_VES)
376 complete(&ch->vsync_completion);
2feb075a
MD		 377 }
378
8564557a
MD		 379 return IRQ_HANDLED;
380}
381
cfb4f5d1
MD		 382static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv *priv,
383 int start)
384{
385 unsigned long tmp = lcdc_read(priv, _LDCNT2R);
386 int k;
387
388 /* start or stop the lcdc */
389 if (start)
390 lcdc_write(priv, _LDCNT2R, tmp | START_LCDC);
391 else
392 lcdc_write(priv, _LDCNT2R, tmp & ~START_LCDC);
393
394 /* wait until power is applied/stopped on all channels */
395 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
396 if (lcdc_read(priv, _LDCNT2R) & priv->ch[k].enabled)
397 while (1) {
398 tmp = lcdc_read_chan(&priv->ch[k], LDPMR) & 3;
399 if (start && tmp == 3)
400 break;
401 if (!start && tmp == 0)
402 break;
403 cpu_relax();
404 }
405
406 if (!start)
407 lcdc_write(priv, _LDDCKSTPR, 1); /* stop dotclock */
408}
409
6011bdea
GL		 410static void sh_mobile_lcdc_geometry(struct sh_mobile_lcdc_chan *ch)
411{
412 struct fb_var_screeninfo *var = &ch->info->var;
413 unsigned long h_total, hsync_pos;
414 u32 tmp;
415
416 tmp = ch->ldmt1r_value;
417 tmp |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1 << 28;
418 tmp |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1 << 27;
419 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWPOL) ? 1 << 26 : 0;
420 tmp |= (ch->cfg.flags & LCDC_FLAGS_DIPOL) ? 1 << 25 : 0;
421 tmp |= (ch->cfg.flags & LCDC_FLAGS_DAPOL) ? 1 << 24 : 0;
422 tmp |= (ch->cfg.flags & LCDC_FLAGS_HSCNT) ? 1 << 17 : 0;
423 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWCNT) ? 1 << 16 : 0;
424 lcdc_write_chan(ch, LDMT1R, tmp);
425
426 /* setup SYS bus */
427 lcdc_write_chan(ch, LDMT2R, ch->cfg.sys_bus_cfg.ldmt2r);
428 lcdc_write_chan(ch, LDMT3R, ch->cfg.sys_bus_cfg.ldmt3r);
429
430 /* horizontal configuration */
431 h_total = var->xres + var->hsync_len +
432 var->left_margin + var->right_margin;
433 tmp = h_total / 8; /* HTCN */
434 tmp |= (var->xres / 8) << 16; /* HDCN */
435 lcdc_write_chan(ch, LDHCNR, tmp);
436
437 hsync_pos = var->xres + var->right_margin;
438 tmp = hsync_pos / 8; /* HSYNP */
439 tmp |= (var->hsync_len / 8) << 16; /* HSYNW */
440 lcdc_write_chan(ch, LDHSYNR, tmp);
441
442 /* vertical configuration */
443 tmp = var->yres + var->vsync_len +
444 var->upper_margin + var->lower_margin; /* VTLN */
445 tmp |= var->yres << 16; /* VDLN */
446 lcdc_write_chan(ch, LDVLNR, tmp);
447
448 tmp = var->yres + var->lower_margin; /* VSYNP */
449 tmp |= var->vsync_len << 16; /* VSYNW */
450 lcdc_write_chan(ch, LDVSYNR, tmp);
451
452 /* Adjust horizontal synchronisation for HDMI */
453 tmp = ((var->xres & 7) << 24) |
454 ((h_total & 7) << 16) |
455 ((var->hsync_len & 7) << 8) |
456 hsync_pos;
457 lcdc_write_chan(ch, LDHAJR, tmp);
458}
459
cfb4f5d1
MD		 460static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
461{
462 struct sh_mobile_lcdc_chan *ch;
463 struct fb_videomode *lcd_cfg;
464 struct sh_mobile_lcdc_board_cfg *board_cfg;
465 unsigned long tmp;
466 int k, m;
467 int ret = 0;
468
8564557a
MD		 469 /* enable clocks before accessing the hardware */
470 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
471 if (priv->ch[k].enabled)
472 sh_mobile_lcdc_clk_on(priv);
473
cfb4f5d1
MD		 474 /* reset */
475 lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LCDC_RESET);
476 lcdc_wait_bit(priv, _LDCNT2R, LCDC_RESET, 0);
477
478 /* enable LCDC channels */
479 tmp = lcdc_read(priv, _LDCNT2R);
480 tmp |= priv->ch[0].enabled;
481 tmp |= priv->ch[1].enabled;
482 lcdc_write(priv, _LDCNT2R, tmp);
483
484 /* read data from external memory, avoid using the BEU for now */
485 lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) & ~DISPLAY_BEU);
486
487 /* stop the lcdc first */
488 sh_mobile_lcdc_start_stop(priv, 0);
489
490 /* configure clocks */
491 tmp = priv->lddckr;
492 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
493 ch = &priv->ch[k];
494
495 if (!priv->ch[k].enabled)
496 continue;
497
498 m = ch->cfg.clock_divider;
499 if (!m)
500 continue;
501
502 if (m == 1)
503 m = 1 << 6;
504 tmp |= m << (lcdc_chan_is_sublcd(ch) ? 8 : 0);
505
506 lcdc_write_chan(ch, LDDCKPAT1R, 0x00000000);
507 lcdc_write_chan(ch, LDDCKPAT2R, (1 << (m/2)) - 1);
508 }
509
510 lcdc_write(priv, _LDDCKR, tmp);
511
512 /* start dotclock again */
513 lcdc_write(priv, _LDDCKSTPR, 0);
514 lcdc_wait_bit(priv, _LDDCKSTPR, ~0, 0);
515
8564557a 516 /* interrupts are disabled to begin with */
cfb4f5d1
MD		 517 lcdc_write(priv, _LDINTR, 0);
518
519 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
520 ch = &priv->ch[k];
521 lcd_cfg = &ch->cfg.lcd_cfg;
522
523 if (!ch->enabled)
524 continue;
525
6011bdea 526 sh_mobile_lcdc_geometry(ch);
cfb4f5d1
MD		 527
528 /* power supply */
529 lcdc_write_chan(ch, LDPMR, 0);
530
cfb4f5d1
MD		 531 board_cfg = &ch->cfg.board_cfg;
532 if (board_cfg->setup_sys)
533 ret = board_cfg->setup_sys(board_cfg->board_data, ch,
534 &sh_mobile_lcdc_sys_bus_ops);
535 if (ret)
536 return ret;
537 }
538
cfb4f5d1
MD		 539 /* word and long word swap */
540 lcdc_write(priv, _LDDDSR, lcdc_read(priv, _LDDDSR) | 6);
541
542 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
543 ch = &priv->ch[k];
544
545 if (!priv->ch[k].enabled)
546 continue;
547
548 /* set bpp format in PKF[4:0] */
549 tmp = lcdc_read_chan(ch, LDDFR);
550 tmp &= ~(0x0001001f);
e33afddc 551 tmp |= (ch->info->var.bits_per_pixel == 16) ? 3 : 0;
cfb4f5d1
MD		 552 lcdc_write_chan(ch, LDDFR, tmp);
553
554 /* point out our frame buffer */
e33afddc 555 lcdc_write_chan(ch, LDSA1R, ch->info->fix.smem_start);
cfb4f5d1
MD		 556
557 /* set line size */
e33afddc 558 lcdc_write_chan(ch, LDMLSR, ch->info->fix.line_length);
cfb4f5d1 559
8564557a
MD		 560 /* setup deferred io if SYS bus */
561 tmp = ch->cfg.sys_bus_cfg.deferred_io_msec;
562 if (ch->ldmt1r_value & (1 << 12) && tmp) {
563 ch->defio.deferred_io = sh_mobile_lcdc_deferred_io;
564 ch->defio.delay = msecs_to_jiffies(tmp);
e33afddc
PM		 565 ch->info->fbdefio = &ch->defio;
566 fb_deferred_io_init(ch->info);
8564557a
MD		 567
568 /* one-shot mode */
569 lcdc_write_chan(ch, LDSM1R, 1);
570
571 /* enable "Frame End Interrupt Enable" bit */
572 lcdc_write(priv, _LDINTR, LDINTR_FE);
573
574 } else {
575 /* continuous read mode */
576 lcdc_write_chan(ch, LDSM1R, 0);
577 }
cfb4f5d1
MD		 578 }
579
580 /* display output */
581 lcdc_write(priv, _LDCNT1R, LCDC_ENABLE);
582
583 /* start the lcdc */
584 sh_mobile_lcdc_start_stop(priv, 1);
8e9bb19e 585 priv->started = 1;
cfb4f5d1
MD		 586
587 /* tell the board code to enable the panel */
588 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
589 ch = &priv->ch[k];
21bc1f02
MD		 590 if (!ch->enabled)
591 continue;
592
cfb4f5d1
MD		 593 board_cfg = &ch->cfg.board_cfg;
594 if (board_cfg->display_on)
c2439398 595 board_cfg->display_on(board_cfg->board_data, ch->info);
cfb4f5d1
MD		 596 }
597
598 return 0;
599}
600
601static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
602{
603 struct sh_mobile_lcdc_chan *ch;
604 struct sh_mobile_lcdc_board_cfg *board_cfg;
605 int k;
606
2feb075a 607 /* clean up deferred io and ask board code to disable panel */
cfb4f5d1
MD		 608 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
609 ch = &priv->ch[k];
21bc1f02
MD		 610 if (!ch->enabled)
611 continue;
8564557a 612
2feb075a
MD		 613 /* deferred io mode:
614 * flush frame, and wait for frame end interrupt
615 * clean up deferred io and enable clock
616 */
5ef6b505 617 if (ch->info && ch->info->fbdefio) {
2feb075a 618 ch->frame_end = 0;
e33afddc 619 schedule_delayed_work(&ch->info->deferred_work, 0);
2feb075a 620 wait_event(ch->frame_end_wait, ch->frame_end);
e33afddc
PM		 621 fb_deferred_io_cleanup(ch->info);
622 ch->info->fbdefio = NULL;
2feb075a 623 sh_mobile_lcdc_clk_on(priv);
8564557a 624 }
2feb075a
MD		 625
626 board_cfg = &ch->cfg.board_cfg;
627 if (board_cfg->display_off)
628 board_cfg->display_off(board_cfg->board_data);
cfb4f5d1
MD		 629 }
630
631 /* stop the lcdc */
8e9bb19e
MD		 632 if (priv->started) {
633 sh_mobile_lcdc_start_stop(priv, 0);
634 priv->started = 0;
635 }
b51339ff 636
8564557a
MD		 637 /* stop clocks */
638 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
639 if (priv->ch[k].enabled)
640 sh_mobile_lcdc_clk_off(priv);
cfb4f5d1
MD		 641}
642
643static int sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan *ch)
644{
645 int ifm, miftyp;
646
647 switch (ch->cfg.interface_type) {
648 case RGB8: ifm = 0; miftyp = 0; break;
649 case RGB9: ifm = 0; miftyp = 4; break;
650 case RGB12A: ifm = 0; miftyp = 5; break;
651 case RGB12B: ifm = 0; miftyp = 6; break;
652 case RGB16: ifm = 0; miftyp = 7; break;
653 case RGB18: ifm = 0; miftyp = 10; break;
654 case RGB24: ifm = 0; miftyp = 11; break;
655 case SYS8A: ifm = 1; miftyp = 0; break;
656 case SYS8B: ifm = 1; miftyp = 1; break;
657 case SYS8C: ifm = 1; miftyp = 2; break;
658 case SYS8D: ifm = 1; miftyp = 3; break;
659 case SYS9: ifm = 1; miftyp = 4; break;
660 case SYS12: ifm = 1; miftyp = 5; break;
661 case SYS16A: ifm = 1; miftyp = 7; break;
662 case SYS16B: ifm = 1; miftyp = 8; break;
663 case SYS16C: ifm = 1; miftyp = 9; break;
664 case SYS18: ifm = 1; miftyp = 10; break;
665 case SYS24: ifm = 1; miftyp = 11; break;
666 default: goto bad;
667 }
668
669 /* SUBLCD only supports SYS interface */
670 if (lcdc_chan_is_sublcd(ch)) {
671 if (ifm == 0)
672 goto bad;
673 else
674 ifm = 0;
675 }
676
677 ch->ldmt1r_value = (ifm << 12) | miftyp;
678 return 0;
679 bad:
680 return -EINVAL;
681}
682
b51339ff
MD		 683static int sh_mobile_lcdc_setup_clocks(struct platform_device *pdev,
684 int clock_source,
cfb4f5d1
MD		 685 struct sh_mobile_lcdc_priv *priv)
686{
687 char *str;
688 int icksel;
689
690 switch (clock_source) {
691 case LCDC_CLK_BUS: str = "bus_clk"; icksel = 0; break;
692 case LCDC_CLK_PERIPHERAL: str = "peripheral_clk"; icksel = 1; break;
693 case LCDC_CLK_EXTERNAL: str = NULL; icksel = 2; break;
694 default:
695 return -EINVAL;
696 }
697
698 priv->lddckr = icksel << 16;
699
700 if (str) {
b51339ff
MD		 701 priv->dot_clk = clk_get(&pdev->dev, str);
702 if (IS_ERR(priv->dot_clk)) {
703 dev_err(&pdev->dev, "cannot get dot clock %s\n", str);
b51339ff 704 return PTR_ERR(priv->dot_clk);
cfb4f5d1 705 }
cfb4f5d1 706 }
0246c471
MD		 707
708 /* Runtime PM support involves two step for this driver:
709 * 1) Enable Runtime PM
710 * 2) Force Runtime PM Resume since hardware is accessed from probe()
711 */
8bed9055 712 priv->dev = &pdev->dev;
0246c471
MD		 713 pm_runtime_enable(priv->dev);
714 pm_runtime_resume(priv->dev);
cfb4f5d1
MD		 715 return 0;
716}
717
718static int sh_mobile_lcdc_setcolreg(u_int regno,
719 u_int red, u_int green, u_int blue,
720 u_int transp, struct fb_info *info)
721{
722 u32 *palette = info->pseudo_palette;
723
724 if (regno >= PALETTE_NR)
725 return -EINVAL;
726
727 /* only FB_VISUAL_TRUECOLOR supported */
728
729 red >>= 16 - info->var.red.length;
730 green >>= 16 - info->var.green.length;
731 blue >>= 16 - info->var.blue.length;
732 transp >>= 16 - info->var.transp.length;
733
734 palette[regno] = (red << info->var.red.offset) |
735 (green << info->var.green.offset) |
736 (blue << info->var.blue.offset) |
737 (transp << info->var.transp.offset);
738
739 return 0;
740}
741
742static struct fb_fix_screeninfo sh_mobile_lcdc_fix = {
743 .id = "SH Mobile LCDC",
744 .type = FB_TYPE_PACKED_PIXELS,
745 .visual = FB_VISUAL_TRUECOLOR,
746 .accel = FB_ACCEL_NONE,
9dd38819
PE		 747 .xpanstep = 0,
748 .ypanstep = 1,
749 .ywrapstep = 0,
cfb4f5d1
MD		 750};
751
8564557a
MD		 752static void sh_mobile_lcdc_fillrect(struct fb_info *info,
753 const struct fb_fillrect *rect)
754{
755 sys_fillrect(info, rect);
756 sh_mobile_lcdc_deferred_io_touch(info);
757}
758
759static void sh_mobile_lcdc_copyarea(struct fb_info *info,
760 const struct fb_copyarea *area)
761{
762 sys_copyarea(info, area);
763 sh_mobile_lcdc_deferred_io_touch(info);
764}
765
766static void sh_mobile_lcdc_imageblit(struct fb_info *info,
767 const struct fb_image *image)
768{
769 sys_imageblit(info, image);
770 sh_mobile_lcdc_deferred_io_touch(info);
771}
772
9dd38819
PE		 773static int sh_mobile_fb_pan_display(struct fb_var_screeninfo *var,
774 struct fb_info *info)
775{
776 struct sh_mobile_lcdc_chan *ch = info->par;
92e1f9a7
PE		 777 struct sh_mobile_lcdc_priv *priv = ch->lcdc;
778 unsigned long ldrcntr;
779 unsigned long new_pan_offset;
780
781 new_pan_offset = (var->yoffset * info->fix.line_length) +
782 (var->xoffset * (info->var.bits_per_pixel / 8));
9dd38819 783
92e1f9a7 784 if (new_pan_offset == ch->pan_offset)
9dd38819
PE		 785 return 0; /* No change, do nothing */
786
92e1f9a7 787 ldrcntr = lcdc_read(priv, _LDRCNTR);
9dd38819 788
92e1f9a7
PE		 789 /* Set the source address for the next refresh */
790 lcdc_write_chan_mirror(ch, LDSA1R, ch->dma_handle + new_pan_offset);
791 if (lcdc_chan_is_sublcd(ch))
792 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_SRS);
793 else
794 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_MRS);
795
796 ch->pan_offset = new_pan_offset;
797
798 sh_mobile_lcdc_deferred_io_touch(info);
9dd38819
PE		 799
800 return 0;
801}
802
40331b21
PE		 803static int sh_mobile_wait_for_vsync(struct fb_info *info)
804{
805 struct sh_mobile_lcdc_chan *ch = info->par;
806 unsigned long ldintr;
807 int ret;
808
809 /* Enable VSync End interrupt */
810 ldintr = lcdc_read(ch->lcdc, _LDINTR);
811 ldintr |= LDINTR_VEE;
812 lcdc_write(ch->lcdc, _LDINTR, ldintr);
813
814 ret = wait_for_completion_interruptible_timeout(&ch->vsync_completion,
815 msecs_to_jiffies(100));
816 if (!ret)
817 return -ETIMEDOUT;
818
819 return 0;
820}
821
822static int sh_mobile_ioctl(struct fb_info *info, unsigned int cmd,
823 unsigned long arg)
824{
825 int retval;
826
827 switch (cmd) {
828 case FBIO_WAITFORVSYNC:
829 retval = sh_mobile_wait_for_vsync(info);
830 break;
831
832 default:
833 retval = -ENOIOCTLCMD;
834 break;
835 }
836 return retval;
837}
838
cfb4f5d1 839static struct fb_ops sh_mobile_lcdc_ops = {
9dd38819 840 .owner = THIS_MODULE,
cfb4f5d1 841 .fb_setcolreg = sh_mobile_lcdc_setcolreg,
2540c111
MD		 842 .fb_read = fb_sys_read,
843 .fb_write = fb_sys_write,
8564557a
MD		 844 .fb_fillrect = sh_mobile_lcdc_fillrect,
845 .fb_copyarea = sh_mobile_lcdc_copyarea,
846 .fb_imageblit = sh_mobile_lcdc_imageblit,
9dd38819 847 .fb_pan_display = sh_mobile_fb_pan_display,
40331b21 848 .fb_ioctl = sh_mobile_ioctl,
cfb4f5d1
MD		 849};
850
851static int sh_mobile_lcdc_set_bpp(struct fb_var_screeninfo *var, int bpp)
852{
853 switch (bpp) {
854 case 16: /* PKF[4:0] = 00011 - RGB 565 */
855 var->red.offset = 11;
856 var->red.length = 5;
857 var->green.offset = 5;
858 var->green.length = 6;
859 var->blue.offset = 0;
860 var->blue.length = 5;
861 var->transp.offset = 0;
862 var->transp.length = 0;
863 break;
864
865 case 32: /* PKF[4:0] = 00000 - RGB 888
866 * sh7722 pdf says 00RRGGBB but reality is GGBB00RR
867 * this may be because LDDDSR has word swap enabled..
868 */
869 var->red.offset = 0;
870 var->red.length = 8;
871 var->green.offset = 24;
872 var->green.length = 8;
873 var->blue.offset = 16;
874 var->blue.length = 8;
875 var->transp.offset = 0;
876 var->transp.length = 0;
877 break;
878 default:
879 return -EINVAL;
880 }
881 var->bits_per_pixel = bpp;
882 var->red.msb_right = 0;
883 var->green.msb_right = 0;
884 var->blue.msb_right = 0;
885 var->transp.msb_right = 0;
886 return 0;
887}
888
2feb075a
MD		 889static int sh_mobile_lcdc_suspend(struct device *dev)
890{
891 struct platform_device *pdev = to_platform_device(dev);
892
893 sh_mobile_lcdc_stop(platform_get_drvdata(pdev));
894 return 0;
895}
896
897static int sh_mobile_lcdc_resume(struct device *dev)
898{
899 struct platform_device *pdev = to_platform_device(dev);
900
901 return sh_mobile_lcdc_start(platform_get_drvdata(pdev));
902}
903
0246c471
MD		 904static int sh_mobile_lcdc_runtime_suspend(struct device *dev)
905{
906 struct platform_device *pdev = to_platform_device(dev);
907 struct sh_mobile_lcdc_priv *p = platform_get_drvdata(pdev);
908 struct sh_mobile_lcdc_chan *ch;
909 int k, n;
910
911 /* save per-channel registers */
912 for (k = 0; k < ARRAY_SIZE(p->ch); k++) {
913 ch = &p->ch[k];
914 if (!ch->enabled)
915 continue;
916 for (n = 0; n < NR_CH_REGS; n++)
917 ch->saved_ch_regs[n] = lcdc_read_chan(ch, n);
918 }
919
920 /* save shared registers */
921 for (n = 0; n < NR_SHARED_REGS; n++)
922 p->saved_shared_regs[n] = lcdc_read(p, lcdc_shared_regs[n]);
923
924 /* turn off LCDC hardware */
925 lcdc_write(p, _LDCNT1R, 0);
926 return 0;
927}
928
929static int sh_mobile_lcdc_runtime_resume(struct device *dev)
930{
931 struct platform_device *pdev = to_platform_device(dev);
932 struct sh_mobile_lcdc_priv *p = platform_get_drvdata(pdev);
933 struct sh_mobile_lcdc_chan *ch;
934 int k, n;
935
936 /* restore per-channel registers */
937 for (k = 0; k < ARRAY_SIZE(p->ch); k++) {
938 ch = &p->ch[k];
939 if (!ch->enabled)
940 continue;
941 for (n = 0; n < NR_CH_REGS; n++)
942 lcdc_write_chan(ch, n, ch->saved_ch_regs[n]);
943 }
944
945 /* restore shared registers */
946 for (n = 0; n < NR_SHARED_REGS; n++)
947 lcdc_write(p, lcdc_shared_regs[n], p->saved_shared_regs[n]);
948
949 return 0;
950}
951
47145210 952static const struct dev_pm_ops sh_mobile_lcdc_dev_pm_ops = {
2feb075a
MD		 953 .suspend = sh_mobile_lcdc_suspend,
954 .resume = sh_mobile_lcdc_resume,
0246c471
MD		 955 .runtime_suspend = sh_mobile_lcdc_runtime_suspend,
956 .runtime_resume = sh_mobile_lcdc_runtime_resume,
2feb075a
MD		 957};
958
6011bdea
GL		 959static int sh_mobile_lcdc_notify(struct notifier_block *nb,
960 unsigned long action, void *data)
961{
962 struct fb_event *event = data;
963 struct fb_info *info = event->info;
964 struct sh_mobile_lcdc_chan *ch = info->par;
965 struct sh_mobile_lcdc_board_cfg *board_cfg = &ch->cfg.board_cfg;
966 struct fb_var_screeninfo *var;
967
968 if (&ch->lcdc->notifier != nb)
969 return 0;
970
971 dev_dbg(info->dev, "%s(): action = %lu, data = %p\n",
972 __func__, action, event->data);
973
974 switch(action) {
975 case FB_EVENT_SUSPEND:
976 if (board_cfg->display_off)
977 board_cfg->display_off(board_cfg->board_data);
978 pm_runtime_put(info->device);
979 break;
980 case FB_EVENT_RESUME:
981 var = &info->var;
982
983 /* HDMI must be enabled before LCDC configuration */
984 if (board_cfg->display_on)
985 board_cfg->display_on(board_cfg->board_data, ch->info);
986
987 /* Check if the new display is not in our modelist */
988 if (ch->info->modelist.next &&
989 !fb_match_mode(var, &ch->info->modelist)) {
990 struct fb_videomode mode;
991 int ret;
992
993 /* Can we handle this display? */
994 if (var->xres > ch->cfg.lcd_cfg.xres ||
995 var->yres > ch->cfg.lcd_cfg.yres)
996 return -ENOMEM;
997
998 /* Add to the modelist */
999 fb_var_to_videomode(&mode, var);
1000 ret = fb_add_videomode(&mode, &ch->info->modelist);
1001 if (ret < 0)
1002 return ret;
1003 }
1004
1005 pm_runtime_get_sync(info->device);
1006
1007 sh_mobile_lcdc_geometry(ch);
1008
1009 break;
1010 }
1011
1012 return 0;
1013}
1014
cfb4f5d1
MD		 1015static int sh_mobile_lcdc_remove(struct platform_device *pdev);
1016
c2e13037 1017static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev)
cfb4f5d1
MD		 1018{
1019 struct fb_info *info;
1020 struct sh_mobile_lcdc_priv *priv;
1021 struct sh_mobile_lcdc_info *pdata;
1022 struct sh_mobile_lcdc_chan_cfg *cfg;
1023 struct resource *res;
1024 int error;
1025 void *buf;
1026 int i, j;
1027
1028 if (!pdev->dev.platform_data) {
1029 dev_err(&pdev->dev, "no platform data defined\n");
8bed9055 1030 return -EINVAL;
cfb4f5d1
MD		 1031 }
1032
1033 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8564557a
MD		 1034 i = platform_get_irq(pdev, 0);
1035 if (!res || i < 0) {
1036 dev_err(&pdev->dev, "cannot get platform resources\n");
8bed9055 1037 return -ENOENT;
cfb4f5d1
MD		 1038 }
1039
1040 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1041 if (!priv) {
1042 dev_err(&pdev->dev, "cannot allocate device data\n");
8bed9055 1043 return -ENOMEM;
cfb4f5d1
MD		 1044 }
1045
8bed9055
GL		 1046 platform_set_drvdata(pdev, priv);
1047
8564557a 1048 error = request_irq(i, sh_mobile_lcdc_irq, IRQF_DISABLED,
7ad33e74 1049 dev_name(&pdev->dev), priv);
8564557a
MD		 1050 if (error) {
1051 dev_err(&pdev->dev, "unable to request irq\n");
1052 goto err1;
1053 }
1054
1055 priv->irq = i;
cfb4f5d1 1056 pdata = pdev->dev.platform_data;
5ef6b505 1057 atomic_set(&priv->hw_usecnt, -1);
cfb4f5d1
MD		 1058
1059 j = 0;
1060 for (i = 0; i < ARRAY_SIZE(pdata->ch); i++) {
1061 priv->ch[j].lcdc = priv;
1062 memcpy(&priv->ch[j].cfg, &pdata->ch[i], sizeof(pdata->ch[i]));
1063
e1f42ff4 1064 error = sh_mobile_lcdc_check_interface(&priv->ch[j]);
cfb4f5d1
MD		 1065 if (error) {
1066 dev_err(&pdev->dev, "unsupported interface type\n");
1067 goto err1;
1068 }
e1f42ff4
GL		 1069 init_waitqueue_head(&priv->ch[j].frame_end_wait);
1070 init_completion(&priv->ch[j].vsync_completion);
9dd38819 1071 priv->ch[j].pan_offset = 0;
cfb4f5d1
MD		 1072
1073 switch (pdata->ch[i].chan) {
1074 case LCDC_CHAN_MAINLCD:
1075 priv->ch[j].enabled = 1 << 1;
1076 priv->ch[j].reg_offs = lcdc_offs_mainlcd;
1077 j++;
1078 break;
1079 case LCDC_CHAN_SUBLCD:
1080 priv->ch[j].enabled = 1 << 2;
1081 priv->ch[j].reg_offs = lcdc_offs_sublcd;
1082 j++;
1083 break;
1084 }
1085 }
1086
1087 if (!j) {
1088 dev_err(&pdev->dev, "no channels defined\n");
1089 error = -EINVAL;
1090 goto err1;
1091 }
1092
dba6f385
GL		 1093 priv->base = ioremap_nocache(res->start, resource_size(res));
1094 if (!priv->base)
1095 goto err1;
1096
b51339ff 1097 error = sh_mobile_lcdc_setup_clocks(pdev, pdata->clock_source, priv);
cfb4f5d1
MD		 1098 if (error) {
1099 dev_err(&pdev->dev, "unable to setup clocks\n");
1100 goto err1;
1101 }
1102
cfb4f5d1 1103 for (i = 0; i < j; i++) {
6011bdea
GL		 1104 struct fb_var_screeninfo *var;
1105 struct fb_videomode *lcd_cfg;
cfb4f5d1
MD		 1106 cfg = &priv->ch[i].cfg;
1107
e33afddc
PM		 1108 priv->ch[i].info = framebuffer_alloc(0, &pdev->dev);
1109 if (!priv->ch[i].info) {
1110 dev_err(&pdev->dev, "unable to allocate fb_info\n");
1111 error = -ENOMEM;
1112 break;
1113 }
1114
1115 info = priv->ch[i].info;
6011bdea
GL		 1116 var = &info->var;
1117 lcd_cfg = &cfg->lcd_cfg;
cfb4f5d1 1118 info->fbops = &sh_mobile_lcdc_ops;
14177a5e 1119 fb_videomode_to_var(var, lcd_cfg);
9dd38819 1120 /* Default Y virtual resolution is 2x panel size */
6011bdea 1121 var->yres_virtual = var->yres * 2;
6011bdea
GL		 1122
1123 error = sh_mobile_lcdc_set_bpp(var, cfg->bpp);
cfb4f5d1
MD		 1124 if (error)
1125 break;
1126
1127 info->fix = sh_mobile_lcdc_fix;
6011bdea 1128 info->fix.line_length = lcd_cfg->xres * (cfg->bpp / 8);
9dd38819 1129 info->fix.smem_len = info->fix.line_length *
6011bdea 1130 var->yres_virtual;
cfb4f5d1
MD		 1131
1132 buf = dma_alloc_coherent(&pdev->dev, info->fix.smem_len,
1133 &priv->ch[i].dma_handle, GFP_KERNEL);
1134 if (!buf) {
1135 dev_err(&pdev->dev, "unable to allocate buffer\n");
1136 error = -ENOMEM;
1137 break;
1138 }
1139
1140 info->pseudo_palette = &priv->ch[i].pseudo_palette;
1141 info->flags = FBINFO_FLAG_DEFAULT;
1142
1143 error = fb_alloc_cmap(&info->cmap, PALETTE_NR, 0);
1144 if (error < 0) {
1145 dev_err(&pdev->dev, "unable to allocate cmap\n");
1146 dma_free_coherent(&pdev->dev, info->fix.smem_len,
1147 buf, priv->ch[i].dma_handle);
1148 break;
1149 }
1150
cfb4f5d1
MD		 1151 info->fix.smem_start = priv->ch[i].dma_handle;
1152 info->screen_base = buf;
1153 info->device = &pdev->dev;
8564557a 1154 info->par = &priv->ch[i];
cfb4f5d1
MD		 1155 }
1156
1157 if (error)
1158 goto err1;
1159
1160 error = sh_mobile_lcdc_start(priv);
1161 if (error) {
1162 dev_err(&pdev->dev, "unable to start hardware\n");
1163 goto err1;
1164 }
1165
1166 for (i = 0; i < j; i++) {
1c6a307a
PM		 1167 struct sh_mobile_lcdc_chan *ch = priv->ch + i;
1168
e33afddc 1169 info = ch->info;
1c6a307a
PM		 1170
1171 if (info->fbdefio) {
8bed9055 1172 ch->sglist = vmalloc(sizeof(struct scatterlist) *
1c6a307a 1173 info->fix.smem_len >> PAGE_SHIFT);
8bed9055 1174 if (!ch->sglist) {
1c6a307a
PM		 1175 dev_err(&pdev->dev, "cannot allocate sglist\n");
1176 goto err1;
1177 }
1178 }
1179
1180 error = register_framebuffer(info);
cfb4f5d1
MD		 1181 if (error < 0)
1182 goto err1;
cfb4f5d1 1183
cfb4f5d1
MD		 1184 dev_info(info->dev,
1185 "registered %s/%s as %dx%d %dbpp.\n",
1186 pdev->name,
1c6a307a 1187 (ch->cfg.chan == LCDC_CHAN_MAINLCD) ?
cfb4f5d1 1188 "mainlcd" : "sublcd",
1c6a307a
PM		 1189 (int) ch->cfg.lcd_cfg.xres,
1190 (int) ch->cfg.lcd_cfg.yres,
1191 ch->cfg.bpp);
8564557a
MD		 1192
1193 /* deferred io mode: disable clock to save power */
6011bdea 1194 if (info->fbdefio || info->state == FBINFO_STATE_SUSPENDED)
8564557a 1195 sh_mobile_lcdc_clk_off(priv);
cfb4f5d1
MD		 1196 }
1197
6011bdea
GL		 1198 /* Failure ignored */
1199 priv->notifier.notifier_call = sh_mobile_lcdc_notify;
1200 fb_register_client(&priv->notifier);
1201
cfb4f5d1 1202 return 0;
8bed9055 1203err1:
cfb4f5d1 1204 sh_mobile_lcdc_remove(pdev);
8bed9055 1205
cfb4f5d1
MD		 1206 return error;
1207}
1208
1209static int sh_mobile_lcdc_remove(struct platform_device *pdev)
1210{
1211 struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
1212 struct fb_info *info;
1213 int i;
1214
6011bdea
GL		 1215 fb_unregister_client(&priv->notifier);
1216
cfb4f5d1 1217 for (i = 0; i < ARRAY_SIZE(priv->ch); i++)
8bed9055 1218 if (priv->ch[i].info && priv->ch[i].info->dev)
e33afddc 1219 unregister_framebuffer(priv->ch[i].info);
cfb4f5d1
MD		 1220
1221 sh_mobile_lcdc_stop(priv);
1222
1223 for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
e33afddc 1224 info = priv->ch[i].info;
cfb4f5d1 1225
e33afddc 1226 if (!info || !info->device)
cfb4f5d1
MD		 1227 continue;
1228
1c6a307a
PM		 1229 if (priv->ch[i].sglist)
1230 vfree(priv->ch[i].sglist);
1231
cfb4f5d1
MD		 1232 dma_free_coherent(&pdev->dev, info->fix.smem_len,
1233 info->screen_base, priv->ch[i].dma_handle);
1234 fb_dealloc_cmap(&info->cmap);
e33afddc 1235 framebuffer_release(info);
cfb4f5d1
MD		 1236 }
1237
b51339ff
MD		 1238 if (priv->dot_clk)
1239 clk_put(priv->dot_clk);
0246c471 1240
8bed9055
GL		 1241 if (priv->dev)
1242 pm_runtime_disable(priv->dev);
cfb4f5d1
MD		 1243
1244 if (priv->base)
1245 iounmap(priv->base);
1246
8564557a
MD		 1247 if (priv->irq)
1248 free_irq(priv->irq, priv);
cfb4f5d1
MD		 1249 kfree(priv);
1250 return 0;
1251}
1252
1253static struct platform_driver sh_mobile_lcdc_driver = {
1254 .driver = {
1255 .name = "sh_mobile_lcdc_fb",
1256 .owner = THIS_MODULE,
2feb075a 1257 .pm = &sh_mobile_lcdc_dev_pm_ops,
cfb4f5d1
MD		 1258 },
1259 .probe = sh_mobile_lcdc_probe,
1260 .remove = sh_mobile_lcdc_remove,
1261};
1262
1263static int __init sh_mobile_lcdc_init(void)
1264{
1265 return platform_driver_register(&sh_mobile_lcdc_driver);
1266}
1267
1268static void __exit sh_mobile_lcdc_exit(void)
1269{
1270 platform_driver_unregister(&sh_mobile_lcdc_driver);
1271}
1272
1273module_init(sh_mobile_lcdc_init);
1274module_exit(sh_mobile_lcdc_exit);
1275
1276MODULE_DESCRIPTION("SuperH Mobile LCDC Framebuffer driver");
1277MODULE_AUTHOR("Magnus Damm <damm@opensource.se>");
1278MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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