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fbdev: sh_mobile_hdmi: implement locking
[deliverable/linux.git] / drivers / video / sh_mobile_lcdcfb.c
CommitLineData
cfb4f5d1
MD		 1/*
2 * SuperH Mobile LCDC Framebuffer
3 *
4 * Copyright (c) 2008 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/delay.h>
14#include <linux/mm.h>
cfb4f5d1 15#include <linux/clk.h>
0246c471 16#include <linux/pm_runtime.h>
cfb4f5d1
MD		 17#include <linux/platform_device.h>
18#include <linux/dma-mapping.h>
8564557a 19#include <linux/interrupt.h>
1c6a307a 20#include <linux/vmalloc.h>
40331b21 21#include <linux/ioctl.h>
5a0e3ad6 22#include <linux/slab.h>
225c9a8d 23#include <video/sh_mobile_lcdc.h>
8564557a 24#include <asm/atomic.h>
cfb4f5d1 25
6de9edd5
GL		 26#include "sh_mobile_lcdcfb.h"
27
a6f15ade
PE		 28#define SIDE_B_OFFSET 0x1000
29#define MIRROR_OFFSET 0x2000
cfb4f5d1 30
cfb4f5d1
MD		 31/* shared registers */
32#define _LDDCKR 0x410
33#define _LDDCKSTPR 0x414
34#define _LDINTR 0x468
35#define _LDSR 0x46c
36#define _LDCNT1R 0x470
37#define _LDCNT2R 0x474
9dd38819 38#define _LDRCNTR 0x478
cfb4f5d1
MD		 39#define _LDDDSR 0x47c
40#define _LDDWD0R 0x800
41#define _LDDRDR 0x840
42#define _LDDWAR 0x900
43#define _LDDRAR 0x904
44
0246c471
MD		 45/* shared registers and their order for context save/restore */
46static int lcdc_shared_regs[] = {
47 _LDDCKR,
48 _LDDCKSTPR,
49 _LDINTR,
50 _LDDDSR,
51 _LDCNT1R,
52 _LDCNT2R,
53};
54#define NR_SHARED_REGS ARRAY_SIZE(lcdc_shared_regs)
55
0246c471 56static unsigned long lcdc_offs_mainlcd[NR_CH_REGS] = {
cfb4f5d1
MD		 57 [LDDCKPAT1R] = 0x400,
58 [LDDCKPAT2R] = 0x404,
59 [LDMT1R] = 0x418,
60 [LDMT2R] = 0x41c,
61 [LDMT3R] = 0x420,
62 [LDDFR] = 0x424,
63 [LDSM1R] = 0x428,
8564557a 64 [LDSM2R] = 0x42c,
cfb4f5d1
MD		 65 [LDSA1R] = 0x430,
66 [LDMLSR] = 0x438,
67 [LDHCNR] = 0x448,
68 [LDHSYNR] = 0x44c,
69 [LDVLNR] = 0x450,
70 [LDVSYNR] = 0x454,
71 [LDPMR] = 0x460,
6011bdea 72 [LDHAJR] = 0x4a0,
cfb4f5d1
MD		 73};
74
0246c471 75static unsigned long lcdc_offs_sublcd[NR_CH_REGS] = {
cfb4f5d1
MD		 76 [LDDCKPAT1R] = 0x408,
77 [LDDCKPAT2R] = 0x40c,
78 [LDMT1R] = 0x600,
79 [LDMT2R] = 0x604,
80 [LDMT3R] = 0x608,
81 [LDDFR] = 0x60c,
82 [LDSM1R] = 0x610,
8564557a 83 [LDSM2R] = 0x614,
cfb4f5d1
MD		 84 [LDSA1R] = 0x618,
85 [LDMLSR] = 0x620,
86 [LDHCNR] = 0x624,
87 [LDHSYNR] = 0x628,
88 [LDVLNR] = 0x62c,
89 [LDVSYNR] = 0x630,
90 [LDPMR] = 0x63c,
91};
92
93#define START_LCDC 0x00000001
94#define LCDC_RESET 0x00000100
95#define DISPLAY_BEU 0x00000008
96#define LCDC_ENABLE 0x00000001
8564557a 97#define LDINTR_FE 0x00000400
9dd38819
PE		 98#define LDINTR_VSE 0x00000200
99#define LDINTR_VEE 0x00000100
8564557a 100#define LDINTR_FS 0x00000004
9dd38819
PE		 101#define LDINTR_VSS 0x00000002
102#define LDINTR_VES 0x00000001
a6f15ade
PE		 103#define LDRCNTR_SRS 0x00020000
104#define LDRCNTR_SRC 0x00010000
105#define LDRCNTR_MRS 0x00000002
106#define LDRCNTR_MRC 0x00000001
40331b21 107#define LDSR_MRS 0x00000100
cfb4f5d1 108
0246c471
MD		 109struct sh_mobile_lcdc_priv {
110 void __iomem *base;
111 int irq;
112 atomic_t hw_usecnt;
113 struct device *dev;
114 struct clk *dot_clk;
115 unsigned long lddckr;
116 struct sh_mobile_lcdc_chan ch[2];
6011bdea 117 struct notifier_block notifier;
0246c471
MD		 118 unsigned long saved_shared_regs[NR_SHARED_REGS];
119 int started;
120};
121
a6f15ade
PE		 122static bool banked(int reg_nr)
123{
124 switch (reg_nr) {
125 case LDMT1R:
126 case LDMT2R:
127 case LDMT3R:
128 case LDDFR:
129 case LDSM1R:
130 case LDSA1R:
131 case LDMLSR:
132 case LDHCNR:
133 case LDHSYNR:
134 case LDVLNR:
135 case LDVSYNR:
136 return true;
137 }
138 return false;
139}
140
cfb4f5d1
MD		 141static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan,
142 int reg_nr, unsigned long data)
143{
144 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]);
a6f15ade
PE		 145 if (banked(reg_nr))
146 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
147 SIDE_B_OFFSET);
148}
149
150static void lcdc_write_chan_mirror(struct sh_mobile_lcdc_chan *chan,
151 int reg_nr, unsigned long data)
152{
153 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
154 MIRROR_OFFSET);
cfb4f5d1
MD		 155}
156
157static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan,
158 int reg_nr)
159{
160 return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]);
161}
162
163static void lcdc_write(struct sh_mobile_lcdc_priv *priv,
164 unsigned long reg_offs, unsigned long data)
165{
166 iowrite32(data, priv->base + reg_offs);
167}
168
169static unsigned long lcdc_read(struct sh_mobile_lcdc_priv *priv,
170 unsigned long reg_offs)
171{
172 return ioread32(priv->base + reg_offs);
173}
174
175static void lcdc_wait_bit(struct sh_mobile_lcdc_priv *priv,
176 unsigned long reg_offs,
177 unsigned long mask, unsigned long until)
178{
179 while ((lcdc_read(priv, reg_offs) & mask) != until)
180 cpu_relax();
181}
182
183static int lcdc_chan_is_sublcd(struct sh_mobile_lcdc_chan *chan)
184{
185 return chan->cfg.chan == LCDC_CHAN_SUBLCD;
186}
187
188static void lcdc_sys_write_index(void *handle, unsigned long data)
189{
190 struct sh_mobile_lcdc_chan *ch = handle;
191
192 lcdc_write(ch->lcdc, _LDDWD0R, data | 0x10000000);
193 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
194 lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
909f10de 195 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
cfb4f5d1
MD		 196}
197
198static void lcdc_sys_write_data(void *handle, unsigned long data)
199{
200 struct sh_mobile_lcdc_chan *ch = handle;
201
202 lcdc_write(ch->lcdc, _LDDWD0R, data | 0x11000000);
203 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
204 lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
909f10de 205 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
cfb4f5d1
MD		 206}
207
208static unsigned long lcdc_sys_read_data(void *handle)
209{
210 struct sh_mobile_lcdc_chan *ch = handle;
211
212 lcdc_write(ch->lcdc, _LDDRDR, 0x01000000);
213 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
214 lcdc_write(ch->lcdc, _LDDRAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
215 udelay(1);
909f10de 216 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
cfb4f5d1 217
ec56b66f 218 return lcdc_read(ch->lcdc, _LDDRDR) & 0x3ffff;
cfb4f5d1
MD		 219}
220
221struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = {
222 lcdc_sys_write_index,
223 lcdc_sys_write_data,
224 lcdc_sys_read_data,
225};
226
8564557a
MD		 227static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv)
228{
0246c471
MD		 229 if (atomic_inc_and_test(&priv->hw_usecnt)) {
230 pm_runtime_get_sync(priv->dev);
8564557a
MD		 231 if (priv->dot_clk)
232 clk_enable(priv->dot_clk);
233 }
234}
235
236static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv)
237{
0246c471 238 if (atomic_sub_return(1, &priv->hw_usecnt) == -1) {
8564557a
MD		 239 if (priv->dot_clk)
240 clk_disable(priv->dot_clk);
0246c471 241 pm_runtime_put(priv->dev);
8564557a
MD		 242 }
243}
8564557a 244
1c6a307a
PM		 245static int sh_mobile_lcdc_sginit(struct fb_info *info,
246 struct list_head *pagelist)
247{
248 struct sh_mobile_lcdc_chan *ch = info->par;
249 unsigned int nr_pages_max = info->fix.smem_len >> PAGE_SHIFT;
250 struct page *page;
251 int nr_pages = 0;
252
253 sg_init_table(ch->sglist, nr_pages_max);
254
255 list_for_each_entry(page, pagelist, lru)
256 sg_set_page(&ch->sglist[nr_pages++], page, PAGE_SIZE, 0);
257
258 return nr_pages;
259}
260
8564557a
MD		 261static void sh_mobile_lcdc_deferred_io(struct fb_info *info,
262 struct list_head *pagelist)
263{
264 struct sh_mobile_lcdc_chan *ch = info->par;
ef61aae4 265 struct sh_mobile_lcdc_board_cfg *bcfg = &ch->cfg.board_cfg;
8564557a
MD		 266
267 /* enable clocks before accessing hardware */
268 sh_mobile_lcdc_clk_on(ch->lcdc);
269
5c1a56b5
PM		 270 /*
271 * It's possible to get here without anything on the pagelist via
272 * sh_mobile_lcdc_deferred_io_touch() or via a userspace fsync()
273 * invocation. In the former case, the acceleration routines are
274 * stepped in to when using the framebuffer console causing the
275 * workqueue to be scheduled without any dirty pages on the list.
276 *
277 * Despite this, a panel update is still needed given that the
278 * acceleration routines have their own methods for writing in
279 * that still need to be updated.
280 *
281 * The fsync() and empty pagelist case could be optimized for,
282 * but we don't bother, as any application exhibiting such
283 * behaviour is fundamentally broken anyways.
284 */
285 if (!list_empty(pagelist)) {
286 unsigned int nr_pages = sh_mobile_lcdc_sginit(info, pagelist);
287
288 /* trigger panel update */
289 dma_map_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
ef61aae4
MD		 290 if (bcfg->start_transfer)
291 bcfg->start_transfer(bcfg->board_data, ch,
292 &sh_mobile_lcdc_sys_bus_ops);
5c1a56b5
PM		 293 lcdc_write_chan(ch, LDSM2R, 1);
294 dma_unmap_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
ef61aae4
MD		 295 } else {
296 if (bcfg->start_transfer)
297 bcfg->start_transfer(bcfg->board_data, ch,
298 &sh_mobile_lcdc_sys_bus_ops);
5c1a56b5 299 lcdc_write_chan(ch, LDSM2R, 1);
ef61aae4 300 }
8564557a
MD		 301}
302
303static void sh_mobile_lcdc_deferred_io_touch(struct fb_info *info)
304{
305 struct fb_deferred_io *fbdefio = info->fbdefio;
306
307 if (fbdefio)
308 schedule_delayed_work(&info->deferred_work, fbdefio->delay);
309}
310
311static irqreturn_t sh_mobile_lcdc_irq(int irq, void *data)
312{
313 struct sh_mobile_lcdc_priv *priv = data;
2feb075a 314 struct sh_mobile_lcdc_chan *ch;
8564557a 315 unsigned long tmp;
9dd38819 316 unsigned long ldintr;
2feb075a
MD		 317 int is_sub;
318 int k;
8564557a
MD		 319
320 /* acknowledge interrupt */
9dd38819
PE		 321 ldintr = tmp = lcdc_read(priv, _LDINTR);
322 /*
323 * disable further VSYNC End IRQs, preserve all other enabled IRQs,
324 * write 0 to bits 0-6 to ack all triggered IRQs.
325 */
326 tmp &= 0xffffff00 & ~LDINTR_VEE;
8564557a
MD		 327 lcdc_write(priv, _LDINTR, tmp);
328
2feb075a
MD		 329 /* figure out if this interrupt is for main or sub lcd */
330 is_sub = (lcdc_read(priv, _LDSR) & (1 << 10)) ? 1 : 0;
331
9dd38819 332 /* wake up channel and disable clocks */
2feb075a
MD		 333 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
334 ch = &priv->ch[k];
335
336 if (!ch->enabled)
337 continue;
338
9dd38819
PE		 339 /* Frame Start */
340 if (ldintr & LDINTR_FS) {
341 if (is_sub == lcdc_chan_is_sublcd(ch)) {
342 ch->frame_end = 1;
343 wake_up(&ch->frame_end_wait);
2feb075a 344
9dd38819
PE		 345 sh_mobile_lcdc_clk_off(priv);
346 }
347 }
348
349 /* VSYNC End */
40331b21
PE		 350 if (ldintr & LDINTR_VES)
351 complete(&ch->vsync_completion);
2feb075a
MD		 352 }
353
8564557a
MD		 354 return IRQ_HANDLED;
355}
356
cfb4f5d1
MD		 357static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv *priv,
358 int start)
359{
360 unsigned long tmp = lcdc_read(priv, _LDCNT2R);
361 int k;
362
363 /* start or stop the lcdc */
364 if (start)
365 lcdc_write(priv, _LDCNT2R, tmp | START_LCDC);
366 else
367 lcdc_write(priv, _LDCNT2R, tmp & ~START_LCDC);
368
369 /* wait until power is applied/stopped on all channels */
370 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
371 if (lcdc_read(priv, _LDCNT2R) & priv->ch[k].enabled)
372 while (1) {
373 tmp = lcdc_read_chan(&priv->ch[k], LDPMR) & 3;
374 if (start && tmp == 3)
375 break;
376 if (!start && tmp == 0)
377 break;
378 cpu_relax();
379 }
380
381 if (!start)
382 lcdc_write(priv, _LDDCKSTPR, 1); /* stop dotclock */
383}
384
6011bdea
GL		 385static void sh_mobile_lcdc_geometry(struct sh_mobile_lcdc_chan *ch)
386{
387 struct fb_var_screeninfo *var = &ch->info->var;
388 unsigned long h_total, hsync_pos;
389 u32 tmp;
390
391 tmp = ch->ldmt1r_value;
392 tmp |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1 << 28;
393 tmp |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1 << 27;
394 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWPOL) ? 1 << 26 : 0;
395 tmp |= (ch->cfg.flags & LCDC_FLAGS_DIPOL) ? 1 << 25 : 0;
396 tmp |= (ch->cfg.flags & LCDC_FLAGS_DAPOL) ? 1 << 24 : 0;
397 tmp |= (ch->cfg.flags & LCDC_FLAGS_HSCNT) ? 1 << 17 : 0;
398 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWCNT) ? 1 << 16 : 0;
399 lcdc_write_chan(ch, LDMT1R, tmp);
400
401 /* setup SYS bus */
402 lcdc_write_chan(ch, LDMT2R, ch->cfg.sys_bus_cfg.ldmt2r);
403 lcdc_write_chan(ch, LDMT3R, ch->cfg.sys_bus_cfg.ldmt3r);
404
405 /* horizontal configuration */
406 h_total = var->xres + var->hsync_len +
407 var->left_margin + var->right_margin;
408 tmp = h_total / 8; /* HTCN */
409 tmp |= (var->xres / 8) << 16; /* HDCN */
410 lcdc_write_chan(ch, LDHCNR, tmp);
411
412 hsync_pos = var->xres + var->right_margin;
413 tmp = hsync_pos / 8; /* HSYNP */
414 tmp |= (var->hsync_len / 8) << 16; /* HSYNW */
415 lcdc_write_chan(ch, LDHSYNR, tmp);
416
417 /* vertical configuration */
418 tmp = var->yres + var->vsync_len +
419 var->upper_margin + var->lower_margin; /* VTLN */
420 tmp |= var->yres << 16; /* VDLN */
421 lcdc_write_chan(ch, LDVLNR, tmp);
422
423 tmp = var->yres + var->lower_margin; /* VSYNP */
424 tmp |= var->vsync_len << 16; /* VSYNW */
425 lcdc_write_chan(ch, LDVSYNR, tmp);
426
427 /* Adjust horizontal synchronisation for HDMI */
428 tmp = ((var->xres & 7) << 24) |
429 ((h_total & 7) << 16) |
430 ((var->hsync_len & 7) << 8) |
431 hsync_pos;
432 lcdc_write_chan(ch, LDHAJR, tmp);
433}
434
cfb4f5d1
MD		 435static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
436{
437 struct sh_mobile_lcdc_chan *ch;
cfb4f5d1
MD		 438 struct sh_mobile_lcdc_board_cfg *board_cfg;
439 unsigned long tmp;
440 int k, m;
441 int ret = 0;
442
8564557a
MD		 443 /* enable clocks before accessing the hardware */
444 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
445 if (priv->ch[k].enabled)
446 sh_mobile_lcdc_clk_on(priv);
447
cfb4f5d1
MD		 448 /* reset */
449 lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LCDC_RESET);
450 lcdc_wait_bit(priv, _LDCNT2R, LCDC_RESET, 0);
451
452 /* enable LCDC channels */
453 tmp = lcdc_read(priv, _LDCNT2R);
454 tmp |= priv->ch[0].enabled;
455 tmp |= priv->ch[1].enabled;
456 lcdc_write(priv, _LDCNT2R, tmp);
457
458 /* read data from external memory, avoid using the BEU for now */
459 lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) & ~DISPLAY_BEU);
460
461 /* stop the lcdc first */
462 sh_mobile_lcdc_start_stop(priv, 0);
463
464 /* configure clocks */
465 tmp = priv->lddckr;
466 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
467 ch = &priv->ch[k];
468
469 if (!priv->ch[k].enabled)
470 continue;
471
472 m = ch->cfg.clock_divider;
473 if (!m)
474 continue;
475
476 if (m == 1)
477 m = 1 << 6;
478 tmp |= m << (lcdc_chan_is_sublcd(ch) ? 8 : 0);
479
480 lcdc_write_chan(ch, LDDCKPAT1R, 0x00000000);
481 lcdc_write_chan(ch, LDDCKPAT2R, (1 << (m/2)) - 1);
482 }
483
484 lcdc_write(priv, _LDDCKR, tmp);
485
486 /* start dotclock again */
487 lcdc_write(priv, _LDDCKSTPR, 0);
488 lcdc_wait_bit(priv, _LDDCKSTPR, ~0, 0);
489
8564557a 490 /* interrupts are disabled to begin with */
cfb4f5d1
MD		 491 lcdc_write(priv, _LDINTR, 0);
492
493 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
494 ch = &priv->ch[k];
cfb4f5d1
MD		 495
496 if (!ch->enabled)
497 continue;
498
6011bdea 499 sh_mobile_lcdc_geometry(ch);
cfb4f5d1
MD		 500
501 /* power supply */
502 lcdc_write_chan(ch, LDPMR, 0);
503
cfb4f5d1
MD		 504 board_cfg = &ch->cfg.board_cfg;
505 if (board_cfg->setup_sys)
506 ret = board_cfg->setup_sys(board_cfg->board_data, ch,
507 &sh_mobile_lcdc_sys_bus_ops);
508 if (ret)
509 return ret;
510 }
511
cfb4f5d1
MD		 512 /* word and long word swap */
513 lcdc_write(priv, _LDDDSR, lcdc_read(priv, _LDDDSR) | 6);
514
515 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
516 ch = &priv->ch[k];
517
518 if (!priv->ch[k].enabled)
519 continue;
520
521 /* set bpp format in PKF[4:0] */
522 tmp = lcdc_read_chan(ch, LDDFR);
523 tmp &= ~(0x0001001f);
e33afddc 524 tmp |= (ch->info->var.bits_per_pixel == 16) ? 3 : 0;
cfb4f5d1
MD		 525 lcdc_write_chan(ch, LDDFR, tmp);
526
527 /* point out our frame buffer */
e33afddc 528 lcdc_write_chan(ch, LDSA1R, ch->info->fix.smem_start);
cfb4f5d1
MD		 529
530 /* set line size */
e33afddc 531 lcdc_write_chan(ch, LDMLSR, ch->info->fix.line_length);
cfb4f5d1 532
8564557a
MD		 533 /* setup deferred io if SYS bus */
534 tmp = ch->cfg.sys_bus_cfg.deferred_io_msec;
535 if (ch->ldmt1r_value & (1 << 12) && tmp) {
536 ch->defio.deferred_io = sh_mobile_lcdc_deferred_io;
537 ch->defio.delay = msecs_to_jiffies(tmp);
e33afddc
PM		 538 ch->info->fbdefio = &ch->defio;
539 fb_deferred_io_init(ch->info);
8564557a
MD		 540
541 /* one-shot mode */
542 lcdc_write_chan(ch, LDSM1R, 1);
543
544 /* enable "Frame End Interrupt Enable" bit */
545 lcdc_write(priv, _LDINTR, LDINTR_FE);
546
547 } else {
548 /* continuous read mode */
549 lcdc_write_chan(ch, LDSM1R, 0);
550 }
cfb4f5d1
MD		 551 }
552
553 /* display output */
554 lcdc_write(priv, _LDCNT1R, LCDC_ENABLE);
555
556 /* start the lcdc */
557 sh_mobile_lcdc_start_stop(priv, 1);
8e9bb19e 558 priv->started = 1;
cfb4f5d1
MD		 559
560 /* tell the board code to enable the panel */
561 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
562 ch = &priv->ch[k];
21bc1f02
MD		 563 if (!ch->enabled)
564 continue;
565
cfb4f5d1 566 board_cfg = &ch->cfg.board_cfg;
6de9edd5 567 if (try_module_get(board_cfg->owner) && board_cfg->display_on) {
c2439398 568 board_cfg->display_on(board_cfg->board_data, ch->info);
6de9edd5
GL		 569 module_put(board_cfg->owner);
570 }
cfb4f5d1
MD		 571 }
572
573 return 0;
574}
575
576static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
577{
578 struct sh_mobile_lcdc_chan *ch;
579 struct sh_mobile_lcdc_board_cfg *board_cfg;
580 int k;
581
2feb075a 582 /* clean up deferred io and ask board code to disable panel */
cfb4f5d1
MD		 583 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
584 ch = &priv->ch[k];
21bc1f02
MD		 585 if (!ch->enabled)
586 continue;
8564557a 587
2feb075a
MD		 588 /* deferred io mode:
589 * flush frame, and wait for frame end interrupt
590 * clean up deferred io and enable clock
591 */
5ef6b505 592 if (ch->info && ch->info->fbdefio) {
2feb075a 593 ch->frame_end = 0;
e33afddc 594 schedule_delayed_work(&ch->info->deferred_work, 0);
2feb075a 595 wait_event(ch->frame_end_wait, ch->frame_end);
e33afddc
PM		 596 fb_deferred_io_cleanup(ch->info);
597 ch->info->fbdefio = NULL;
2feb075a 598 sh_mobile_lcdc_clk_on(priv);
8564557a 599 }
2feb075a
MD		 600
601 board_cfg = &ch->cfg.board_cfg;
6de9edd5 602 if (try_module_get(board_cfg->owner) && board_cfg->display_off) {
2feb075a 603 board_cfg->display_off(board_cfg->board_data);
6de9edd5
GL		 604 module_put(board_cfg->owner);
605 }
cfb4f5d1
MD		 606 }
607
608 /* stop the lcdc */
8e9bb19e
MD		 609 if (priv->started) {
610 sh_mobile_lcdc_start_stop(priv, 0);
611 priv->started = 0;
612 }
b51339ff 613
8564557a
MD		 614 /* stop clocks */
615 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
616 if (priv->ch[k].enabled)
617 sh_mobile_lcdc_clk_off(priv);
cfb4f5d1
MD		 618}
619
620static int sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan *ch)
621{
622 int ifm, miftyp;
623
624 switch (ch->cfg.interface_type) {
625 case RGB8: ifm = 0; miftyp = 0; break;
626 case RGB9: ifm = 0; miftyp = 4; break;
627 case RGB12A: ifm = 0; miftyp = 5; break;
628 case RGB12B: ifm = 0; miftyp = 6; break;
629 case RGB16: ifm = 0; miftyp = 7; break;
630 case RGB18: ifm = 0; miftyp = 10; break;
631 case RGB24: ifm = 0; miftyp = 11; break;
632 case SYS8A: ifm = 1; miftyp = 0; break;
633 case SYS8B: ifm = 1; miftyp = 1; break;
634 case SYS8C: ifm = 1; miftyp = 2; break;
635 case SYS8D: ifm = 1; miftyp = 3; break;
636 case SYS9: ifm = 1; miftyp = 4; break;
637 case SYS12: ifm = 1; miftyp = 5; break;
638 case SYS16A: ifm = 1; miftyp = 7; break;
639 case SYS16B: ifm = 1; miftyp = 8; break;
640 case SYS16C: ifm = 1; miftyp = 9; break;
641 case SYS18: ifm = 1; miftyp = 10; break;
642 case SYS24: ifm = 1; miftyp = 11; break;
643 default: goto bad;
644 }
645
646 /* SUBLCD only supports SYS interface */
647 if (lcdc_chan_is_sublcd(ch)) {
648 if (ifm == 0)
649 goto bad;
650 else
651 ifm = 0;
652 }
653
654 ch->ldmt1r_value = (ifm << 12) | miftyp;
655 return 0;
656 bad:
657 return -EINVAL;
658}
659
b51339ff
MD		 660static int sh_mobile_lcdc_setup_clocks(struct platform_device *pdev,
661 int clock_source,
cfb4f5d1
MD		 662 struct sh_mobile_lcdc_priv *priv)
663{
664 char *str;
665 int icksel;
666
667 switch (clock_source) {
668 case LCDC_CLK_BUS: str = "bus_clk"; icksel = 0; break;
669 case LCDC_CLK_PERIPHERAL: str = "peripheral_clk"; icksel = 1; break;
670 case LCDC_CLK_EXTERNAL: str = NULL; icksel = 2; break;
671 default:
672 return -EINVAL;
673 }
674
675 priv->lddckr = icksel << 16;
676
677 if (str) {
b51339ff
MD		 678 priv->dot_clk = clk_get(&pdev->dev, str);
679 if (IS_ERR(priv->dot_clk)) {
680 dev_err(&pdev->dev, "cannot get dot clock %s\n", str);
b51339ff 681 return PTR_ERR(priv->dot_clk);
cfb4f5d1 682 }
cfb4f5d1 683 }
0246c471
MD		 684
685 /* Runtime PM support involves two step for this driver:
686 * 1) Enable Runtime PM
687 * 2) Force Runtime PM Resume since hardware is accessed from probe()
688 */
8bed9055 689 priv->dev = &pdev->dev;
0246c471
MD		 690 pm_runtime_enable(priv->dev);
691 pm_runtime_resume(priv->dev);
cfb4f5d1
MD		 692 return 0;
693}
694
695static int sh_mobile_lcdc_setcolreg(u_int regno,
696 u_int red, u_int green, u_int blue,
697 u_int transp, struct fb_info *info)
698{
699 u32 *palette = info->pseudo_palette;
700
701 if (regno >= PALETTE_NR)
702 return -EINVAL;
703
704 /* only FB_VISUAL_TRUECOLOR supported */
705
706 red >>= 16 - info->var.red.length;
707 green >>= 16 - info->var.green.length;
708 blue >>= 16 - info->var.blue.length;
709 transp >>= 16 - info->var.transp.length;
710
711 palette[regno] = (red << info->var.red.offset) |
712 (green << info->var.green.offset) |
713 (blue << info->var.blue.offset) |
714 (transp << info->var.transp.offset);
715
716 return 0;
717}
718
719static struct fb_fix_screeninfo sh_mobile_lcdc_fix = {
720 .id = "SH Mobile LCDC",
721 .type = FB_TYPE_PACKED_PIXELS,
722 .visual = FB_VISUAL_TRUECOLOR,
723 .accel = FB_ACCEL_NONE,
9dd38819
PE		 724 .xpanstep = 0,
725 .ypanstep = 1,
726 .ywrapstep = 0,
cfb4f5d1
MD		 727};
728
8564557a
MD		 729static void sh_mobile_lcdc_fillrect(struct fb_info *info,
730 const struct fb_fillrect *rect)
731{
732 sys_fillrect(info, rect);
733 sh_mobile_lcdc_deferred_io_touch(info);
734}
735
736static void sh_mobile_lcdc_copyarea(struct fb_info *info,
737 const struct fb_copyarea *area)
738{
739 sys_copyarea(info, area);
740 sh_mobile_lcdc_deferred_io_touch(info);
741}
742
743static void sh_mobile_lcdc_imageblit(struct fb_info *info,
744 const struct fb_image *image)
745{
746 sys_imageblit(info, image);
747 sh_mobile_lcdc_deferred_io_touch(info);
748}
749
9dd38819
PE		 750static int sh_mobile_fb_pan_display(struct fb_var_screeninfo *var,
751 struct fb_info *info)
752{
753 struct sh_mobile_lcdc_chan *ch = info->par;
92e1f9a7
PE		 754 struct sh_mobile_lcdc_priv *priv = ch->lcdc;
755 unsigned long ldrcntr;
756 unsigned long new_pan_offset;
757
758 new_pan_offset = (var->yoffset * info->fix.line_length) +
759 (var->xoffset * (info->var.bits_per_pixel / 8));
9dd38819 760
92e1f9a7 761 if (new_pan_offset == ch->pan_offset)
9dd38819
PE		 762 return 0; /* No change, do nothing */
763
92e1f9a7 764 ldrcntr = lcdc_read(priv, _LDRCNTR);
9dd38819 765
92e1f9a7
PE		 766 /* Set the source address for the next refresh */
767 lcdc_write_chan_mirror(ch, LDSA1R, ch->dma_handle + new_pan_offset);
768 if (lcdc_chan_is_sublcd(ch))
769 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_SRS);
770 else
771 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_MRS);
772
773 ch->pan_offset = new_pan_offset;
774
775 sh_mobile_lcdc_deferred_io_touch(info);
9dd38819
PE		 776
777 return 0;
778}
779
40331b21
PE		 780static int sh_mobile_wait_for_vsync(struct fb_info *info)
781{
782 struct sh_mobile_lcdc_chan *ch = info->par;
783 unsigned long ldintr;
784 int ret;
785
786 /* Enable VSync End interrupt */
787 ldintr = lcdc_read(ch->lcdc, _LDINTR);
788 ldintr |= LDINTR_VEE;
789 lcdc_write(ch->lcdc, _LDINTR, ldintr);
790
791 ret = wait_for_completion_interruptible_timeout(&ch->vsync_completion,
792 msecs_to_jiffies(100));
793 if (!ret)
794 return -ETIMEDOUT;
795
796 return 0;
797}
798
799static int sh_mobile_ioctl(struct fb_info *info, unsigned int cmd,
800 unsigned long arg)
801{
802 int retval;
803
804 switch (cmd) {
805 case FBIO_WAITFORVSYNC:
806 retval = sh_mobile_wait_for_vsync(info);
807 break;
808
809 default:
810 retval = -ENOIOCTLCMD;
811 break;
812 }
813 return retval;
814}
815
cfb4f5d1 816static struct fb_ops sh_mobile_lcdc_ops = {
9dd38819 817 .owner = THIS_MODULE,
cfb4f5d1 818 .fb_setcolreg = sh_mobile_lcdc_setcolreg,
2540c111
MD		 819 .fb_read = fb_sys_read,
820 .fb_write = fb_sys_write,
8564557a
MD		 821 .fb_fillrect = sh_mobile_lcdc_fillrect,
822 .fb_copyarea = sh_mobile_lcdc_copyarea,
823 .fb_imageblit = sh_mobile_lcdc_imageblit,
9dd38819 824 .fb_pan_display = sh_mobile_fb_pan_display,
40331b21 825 .fb_ioctl = sh_mobile_ioctl,
cfb4f5d1
MD		 826};
827
828static int sh_mobile_lcdc_set_bpp(struct fb_var_screeninfo *var, int bpp)
829{
830 switch (bpp) {
831 case 16: /* PKF[4:0] = 00011 - RGB 565 */
832 var->red.offset = 11;
833 var->red.length = 5;
834 var->green.offset = 5;
835 var->green.length = 6;
836 var->blue.offset = 0;
837 var->blue.length = 5;
838 var->transp.offset = 0;
839 var->transp.length = 0;
840 break;
841
842 case 32: /* PKF[4:0] = 00000 - RGB 888
843 * sh7722 pdf says 00RRGGBB but reality is GGBB00RR
844 * this may be because LDDDSR has word swap enabled..
845 */
846 var->red.offset = 0;
847 var->red.length = 8;
848 var->green.offset = 24;
849 var->green.length = 8;
850 var->blue.offset = 16;
851 var->blue.length = 8;
852 var->transp.offset = 0;
853 var->transp.length = 0;
854 break;
855 default:
856 return -EINVAL;
857 }
858 var->bits_per_pixel = bpp;
859 var->red.msb_right = 0;
860 var->green.msb_right = 0;
861 var->blue.msb_right = 0;
862 var->transp.msb_right = 0;
863 return 0;
864}
865
2feb075a
MD		 866static int sh_mobile_lcdc_suspend(struct device *dev)
867{
868 struct platform_device *pdev = to_platform_device(dev);
869
870 sh_mobile_lcdc_stop(platform_get_drvdata(pdev));
871 return 0;
872}
873
874static int sh_mobile_lcdc_resume(struct device *dev)
875{
876 struct platform_device *pdev = to_platform_device(dev);
877
878 return sh_mobile_lcdc_start(platform_get_drvdata(pdev));
879}
880
0246c471
MD		 881static int sh_mobile_lcdc_runtime_suspend(struct device *dev)
882{
883 struct platform_device *pdev = to_platform_device(dev);
884 struct sh_mobile_lcdc_priv *p = platform_get_drvdata(pdev);
885 struct sh_mobile_lcdc_chan *ch;
886 int k, n;
887
888 /* save per-channel registers */
889 for (k = 0; k < ARRAY_SIZE(p->ch); k++) {
890 ch = &p->ch[k];
891 if (!ch->enabled)
892 continue;
893 for (n = 0; n < NR_CH_REGS; n++)
894 ch->saved_ch_regs[n] = lcdc_read_chan(ch, n);
895 }
896
897 /* save shared registers */
898 for (n = 0; n < NR_SHARED_REGS; n++)
899 p->saved_shared_regs[n] = lcdc_read(p, lcdc_shared_regs[n]);
900
901 /* turn off LCDC hardware */
902 lcdc_write(p, _LDCNT1R, 0);
903 return 0;
904}
905
906static int sh_mobile_lcdc_runtime_resume(struct device *dev)
907{
908 struct platform_device *pdev = to_platform_device(dev);
909 struct sh_mobile_lcdc_priv *p = platform_get_drvdata(pdev);
910 struct sh_mobile_lcdc_chan *ch;
911 int k, n;
912
913 /* restore per-channel registers */
914 for (k = 0; k < ARRAY_SIZE(p->ch); k++) {
915 ch = &p->ch[k];
916 if (!ch->enabled)
917 continue;
918 for (n = 0; n < NR_CH_REGS; n++)
919 lcdc_write_chan(ch, n, ch->saved_ch_regs[n]);
920 }
921
922 /* restore shared registers */
923 for (n = 0; n < NR_SHARED_REGS; n++)
924 lcdc_write(p, lcdc_shared_regs[n], p->saved_shared_regs[n]);
925
926 return 0;
927}
928
47145210 929static const struct dev_pm_ops sh_mobile_lcdc_dev_pm_ops = {
2feb075a
MD		 930 .suspend = sh_mobile_lcdc_suspend,
931 .resume = sh_mobile_lcdc_resume,
0246c471
MD		 932 .runtime_suspend = sh_mobile_lcdc_runtime_suspend,
933 .runtime_resume = sh_mobile_lcdc_runtime_resume,
2feb075a
MD		 934};
935
6de9edd5 936/* locking: called with info->lock held */
6011bdea
GL		 937static int sh_mobile_lcdc_notify(struct notifier_block *nb,
938 unsigned long action, void *data)
939{
940 struct fb_event *event = data;
941 struct fb_info *info = event->info;
942 struct sh_mobile_lcdc_chan *ch = info->par;
943 struct sh_mobile_lcdc_board_cfg *board_cfg = &ch->cfg.board_cfg;
944 struct fb_var_screeninfo *var;
945
946 if (&ch->lcdc->notifier != nb)
baf16374 947 return NOTIFY_DONE;
6011bdea
GL		 948
949 dev_dbg(info->dev, "%s(): action = %lu, data = %p\n",
950 __func__, action, event->data);
951
952 switch(action) {
953 case FB_EVENT_SUSPEND:
6de9edd5 954 if (try_module_get(board_cfg->owner) && board_cfg->display_off) {
6011bdea 955 board_cfg->display_off(board_cfg->board_data);
6de9edd5
GL		 956 module_put(board_cfg->owner);
957 }
6011bdea
GL		 958 pm_runtime_put(info->device);
959 break;
960 case FB_EVENT_RESUME:
961 var = &info->var;
962
963 /* HDMI must be enabled before LCDC configuration */
6de9edd5 964 if (try_module_get(board_cfg->owner) && board_cfg->display_on) {
6011bdea 965 board_cfg->display_on(board_cfg->board_data, ch->info);
6de9edd5
GL		 966 module_put(board_cfg->owner);
967 }
6011bdea
GL		 968
969 /* Check if the new display is not in our modelist */
970 if (ch->info->modelist.next &&
971 !fb_match_mode(var, &ch->info->modelist)) {
972 struct fb_videomode mode;
973 int ret;
974
975 /* Can we handle this display? */
44432407
GL		 976 if (var->xres > ch->cfg.lcd_cfg[0].xres ||
977 var->yres > ch->cfg.lcd_cfg[0].yres)
baf16374
GL		 978 /*
979 * LCDC resume failed, no need to continue with
980 * the notifier chain
981 */
982 return notifier_from_errno(-ENOMEM);
6011bdea
GL		 983
984 /* Add to the modelist */
985 fb_var_to_videomode(&mode, var);
986 ret = fb_add_videomode(&mode, &ch->info->modelist);
987 if (ret < 0)
baf16374 988 return notifier_from_errno(ret);
6011bdea
GL		 989 }
990
991 pm_runtime_get_sync(info->device);
992
993 sh_mobile_lcdc_geometry(ch);
6011bdea
GL		 994 }
995
baf16374 996 return NOTIFY_OK;
6011bdea
GL		 997}
998
cfb4f5d1
MD		 999static int sh_mobile_lcdc_remove(struct platform_device *pdev);
1000
c2e13037 1001static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev)
cfb4f5d1
MD		 1002{
1003 struct fb_info *info;
1004 struct sh_mobile_lcdc_priv *priv;
01ac25b5 1005 struct sh_mobile_lcdc_info *pdata = pdev->dev.platform_data;
cfb4f5d1
MD		 1006 struct sh_mobile_lcdc_chan_cfg *cfg;
1007 struct resource *res;
1008 int error;
1009 void *buf;
1010 int i, j;
1011
01ac25b5 1012 if (!pdata) {
cfb4f5d1 1013 dev_err(&pdev->dev, "no platform data defined\n");
8bed9055 1014 return -EINVAL;
cfb4f5d1
MD		 1015 }
1016
1017 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8564557a
MD		 1018 i = platform_get_irq(pdev, 0);
1019 if (!res || i < 0) {
1020 dev_err(&pdev->dev, "cannot get platform resources\n");
8bed9055 1021 return -ENOENT;
cfb4f5d1
MD		 1022 }
1023
1024 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1025 if (!priv) {
1026 dev_err(&pdev->dev, "cannot allocate device data\n");
8bed9055 1027 return -ENOMEM;
cfb4f5d1
MD		 1028 }
1029
8bed9055
GL		 1030 platform_set_drvdata(pdev, priv);
1031
8564557a 1032 error = request_irq(i, sh_mobile_lcdc_irq, IRQF_DISABLED,
7ad33e74 1033 dev_name(&pdev->dev), priv);
8564557a
MD		 1034 if (error) {
1035 dev_err(&pdev->dev, "unable to request irq\n");
1036 goto err1;
1037 }
1038
1039 priv->irq = i;
5ef6b505 1040 atomic_set(&priv->hw_usecnt, -1);
cfb4f5d1
MD		 1041
1042 j = 0;
1043 for (i = 0; i < ARRAY_SIZE(pdata->ch); i++) {
01ac25b5 1044 struct sh_mobile_lcdc_chan *ch = priv->ch + j;
cfb4f5d1 1045
01ac25b5
GL		 1046 ch->lcdc = priv;
1047 memcpy(&ch->cfg, &pdata->ch[i], sizeof(pdata->ch[i]));
1048
1049 error = sh_mobile_lcdc_check_interface(ch);
cfb4f5d1
MD		 1050 if (error) {
1051 dev_err(&pdev->dev, "unsupported interface type\n");
1052 goto err1;
1053 }
01ac25b5
GL		 1054 init_waitqueue_head(&ch->frame_end_wait);
1055 init_completion(&ch->vsync_completion);
1056 ch->pan_offset = 0;
cfb4f5d1
MD		 1057
1058 switch (pdata->ch[i].chan) {
1059 case LCDC_CHAN_MAINLCD:
01ac25b5
GL		 1060 ch->enabled = 1 << 1;
1061 ch->reg_offs = lcdc_offs_mainlcd;
cfb4f5d1
MD		 1062 j++;
1063 break;
1064 case LCDC_CHAN_SUBLCD:
01ac25b5
GL		 1065 ch->enabled = 1 << 2;
1066 ch->reg_offs = lcdc_offs_sublcd;
cfb4f5d1
MD		 1067 j++;
1068 break;
1069 }
1070 }
1071
1072 if (!j) {
1073 dev_err(&pdev->dev, "no channels defined\n");
1074 error = -EINVAL;
1075 goto err1;
1076 }
1077
dba6f385
GL		 1078 priv->base = ioremap_nocache(res->start, resource_size(res));
1079 if (!priv->base)
1080 goto err1;
1081
b51339ff 1082 error = sh_mobile_lcdc_setup_clocks(pdev, pdata->clock_source, priv);
cfb4f5d1
MD		 1083 if (error) {
1084 dev_err(&pdev->dev, "unable to setup clocks\n");
1085 goto err1;
1086 }
1087
cfb4f5d1 1088 for (i = 0; i < j; i++) {
6011bdea 1089 struct fb_var_screeninfo *var;
71d3b0fc 1090 const struct fb_videomode *lcd_cfg, *max_cfg = NULL;
01ac25b5 1091 struct sh_mobile_lcdc_chan *ch = priv->ch + i;
71d3b0fc
GL		 1092 unsigned long max_size = 0;
1093 int k;
cfb4f5d1 1094
01ac25b5
GL		 1095 cfg = &ch->cfg;
1096
1097 ch->info = framebuffer_alloc(0, &pdev->dev);
1098 if (!ch->info) {
e33afddc
PM		 1099 dev_err(&pdev->dev, "unable to allocate fb_info\n");
1100 error = -ENOMEM;
1101 break;
1102 }
1103
01ac25b5 1104 info = ch->info;
6011bdea 1105 var = &info->var;
cfb4f5d1 1106 info->fbops = &sh_mobile_lcdc_ops;
71d3b0fc 1107 fb_videomode_to_var(var, &cfg->lcd_cfg[0]);
9dd38819 1108 /* Default Y virtual resolution is 2x panel size */
6011bdea 1109 var->yres_virtual = var->yres * 2;
6011bdea
GL		 1110
1111 error = sh_mobile_lcdc_set_bpp(var, cfg->bpp);
cfb4f5d1
MD		 1112 if (error)
1113 break;
1114
71d3b0fc
GL		 1115 for (k = 0, lcd_cfg = cfg->lcd_cfg;
1116 k < cfg->num_cfg;
1117 k++, lcd_cfg++) {
1118 unsigned long size = lcd_cfg->yres * lcd_cfg->xres;
1119
1120 if (size > max_size) {
1121 max_cfg = lcd_cfg;
1122 max_size = size;
1123 }
1124 }
1125
1126 dev_dbg(&pdev->dev, "Found largest videomode %ux%u\n",
1127 max_cfg->xres, max_cfg->yres);
1128
cfb4f5d1 1129 info->fix = sh_mobile_lcdc_fix;
71d3b0fc
GL		 1130 info->fix.line_length = cfg->lcd_cfg[0].xres * (cfg->bpp / 8);
1131 info->fix.smem_len = max_size * (cfg->bpp / 8) * 2;
cfb4f5d1
MD		 1132
1133 buf = dma_alloc_coherent(&pdev->dev, info->fix.smem_len,
01ac25b5 1134 &ch->dma_handle, GFP_KERNEL);
cfb4f5d1
MD		 1135 if (!buf) {
1136 dev_err(&pdev->dev, "unable to allocate buffer\n");
1137 error = -ENOMEM;
1138 break;
1139 }
1140
01ac25b5 1141 info->pseudo_palette = &ch->pseudo_palette;
cfb4f5d1
MD		 1142 info->flags = FBINFO_FLAG_DEFAULT;
1143
1144 error = fb_alloc_cmap(&info->cmap, PALETTE_NR, 0);
1145 if (error < 0) {
1146 dev_err(&pdev->dev, "unable to allocate cmap\n");
1147 dma_free_coherent(&pdev->dev, info->fix.smem_len,
01ac25b5 1148 buf, ch->dma_handle);
cfb4f5d1
MD		 1149 break;
1150 }
1151
01ac25b5 1152 info->fix.smem_start = ch->dma_handle;
cfb4f5d1
MD		 1153 info->screen_base = buf;
1154 info->device = &pdev->dev;
01ac25b5 1155 info->par = ch;
cfb4f5d1
MD		 1156 }
1157
1158 if (error)
1159 goto err1;
1160
1161 error = sh_mobile_lcdc_start(priv);
1162 if (error) {
1163 dev_err(&pdev->dev, "unable to start hardware\n");
1164 goto err1;
1165 }
1166
1167 for (i = 0; i < j; i++) {
1c6a307a
PM		 1168 struct sh_mobile_lcdc_chan *ch = priv->ch + i;
1169
e33afddc 1170 info = ch->info;
1c6a307a
PM		 1171
1172 if (info->fbdefio) {
8bed9055 1173 ch->sglist = vmalloc(sizeof(struct scatterlist) *
1c6a307a 1174 info->fix.smem_len >> PAGE_SHIFT);
8bed9055 1175 if (!ch->sglist) {
1c6a307a
PM		 1176 dev_err(&pdev->dev, "cannot allocate sglist\n");
1177 goto err1;
1178 }
1179 }
1180
1181 error = register_framebuffer(info);
cfb4f5d1
MD		 1182 if (error < 0)
1183 goto err1;
cfb4f5d1 1184
cfb4f5d1
MD		 1185 dev_info(info->dev,
1186 "registered %s/%s as %dx%d %dbpp.\n",
1187 pdev->name,
1c6a307a 1188 (ch->cfg.chan == LCDC_CHAN_MAINLCD) ?
cfb4f5d1 1189 "mainlcd" : "sublcd",
44432407
GL		 1190 (int) ch->cfg.lcd_cfg[0].xres,
1191 (int) ch->cfg.lcd_cfg[0].yres,
1c6a307a 1192 ch->cfg.bpp);
8564557a
MD		 1193
1194 /* deferred io mode: disable clock to save power */
6011bdea 1195 if (info->fbdefio || info->state == FBINFO_STATE_SUSPENDED)
8564557a 1196 sh_mobile_lcdc_clk_off(priv);
cfb4f5d1
MD		 1197 }
1198
6011bdea
GL		 1199 /* Failure ignored */
1200 priv->notifier.notifier_call = sh_mobile_lcdc_notify;
1201 fb_register_client(&priv->notifier);
1202
cfb4f5d1 1203 return 0;
8bed9055 1204err1:
cfb4f5d1 1205 sh_mobile_lcdc_remove(pdev);
8bed9055 1206
cfb4f5d1
MD		 1207 return error;
1208}
1209
1210static int sh_mobile_lcdc_remove(struct platform_device *pdev)
1211{
1212 struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
1213 struct fb_info *info;
1214 int i;
1215
6011bdea
GL		 1216 fb_unregister_client(&priv->notifier);
1217
cfb4f5d1 1218 for (i = 0; i < ARRAY_SIZE(priv->ch); i++)
8bed9055 1219 if (priv->ch[i].info && priv->ch[i].info->dev)
e33afddc 1220 unregister_framebuffer(priv->ch[i].info);
cfb4f5d1
MD		 1221
1222 sh_mobile_lcdc_stop(priv);
1223
1224 for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
e33afddc 1225 info = priv->ch[i].info;
cfb4f5d1 1226
e33afddc 1227 if (!info || !info->device)
cfb4f5d1
MD		 1228 continue;
1229
1c6a307a
PM		 1230 if (priv->ch[i].sglist)
1231 vfree(priv->ch[i].sglist);
1232
cfb4f5d1
MD		 1233 dma_free_coherent(&pdev->dev, info->fix.smem_len,
1234 info->screen_base, priv->ch[i].dma_handle);
1235 fb_dealloc_cmap(&info->cmap);
e33afddc 1236 framebuffer_release(info);
cfb4f5d1
MD		 1237 }
1238
b51339ff
MD		 1239 if (priv->dot_clk)
1240 clk_put(priv->dot_clk);
0246c471 1241
8bed9055
GL		 1242 if (priv->dev)
1243 pm_runtime_disable(priv->dev);
cfb4f5d1
MD		 1244
1245 if (priv->base)
1246 iounmap(priv->base);
1247
8564557a
MD		 1248 if (priv->irq)
1249 free_irq(priv->irq, priv);
cfb4f5d1
MD		 1250 kfree(priv);
1251 return 0;
1252}
1253
1254static struct platform_driver sh_mobile_lcdc_driver = {
1255 .driver = {
1256 .name = "sh_mobile_lcdc_fb",
1257 .owner = THIS_MODULE,
2feb075a 1258 .pm = &sh_mobile_lcdc_dev_pm_ops,
cfb4f5d1
MD		 1259 },
1260 .probe = sh_mobile_lcdc_probe,
1261 .remove = sh_mobile_lcdc_remove,
1262};
1263
1264static int __init sh_mobile_lcdc_init(void)
1265{
1266 return platform_driver_register(&sh_mobile_lcdc_driver);
1267}
1268
1269static void __exit sh_mobile_lcdc_exit(void)
1270{
1271 platform_driver_unregister(&sh_mobile_lcdc_driver);
1272}
1273
1274module_init(sh_mobile_lcdc_init);
1275module_exit(sh_mobile_lcdc_exit);
1276
1277MODULE_DESCRIPTION("SuperH Mobile LCDC Framebuffer driver");
1278MODULE_AUTHOR("Magnus Damm <damm@opensource.se>");
1279MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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