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sh_mobile_meram: MERAM framework for LCDC
[deliverable/linux.git] / drivers / video / sh_mobile_lcdcfb.c
CommitLineData
cfb4f5d1
MD		 1/*
2 * SuperH Mobile LCDC Framebuffer
3 *
4 * Copyright (c) 2008 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/delay.h>
14#include <linux/mm.h>
cfb4f5d1 15#include <linux/clk.h>
0246c471 16#include <linux/pm_runtime.h>
cfb4f5d1
MD		 17#include <linux/platform_device.h>
18#include <linux/dma-mapping.h>
8564557a 19#include <linux/interrupt.h>
1c6a307a 20#include <linux/vmalloc.h>
40331b21 21#include <linux/ioctl.h>
5a0e3ad6 22#include <linux/slab.h>
dd210503 23#include <linux/console.h>
3b0fd9d7
AC		 24#include <linux/backlight.h>
25#include <linux/gpio.h>
225c9a8d 26#include <video/sh_mobile_lcdc.h>
8564557a 27#include <asm/atomic.h>
cfb4f5d1 28
6de9edd5 29#include "sh_mobile_lcdcfb.h"
7caa4342 30#include "sh_mobile_meram.h"
6de9edd5 31
a6f15ade
PE		 32#define SIDE_B_OFFSET 0x1000
33#define MIRROR_OFFSET 0x2000
cfb4f5d1 34
cfb4f5d1
MD		 35/* shared registers */
36#define _LDDCKR 0x410
37#define _LDDCKSTPR 0x414
38#define _LDINTR 0x468
39#define _LDSR 0x46c
40#define _LDCNT1R 0x470
41#define _LDCNT2R 0x474
9dd38819 42#define _LDRCNTR 0x478
cfb4f5d1
MD		 43#define _LDDDSR 0x47c
44#define _LDDWD0R 0x800
45#define _LDDRDR 0x840
46#define _LDDWAR 0x900
47#define _LDDRAR 0x904
48
0246c471
MD		 49/* shared registers and their order for context save/restore */
50static int lcdc_shared_regs[] = {
51 _LDDCKR,
52 _LDDCKSTPR,
53 _LDINTR,
54 _LDDDSR,
55 _LDCNT1R,
56 _LDCNT2R,
57};
58#define NR_SHARED_REGS ARRAY_SIZE(lcdc_shared_regs)
59
d2ecbab5
GL		 60#define MAX_XRES 1920
61#define MAX_YRES 1080
cfb4f5d1 62
0246c471 63static unsigned long lcdc_offs_mainlcd[NR_CH_REGS] = {
cfb4f5d1
MD		 64 [LDDCKPAT1R] = 0x400,
65 [LDDCKPAT2R] = 0x404,
66 [LDMT1R] = 0x418,
67 [LDMT2R] = 0x41c,
68 [LDMT3R] = 0x420,
69 [LDDFR] = 0x424,
70 [LDSM1R] = 0x428,
8564557a 71 [LDSM2R] = 0x42c,
cfb4f5d1 72 [LDSA1R] = 0x430,
53b50314 73 [LDSA2R] = 0x434,
cfb4f5d1
MD		 74 [LDMLSR] = 0x438,
75 [LDHCNR] = 0x448,
76 [LDHSYNR] = 0x44c,
77 [LDVLNR] = 0x450,
78 [LDVSYNR] = 0x454,
79 [LDPMR] = 0x460,
6011bdea 80 [LDHAJR] = 0x4a0,
cfb4f5d1
MD		 81};
82
0246c471 83static unsigned long lcdc_offs_sublcd[NR_CH_REGS] = {
cfb4f5d1
MD		 84 [LDDCKPAT1R] = 0x408,
85 [LDDCKPAT2R] = 0x40c,
86 [LDMT1R] = 0x600,
87 [LDMT2R] = 0x604,
88 [LDMT3R] = 0x608,
89 [LDDFR] = 0x60c,
90 [LDSM1R] = 0x610,
8564557a 91 [LDSM2R] = 0x614,
cfb4f5d1
MD		 92 [LDSA1R] = 0x618,
93 [LDMLSR] = 0x620,
94 [LDHCNR] = 0x624,
95 [LDHSYNR] = 0x628,
96 [LDVLNR] = 0x62c,
97 [LDVSYNR] = 0x630,
98 [LDPMR] = 0x63c,
99};
100
101#define START_LCDC 0x00000001
102#define LCDC_RESET 0x00000100
103#define DISPLAY_BEU 0x00000008
104#define LCDC_ENABLE 0x00000001
8564557a 105#define LDINTR_FE 0x00000400
9dd38819
PE		 106#define LDINTR_VSE 0x00000200
107#define LDINTR_VEE 0x00000100
8564557a 108#define LDINTR_FS 0x00000004
9dd38819
PE		 109#define LDINTR_VSS 0x00000002
110#define LDINTR_VES 0x00000001
a6f15ade
PE		 111#define LDRCNTR_SRS 0x00020000
112#define LDRCNTR_SRC 0x00010000
113#define LDRCNTR_MRS 0x00000002
114#define LDRCNTR_MRC 0x00000001
40331b21 115#define LDSR_MRS 0x00000100
cfb4f5d1 116
c44f9f76
GL		 117static const struct fb_videomode default_720p = {
118 .name = "HDMI 720p",
119 .xres = 1280,
120 .yres = 720,
121
5ae0cf82
GL		 122 .left_margin = 220,
123 .right_margin = 110,
124 .hsync_len = 40,
c44f9f76
GL		 125
126 .upper_margin = 20,
127 .lower_margin = 5,
128 .vsync_len = 5,
129
130 .pixclock = 13468,
5ae0cf82 131 .refresh = 60,
c44f9f76 132 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
0246c471
MD		 133};
134
135struct sh_mobile_lcdc_priv {
136 void __iomem *base;
137 int irq;
138 atomic_t hw_usecnt;
139 struct device *dev;
140 struct clk *dot_clk;
141 unsigned long lddckr;
142 struct sh_mobile_lcdc_chan ch[2];
6011bdea 143 struct notifier_block notifier;
0246c471
MD		 144 unsigned long saved_shared_regs[NR_SHARED_REGS];
145 int started;
417d4827 146 int forced_bpp; /* 2 channel LCDC must share bpp setting */
7caa4342 147 struct sh_mobile_meram_info *meram_dev;
0246c471
MD		 148};
149
a6f15ade
PE		 150static bool banked(int reg_nr)
151{
152 switch (reg_nr) {
153 case LDMT1R:
154 case LDMT2R:
155 case LDMT3R:
156 case LDDFR:
157 case LDSM1R:
158 case LDSA1R:
53b50314 159 case LDSA2R:
a6f15ade
PE		 160 case LDMLSR:
161 case LDHCNR:
162 case LDHSYNR:
163 case LDVLNR:
164 case LDVSYNR:
165 return true;
166 }
167 return false;
168}
169
cfb4f5d1
MD		 170static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan,
171 int reg_nr, unsigned long data)
172{
173 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]);
a6f15ade
PE		 174 if (banked(reg_nr))
175 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
176 SIDE_B_OFFSET);
177}
178
179static void lcdc_write_chan_mirror(struct sh_mobile_lcdc_chan *chan,
180 int reg_nr, unsigned long data)
181{
182 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
183 MIRROR_OFFSET);
cfb4f5d1
MD		 184}
185
186static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan,
187 int reg_nr)
188{
189 return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]);
190}
191
192static void lcdc_write(struct sh_mobile_lcdc_priv *priv,
193 unsigned long reg_offs, unsigned long data)
194{
195 iowrite32(data, priv->base + reg_offs);
196}
197
198static unsigned long lcdc_read(struct sh_mobile_lcdc_priv *priv,
199 unsigned long reg_offs)
200{
201 return ioread32(priv->base + reg_offs);
202}
203
204static void lcdc_wait_bit(struct sh_mobile_lcdc_priv *priv,
205 unsigned long reg_offs,
206 unsigned long mask, unsigned long until)
207{
208 while ((lcdc_read(priv, reg_offs) & mask) != until)
209 cpu_relax();
210}
211
212static int lcdc_chan_is_sublcd(struct sh_mobile_lcdc_chan *chan)
213{
214 return chan->cfg.chan == LCDC_CHAN_SUBLCD;
215}
216
217static void lcdc_sys_write_index(void *handle, unsigned long data)
218{
219 struct sh_mobile_lcdc_chan *ch = handle;
220
221 lcdc_write(ch->lcdc, _LDDWD0R, data | 0x10000000);
222 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
223 lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
909f10de 224 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
cfb4f5d1
MD		 225}
226
227static void lcdc_sys_write_data(void *handle, unsigned long data)
228{
229 struct sh_mobile_lcdc_chan *ch = handle;
230
231 lcdc_write(ch->lcdc, _LDDWD0R, data | 0x11000000);
232 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
233 lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
909f10de 234 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
cfb4f5d1
MD		 235}
236
237static unsigned long lcdc_sys_read_data(void *handle)
238{
239 struct sh_mobile_lcdc_chan *ch = handle;
240
241 lcdc_write(ch->lcdc, _LDDRDR, 0x01000000);
242 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
243 lcdc_write(ch->lcdc, _LDDRAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
244 udelay(1);
909f10de 245 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
cfb4f5d1 246
ec56b66f 247 return lcdc_read(ch->lcdc, _LDDRDR) & 0x3ffff;
cfb4f5d1
MD		 248}
249
250struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = {
251 lcdc_sys_write_index,
252 lcdc_sys_write_data,
253 lcdc_sys_read_data,
254};
255
8564557a
MD		 256static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv)
257{
0246c471
MD		 258 if (atomic_inc_and_test(&priv->hw_usecnt)) {
259 pm_runtime_get_sync(priv->dev);
8564557a
MD		 260 if (priv->dot_clk)
261 clk_enable(priv->dot_clk);
262 }
263}
264
265static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv)
266{
0246c471 267 if (atomic_sub_return(1, &priv->hw_usecnt) == -1) {
8564557a
MD		 268 if (priv->dot_clk)
269 clk_disable(priv->dot_clk);
0246c471 270 pm_runtime_put(priv->dev);
8564557a
MD		 271 }
272}
8564557a 273
1c6a307a
PM		 274static int sh_mobile_lcdc_sginit(struct fb_info *info,
275 struct list_head *pagelist)
276{
277 struct sh_mobile_lcdc_chan *ch = info->par;
278 unsigned int nr_pages_max = info->fix.smem_len >> PAGE_SHIFT;
279 struct page *page;
280 int nr_pages = 0;
281
282 sg_init_table(ch->sglist, nr_pages_max);
283
284 list_for_each_entry(page, pagelist, lru)
285 sg_set_page(&ch->sglist[nr_pages++], page, PAGE_SIZE, 0);
286
287 return nr_pages;
288}
289
8564557a
MD		 290static void sh_mobile_lcdc_deferred_io(struct fb_info *info,
291 struct list_head *pagelist)
292{
293 struct sh_mobile_lcdc_chan *ch = info->par;
ef61aae4 294 struct sh_mobile_lcdc_board_cfg *bcfg = &ch->cfg.board_cfg;
8564557a
MD		 295
296 /* enable clocks before accessing hardware */
297 sh_mobile_lcdc_clk_on(ch->lcdc);
298
5c1a56b5
PM		 299 /*
300 * It's possible to get here without anything on the pagelist via
301 * sh_mobile_lcdc_deferred_io_touch() or via a userspace fsync()
302 * invocation. In the former case, the acceleration routines are
303 * stepped in to when using the framebuffer console causing the
304 * workqueue to be scheduled without any dirty pages on the list.
305 *
306 * Despite this, a panel update is still needed given that the
307 * acceleration routines have their own methods for writing in
308 * that still need to be updated.
309 *
310 * The fsync() and empty pagelist case could be optimized for,
311 * but we don't bother, as any application exhibiting such
312 * behaviour is fundamentally broken anyways.
313 */
314 if (!list_empty(pagelist)) {
315 unsigned int nr_pages = sh_mobile_lcdc_sginit(info, pagelist);
316
317 /* trigger panel update */
318 dma_map_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
ef61aae4
MD		 319 if (bcfg->start_transfer)
320 bcfg->start_transfer(bcfg->board_data, ch,
321 &sh_mobile_lcdc_sys_bus_ops);
5c1a56b5
PM		 322 lcdc_write_chan(ch, LDSM2R, 1);
323 dma_unmap_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
ef61aae4
MD		 324 } else {
325 if (bcfg->start_transfer)
326 bcfg->start_transfer(bcfg->board_data, ch,
327 &sh_mobile_lcdc_sys_bus_ops);
5c1a56b5 328 lcdc_write_chan(ch, LDSM2R, 1);
ef61aae4 329 }
8564557a
MD		 330}
331
332static void sh_mobile_lcdc_deferred_io_touch(struct fb_info *info)
333{
334 struct fb_deferred_io *fbdefio = info->fbdefio;
335
336 if (fbdefio)
337 schedule_delayed_work(&info->deferred_work, fbdefio->delay);
338}
339
340static irqreturn_t sh_mobile_lcdc_irq(int irq, void *data)
341{
342 struct sh_mobile_lcdc_priv *priv = data;
2feb075a 343 struct sh_mobile_lcdc_chan *ch;
8564557a 344 unsigned long tmp;
9dd38819 345 unsigned long ldintr;
2feb075a
MD		 346 int is_sub;
347 int k;
8564557a
MD		 348
349 /* acknowledge interrupt */
9dd38819
PE		 350 ldintr = tmp = lcdc_read(priv, _LDINTR);
351 /*
352 * disable further VSYNC End IRQs, preserve all other enabled IRQs,
353 * write 0 to bits 0-6 to ack all triggered IRQs.
354 */
355 tmp &= 0xffffff00 & ~LDINTR_VEE;
8564557a
MD		 356 lcdc_write(priv, _LDINTR, tmp);
357
2feb075a
MD		 358 /* figure out if this interrupt is for main or sub lcd */
359 is_sub = (lcdc_read(priv, _LDSR) & (1 << 10)) ? 1 : 0;
360
9dd38819 361 /* wake up channel and disable clocks */
2feb075a
MD		 362 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
363 ch = &priv->ch[k];
364
365 if (!ch->enabled)
366 continue;
367
9dd38819
PE		 368 /* Frame Start */
369 if (ldintr & LDINTR_FS) {
370 if (is_sub == lcdc_chan_is_sublcd(ch)) {
371 ch->frame_end = 1;
372 wake_up(&ch->frame_end_wait);
2feb075a 373
9dd38819
PE		 374 sh_mobile_lcdc_clk_off(priv);
375 }
376 }
377
378 /* VSYNC End */
40331b21
PE		 379 if (ldintr & LDINTR_VES)
380 complete(&ch->vsync_completion);
2feb075a
MD		 381 }
382
8564557a
MD		 383 return IRQ_HANDLED;
384}
385
cfb4f5d1
MD		 386static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv *priv,
387 int start)
388{
389 unsigned long tmp = lcdc_read(priv, _LDCNT2R);
390 int k;
391
392 /* start or stop the lcdc */
393 if (start)
394 lcdc_write(priv, _LDCNT2R, tmp | START_LCDC);
395 else
396 lcdc_write(priv, _LDCNT2R, tmp & ~START_LCDC);
397
398 /* wait until power is applied/stopped on all channels */
399 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
400 if (lcdc_read(priv, _LDCNT2R) & priv->ch[k].enabled)
401 while (1) {
402 tmp = lcdc_read_chan(&priv->ch[k], LDPMR) & 3;
403 if (start && tmp == 3)
404 break;
405 if (!start && tmp == 0)
406 break;
407 cpu_relax();
408 }
409
410 if (!start)
411 lcdc_write(priv, _LDDCKSTPR, 1); /* stop dotclock */
412}
413
6011bdea
GL		 414static void sh_mobile_lcdc_geometry(struct sh_mobile_lcdc_chan *ch)
415{
1c120deb
GL		 416 struct fb_var_screeninfo *var = &ch->info->var, *display_var = &ch->display_var;
417 unsigned long h_total, hsync_pos, display_h_total;
6011bdea
GL		 418 u32 tmp;
419
420 tmp = ch->ldmt1r_value;
421 tmp |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1 << 28;
422 tmp |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1 << 27;
423 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWPOL) ? 1 << 26 : 0;
424 tmp |= (ch->cfg.flags & LCDC_FLAGS_DIPOL) ? 1 << 25 : 0;
425 tmp |= (ch->cfg.flags & LCDC_FLAGS_DAPOL) ? 1 << 24 : 0;
426 tmp |= (ch->cfg.flags & LCDC_FLAGS_HSCNT) ? 1 << 17 : 0;
427 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWCNT) ? 1 << 16 : 0;
428 lcdc_write_chan(ch, LDMT1R, tmp);
429
430 /* setup SYS bus */
431 lcdc_write_chan(ch, LDMT2R, ch->cfg.sys_bus_cfg.ldmt2r);
432 lcdc_write_chan(ch, LDMT3R, ch->cfg.sys_bus_cfg.ldmt3r);
433
434 /* horizontal configuration */
1c120deb
GL		 435 h_total = display_var->xres + display_var->hsync_len +
436 display_var->left_margin + display_var->right_margin;
6011bdea 437 tmp = h_total / 8; /* HTCN */
1c120deb 438 tmp |= (min(display_var->xres, var->xres) / 8) << 16; /* HDCN */
6011bdea
GL		 439 lcdc_write_chan(ch, LDHCNR, tmp);
440
1c120deb 441 hsync_pos = display_var->xres + display_var->right_margin;
6011bdea 442 tmp = hsync_pos / 8; /* HSYNP */
1c120deb 443 tmp |= (display_var->hsync_len / 8) << 16; /* HSYNW */
6011bdea
GL		 444 lcdc_write_chan(ch, LDHSYNR, tmp);
445
446 /* vertical configuration */
1c120deb
GL		 447 tmp = display_var->yres + display_var->vsync_len +
448 display_var->upper_margin + display_var->lower_margin; /* VTLN */
449 tmp |= min(display_var->yres, var->yres) << 16; /* VDLN */
6011bdea
GL		 450 lcdc_write_chan(ch, LDVLNR, tmp);
451
1c120deb
GL		 452 tmp = display_var->yres + display_var->lower_margin; /* VSYNP */
453 tmp |= display_var->vsync_len << 16; /* VSYNW */
6011bdea
GL		 454 lcdc_write_chan(ch, LDVSYNR, tmp);
455
456 /* Adjust horizontal synchronisation for HDMI */
1c120deb
GL		 457 display_h_total = display_var->xres + display_var->hsync_len +
458 display_var->left_margin + display_var->right_margin;
459 tmp = ((display_var->xres & 7) << 24) |
460 ((display_h_total & 7) << 16) |
461 ((display_var->hsync_len & 7) << 8) |
6011bdea
GL		 462 hsync_pos;
463 lcdc_write_chan(ch, LDHAJR, tmp);
464}
465
cfb4f5d1
MD		 466static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
467{
468 struct sh_mobile_lcdc_chan *ch;
cfb4f5d1
MD		 469 struct sh_mobile_lcdc_board_cfg *board_cfg;
470 unsigned long tmp;
417d4827 471 int bpp = 0;
53b50314 472 unsigned long ldddsr;
cfb4f5d1
MD		 473 int k, m;
474 int ret = 0;
475
8564557a 476 /* enable clocks before accessing the hardware */
417d4827
MD		 477 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
478 if (priv->ch[k].enabled) {
8564557a 479 sh_mobile_lcdc_clk_on(priv);
417d4827
MD		 480 if (!bpp)
481 bpp = priv->ch[k].info->var.bits_per_pixel;
482 }
483 }
8564557a 484
cfb4f5d1
MD		 485 /* reset */
486 lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LCDC_RESET);
487 lcdc_wait_bit(priv, _LDCNT2R, LCDC_RESET, 0);
488
489 /* enable LCDC channels */
490 tmp = lcdc_read(priv, _LDCNT2R);
491 tmp |= priv->ch[0].enabled;
492 tmp |= priv->ch[1].enabled;
493 lcdc_write(priv, _LDCNT2R, tmp);
494
495 /* read data from external memory, avoid using the BEU for now */
496 lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) & ~DISPLAY_BEU);
497
498 /* stop the lcdc first */
499 sh_mobile_lcdc_start_stop(priv, 0);
500
501 /* configure clocks */
502 tmp = priv->lddckr;
503 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
504 ch = &priv->ch[k];
505
506 if (!priv->ch[k].enabled)
507 continue;
508
509 m = ch->cfg.clock_divider;
510 if (!m)
511 continue;
512
513 if (m == 1)
514 m = 1 << 6;
515 tmp |= m << (lcdc_chan_is_sublcd(ch) ? 8 : 0);
516
dd210503 517 /* FIXME: sh7724 can only use 42, 48, 54 and 60 for the divider denominator */
1c120deb 518 lcdc_write_chan(ch, LDDCKPAT1R, 0);
cfb4f5d1
MD		 519 lcdc_write_chan(ch, LDDCKPAT2R, (1 << (m/2)) - 1);
520 }
521
522 lcdc_write(priv, _LDDCKR, tmp);
523
524 /* start dotclock again */
525 lcdc_write(priv, _LDDCKSTPR, 0);
526 lcdc_wait_bit(priv, _LDDCKSTPR, ~0, 0);
527
8564557a 528 /* interrupts are disabled to begin with */
cfb4f5d1
MD		 529 lcdc_write(priv, _LDINTR, 0);
530
531 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
532 ch = &priv->ch[k];
cfb4f5d1
MD		 533
534 if (!ch->enabled)
535 continue;
536
6011bdea 537 sh_mobile_lcdc_geometry(ch);
cfb4f5d1
MD		 538
539 /* power supply */
540 lcdc_write_chan(ch, LDPMR, 0);
541
cfb4f5d1
MD		 542 board_cfg = &ch->cfg.board_cfg;
543 if (board_cfg->setup_sys)
544 ret = board_cfg->setup_sys(board_cfg->board_data, ch,
545 &sh_mobile_lcdc_sys_bus_ops);
546 if (ret)
547 return ret;
548 }
549
cfb4f5d1 550 /* word and long word swap */
53b50314
DHG		 551 ldddsr = lcdc_read(priv, _LDDDSR);
552 if (priv->ch[0].info->var.nonstd)
553 lcdc_write(priv, _LDDDSR, ldddsr | 7);
554 else {
555 switch (bpp) {
556 case 16:
557 lcdc_write(priv, _LDDDSR, ldddsr | 6);
558 break;
559 case 24:
560 lcdc_write(priv, _LDDDSR, ldddsr | 7);
561 break;
562 case 32:
563 lcdc_write(priv, _LDDDSR, ldddsr | 4);
564 break;
565 }
417d4827 566 }
cfb4f5d1
MD		 567
568 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
7caa4342
D		 569 unsigned long base_addr_y;
570 unsigned long base_addr_c = 0;
571 int pitch;
cfb4f5d1
MD		 572 ch = &priv->ch[k];
573
574 if (!priv->ch[k].enabled)
575 continue;
576
577 /* set bpp format in PKF[4:0] */
578 tmp = lcdc_read_chan(ch, LDDFR);
53b50314
DHG		 579 tmp &= ~0x0003031f;
580 if (ch->info->var.nonstd) {
581 tmp |= (ch->info->var.nonstd << 16);
582 switch (ch->info->var.bits_per_pixel) {
583 case 12:
584 break;
585 case 16:
586 tmp |= (0x1 << 8);
587 break;
588 case 24:
589 tmp |= (0x2 << 8);
590 break;
591 }
592 } else {
593 switch (ch->info->var.bits_per_pixel) {
594 case 16:
595 tmp |= 0x03;
596 break;
597 case 24:
598 tmp |= 0x0b;
599 break;
600 case 32:
601 break;
602 }
417d4827 603 }
cfb4f5d1
MD		 604 lcdc_write_chan(ch, LDDFR, tmp);
605
7caa4342
D		 606 base_addr_y = ch->info->fix.smem_start;
607 base_addr_c = base_addr_y +
608 ch->info->var.xres *
609 ch->info->var.yres_virtual;
610 pitch = ch->info->fix.line_length;
611
612 /* test if we can enable meram */
613 if (ch->cfg.meram_cfg && priv->meram_dev) {
614 struct sh_mobile_meram_cfg *cfg;
615 struct sh_mobile_meram_info *mdev;
616 unsigned long icb_addr_y, icb_addr_c;
617 int icb_pitch;
618 int pf;
619
620 cfg = ch->cfg.meram_cfg;
621 mdev = priv->meram_dev;
622 /* we need to de-init configured ICBs before we
623 * we can re-initialize them.
624 */
625 if (ch->meram_enabled)
626 mdev->ops->meram_unregister(mdev, cfg);
627
628 ch->meram_enabled = 0;
629
630 if (ch->info->var.nonstd)
631 pf = SH_MOBILE_MERAM_PF_NV;
632 else
633 pf = SH_MOBILE_MERAM_PF_RGB;
634
635 ret = mdev->ops->meram_register(mdev, cfg, pitch,
636 ch->info->var.yres,
637 pf,
638 base_addr_y,
639 base_addr_c,
640 &icb_addr_y,
641 &icb_addr_c,
642 &icb_pitch);
643 if (!ret) {
644 /* set LDSA1R value */
645 base_addr_y = icb_addr_y;
646 pitch = icb_pitch;
647
648 /* set LDSA2R value if required */
649 if (base_addr_c)
650 base_addr_c = icb_addr_c;
651
652 ch->meram_enabled = 1;
653 }
654 }
655
cfb4f5d1 656 /* point out our frame buffer */
7caa4342 657 lcdc_write_chan(ch, LDSA1R, base_addr_y);
53b50314 658 if (ch->info->var.nonstd)
7caa4342 659 lcdc_write_chan(ch, LDSA2R, base_addr_c);
cfb4f5d1
MD		 660
661 /* set line size */
7caa4342 662 lcdc_write_chan(ch, LDMLSR, pitch);
cfb4f5d1 663
8564557a
MD		 664 /* setup deferred io if SYS bus */
665 tmp = ch->cfg.sys_bus_cfg.deferred_io_msec;
666 if (ch->ldmt1r_value & (1 << 12) && tmp) {
667 ch->defio.deferred_io = sh_mobile_lcdc_deferred_io;
668 ch->defio.delay = msecs_to_jiffies(tmp);
e33afddc
PM		 669 ch->info->fbdefio = &ch->defio;
670 fb_deferred_io_init(ch->info);
8564557a
MD		 671
672 /* one-shot mode */
673 lcdc_write_chan(ch, LDSM1R, 1);
674
675 /* enable "Frame End Interrupt Enable" bit */
676 lcdc_write(priv, _LDINTR, LDINTR_FE);
677
678 } else {
679 /* continuous read mode */
680 lcdc_write_chan(ch, LDSM1R, 0);
681 }
cfb4f5d1
MD		 682 }
683
684 /* display output */
685 lcdc_write(priv, _LDCNT1R, LCDC_ENABLE);
686
687 /* start the lcdc */
688 sh_mobile_lcdc_start_stop(priv, 1);
8e9bb19e 689 priv->started = 1;
cfb4f5d1
MD		 690
691 /* tell the board code to enable the panel */
692 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
693 ch = &priv->ch[k];
21bc1f02
MD		 694 if (!ch->enabled)
695 continue;
696
cfb4f5d1 697 board_cfg = &ch->cfg.board_cfg;
247f9938 698 if (board_cfg->display_on && try_module_get(board_cfg->owner)) {
c2439398 699 board_cfg->display_on(board_cfg->board_data, ch->info);
6de9edd5
GL		 700 module_put(board_cfg->owner);
701 }
3b0fd9d7
AC		 702
703 if (ch->bl) {
704 ch->bl->props.power = FB_BLANK_UNBLANK;
705 backlight_update_status(ch->bl);
706 }
cfb4f5d1
MD		 707 }
708
709 return 0;
710}
711
712static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
713{
714 struct sh_mobile_lcdc_chan *ch;
715 struct sh_mobile_lcdc_board_cfg *board_cfg;
716 int k;
717
2feb075a 718 /* clean up deferred io and ask board code to disable panel */
cfb4f5d1
MD		 719 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
720 ch = &priv->ch[k];
21bc1f02
MD		 721 if (!ch->enabled)
722 continue;
8564557a 723
2feb075a
MD		 724 /* deferred io mode:
725 * flush frame, and wait for frame end interrupt
726 * clean up deferred io and enable clock
727 */
5ef6b505 728 if (ch->info && ch->info->fbdefio) {
2feb075a 729 ch->frame_end = 0;
e33afddc 730 schedule_delayed_work(&ch->info->deferred_work, 0);
2feb075a 731 wait_event(ch->frame_end_wait, ch->frame_end);
e33afddc
PM		 732 fb_deferred_io_cleanup(ch->info);
733 ch->info->fbdefio = NULL;
2feb075a 734 sh_mobile_lcdc_clk_on(priv);
8564557a 735 }
2feb075a 736
3b0fd9d7
AC		 737 if (ch->bl) {
738 ch->bl->props.power = FB_BLANK_POWERDOWN;
739 backlight_update_status(ch->bl);
740 }
741
2feb075a 742 board_cfg = &ch->cfg.board_cfg;
247f9938 743 if (board_cfg->display_off && try_module_get(board_cfg->owner)) {
2feb075a 744 board_cfg->display_off(board_cfg->board_data);
6de9edd5
GL		 745 module_put(board_cfg->owner);
746 }
7caa4342
D		 747
748 /* disable the meram */
749 if (ch->meram_enabled) {
750 struct sh_mobile_meram_cfg *cfg;
751 struct sh_mobile_meram_info *mdev;
752 cfg = ch->cfg.meram_cfg;
753 mdev = priv->meram_dev;
754 mdev->ops->meram_unregister(mdev, cfg);
755 ch->meram_enabled = 0;
756 }
757
cfb4f5d1
MD		 758 }
759
760 /* stop the lcdc */
8e9bb19e
MD		 761 if (priv->started) {
762 sh_mobile_lcdc_start_stop(priv, 0);
763 priv->started = 0;
764 }
b51339ff 765
8564557a
MD		 766 /* stop clocks */
767 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
768 if (priv->ch[k].enabled)
769 sh_mobile_lcdc_clk_off(priv);
cfb4f5d1
MD		 770}
771
772static int sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan *ch)
773{
774 int ifm, miftyp;
775
776 switch (ch->cfg.interface_type) {
777 case RGB8: ifm = 0; miftyp = 0; break;
778 case RGB9: ifm = 0; miftyp = 4; break;
779 case RGB12A: ifm = 0; miftyp = 5; break;
780 case RGB12B: ifm = 0; miftyp = 6; break;
781 case RGB16: ifm = 0; miftyp = 7; break;
782 case RGB18: ifm = 0; miftyp = 10; break;
783 case RGB24: ifm = 0; miftyp = 11; break;
784 case SYS8A: ifm = 1; miftyp = 0; break;
785 case SYS8B: ifm = 1; miftyp = 1; break;
786 case SYS8C: ifm = 1; miftyp = 2; break;
787 case SYS8D: ifm = 1; miftyp = 3; break;
788 case SYS9: ifm = 1; miftyp = 4; break;
789 case SYS12: ifm = 1; miftyp = 5; break;
790 case SYS16A: ifm = 1; miftyp = 7; break;
791 case SYS16B: ifm = 1; miftyp = 8; break;
792 case SYS16C: ifm = 1; miftyp = 9; break;
793 case SYS18: ifm = 1; miftyp = 10; break;
794 case SYS24: ifm = 1; miftyp = 11; break;
795 default: goto bad;
796 }
797
798 /* SUBLCD only supports SYS interface */
799 if (lcdc_chan_is_sublcd(ch)) {
800 if (ifm == 0)
801 goto bad;
802 else
803 ifm = 0;
804 }
805
806 ch->ldmt1r_value = (ifm << 12) | miftyp;
807 return 0;
808 bad:
809 return -EINVAL;
810}
811
b51339ff
MD		 812static int sh_mobile_lcdc_setup_clocks(struct platform_device *pdev,
813 int clock_source,
cfb4f5d1
MD		 814 struct sh_mobile_lcdc_priv *priv)
815{
816 char *str;
817 int icksel;
818
819 switch (clock_source) {
820 case LCDC_CLK_BUS: str = "bus_clk"; icksel = 0; break;
821 case LCDC_CLK_PERIPHERAL: str = "peripheral_clk"; icksel = 1; break;
822 case LCDC_CLK_EXTERNAL: str = NULL; icksel = 2; break;
823 default:
824 return -EINVAL;
825 }
826
827 priv->lddckr = icksel << 16;
828
829 if (str) {
b51339ff
MD		 830 priv->dot_clk = clk_get(&pdev->dev, str);
831 if (IS_ERR(priv->dot_clk)) {
832 dev_err(&pdev->dev, "cannot get dot clock %s\n", str);
b51339ff 833 return PTR_ERR(priv->dot_clk);
cfb4f5d1 834 }
cfb4f5d1 835 }
0246c471
MD		 836
837 /* Runtime PM support involves two step for this driver:
838 * 1) Enable Runtime PM
839 * 2) Force Runtime PM Resume since hardware is accessed from probe()
840 */
8bed9055 841 priv->dev = &pdev->dev;
0246c471
MD		 842 pm_runtime_enable(priv->dev);
843 pm_runtime_resume(priv->dev);
cfb4f5d1
MD		 844 return 0;
845}
846
847static int sh_mobile_lcdc_setcolreg(u_int regno,
848 u_int red, u_int green, u_int blue,
849 u_int transp, struct fb_info *info)
850{
851 u32 *palette = info->pseudo_palette;
852
853 if (regno >= PALETTE_NR)
854 return -EINVAL;
855
856 /* only FB_VISUAL_TRUECOLOR supported */
857
858 red >>= 16 - info->var.red.length;
859 green >>= 16 - info->var.green.length;
860 blue >>= 16 - info->var.blue.length;
861 transp >>= 16 - info->var.transp.length;
862
863 palette[regno] = (red << info->var.red.offset) |
864 (green << info->var.green.offset) |
865 (blue << info->var.blue.offset) |
866 (transp << info->var.transp.offset);
867
868 return 0;
869}
870
871static struct fb_fix_screeninfo sh_mobile_lcdc_fix = {
872 .id = "SH Mobile LCDC",
873 .type = FB_TYPE_PACKED_PIXELS,
874 .visual = FB_VISUAL_TRUECOLOR,
875 .accel = FB_ACCEL_NONE,
9dd38819
PE		 876 .xpanstep = 0,
877 .ypanstep = 1,
878 .ywrapstep = 0,
cfb4f5d1
MD		 879};
880
8564557a
MD		 881static void sh_mobile_lcdc_fillrect(struct fb_info *info,
882 const struct fb_fillrect *rect)
883{
884 sys_fillrect(info, rect);
885 sh_mobile_lcdc_deferred_io_touch(info);
886}
887
888static void sh_mobile_lcdc_copyarea(struct fb_info *info,
889 const struct fb_copyarea *area)
890{
891 sys_copyarea(info, area);
892 sh_mobile_lcdc_deferred_io_touch(info);
893}
894
895static void sh_mobile_lcdc_imageblit(struct fb_info *info,
896 const struct fb_image *image)
897{
898 sys_imageblit(info, image);
899 sh_mobile_lcdc_deferred_io_touch(info);
900}
901
9dd38819
PE		 902static int sh_mobile_fb_pan_display(struct fb_var_screeninfo *var,
903 struct fb_info *info)
904{
905 struct sh_mobile_lcdc_chan *ch = info->par;
92e1f9a7
PE		 906 struct sh_mobile_lcdc_priv *priv = ch->lcdc;
907 unsigned long ldrcntr;
908 unsigned long new_pan_offset;
53b50314
DHG		 909 unsigned long base_addr_y, base_addr_c;
910 unsigned long c_offset;
92e1f9a7 911
53b50314
DHG		 912 if (!var->nonstd)
913 new_pan_offset = (var->yoffset * info->fix.line_length) +
914 (var->xoffset * (info->var.bits_per_pixel / 8));
915 else
916 new_pan_offset = (var->yoffset * info->fix.line_length) +
917 (var->xoffset);
9dd38819 918
92e1f9a7 919 if (new_pan_offset == ch->pan_offset)
9dd38819
PE		 920 return 0; /* No change, do nothing */
921
92e1f9a7 922 ldrcntr = lcdc_read(priv, _LDRCNTR);
9dd38819 923
92e1f9a7 924 /* Set the source address for the next refresh */
53b50314
DHG		 925 base_addr_y = ch->dma_handle + new_pan_offset;
926 if (var->nonstd) {
927 /* Set y offset */
928 c_offset = (var->yoffset *
929 info->fix.line_length *
930 (info->var.bits_per_pixel - 8)) / 8;
931 base_addr_c = ch->dma_handle + var->xres * var->yres_virtual +
932 c_offset;
933 /* Set x offset */
934 if (info->var.bits_per_pixel == 24)
935 base_addr_c += 2 * var->xoffset;
936 else
937 base_addr_c += var->xoffset;
938 } else
939 base_addr_c = 0;
940
7caa4342
D		 941 if (!ch->meram_enabled) {
942 lcdc_write_chan_mirror(ch, LDSA1R, base_addr_y);
943 if (base_addr_c)
944 lcdc_write_chan_mirror(ch, LDSA2R, base_addr_c);
945 } else {
946 struct sh_mobile_meram_cfg *cfg;
947 struct sh_mobile_meram_info *mdev;
948 unsigned long icb_addr_y, icb_addr_c;
949 int ret;
950
951 cfg = ch->cfg.meram_cfg;
952 mdev = priv->meram_dev;
953 ret = mdev->ops->meram_update(mdev, cfg,
954 base_addr_y, base_addr_c,
955 &icb_addr_y, &icb_addr_c);
956 if (ret)
957 return ret;
958
959 lcdc_write_chan_mirror(ch, LDSA1R, icb_addr_y);
960 if (icb_addr_c)
961 lcdc_write_chan_mirror(ch, LDSA2R, icb_addr_c);
962
963 }
53b50314 964
92e1f9a7
PE		 965 if (lcdc_chan_is_sublcd(ch))
966 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_SRS);
967 else
968 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_MRS);
969
970 ch->pan_offset = new_pan_offset;
971
972 sh_mobile_lcdc_deferred_io_touch(info);
9dd38819
PE		 973
974 return 0;
975}
976
40331b21
PE		 977static int sh_mobile_wait_for_vsync(struct fb_info *info)
978{
979 struct sh_mobile_lcdc_chan *ch = info->par;
980 unsigned long ldintr;
981 int ret;
982
983 /* Enable VSync End interrupt */
984 ldintr = lcdc_read(ch->lcdc, _LDINTR);
985 ldintr |= LDINTR_VEE;
986 lcdc_write(ch->lcdc, _LDINTR, ldintr);
987
988 ret = wait_for_completion_interruptible_timeout(&ch->vsync_completion,
989 msecs_to_jiffies(100));
990 if (!ret)
991 return -ETIMEDOUT;
992
993 return 0;
994}
995
996static int sh_mobile_ioctl(struct fb_info *info, unsigned int cmd,
997 unsigned long arg)
998{
999 int retval;
1000
1001 switch (cmd) {
1002 case FBIO_WAITFORVSYNC:
1003 retval = sh_mobile_wait_for_vsync(info);
1004 break;
1005
1006 default:
1007 retval = -ENOIOCTLCMD;
1008 break;
1009 }
1010 return retval;
1011}
1012
dd210503
GL		 1013static void sh_mobile_fb_reconfig(struct fb_info *info)
1014{
1015 struct sh_mobile_lcdc_chan *ch = info->par;
1016 struct fb_videomode mode1, mode2;
1017 struct fb_event event;
1018 int evnt = FB_EVENT_MODE_CHANGE_ALL;
1019
1020 if (ch->use_count > 1 || (ch->use_count == 1 && !info->fbcon_par))
1021 /* More framebuffer users are active */
1022 return;
1023
1024 fb_var_to_videomode(&mode1, &ch->display_var);
1025 fb_var_to_videomode(&mode2, &info->var);
1026
1027 if (fb_mode_is_equal(&mode1, &mode2))
1028 return;
1029
1030 /* Display has been re-plugged, framebuffer is free now, reconfigure */
1031 if (fb_set_var(info, &ch->display_var) < 0)
1032 /* Couldn't reconfigure, hopefully, can continue as before */
1033 return;
1034
53b50314
DHG		 1035 if (info->var.nonstd)
1036 info->fix.line_length = mode1.xres;
1037 else
1038 info->fix.line_length = mode1.xres * (ch->cfg.bpp / 8);
dd210503
GL		 1039
1040 /*
1041 * fb_set_var() calls the notifier change internally, only if
1042 * FBINFO_MISC_USEREVENT flag is set. Since we do not want to fake a
1043 * user event, we have to call the chain ourselves.
1044 */
1045 event.info = info;
cc267ec5 1046 event.data = &mode1;
dd210503
GL		 1047 fb_notifier_call_chain(evnt, &event);
1048}
1049
1050/*
1051 * Locking: both .fb_release() and .fb_open() are called with info->lock held if
1052 * user == 1, or with console sem held, if user == 0.
1053 */
1054static int sh_mobile_release(struct fb_info *info, int user)
1055{
1056 struct sh_mobile_lcdc_chan *ch = info->par;
1057
1058 mutex_lock(&ch->open_lock);
1059 dev_dbg(info->dev, "%s(): %d users\n", __func__, ch->use_count);
1060
1061 ch->use_count--;
1062
1063 /* Nothing to reconfigure, when called from fbcon */
1064 if (user) {
ac751efa 1065 console_lock();
dd210503 1066 sh_mobile_fb_reconfig(info);
ac751efa 1067 console_unlock();
dd210503
GL		 1068 }
1069
1070 mutex_unlock(&ch->open_lock);
1071
1072 return 0;
1073}
1074
1075static int sh_mobile_open(struct fb_info *info, int user)
1076{
1077 struct sh_mobile_lcdc_chan *ch = info->par;
1078
1079 mutex_lock(&ch->open_lock);
1080 ch->use_count++;
1081
1082 dev_dbg(info->dev, "%s(): %d users\n", __func__, ch->use_count);
1083 mutex_unlock(&ch->open_lock);
1084
1085 return 0;
1086}
1087
1088static int sh_mobile_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1089{
1090 struct sh_mobile_lcdc_chan *ch = info->par;
417d4827 1091 struct sh_mobile_lcdc_priv *p = ch->lcdc;
dd210503 1092
d2ecbab5 1093 if (var->xres > MAX_XRES || var->yres > MAX_YRES ||
dd210503 1094 var->xres * var->yres * (ch->cfg.bpp / 8) * 2 > info->fix.smem_len) {
830539d1 1095 dev_warn(info->dev, "Invalid info: %u-%u-%u-%u x %u-%u-%u-%u @ %lukHz!\n",
d2ecbab5
GL		 1096 var->left_margin, var->xres, var->right_margin, var->hsync_len,
1097 var->upper_margin, var->yres, var->lower_margin, var->vsync_len,
1098 PICOS2KHZ(var->pixclock));
dd210503
GL		 1099 return -EINVAL;
1100 }
417d4827
MD		 1101
1102 /* only accept the forced_bpp for dual channel configurations */
1103 if (p->forced_bpp && p->forced_bpp != var->bits_per_pixel)
1104 return -EINVAL;
1105
1106 switch (var->bits_per_pixel) {
1107 case 16: /* PKF[4:0] = 00011 - RGB 565 */
1108 case 24: /* PKF[4:0] = 01011 - RGB 888 */
1109 case 32: /* PKF[4:0] = 00000 - RGBA 888 */
1110 break;
1111 default:
1112 return -EINVAL;
1113 }
1114
dd210503
GL		 1115 return 0;
1116}
40331b21 1117
8857b9aa
AC		 1118/*
1119 * Screen blanking. Behavior is as follows:
1120 * FB_BLANK_UNBLANK: screen unblanked, clocks enabled
1121 * FB_BLANK_NORMAL: screen blanked, clocks enabled
1122 * FB_BLANK_VSYNC,
1123 * FB_BLANK_HSYNC,
1124 * FB_BLANK_POWEROFF: screen blanked, clocks disabled
1125 */
1126static int sh_mobile_lcdc_blank(int blank, struct fb_info *info)
1127{
1128 struct sh_mobile_lcdc_chan *ch = info->par;
1129 struct sh_mobile_lcdc_priv *p = ch->lcdc;
1130
1131 /* blank the screen? */
1132 if (blank > FB_BLANK_UNBLANK && ch->blank_status == FB_BLANK_UNBLANK) {
1133 struct fb_fillrect rect = {
1134 .width = info->var.xres,
1135 .height = info->var.yres,
1136 };
1137 sh_mobile_lcdc_fillrect(info, &rect);
1138 }
1139 /* turn clocks on? */
1140 if (blank <= FB_BLANK_NORMAL && ch->blank_status > FB_BLANK_NORMAL) {
1141 sh_mobile_lcdc_clk_on(p);
1142 }
1143 /* turn clocks off? */
1144 if (blank > FB_BLANK_NORMAL && ch->blank_status <= FB_BLANK_NORMAL) {
1145 /* make sure the screen is updated with the black fill before
1146 * switching the clocks off. one vsync is not enough since
1147 * blanking may occur in the middle of a refresh. deferred io
1148 * mode will reenable the clocks and update the screen in time,
1149 * so it does not need this. */
1150 if (!info->fbdefio) {
1151 sh_mobile_wait_for_vsync(info);
1152 sh_mobile_wait_for_vsync(info);
1153 }
1154 sh_mobile_lcdc_clk_off(p);
1155 }
1156
1157 ch->blank_status = blank;
1158 return 0;
1159}
1160
cfb4f5d1 1161static struct fb_ops sh_mobile_lcdc_ops = {
9dd38819 1162 .owner = THIS_MODULE,
cfb4f5d1 1163 .fb_setcolreg = sh_mobile_lcdc_setcolreg,
2540c111
MD		 1164 .fb_read = fb_sys_read,
1165 .fb_write = fb_sys_write,
8564557a
MD		 1166 .fb_fillrect = sh_mobile_lcdc_fillrect,
1167 .fb_copyarea = sh_mobile_lcdc_copyarea,
1168 .fb_imageblit = sh_mobile_lcdc_imageblit,
8857b9aa 1169 .fb_blank = sh_mobile_lcdc_blank,
9dd38819 1170 .fb_pan_display = sh_mobile_fb_pan_display,
40331b21 1171 .fb_ioctl = sh_mobile_ioctl,
dd210503
GL		 1172 .fb_open = sh_mobile_open,
1173 .fb_release = sh_mobile_release,
1174 .fb_check_var = sh_mobile_check_var,
cfb4f5d1
MD		 1175};
1176
3b0fd9d7
AC		 1177static int sh_mobile_lcdc_update_bl(struct backlight_device *bdev)
1178{
1179 struct sh_mobile_lcdc_chan *ch = bl_get_data(bdev);
1180 struct sh_mobile_lcdc_board_cfg *cfg = &ch->cfg.board_cfg;
1181 int brightness = bdev->props.brightness;
1182
1183 if (bdev->props.power != FB_BLANK_UNBLANK ||
1184 bdev->props.state & (BL_CORE_SUSPENDED | BL_CORE_FBBLANK))
1185 brightness = 0;
1186
1187 return cfg->set_brightness(cfg->board_data, brightness);
1188}
1189
1190static int sh_mobile_lcdc_get_brightness(struct backlight_device *bdev)
1191{
1192 struct sh_mobile_lcdc_chan *ch = bl_get_data(bdev);
1193 struct sh_mobile_lcdc_board_cfg *cfg = &ch->cfg.board_cfg;
1194
1195 return cfg->get_brightness(cfg->board_data);
1196}
1197
1198static int sh_mobile_lcdc_check_fb(struct backlight_device *bdev,
1199 struct fb_info *info)
1200{
1201 return (info->bl_dev == bdev);
1202}
1203
1204static struct backlight_ops sh_mobile_lcdc_bl_ops = {
1205 .options = BL_CORE_SUSPENDRESUME,
1206 .update_status = sh_mobile_lcdc_update_bl,
1207 .get_brightness = sh_mobile_lcdc_get_brightness,
1208 .check_fb = sh_mobile_lcdc_check_fb,
1209};
1210
1211static struct backlight_device *sh_mobile_lcdc_bl_probe(struct device *parent,
1212 struct sh_mobile_lcdc_chan *ch)
1213{
1214 struct backlight_device *bl;
1215
1216 bl = backlight_device_register(ch->cfg.bl_info.name, parent, ch,
1217 &sh_mobile_lcdc_bl_ops, NULL);
beee1f20
DC		 1218 if (IS_ERR(bl)) {
1219 dev_err(parent, "unable to register backlight device: %ld\n",
1220 PTR_ERR(bl));
3b0fd9d7
AC		 1221 return NULL;
1222 }
1223
1224 bl->props.max_brightness = ch->cfg.bl_info.max_brightness;
1225 bl->props.brightness = bl->props.max_brightness;
1226 backlight_update_status(bl);
1227
1228 return bl;
1229}
1230
1231static void sh_mobile_lcdc_bl_remove(struct backlight_device *bdev)
1232{
1233 backlight_device_unregister(bdev);
1234}
1235
53b50314
DHG		 1236static int sh_mobile_lcdc_set_bpp(struct fb_var_screeninfo *var, int bpp,
1237 int nonstd)
cfb4f5d1 1238{
53b50314
DHG		 1239 if (nonstd) {
1240 switch (bpp) {
1241 case 12:
1242 case 16:
1243 case 24:
1244 var->bits_per_pixel = bpp;
1245 var->nonstd = nonstd;
1246 return 0;
1247 default:
1248 return -EINVAL;
1249 }
1250 }
1251
cfb4f5d1
MD		 1252 switch (bpp) {
1253 case 16: /* PKF[4:0] = 00011 - RGB 565 */
1254 var->red.offset = 11;
1255 var->red.length = 5;
1256 var->green.offset = 5;
1257 var->green.length = 6;
1258 var->blue.offset = 0;
1259 var->blue.length = 5;
1260 var->transp.offset = 0;
1261 var->transp.length = 0;
1262 break;
1263
417d4827
MD		 1264 case 24: /* PKF[4:0] = 01011 - RGB 888 */
1265 var->red.offset = 16;
cfb4f5d1 1266 var->red.length = 8;
417d4827 1267 var->green.offset = 8;
cfb4f5d1 1268 var->green.length = 8;
417d4827 1269 var->blue.offset = 0;
cfb4f5d1
MD		 1270 var->blue.length = 8;
1271 var->transp.offset = 0;
1272 var->transp.length = 0;
1273 break;
417d4827
MD		 1274
1275 case 32: /* PKF[4:0] = 00000 - RGBA 888 */
1276 var->red.offset = 16;
1277 var->red.length = 8;
1278 var->green.offset = 8;
1279 var->green.length = 8;
1280 var->blue.offset = 0;
1281 var->blue.length = 8;
1282 var->transp.offset = 24;
1283 var->transp.length = 8;
1284 break;
cfb4f5d1
MD		 1285 default:
1286 return -EINVAL;
1287 }
1288 var->bits_per_pixel = bpp;
1289 var->red.msb_right = 0;
1290 var->green.msb_right = 0;
1291 var->blue.msb_right = 0;
1292 var->transp.msb_right = 0;
1293 return 0;
1294}
1295
2feb075a
MD		 1296static int sh_mobile_lcdc_suspend(struct device *dev)
1297{
1298 struct platform_device *pdev = to_platform_device(dev);
1299
1300 sh_mobile_lcdc_stop(platform_get_drvdata(pdev));
1301 return 0;
1302}
1303
1304static int sh_mobile_lcdc_resume(struct device *dev)
1305{
1306 struct platform_device *pdev = to_platform_device(dev);
1307
1308 return sh_mobile_lcdc_start(platform_get_drvdata(pdev));
1309}
1310
0246c471
MD		 1311static int sh_mobile_lcdc_runtime_suspend(struct device *dev)
1312{
1313 struct platform_device *pdev = to_platform_device(dev);
1314 struct sh_mobile_lcdc_priv *p = platform_get_drvdata(pdev);
1315 struct sh_mobile_lcdc_chan *ch;
1316 int k, n;
1317
1318 /* save per-channel registers */
1319 for (k = 0; k < ARRAY_SIZE(p->ch); k++) {
1320 ch = &p->ch[k];
1321 if (!ch->enabled)
1322 continue;
1323 for (n = 0; n < NR_CH_REGS; n++)
1324 ch->saved_ch_regs[n] = lcdc_read_chan(ch, n);
1325 }
1326
1327 /* save shared registers */
1328 for (n = 0; n < NR_SHARED_REGS; n++)
1329 p->saved_shared_regs[n] = lcdc_read(p, lcdc_shared_regs[n]);
1330
1331 /* turn off LCDC hardware */
1332 lcdc_write(p, _LDCNT1R, 0);
1333 return 0;
1334}
1335
1336static int sh_mobile_lcdc_runtime_resume(struct device *dev)
1337{
1338 struct platform_device *pdev = to_platform_device(dev);
1339 struct sh_mobile_lcdc_priv *p = platform_get_drvdata(pdev);
1340 struct sh_mobile_lcdc_chan *ch;
1341 int k, n;
1342
1343 /* restore per-channel registers */
1344 for (k = 0; k < ARRAY_SIZE(p->ch); k++) {
1345 ch = &p->ch[k];
1346 if (!ch->enabled)
1347 continue;
1348 for (n = 0; n < NR_CH_REGS; n++)
1349 lcdc_write_chan(ch, n, ch->saved_ch_regs[n]);
1350 }
1351
1352 /* restore shared registers */
1353 for (n = 0; n < NR_SHARED_REGS; n++)
1354 lcdc_write(p, lcdc_shared_regs[n], p->saved_shared_regs[n]);
1355
1356 return 0;
1357}
1358
47145210 1359static const struct dev_pm_ops sh_mobile_lcdc_dev_pm_ops = {
2feb075a
MD		 1360 .suspend = sh_mobile_lcdc_suspend,
1361 .resume = sh_mobile_lcdc_resume,
0246c471
MD		 1362 .runtime_suspend = sh_mobile_lcdc_runtime_suspend,
1363 .runtime_resume = sh_mobile_lcdc_runtime_resume,
2feb075a
MD		 1364};
1365
6de9edd5 1366/* locking: called with info->lock held */
6011bdea
GL		 1367static int sh_mobile_lcdc_notify(struct notifier_block *nb,
1368 unsigned long action, void *data)
1369{
1370 struct fb_event *event = data;
1371 struct fb_info *info = event->info;
1372 struct sh_mobile_lcdc_chan *ch = info->par;
1373 struct sh_mobile_lcdc_board_cfg *board_cfg = &ch->cfg.board_cfg;
afe417c0 1374 int ret;
6011bdea
GL		 1375
1376 if (&ch->lcdc->notifier != nb)
baf16374 1377 return NOTIFY_DONE;
6011bdea
GL		 1378
1379 dev_dbg(info->dev, "%s(): action = %lu, data = %p\n",
1380 __func__, action, event->data);
1381
1382 switch(action) {
1383 case FB_EVENT_SUSPEND:
247f9938 1384 if (board_cfg->display_off && try_module_get(board_cfg->owner)) {
6011bdea 1385 board_cfg->display_off(board_cfg->board_data);
6de9edd5
GL		 1386 module_put(board_cfg->owner);
1387 }
6011bdea 1388 pm_runtime_put(info->device);
afe417c0 1389 sh_mobile_lcdc_stop(ch->lcdc);
6011bdea
GL		 1390 break;
1391 case FB_EVENT_RESUME:
dd210503
GL		 1392 mutex_lock(&ch->open_lock);
1393 sh_mobile_fb_reconfig(info);
1394 mutex_unlock(&ch->open_lock);
6011bdea
GL		 1395
1396 /* HDMI must be enabled before LCDC configuration */
247f9938 1397 if (board_cfg->display_on && try_module_get(board_cfg->owner)) {
dd210503 1398 board_cfg->display_on(board_cfg->board_data, info);
6de9edd5 1399 module_put(board_cfg->owner);
6011bdea
GL		 1400 }
1401
afe417c0
GL		 1402 ret = sh_mobile_lcdc_start(ch->lcdc);
1403 if (!ret)
1404 pm_runtime_get_sync(info->device);
6011bdea
GL		 1405 }
1406
baf16374 1407 return NOTIFY_OK;
6011bdea
GL		 1408}
1409
cfb4f5d1
MD		 1410static int sh_mobile_lcdc_remove(struct platform_device *pdev);
1411
c2e13037 1412static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev)
cfb4f5d1
MD		 1413{
1414 struct fb_info *info;
1415 struct sh_mobile_lcdc_priv *priv;
01ac25b5 1416 struct sh_mobile_lcdc_info *pdata = pdev->dev.platform_data;
cfb4f5d1
MD		 1417 struct resource *res;
1418 int error;
1419 void *buf;
1420 int i, j;
1421
01ac25b5 1422 if (!pdata) {
cfb4f5d1 1423 dev_err(&pdev->dev, "no platform data defined\n");
8bed9055 1424 return -EINVAL;
cfb4f5d1
MD		 1425 }
1426
1427 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8564557a
MD		 1428 i = platform_get_irq(pdev, 0);
1429 if (!res || i < 0) {
1430 dev_err(&pdev->dev, "cannot get platform resources\n");
8bed9055 1431 return -ENOENT;
cfb4f5d1
MD		 1432 }
1433
1434 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1435 if (!priv) {
1436 dev_err(&pdev->dev, "cannot allocate device data\n");
8bed9055 1437 return -ENOMEM;
cfb4f5d1
MD		 1438 }
1439
8bed9055
GL		 1440 platform_set_drvdata(pdev, priv);
1441
8564557a 1442 error = request_irq(i, sh_mobile_lcdc_irq, IRQF_DISABLED,
7ad33e74 1443 dev_name(&pdev->dev), priv);
8564557a
MD		 1444 if (error) {
1445 dev_err(&pdev->dev, "unable to request irq\n");
1446 goto err1;
1447 }
1448
1449 priv->irq = i;
5ef6b505 1450 atomic_set(&priv->hw_usecnt, -1);
cfb4f5d1
MD		 1451
1452 j = 0;
1453 for (i = 0; i < ARRAY_SIZE(pdata->ch); i++) {
01ac25b5 1454 struct sh_mobile_lcdc_chan *ch = priv->ch + j;
cfb4f5d1 1455
01ac25b5
GL		 1456 ch->lcdc = priv;
1457 memcpy(&ch->cfg, &pdata->ch[i], sizeof(pdata->ch[i]));
cfb4f5d1 1458
01ac25b5 1459 error = sh_mobile_lcdc_check_interface(ch);
cfb4f5d1
MD		 1460 if (error) {
1461 dev_err(&pdev->dev, "unsupported interface type\n");
1462 goto err1;
1463 }
01ac25b5
GL		 1464 init_waitqueue_head(&ch->frame_end_wait);
1465 init_completion(&ch->vsync_completion);
1466 ch->pan_offset = 0;
cfb4f5d1 1467
3b0fd9d7
AC		 1468 /* probe the backlight is there is one defined */
1469 if (ch->cfg.bl_info.max_brightness)
1470 ch->bl = sh_mobile_lcdc_bl_probe(&pdev->dev, ch);
1471
cfb4f5d1
MD		 1472 switch (pdata->ch[i].chan) {
1473 case LCDC_CHAN_MAINLCD:
01ac25b5
GL		 1474 ch->enabled = 1 << 1;
1475 ch->reg_offs = lcdc_offs_mainlcd;
cfb4f5d1
MD		 1476 j++;
1477 break;
1478 case LCDC_CHAN_SUBLCD:
01ac25b5
GL		 1479 ch->enabled = 1 << 2;
1480 ch->reg_offs = lcdc_offs_sublcd;
cfb4f5d1
MD		 1481 j++;
1482 break;
1483 }
1484 }
1485
1486 if (!j) {
1487 dev_err(&pdev->dev, "no channels defined\n");
1488 error = -EINVAL;
1489 goto err1;
1490 }
1491
417d4827
MD		 1492 /* for dual channel LCDC (MAIN + SUB) force shared bpp setting */
1493 if (j == 2)
1494 priv->forced_bpp = pdata->ch[0].bpp;
1495
dba6f385
GL		 1496 priv->base = ioremap_nocache(res->start, resource_size(res));
1497 if (!priv->base)
1498 goto err1;
1499
b51339ff 1500 error = sh_mobile_lcdc_setup_clocks(pdev, pdata->clock_source, priv);
cfb4f5d1
MD		 1501 if (error) {
1502 dev_err(&pdev->dev, "unable to setup clocks\n");
1503 goto err1;
1504 }
1505
7caa4342
D		 1506 priv->meram_dev = pdata->meram_dev;
1507
cfb4f5d1 1508 for (i = 0; i < j; i++) {
6011bdea 1509 struct fb_var_screeninfo *var;
71d3b0fc 1510 const struct fb_videomode *lcd_cfg, *max_cfg = NULL;
01ac25b5 1511 struct sh_mobile_lcdc_chan *ch = priv->ch + i;
c44f9f76
GL		 1512 struct sh_mobile_lcdc_chan_cfg *cfg = &ch->cfg;
1513 const struct fb_videomode *mode = cfg->lcd_cfg;
71d3b0fc
GL		 1514 unsigned long max_size = 0;
1515 int k;
5fd284e6 1516 int num_cfg;
cfb4f5d1 1517
01ac25b5
GL		 1518 ch->info = framebuffer_alloc(0, &pdev->dev);
1519 if (!ch->info) {
e33afddc
PM		 1520 dev_err(&pdev->dev, "unable to allocate fb_info\n");
1521 error = -ENOMEM;
1522 break;
1523 }
1524
01ac25b5 1525 info = ch->info;
6011bdea 1526 var = &info->var;
cfb4f5d1 1527 info->fbops = &sh_mobile_lcdc_ops;
c44f9f76 1528 info->par = ch;
dd210503
GL		 1529
1530 mutex_init(&ch->open_lock);
1531
c44f9f76
GL		 1532 for (k = 0, lcd_cfg = mode;
1533 k < cfg->num_cfg && lcd_cfg;
71d3b0fc
GL		 1534 k++, lcd_cfg++) {
1535 unsigned long size = lcd_cfg->yres * lcd_cfg->xres;
53b50314
DHG		 1536 /* NV12 buffers must have even number of lines */
1537 if ((cfg->nonstd) && cfg->bpp == 12 &&
1538 (lcd_cfg->yres & 0x1)) {
1539 dev_err(&pdev->dev, "yres must be multiple of 2"
1540 " for YCbCr420 mode.\n");
1541 error = -EINVAL;
1542 goto err1;
1543 }
71d3b0fc
GL		 1544
1545 if (size > max_size) {
1546 max_cfg = lcd_cfg;
1547 max_size = size;
1548 }
1549 }
1550
c44f9f76 1551 if (!mode)
d2ecbab5 1552 max_size = MAX_XRES * MAX_YRES;
c44f9f76
GL		 1553 else if (max_cfg)
1554 dev_dbg(&pdev->dev, "Found largest videomode %ux%u\n",
1555 max_cfg->xres, max_cfg->yres);
71d3b0fc 1556
cfb4f5d1 1557 info->fix = sh_mobile_lcdc_fix;
53b50314
DHG		 1558 info->fix.smem_len = max_size * 2 * cfg->bpp / 8;
1559
1560 /* Only pan in 2 line steps for NV12 */
1561 if (cfg->nonstd && cfg->bpp == 12)
1562 info->fix.ypanstep = 2;
cfb4f5d1 1563
5fd284e6 1564 if (!mode) {
c44f9f76 1565 mode = &default_720p;
5fd284e6
GL		 1566 num_cfg = 1;
1567 } else {
e0b9fb26 1568 num_cfg = cfg->num_cfg;
5fd284e6
GL		 1569 }
1570
1571 fb_videomode_to_modelist(mode, num_cfg, &info->modelist);
c44f9f76
GL		 1572
1573 fb_videomode_to_var(var, mode);
e0b9fb26
GL		 1574 var->width = cfg->lcd_size_cfg.width;
1575 var->height = cfg->lcd_size_cfg.height;
9dd38819 1576 /* Default Y virtual resolution is 2x panel size */
6011bdea 1577 var->yres_virtual = var->yres * 2;
6011bdea 1578 var->activate = FB_ACTIVATE_NOW;
6011bdea 1579
53b50314 1580 error = sh_mobile_lcdc_set_bpp(var, cfg->bpp, cfg->nonstd);
cfb4f5d1
MD		 1581 if (error)
1582 break;
1583
cfb4f5d1 1584 buf = dma_alloc_coherent(&pdev->dev, info->fix.smem_len,
01ac25b5 1585 &ch->dma_handle, GFP_KERNEL);
cfb4f5d1
MD		 1586 if (!buf) {
1587 dev_err(&pdev->dev, "unable to allocate buffer\n");
1588 error = -ENOMEM;
1589 break;
1590 }
1591
01ac25b5 1592 info->pseudo_palette = &ch->pseudo_palette;
cfb4f5d1
MD		 1593 info->flags = FBINFO_FLAG_DEFAULT;
1594
1595 error = fb_alloc_cmap(&info->cmap, PALETTE_NR, 0);
1596 if (error < 0) {
1597 dev_err(&pdev->dev, "unable to allocate cmap\n");
1598 dma_free_coherent(&pdev->dev, info->fix.smem_len,
01ac25b5 1599 buf, ch->dma_handle);
cfb4f5d1
MD		 1600 break;
1601 }
1602
01ac25b5 1603 info->fix.smem_start = ch->dma_handle;
53b50314
DHG		 1604 if (var->nonstd)
1605 info->fix.line_length = var->xres;
1606 else
1607 info->fix.line_length = var->xres * (cfg->bpp / 8);
1608
cfb4f5d1
MD		 1609 info->screen_base = buf;
1610 info->device = &pdev->dev;
1c120deb 1611 ch->display_var = *var;
cfb4f5d1
MD		 1612 }
1613
1614 if (error)
1615 goto err1;
1616
1617 error = sh_mobile_lcdc_start(priv);
1618 if (error) {
1619 dev_err(&pdev->dev, "unable to start hardware\n");
1620 goto err1;
1621 }
1622
1623 for (i = 0; i < j; i++) {
1c6a307a
PM		 1624 struct sh_mobile_lcdc_chan *ch = priv->ch + i;
1625
e33afddc 1626 info = ch->info;
1c6a307a
PM		 1627
1628 if (info->fbdefio) {
8bed9055 1629 ch->sglist = vmalloc(sizeof(struct scatterlist) *
1c6a307a 1630 info->fix.smem_len >> PAGE_SHIFT);
8bed9055 1631 if (!ch->sglist) {
1c6a307a
PM		 1632 dev_err(&pdev->dev, "cannot allocate sglist\n");
1633 goto err1;
1634 }
1635 }
1636
3b0fd9d7
AC		 1637 info->bl_dev = ch->bl;
1638
1c6a307a 1639 error = register_framebuffer(info);
cfb4f5d1
MD		 1640 if (error < 0)
1641 goto err1;
cfb4f5d1 1642
cfb4f5d1
MD		 1643 dev_info(info->dev,
1644 "registered %s/%s as %dx%d %dbpp.\n",
1645 pdev->name,
1c6a307a 1646 (ch->cfg.chan == LCDC_CHAN_MAINLCD) ?
cfb4f5d1 1647 "mainlcd" : "sublcd",
c44f9f76 1648 info->var.xres, info->var.yres,
1c6a307a 1649 ch->cfg.bpp);
8564557a
MD		 1650
1651 /* deferred io mode: disable clock to save power */
6011bdea 1652 if (info->fbdefio || info->state == FBINFO_STATE_SUSPENDED)
8564557a 1653 sh_mobile_lcdc_clk_off(priv);
cfb4f5d1
MD		 1654 }
1655
6011bdea
GL		 1656 /* Failure ignored */
1657 priv->notifier.notifier_call = sh_mobile_lcdc_notify;
1658 fb_register_client(&priv->notifier);
1659
cfb4f5d1 1660 return 0;
8bed9055 1661err1:
cfb4f5d1 1662 sh_mobile_lcdc_remove(pdev);
8bed9055 1663
cfb4f5d1
MD		 1664 return error;
1665}
1666
1667static int sh_mobile_lcdc_remove(struct platform_device *pdev)
1668{
1669 struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
1670 struct fb_info *info;
1671 int i;
1672
6011bdea
GL		 1673 fb_unregister_client(&priv->notifier);
1674
cfb4f5d1 1675 for (i = 0; i < ARRAY_SIZE(priv->ch); i++)
8bed9055 1676 if (priv->ch[i].info && priv->ch[i].info->dev)
e33afddc 1677 unregister_framebuffer(priv->ch[i].info);
cfb4f5d1
MD		 1678
1679 sh_mobile_lcdc_stop(priv);
1680
1681 for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
e33afddc 1682 info = priv->ch[i].info;
cfb4f5d1 1683
e33afddc 1684 if (!info || !info->device)
cfb4f5d1
MD		 1685 continue;
1686
1c6a307a
PM		 1687 if (priv->ch[i].sglist)
1688 vfree(priv->ch[i].sglist);
1689
1ffbb037
MD		 1690 if (info->screen_base)
1691 dma_free_coherent(&pdev->dev, info->fix.smem_len,
1692 info->screen_base,
1693 priv->ch[i].dma_handle);
cfb4f5d1 1694 fb_dealloc_cmap(&info->cmap);
e33afddc 1695 framebuffer_release(info);
cfb4f5d1
MD		 1696 }
1697
3b0fd9d7
AC		 1698 for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
1699 if (priv->ch[i].bl)
1700 sh_mobile_lcdc_bl_remove(priv->ch[i].bl);
1701 }
1702
b51339ff
MD		 1703 if (priv->dot_clk)
1704 clk_put(priv->dot_clk);
0246c471 1705
8bed9055
GL		 1706 if (priv->dev)
1707 pm_runtime_disable(priv->dev);
cfb4f5d1
MD		 1708
1709 if (priv->base)
1710 iounmap(priv->base);
1711
8564557a
MD		 1712 if (priv->irq)
1713 free_irq(priv->irq, priv);
cfb4f5d1
MD		 1714 kfree(priv);
1715 return 0;
1716}
1717
1718static struct platform_driver sh_mobile_lcdc_driver = {
1719 .driver = {
1720 .name = "sh_mobile_lcdc_fb",
1721 .owner = THIS_MODULE,
2feb075a 1722 .pm = &sh_mobile_lcdc_dev_pm_ops,
cfb4f5d1
MD		 1723 },
1724 .probe = sh_mobile_lcdc_probe,
1725 .remove = sh_mobile_lcdc_remove,
1726};
1727
1728static int __init sh_mobile_lcdc_init(void)
1729{
1730 return platform_driver_register(&sh_mobile_lcdc_driver);
1731}
1732
1733static void __exit sh_mobile_lcdc_exit(void)
1734{
1735 platform_driver_unregister(&sh_mobile_lcdc_driver);
1736}
1737
1738module_init(sh_mobile_lcdc_init);
1739module_exit(sh_mobile_lcdc_exit);
1740
1741MODULE_DESCRIPTION("SuperH Mobile LCDC Framebuffer driver");
1742MODULE_AUTHOR("Magnus Damm <damm@opensource.se>");
1743MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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