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fbdev: sh_mobile_lcdc: Split LCDC start code from sh_mobile_lcdc_start
[deliverable/linux.git] / drivers / video / sh_mobile_lcdcfb.c
CommitLineData
cfb4f5d1
MD		 1/*
2 * SuperH Mobile LCDC Framebuffer
3 *
4 * Copyright (c) 2008 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/delay.h>
14#include <linux/mm.h>
cfb4f5d1 15#include <linux/clk.h>
0246c471 16#include <linux/pm_runtime.h>
cfb4f5d1
MD		 17#include <linux/platform_device.h>
18#include <linux/dma-mapping.h>
8564557a 19#include <linux/interrupt.h>
1c6a307a 20#include <linux/vmalloc.h>
40331b21 21#include <linux/ioctl.h>
5a0e3ad6 22#include <linux/slab.h>
dd210503 23#include <linux/console.h>
3b0fd9d7
AC		 24#include <linux/backlight.h>
25#include <linux/gpio.h>
225c9a8d 26#include <video/sh_mobile_lcdc.h>
60063497 27#include <linux/atomic.h>
cfb4f5d1 28
6de9edd5 29#include "sh_mobile_lcdcfb.h"
7caa4342 30#include "sh_mobile_meram.h"
6de9edd5 31
a6f15ade
PE		 32#define SIDE_B_OFFSET 0x1000
33#define MIRROR_OFFSET 0x2000
cfb4f5d1 34
0246c471
MD		 35/* shared registers and their order for context save/restore */
36static int lcdc_shared_regs[] = {
37 _LDDCKR,
38 _LDDCKSTPR,
39 _LDINTR,
40 _LDDDSR,
41 _LDCNT1R,
42 _LDCNT2R,
43};
44#define NR_SHARED_REGS ARRAY_SIZE(lcdc_shared_regs)
45
d2ecbab5
GL		 46#define MAX_XRES 1920
47#define MAX_YRES 1080
cfb4f5d1 48
0246c471 49static unsigned long lcdc_offs_mainlcd[NR_CH_REGS] = {
cfb4f5d1
MD		 50 [LDDCKPAT1R] = 0x400,
51 [LDDCKPAT2R] = 0x404,
52 [LDMT1R] = 0x418,
53 [LDMT2R] = 0x41c,
54 [LDMT3R] = 0x420,
55 [LDDFR] = 0x424,
56 [LDSM1R] = 0x428,
8564557a 57 [LDSM2R] = 0x42c,
cfb4f5d1 58 [LDSA1R] = 0x430,
53b50314 59 [LDSA2R] = 0x434,
cfb4f5d1
MD		 60 [LDMLSR] = 0x438,
61 [LDHCNR] = 0x448,
62 [LDHSYNR] = 0x44c,
63 [LDVLNR] = 0x450,
64 [LDVSYNR] = 0x454,
65 [LDPMR] = 0x460,
6011bdea 66 [LDHAJR] = 0x4a0,
cfb4f5d1
MD		 67};
68
0246c471 69static unsigned long lcdc_offs_sublcd[NR_CH_REGS] = {
cfb4f5d1
MD		 70 [LDDCKPAT1R] = 0x408,
71 [LDDCKPAT2R] = 0x40c,
72 [LDMT1R] = 0x600,
73 [LDMT2R] = 0x604,
74 [LDMT3R] = 0x608,
75 [LDDFR] = 0x60c,
76 [LDSM1R] = 0x610,
8564557a 77 [LDSM2R] = 0x614,
cfb4f5d1
MD		 78 [LDSA1R] = 0x618,
79 [LDMLSR] = 0x620,
80 [LDHCNR] = 0x624,
81 [LDHSYNR] = 0x628,
82 [LDVLNR] = 0x62c,
83 [LDVSYNR] = 0x630,
84 [LDPMR] = 0x63c,
85};
86
c44f9f76
GL		 87static const struct fb_videomode default_720p = {
88 .name = "HDMI 720p",
89 .xres = 1280,
90 .yres = 720,
91
5ae0cf82
GL		 92 .left_margin = 220,
93 .right_margin = 110,
94 .hsync_len = 40,
c44f9f76
GL		 95
96 .upper_margin = 20,
97 .lower_margin = 5,
98 .vsync_len = 5,
99
100 .pixclock = 13468,
5ae0cf82 101 .refresh = 60,
c44f9f76 102 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
0246c471
MD		 103};
104
105struct sh_mobile_lcdc_priv {
106 void __iomem *base;
107 int irq;
108 atomic_t hw_usecnt;
109 struct device *dev;
110 struct clk *dot_clk;
111 unsigned long lddckr;
112 struct sh_mobile_lcdc_chan ch[2];
6011bdea 113 struct notifier_block notifier;
0246c471
MD		 114 unsigned long saved_shared_regs[NR_SHARED_REGS];
115 int started;
417d4827 116 int forced_bpp; /* 2 channel LCDC must share bpp setting */
7caa4342 117 struct sh_mobile_meram_info *meram_dev;
0246c471
MD		 118};
119
a6f15ade
PE		 120static bool banked(int reg_nr)
121{
122 switch (reg_nr) {
123 case LDMT1R:
124 case LDMT2R:
125 case LDMT3R:
126 case LDDFR:
127 case LDSM1R:
128 case LDSA1R:
53b50314 129 case LDSA2R:
a6f15ade
PE		 130 case LDMLSR:
131 case LDHCNR:
132 case LDHSYNR:
133 case LDVLNR:
134 case LDVSYNR:
135 return true;
136 }
137 return false;
138}
139
cfb4f5d1
MD		 140static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan,
141 int reg_nr, unsigned long data)
142{
143 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]);
a6f15ade
PE		 144 if (banked(reg_nr))
145 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
146 SIDE_B_OFFSET);
147}
148
149static void lcdc_write_chan_mirror(struct sh_mobile_lcdc_chan *chan,
150 int reg_nr, unsigned long data)
151{
152 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
153 MIRROR_OFFSET);
cfb4f5d1
MD		 154}
155
156static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan,
157 int reg_nr)
158{
159 return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]);
160}
161
162static void lcdc_write(struct sh_mobile_lcdc_priv *priv,
163 unsigned long reg_offs, unsigned long data)
164{
165 iowrite32(data, priv->base + reg_offs);
166}
167
168static unsigned long lcdc_read(struct sh_mobile_lcdc_priv *priv,
169 unsigned long reg_offs)
170{
171 return ioread32(priv->base + reg_offs);
172}
173
174static void lcdc_wait_bit(struct sh_mobile_lcdc_priv *priv,
175 unsigned long reg_offs,
176 unsigned long mask, unsigned long until)
177{
178 while ((lcdc_read(priv, reg_offs) & mask) != until)
179 cpu_relax();
180}
181
182static int lcdc_chan_is_sublcd(struct sh_mobile_lcdc_chan *chan)
183{
184 return chan->cfg.chan == LCDC_CHAN_SUBLCD;
185}
186
187static void lcdc_sys_write_index(void *handle, unsigned long data)
188{
189 struct sh_mobile_lcdc_chan *ch = handle;
190
ce1c0b08
LP		 191 lcdc_write(ch->lcdc, _LDDWD0R, data | LDDWDxR_WDACT);
192 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
193 lcdc_write(ch->lcdc, _LDDWAR, LDDWAR_WA |
194 (lcdc_chan_is_sublcd(ch) ? 2 : 0));
195 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
cfb4f5d1
MD		 196}
197
198static void lcdc_sys_write_data(void *handle, unsigned long data)
199{
200 struct sh_mobile_lcdc_chan *ch = handle;
201
ce1c0b08
LP		 202 lcdc_write(ch->lcdc, _LDDWD0R, data | LDDWDxR_WDACT | LDDWDxR_RSW);
203 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
204 lcdc_write(ch->lcdc, _LDDWAR, LDDWAR_WA |
205 (lcdc_chan_is_sublcd(ch) ? 2 : 0));
206 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
cfb4f5d1
MD		 207}
208
209static unsigned long lcdc_sys_read_data(void *handle)
210{
211 struct sh_mobile_lcdc_chan *ch = handle;
212
ce1c0b08
LP		 213 lcdc_write(ch->lcdc, _LDDRDR, LDDRDR_RSR);
214 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
215 lcdc_write(ch->lcdc, _LDDRAR, LDDRAR_RA |
216 (lcdc_chan_is_sublcd(ch) ? 2 : 0));
cfb4f5d1 217 udelay(1);
ce1c0b08 218 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
cfb4f5d1 219
ce1c0b08 220 return lcdc_read(ch->lcdc, _LDDRDR) & LDDRDR_DRD_MASK;
cfb4f5d1
MD		 221}
222
223struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = {
224 lcdc_sys_write_index,
225 lcdc_sys_write_data,
226 lcdc_sys_read_data,
227};
228
8564557a
MD		 229static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv)
230{
0246c471 231 if (atomic_inc_and_test(&priv->hw_usecnt)) {
8564557a
MD		 232 if (priv->dot_clk)
233 clk_enable(priv->dot_clk);
f1ad90da 234 pm_runtime_get_sync(priv->dev);
ec19b9e0
DHG		 235 if (priv->meram_dev && priv->meram_dev->pdev)
236 pm_runtime_get_sync(&priv->meram_dev->pdev->dev);
8564557a
MD		 237 }
238}
239
240static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv)
241{
0246c471 242 if (atomic_sub_return(1, &priv->hw_usecnt) == -1) {
ec19b9e0
DHG		 243 if (priv->meram_dev && priv->meram_dev->pdev)
244 pm_runtime_put_sync(&priv->meram_dev->pdev->dev);
0246c471 245 pm_runtime_put(priv->dev);
f1ad90da
LP		 246 if (priv->dot_clk)
247 clk_disable(priv->dot_clk);
8564557a
MD		 248 }
249}
8564557a 250
1c6a307a
PM		 251static int sh_mobile_lcdc_sginit(struct fb_info *info,
252 struct list_head *pagelist)
253{
254 struct sh_mobile_lcdc_chan *ch = info->par;
255 unsigned int nr_pages_max = info->fix.smem_len >> PAGE_SHIFT;
256 struct page *page;
257 int nr_pages = 0;
258
259 sg_init_table(ch->sglist, nr_pages_max);
260
261 list_for_each_entry(page, pagelist, lru)
262 sg_set_page(&ch->sglist[nr_pages++], page, PAGE_SIZE, 0);
263
264 return nr_pages;
265}
266
8564557a
MD		 267static void sh_mobile_lcdc_deferred_io(struct fb_info *info,
268 struct list_head *pagelist)
269{
270 struct sh_mobile_lcdc_chan *ch = info->par;
ef61aae4 271 struct sh_mobile_lcdc_board_cfg *bcfg = &ch->cfg.board_cfg;
8564557a
MD		 272
273 /* enable clocks before accessing hardware */
274 sh_mobile_lcdc_clk_on(ch->lcdc);
275
5c1a56b5
PM		 276 /*
277 * It's possible to get here without anything on the pagelist via
278 * sh_mobile_lcdc_deferred_io_touch() or via a userspace fsync()
279 * invocation. In the former case, the acceleration routines are
280 * stepped in to when using the framebuffer console causing the
281 * workqueue to be scheduled without any dirty pages on the list.
282 *
283 * Despite this, a panel update is still needed given that the
284 * acceleration routines have their own methods for writing in
285 * that still need to be updated.
286 *
287 * The fsync() and empty pagelist case could be optimized for,
288 * but we don't bother, as any application exhibiting such
289 * behaviour is fundamentally broken anyways.
290 */
291 if (!list_empty(pagelist)) {
292 unsigned int nr_pages = sh_mobile_lcdc_sginit(info, pagelist);
293
294 /* trigger panel update */
295 dma_map_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
ef61aae4
MD		 296 if (bcfg->start_transfer)
297 bcfg->start_transfer(bcfg->board_data, ch,
298 &sh_mobile_lcdc_sys_bus_ops);
ce1c0b08 299 lcdc_write_chan(ch, LDSM2R, LDSM2R_OSTRG);
5c1a56b5 300 dma_unmap_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
ef61aae4
MD		 301 } else {
302 if (bcfg->start_transfer)
303 bcfg->start_transfer(bcfg->board_data, ch,
304 &sh_mobile_lcdc_sys_bus_ops);
ce1c0b08 305 lcdc_write_chan(ch, LDSM2R, LDSM2R_OSTRG);
ef61aae4 306 }
8564557a
MD		 307}
308
309static void sh_mobile_lcdc_deferred_io_touch(struct fb_info *info)
310{
311 struct fb_deferred_io *fbdefio = info->fbdefio;
312
313 if (fbdefio)
314 schedule_delayed_work(&info->deferred_work, fbdefio->delay);
315}
316
317static irqreturn_t sh_mobile_lcdc_irq(int irq, void *data)
318{
319 struct sh_mobile_lcdc_priv *priv = data;
2feb075a 320 struct sh_mobile_lcdc_chan *ch;
9dd38819 321 unsigned long ldintr;
2feb075a
MD		 322 int is_sub;
323 int k;
8564557a 324
dc48665f
LP		 325 /* Acknowledge interrupts and disable further VSYNC End IRQs. */
326 ldintr = lcdc_read(priv, _LDINTR);
327 lcdc_write(priv, _LDINTR, (ldintr ^ LDINTR_STATUS_MASK) & ~LDINTR_VEE);
8564557a 328
2feb075a 329 /* figure out if this interrupt is for main or sub lcd */
ce1c0b08 330 is_sub = (lcdc_read(priv, _LDSR) & LDSR_MSS) ? 1 : 0;
2feb075a 331
9dd38819 332 /* wake up channel and disable clocks */
2feb075a
MD		 333 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
334 ch = &priv->ch[k];
335
336 if (!ch->enabled)
337 continue;
338
dc48665f 339 /* Frame End */
9dd38819
PE		 340 if (ldintr & LDINTR_FS) {
341 if (is_sub == lcdc_chan_is_sublcd(ch)) {
342 ch->frame_end = 1;
343 wake_up(&ch->frame_end_wait);
2feb075a 344
9dd38819
PE		 345 sh_mobile_lcdc_clk_off(priv);
346 }
347 }
348
349 /* VSYNC End */
40331b21
PE		 350 if (ldintr & LDINTR_VES)
351 complete(&ch->vsync_completion);
2feb075a
MD		 352 }
353
8564557a
MD		 354 return IRQ_HANDLED;
355}
356
cfb4f5d1
MD		 357static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv *priv,
358 int start)
359{
360 unsigned long tmp = lcdc_read(priv, _LDCNT2R);
361 int k;
362
363 /* start or stop the lcdc */
364 if (start)
ce1c0b08 365 lcdc_write(priv, _LDCNT2R, tmp | LDCNT2R_DO);
cfb4f5d1 366 else
ce1c0b08 367 lcdc_write(priv, _LDCNT2R, tmp & ~LDCNT2R_DO);
cfb4f5d1
MD		 368
369 /* wait until power is applied/stopped on all channels */
370 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
371 if (lcdc_read(priv, _LDCNT2R) & priv->ch[k].enabled)
372 while (1) {
ce1c0b08
LP		 373 tmp = lcdc_read_chan(&priv->ch[k], LDPMR)
374 & LDPMR_LPS;
375 if (start && tmp == LDPMR_LPS)
cfb4f5d1
MD		 376 break;
377 if (!start && tmp == 0)
378 break;
379 cpu_relax();
380 }
381
382 if (!start)
383 lcdc_write(priv, _LDDCKSTPR, 1); /* stop dotclock */
384}
385
6011bdea
GL		 386static void sh_mobile_lcdc_geometry(struct sh_mobile_lcdc_chan *ch)
387{
1c120deb
GL		 388 struct fb_var_screeninfo *var = &ch->info->var, *display_var = &ch->display_var;
389 unsigned long h_total, hsync_pos, display_h_total;
6011bdea
GL		 390 u32 tmp;
391
392 tmp = ch->ldmt1r_value;
ce1c0b08
LP		 393 tmp |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : LDMT1R_VPOL;
394 tmp |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : LDMT1R_HPOL;
395 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWPOL) ? LDMT1R_DWPOL : 0;
396 tmp |= (ch->cfg.flags & LCDC_FLAGS_DIPOL) ? LDMT1R_DIPOL : 0;
397 tmp |= (ch->cfg.flags & LCDC_FLAGS_DAPOL) ? LDMT1R_DAPOL : 0;
398 tmp |= (ch->cfg.flags & LCDC_FLAGS_HSCNT) ? LDMT1R_HSCNT : 0;
399 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWCNT) ? LDMT1R_DWCNT : 0;
6011bdea
GL		 400 lcdc_write_chan(ch, LDMT1R, tmp);
401
402 /* setup SYS bus */
403 lcdc_write_chan(ch, LDMT2R, ch->cfg.sys_bus_cfg.ldmt2r);
404 lcdc_write_chan(ch, LDMT3R, ch->cfg.sys_bus_cfg.ldmt3r);
405
406 /* horizontal configuration */
1c120deb
GL		 407 h_total = display_var->xres + display_var->hsync_len +
408 display_var->left_margin + display_var->right_margin;
6011bdea 409 tmp = h_total / 8; /* HTCN */
1c120deb 410 tmp |= (min(display_var->xres, var->xres) / 8) << 16; /* HDCN */
6011bdea
GL		 411 lcdc_write_chan(ch, LDHCNR, tmp);
412
1c120deb 413 hsync_pos = display_var->xres + display_var->right_margin;
6011bdea 414 tmp = hsync_pos / 8; /* HSYNP */
1c120deb 415 tmp |= (display_var->hsync_len / 8) << 16; /* HSYNW */
6011bdea
GL		 416 lcdc_write_chan(ch, LDHSYNR, tmp);
417
418 /* vertical configuration */
1c120deb
GL		 419 tmp = display_var->yres + display_var->vsync_len +
420 display_var->upper_margin + display_var->lower_margin; /* VTLN */
421 tmp |= min(display_var->yres, var->yres) << 16; /* VDLN */
6011bdea
GL		 422 lcdc_write_chan(ch, LDVLNR, tmp);
423
1c120deb
GL		 424 tmp = display_var->yres + display_var->lower_margin; /* VSYNP */
425 tmp |= display_var->vsync_len << 16; /* VSYNW */
6011bdea
GL		 426 lcdc_write_chan(ch, LDVSYNR, tmp);
427
428 /* Adjust horizontal synchronisation for HDMI */
1c120deb
GL		 429 display_h_total = display_var->xres + display_var->hsync_len +
430 display_var->left_margin + display_var->right_margin;
431 tmp = ((display_var->xres & 7) << 24) |
432 ((display_h_total & 7) << 16) |
433 ((display_var->hsync_len & 7) << 8) |
6011bdea
GL		 434 hsync_pos;
435 lcdc_write_chan(ch, LDHAJR, tmp);
436}
437
9a217e34
LP		 438/*
439 * __sh_mobile_lcdc_start - Configure and tart the LCDC
440 * @priv: LCDC device
441 *
442 * Configure all enabled channels and start the LCDC device. All external
443 * devices (clocks, MERAM, panels, ...) are not touched by this function.
444 */
445static void __sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
cfb4f5d1
MD		 446{
447 struct sh_mobile_lcdc_chan *ch;
cfb4f5d1 448 unsigned long tmp;
417d4827 449 int bpp = 0;
9a217e34 450 int k, m;
8564557a 451
9a217e34
LP		 452 /* Enable LCDC channels. Read data from external memory, avoid using the
453 * BEU for now.
454 */
455 lcdc_write(priv, _LDCNT2R, priv->ch[0].enabled | priv->ch[1].enabled);
cfb4f5d1 456
9a217e34 457 /* Stop the LCDC first and disable all interrupts. */
cfb4f5d1 458 sh_mobile_lcdc_start_stop(priv, 0);
9a217e34 459 lcdc_write(priv, _LDINTR, 0);
cfb4f5d1 460
9a217e34 461 /* Configure power supply, dot clocks and start them. */
cfb4f5d1
MD		 462 tmp = priv->lddckr;
463 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
464 ch = &priv->ch[k];
9a217e34 465 if (!ch->enabled)
cfb4f5d1
MD		 466 continue;
467
9a217e34
LP		 468 if (!bpp)
469 bpp = ch->info->var.bits_per_pixel;
470
471 /* Power supply */
472 lcdc_write_chan(ch, LDPMR, 0);
473
cfb4f5d1
MD		 474 m = ch->cfg.clock_divider;
475 if (!m)
476 continue;
477
505c7de5
LP		 478 /* FIXME: sh7724 can only use 42, 48, 54 and 60 for the divider
479 * denominator.
480 */
481 lcdc_write_chan(ch, LDDCKPAT1R, 0);
482 lcdc_write_chan(ch, LDDCKPAT2R, (1 << (m/2)) - 1);
483
cfb4f5d1 484 if (m == 1)
ce1c0b08 485 m = LDDCKR_MOSEL;
cfb4f5d1 486 tmp |= m << (lcdc_chan_is_sublcd(ch) ? 8 : 0);
cfb4f5d1
MD		 487 }
488
489 lcdc_write(priv, _LDDCKR, tmp);
cfb4f5d1
MD		 490 lcdc_write(priv, _LDDCKSTPR, 0);
491 lcdc_wait_bit(priv, _LDDCKSTPR, ~0, 0);
492
9a217e34 493 /* Setup geometry, format, frame buffer memory and operation mode. */
cfb4f5d1
MD		 494 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
495 ch = &priv->ch[k];
cfb4f5d1
MD		 496 if (!ch->enabled)
497 continue;
498
6011bdea 499 sh_mobile_lcdc_geometry(ch);
cfb4f5d1 500
53b50314 501 if (ch->info->var.nonstd) {
9a217e34 502 tmp = (ch->info->var.nonstd << 16);
53b50314
DHG		 503 switch (ch->info->var.bits_per_pixel) {
504 case 12:
9a217e34 505 tmp |= LDDFR_YF_420;
53b50314
DHG		 506 break;
507 case 16:
ce1c0b08 508 tmp |= LDDFR_YF_422;
53b50314
DHG		 509 break;
510 case 24:
9a217e34 511 default:
ce1c0b08 512 tmp |= LDDFR_YF_444;
53b50314
DHG		 513 break;
514 }
515 } else {
516 switch (ch->info->var.bits_per_pixel) {
517 case 16:
9a217e34 518 tmp = LDDFR_PKF_RGB16;
53b50314
DHG		 519 break;
520 case 24:
9a217e34 521 tmp = LDDFR_PKF_RGB24;
53b50314
DHG		 522 break;
523 case 32:
9a217e34
LP		 524 default:
525 tmp = LDDFR_PKF_ARGB32;
53b50314
DHG		 526 break;
527 }
417d4827 528 }
7caa4342 529
9a217e34
LP		 530 lcdc_write_chan(ch, LDDFR, tmp);
531 lcdc_write_chan(ch, LDMLSR, ch->pitch);
532 lcdc_write_chan(ch, LDSA1R, ch->base_addr_y);
533 if (ch->info->var.nonstd)
534 lcdc_write_chan(ch, LDSA2R, ch->base_addr_c);
7caa4342 535
9a217e34
LP		 536 /* When using deferred I/O mode, configure the LCDC for one-shot
537 * operation and enable the frame end interrupt. Otherwise use
538 * continuous read mode.
539 */
540 if (ch->ldmt1r_value & LDMT1R_IFM &&
541 ch->cfg.sys_bus_cfg.deferred_io_msec) {
542 lcdc_write_chan(ch, LDSM1R, LDSM1R_OS);
543 lcdc_write(priv, _LDINTR, LDINTR_FE);
544 } else {
545 lcdc_write_chan(ch, LDSM1R, 0);
546 }
547 }
7caa4342 548
9a217e34
LP		 549 /* Word and long word swap. */
550 if (priv->ch[0].info->var.nonstd)
551 tmp = LDDDSR_LS | LDDDSR_WS | LDDDSR_BS;
552 else {
553 switch (bpp) {
554 case 16:
555 tmp = LDDDSR_LS | LDDDSR_WS;
556 break;
557 case 24:
558 tmp = LDDDSR_LS | LDDDSR_WS | LDDDSR_BS;
559 break;
560 case 32:
561 default:
562 tmp = LDDDSR_LS;
563 break;
7caa4342 564 }
9a217e34
LP		 565 }
566 lcdc_write(priv, _LDDDSR, tmp);
7caa4342 567
9a217e34
LP		 568 /* Enable the display output. */
569 lcdc_write(priv, _LDCNT1R, LDCNT1R_DE);
570 sh_mobile_lcdc_start_stop(priv, 1);
571 priv->started = 1;
572}
cfb4f5d1 573
9a217e34
LP		 574static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
575{
576 struct sh_mobile_meram_info *mdev = priv->meram_dev;
577 struct sh_mobile_lcdc_board_cfg *board_cfg;
578 struct sh_mobile_lcdc_chan *ch;
579 unsigned long tmp;
580 int ret;
581 int k;
cfb4f5d1 582
9a217e34
LP		 583 /* enable clocks before accessing the hardware */
584 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
585 if (priv->ch[k].enabled)
586 sh_mobile_lcdc_clk_on(priv);
587 }
8564557a 588
9a217e34
LP		 589 /* reset */
590 lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LDCNT2R_BR);
591 lcdc_wait_bit(priv, _LDCNT2R, LDCNT2R_BR, 0);
8564557a 592
9a217e34
LP		 593 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
594 ch = &priv->ch[k];
8564557a 595
9a217e34
LP		 596 if (!ch->enabled)
597 continue;
598
599 board_cfg = &ch->cfg.board_cfg;
600 if (board_cfg->setup_sys) {
601 ret = board_cfg->setup_sys(board_cfg->board_data, ch,
602 &sh_mobile_lcdc_sys_bus_ops);
603 if (ret)
604 return ret;
8564557a 605 }
cfb4f5d1
MD		 606 }
607
9a217e34
LP		 608 /* Compute frame buffer base address and pitch for each channel. */
609 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
610 struct sh_mobile_meram_cfg *cfg;
611 int pixelformat;
cfb4f5d1 612
9a217e34
LP		 613 ch = &priv->ch[k];
614 if (!ch->enabled)
615 continue;
cfb4f5d1 616
9a217e34
LP		 617 ch->base_addr_y = ch->info->fix.smem_start;
618 ch->base_addr_c = ch->base_addr_y
619 + ch->info->var.xres
620 * ch->info->var.yres_virtual;
621 ch->pitch = ch->info->fix.line_length;
622
623 /* Enable MERAM if possible. */
624 cfg = ch->cfg.meram_cfg;
625 if (mdev == NULL || mdev->ops == NULL || cfg == NULL)
626 continue;
627
628 /* we need to de-init configured ICBs before we can
629 * re-initialize them.
630 */
631 if (ch->meram_enabled) {
632 mdev->ops->meram_unregister(mdev, cfg);
633 ch->meram_enabled = 0;
634 }
635
636 if (!ch->info->var.nonstd)
637 pixelformat = SH_MOBILE_MERAM_PF_RGB;
638 else if (ch->info->var.bits_per_pixel == 24)
639 pixelformat = SH_MOBILE_MERAM_PF_NV24;
640 else
641 pixelformat = SH_MOBILE_MERAM_PF_NV;
642
643 ret = mdev->ops->meram_register(mdev, cfg, ch->pitch,
644 ch->info->var.yres, pixelformat,
645 ch->base_addr_y, ch->base_addr_c,
646 &ch->base_addr_y, &ch->base_addr_c,
647 &ch->pitch);
648 if (!ret)
649 ch->meram_enabled = 1;
650 }
651
652 /* Start the LCDC. */
653 __sh_mobile_lcdc_start(priv);
654
655 /* Setup deferred I/O, tell the board code to enable the panels, and
656 * turn backlight on.
657 */
cfb4f5d1
MD		 658 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
659 ch = &priv->ch[k];
21bc1f02
MD		 660 if (!ch->enabled)
661 continue;
662
9a217e34
LP		 663 tmp = ch->cfg.sys_bus_cfg.deferred_io_msec;
664 if (ch->ldmt1r_value & LDMT1R_IFM && tmp) {
665 ch->defio.deferred_io = sh_mobile_lcdc_deferred_io;
666 ch->defio.delay = msecs_to_jiffies(tmp);
667 ch->info->fbdefio = &ch->defio;
668 fb_deferred_io_init(ch->info);
669 }
670
cfb4f5d1 671 board_cfg = &ch->cfg.board_cfg;
247f9938 672 if (board_cfg->display_on && try_module_get(board_cfg->owner)) {
c2439398 673 board_cfg->display_on(board_cfg->board_data, ch->info);
6de9edd5
GL		 674 module_put(board_cfg->owner);
675 }
3b0fd9d7
AC		 676
677 if (ch->bl) {
678 ch->bl->props.power = FB_BLANK_UNBLANK;
679 backlight_update_status(ch->bl);
680 }
cfb4f5d1
MD		 681 }
682
683 return 0;
684}
685
686static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
687{
688 struct sh_mobile_lcdc_chan *ch;
689 struct sh_mobile_lcdc_board_cfg *board_cfg;
690 int k;
691
2feb075a 692 /* clean up deferred io and ask board code to disable panel */
cfb4f5d1
MD		 693 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
694 ch = &priv->ch[k];
21bc1f02
MD		 695 if (!ch->enabled)
696 continue;
8564557a 697
2feb075a
MD		 698 /* deferred io mode:
699 * flush frame, and wait for frame end interrupt
700 * clean up deferred io and enable clock
701 */
5ef6b505 702 if (ch->info && ch->info->fbdefio) {
2feb075a 703 ch->frame_end = 0;
e33afddc 704 schedule_delayed_work(&ch->info->deferred_work, 0);
2feb075a 705 wait_event(ch->frame_end_wait, ch->frame_end);
e33afddc
PM		 706 fb_deferred_io_cleanup(ch->info);
707 ch->info->fbdefio = NULL;
2feb075a 708 sh_mobile_lcdc_clk_on(priv);
8564557a 709 }
2feb075a 710
3b0fd9d7
AC		 711 if (ch->bl) {
712 ch->bl->props.power = FB_BLANK_POWERDOWN;
713 backlight_update_status(ch->bl);
714 }
715
2feb075a 716 board_cfg = &ch->cfg.board_cfg;
247f9938 717 if (board_cfg->display_off && try_module_get(board_cfg->owner)) {
2feb075a 718 board_cfg->display_off(board_cfg->board_data);
6de9edd5
GL		 719 module_put(board_cfg->owner);
720 }
7caa4342
D		 721
722 /* disable the meram */
723 if (ch->meram_enabled) {
724 struct sh_mobile_meram_cfg *cfg;
725 struct sh_mobile_meram_info *mdev;
726 cfg = ch->cfg.meram_cfg;
727 mdev = priv->meram_dev;
728 mdev->ops->meram_unregister(mdev, cfg);
729 ch->meram_enabled = 0;
730 }
731
cfb4f5d1
MD		 732 }
733
734 /* stop the lcdc */
8e9bb19e
MD		 735 if (priv->started) {
736 sh_mobile_lcdc_start_stop(priv, 0);
737 priv->started = 0;
738 }
b51339ff 739
8564557a
MD		 740 /* stop clocks */
741 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
742 if (priv->ch[k].enabled)
743 sh_mobile_lcdc_clk_off(priv);
cfb4f5d1
MD		 744}
745
746static int sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan *ch)
747{
ce1c0b08
LP		 748 int interface_type = ch->cfg.interface_type;
749
750 switch (interface_type) {
751 case RGB8:
752 case RGB9:
753 case RGB12A:
754 case RGB12B:
755 case RGB16:
756 case RGB18:
757 case RGB24:
758 case SYS8A:
759 case SYS8B:
760 case SYS8C:
761 case SYS8D:
762 case SYS9:
763 case SYS12:
764 case SYS16A:
765 case SYS16B:
766 case SYS16C:
767 case SYS18:
768 case SYS24:
769 break;
770 default:
771 return -EINVAL;
cfb4f5d1
MD		 772 }
773
774 /* SUBLCD only supports SYS interface */
775 if (lcdc_chan_is_sublcd(ch)) {
ce1c0b08
LP		 776 if (!(interface_type & LDMT1R_IFM))
777 return -EINVAL;
778
779 interface_type &= ~LDMT1R_IFM;
cfb4f5d1
MD		 780 }
781
ce1c0b08 782 ch->ldmt1r_value = interface_type;
cfb4f5d1 783 return 0;
cfb4f5d1
MD		 784}
785
b51339ff
MD		 786static int sh_mobile_lcdc_setup_clocks(struct platform_device *pdev,
787 int clock_source,
cfb4f5d1
MD		 788 struct sh_mobile_lcdc_priv *priv)
789{
790 char *str;
cfb4f5d1
MD		 791
792 switch (clock_source) {
ce1c0b08
LP		 793 case LCDC_CLK_BUS:
794 str = "bus_clk";
795 priv->lddckr = LDDCKR_ICKSEL_BUS;
796 break;
797 case LCDC_CLK_PERIPHERAL:
798 str = "peripheral_clk";
799 priv->lddckr = LDDCKR_ICKSEL_MIPI;
800 break;
801 case LCDC_CLK_EXTERNAL:
802 str = NULL;
803 priv->lddckr = LDDCKR_ICKSEL_HDMI;
804 break;
cfb4f5d1
MD		 805 default:
806 return -EINVAL;
807 }
808
cfb4f5d1 809 if (str) {
b51339ff
MD		 810 priv->dot_clk = clk_get(&pdev->dev, str);
811 if (IS_ERR(priv->dot_clk)) {
812 dev_err(&pdev->dev, "cannot get dot clock %s\n", str);
b51339ff 813 return PTR_ERR(priv->dot_clk);
cfb4f5d1 814 }
cfb4f5d1 815 }
0246c471
MD		 816
817 /* Runtime PM support involves two step for this driver:
818 * 1) Enable Runtime PM
819 * 2) Force Runtime PM Resume since hardware is accessed from probe()
820 */
8bed9055 821 priv->dev = &pdev->dev;
0246c471
MD		 822 pm_runtime_enable(priv->dev);
823 pm_runtime_resume(priv->dev);
cfb4f5d1
MD		 824 return 0;
825}
826
827static int sh_mobile_lcdc_setcolreg(u_int regno,
828 u_int red, u_int green, u_int blue,
829 u_int transp, struct fb_info *info)
830{
831 u32 *palette = info->pseudo_palette;
832
833 if (regno >= PALETTE_NR)
834 return -EINVAL;
835
836 /* only FB_VISUAL_TRUECOLOR supported */
837
838 red >>= 16 - info->var.red.length;
839 green >>= 16 - info->var.green.length;
840 blue >>= 16 - info->var.blue.length;
841 transp >>= 16 - info->var.transp.length;
842
843 palette[regno] = (red << info->var.red.offset) |
844 (green << info->var.green.offset) |
845 (blue << info->var.blue.offset) |
846 (transp << info->var.transp.offset);
847
848 return 0;
849}
850
851static struct fb_fix_screeninfo sh_mobile_lcdc_fix = {
852 .id = "SH Mobile LCDC",
853 .type = FB_TYPE_PACKED_PIXELS,
854 .visual = FB_VISUAL_TRUECOLOR,
855 .accel = FB_ACCEL_NONE,
9dd38819
PE		 856 .xpanstep = 0,
857 .ypanstep = 1,
858 .ywrapstep = 0,
cfb4f5d1
MD		 859};
860
8564557a
MD		 861static void sh_mobile_lcdc_fillrect(struct fb_info *info,
862 const struct fb_fillrect *rect)
863{
864 sys_fillrect(info, rect);
865 sh_mobile_lcdc_deferred_io_touch(info);
866}
867
868static void sh_mobile_lcdc_copyarea(struct fb_info *info,
869 const struct fb_copyarea *area)
870{
871 sys_copyarea(info, area);
872 sh_mobile_lcdc_deferred_io_touch(info);
873}
874
875static void sh_mobile_lcdc_imageblit(struct fb_info *info,
876 const struct fb_image *image)
877{
878 sys_imageblit(info, image);
879 sh_mobile_lcdc_deferred_io_touch(info);
880}
881
9dd38819
PE		 882static int sh_mobile_fb_pan_display(struct fb_var_screeninfo *var,
883 struct fb_info *info)
884{
885 struct sh_mobile_lcdc_chan *ch = info->par;
92e1f9a7
PE		 886 struct sh_mobile_lcdc_priv *priv = ch->lcdc;
887 unsigned long ldrcntr;
888 unsigned long new_pan_offset;
53b50314
DHG		 889 unsigned long base_addr_y, base_addr_c;
890 unsigned long c_offset;
92e1f9a7 891
53b50314
DHG		 892 if (!var->nonstd)
893 new_pan_offset = (var->yoffset * info->fix.line_length) +
894 (var->xoffset * (info->var.bits_per_pixel / 8));
895 else
896 new_pan_offset = (var->yoffset * info->fix.line_length) +
897 (var->xoffset);
9dd38819 898
92e1f9a7 899 if (new_pan_offset == ch->pan_offset)
9dd38819
PE		 900 return 0; /* No change, do nothing */
901
92e1f9a7 902 ldrcntr = lcdc_read(priv, _LDRCNTR);
9dd38819 903
92e1f9a7 904 /* Set the source address for the next refresh */
53b50314
DHG		 905 base_addr_y = ch->dma_handle + new_pan_offset;
906 if (var->nonstd) {
907 /* Set y offset */
908 c_offset = (var->yoffset *
909 info->fix.line_length *
910 (info->var.bits_per_pixel - 8)) / 8;
911 base_addr_c = ch->dma_handle + var->xres * var->yres_virtual +
912 c_offset;
913 /* Set x offset */
914 if (info->var.bits_per_pixel == 24)
915 base_addr_c += 2 * var->xoffset;
916 else
917 base_addr_c += var->xoffset;
918 } else
919 base_addr_c = 0;
920
7caa4342
D		 921 if (!ch->meram_enabled) {
922 lcdc_write_chan_mirror(ch, LDSA1R, base_addr_y);
923 if (base_addr_c)
924 lcdc_write_chan_mirror(ch, LDSA2R, base_addr_c);
925 } else {
926 struct sh_mobile_meram_cfg *cfg;
927 struct sh_mobile_meram_info *mdev;
928 unsigned long icb_addr_y, icb_addr_c;
929 int ret;
930
931 cfg = ch->cfg.meram_cfg;
932 mdev = priv->meram_dev;
933 ret = mdev->ops->meram_update(mdev, cfg,
934 base_addr_y, base_addr_c,
935 &icb_addr_y, &icb_addr_c);
936 if (ret)
937 return ret;
938
939 lcdc_write_chan_mirror(ch, LDSA1R, icb_addr_y);
940 if (icb_addr_c)
941 lcdc_write_chan_mirror(ch, LDSA2R, icb_addr_c);
942
943 }
53b50314 944
92e1f9a7
PE		 945 if (lcdc_chan_is_sublcd(ch))
946 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_SRS);
947 else
948 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_MRS);
949
950 ch->pan_offset = new_pan_offset;
951
952 sh_mobile_lcdc_deferred_io_touch(info);
9dd38819
PE		 953
954 return 0;
955}
956
40331b21
PE		 957static int sh_mobile_wait_for_vsync(struct fb_info *info)
958{
959 struct sh_mobile_lcdc_chan *ch = info->par;
960 unsigned long ldintr;
961 int ret;
962
dc48665f
LP		 963 /* Enable VSync End interrupt and be careful not to acknowledge any
964 * pending interrupt.
965 */
40331b21 966 ldintr = lcdc_read(ch->lcdc, _LDINTR);
dc48665f 967 ldintr |= LDINTR_VEE | LDINTR_STATUS_MASK;
40331b21
PE		 968 lcdc_write(ch->lcdc, _LDINTR, ldintr);
969
970 ret = wait_for_completion_interruptible_timeout(&ch->vsync_completion,
971 msecs_to_jiffies(100));
972 if (!ret)
973 return -ETIMEDOUT;
974
975 return 0;
976}
977
978static int sh_mobile_ioctl(struct fb_info *info, unsigned int cmd,
979 unsigned long arg)
980{
981 int retval;
982
983 switch (cmd) {
984 case FBIO_WAITFORVSYNC:
985 retval = sh_mobile_wait_for_vsync(info);
986 break;
987
988 default:
989 retval = -ENOIOCTLCMD;
990 break;
991 }
992 return retval;
993}
994
dd210503
GL		 995static void sh_mobile_fb_reconfig(struct fb_info *info)
996{
997 struct sh_mobile_lcdc_chan *ch = info->par;
998 struct fb_videomode mode1, mode2;
999 struct fb_event event;
1000 int evnt = FB_EVENT_MODE_CHANGE_ALL;
1001
1002 if (ch->use_count > 1 || (ch->use_count == 1 && !info->fbcon_par))
1003 /* More framebuffer users are active */
1004 return;
1005
1006 fb_var_to_videomode(&mode1, &ch->display_var);
1007 fb_var_to_videomode(&mode2, &info->var);
1008
1009 if (fb_mode_is_equal(&mode1, &mode2))
1010 return;
1011
1012 /* Display has been re-plugged, framebuffer is free now, reconfigure */
1013 if (fb_set_var(info, &ch->display_var) < 0)
1014 /* Couldn't reconfigure, hopefully, can continue as before */
1015 return;
1016
53b50314
DHG		 1017 if (info->var.nonstd)
1018 info->fix.line_length = mode1.xres;
1019 else
1020 info->fix.line_length = mode1.xres * (ch->cfg.bpp / 8);
dd210503
GL		 1021
1022 /*
1023 * fb_set_var() calls the notifier change internally, only if
1024 * FBINFO_MISC_USEREVENT flag is set. Since we do not want to fake a
1025 * user event, we have to call the chain ourselves.
1026 */
1027 event.info = info;
cc267ec5 1028 event.data = &mode1;
dd210503
GL		 1029 fb_notifier_call_chain(evnt, &event);
1030}
1031
1032/*
1033 * Locking: both .fb_release() and .fb_open() are called with info->lock held if
1034 * user == 1, or with console sem held, if user == 0.
1035 */
1036static int sh_mobile_release(struct fb_info *info, int user)
1037{
1038 struct sh_mobile_lcdc_chan *ch = info->par;
1039
1040 mutex_lock(&ch->open_lock);
1041 dev_dbg(info->dev, "%s(): %d users\n", __func__, ch->use_count);
1042
1043 ch->use_count--;
1044
1045 /* Nothing to reconfigure, when called from fbcon */
1046 if (user) {
ac751efa 1047 console_lock();
dd210503 1048 sh_mobile_fb_reconfig(info);
ac751efa 1049 console_unlock();
dd210503
GL		 1050 }
1051
1052 mutex_unlock(&ch->open_lock);
1053
1054 return 0;
1055}
1056
1057static int sh_mobile_open(struct fb_info *info, int user)
1058{
1059 struct sh_mobile_lcdc_chan *ch = info->par;
1060
1061 mutex_lock(&ch->open_lock);
1062 ch->use_count++;
1063
1064 dev_dbg(info->dev, "%s(): %d users\n", __func__, ch->use_count);
1065 mutex_unlock(&ch->open_lock);
1066
1067 return 0;
1068}
1069
1070static int sh_mobile_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1071{
1072 struct sh_mobile_lcdc_chan *ch = info->par;
417d4827 1073 struct sh_mobile_lcdc_priv *p = ch->lcdc;
dd210503 1074
d2ecbab5 1075 if (var->xres > MAX_XRES || var->yres > MAX_YRES ||
dd210503 1076 var->xres * var->yres * (ch->cfg.bpp / 8) * 2 > info->fix.smem_len) {
830539d1 1077 dev_warn(info->dev, "Invalid info: %u-%u-%u-%u x %u-%u-%u-%u @ %lukHz!\n",
d2ecbab5
GL		 1078 var->left_margin, var->xres, var->right_margin, var->hsync_len,
1079 var->upper_margin, var->yres, var->lower_margin, var->vsync_len,
1080 PICOS2KHZ(var->pixclock));
dd210503
GL		 1081 return -EINVAL;
1082 }
417d4827
MD		 1083
1084 /* only accept the forced_bpp for dual channel configurations */
1085 if (p->forced_bpp && p->forced_bpp != var->bits_per_pixel)
1086 return -EINVAL;
1087
1088 switch (var->bits_per_pixel) {
1089 case 16: /* PKF[4:0] = 00011 - RGB 565 */
1090 case 24: /* PKF[4:0] = 01011 - RGB 888 */
1091 case 32: /* PKF[4:0] = 00000 - RGBA 888 */
1092 break;
1093 default:
1094 return -EINVAL;
1095 }
1096
dd210503
GL		 1097 return 0;
1098}
40331b21 1099
8857b9aa
AC		 1100/*
1101 * Screen blanking. Behavior is as follows:
1102 * FB_BLANK_UNBLANK: screen unblanked, clocks enabled
1103 * FB_BLANK_NORMAL: screen blanked, clocks enabled
1104 * FB_BLANK_VSYNC,
1105 * FB_BLANK_HSYNC,
1106 * FB_BLANK_POWEROFF: screen blanked, clocks disabled
1107 */
1108static int sh_mobile_lcdc_blank(int blank, struct fb_info *info)
1109{
1110 struct sh_mobile_lcdc_chan *ch = info->par;
1111 struct sh_mobile_lcdc_priv *p = ch->lcdc;
1112
1113 /* blank the screen? */
1114 if (blank > FB_BLANK_UNBLANK && ch->blank_status == FB_BLANK_UNBLANK) {
1115 struct fb_fillrect rect = {
1116 .width = info->var.xres,
1117 .height = info->var.yres,
1118 };
1119 sh_mobile_lcdc_fillrect(info, &rect);
1120 }
1121 /* turn clocks on? */
1122 if (blank <= FB_BLANK_NORMAL && ch->blank_status > FB_BLANK_NORMAL) {
1123 sh_mobile_lcdc_clk_on(p);
1124 }
1125 /* turn clocks off? */
1126 if (blank > FB_BLANK_NORMAL && ch->blank_status <= FB_BLANK_NORMAL) {
1127 /* make sure the screen is updated with the black fill before
1128 * switching the clocks off. one vsync is not enough since
1129 * blanking may occur in the middle of a refresh. deferred io
1130 * mode will reenable the clocks and update the screen in time,
1131 * so it does not need this. */
1132 if (!info->fbdefio) {
1133 sh_mobile_wait_for_vsync(info);
1134 sh_mobile_wait_for_vsync(info);
1135 }
1136 sh_mobile_lcdc_clk_off(p);
1137 }
1138
1139 ch->blank_status = blank;
1140 return 0;
1141}
1142
cfb4f5d1 1143static struct fb_ops sh_mobile_lcdc_ops = {
9dd38819 1144 .owner = THIS_MODULE,
cfb4f5d1 1145 .fb_setcolreg = sh_mobile_lcdc_setcolreg,
2540c111
MD		 1146 .fb_read = fb_sys_read,
1147 .fb_write = fb_sys_write,
8564557a
MD		 1148 .fb_fillrect = sh_mobile_lcdc_fillrect,
1149 .fb_copyarea = sh_mobile_lcdc_copyarea,
1150 .fb_imageblit = sh_mobile_lcdc_imageblit,
8857b9aa 1151 .fb_blank = sh_mobile_lcdc_blank,
9dd38819 1152 .fb_pan_display = sh_mobile_fb_pan_display,
40331b21 1153 .fb_ioctl = sh_mobile_ioctl,
dd210503
GL		 1154 .fb_open = sh_mobile_open,
1155 .fb_release = sh_mobile_release,
1156 .fb_check_var = sh_mobile_check_var,
cfb4f5d1
MD		 1157};
1158
3b0fd9d7
AC		 1159static int sh_mobile_lcdc_update_bl(struct backlight_device *bdev)
1160{
1161 struct sh_mobile_lcdc_chan *ch = bl_get_data(bdev);
1162 struct sh_mobile_lcdc_board_cfg *cfg = &ch->cfg.board_cfg;
1163 int brightness = bdev->props.brightness;
1164
1165 if (bdev->props.power != FB_BLANK_UNBLANK ||
1166 bdev->props.state & (BL_CORE_SUSPENDED | BL_CORE_FBBLANK))
1167 brightness = 0;
1168
1169 return cfg->set_brightness(cfg->board_data, brightness);
1170}
1171
1172static int sh_mobile_lcdc_get_brightness(struct backlight_device *bdev)
1173{
1174 struct sh_mobile_lcdc_chan *ch = bl_get_data(bdev);
1175 struct sh_mobile_lcdc_board_cfg *cfg = &ch->cfg.board_cfg;
1176
1177 return cfg->get_brightness(cfg->board_data);
1178}
1179
1180static int sh_mobile_lcdc_check_fb(struct backlight_device *bdev,
1181 struct fb_info *info)
1182{
1183 return (info->bl_dev == bdev);
1184}
1185
1186static struct backlight_ops sh_mobile_lcdc_bl_ops = {
1187 .options = BL_CORE_SUSPENDRESUME,
1188 .update_status = sh_mobile_lcdc_update_bl,
1189 .get_brightness = sh_mobile_lcdc_get_brightness,
1190 .check_fb = sh_mobile_lcdc_check_fb,
1191};
1192
1193static struct backlight_device *sh_mobile_lcdc_bl_probe(struct device *parent,
1194 struct sh_mobile_lcdc_chan *ch)
1195{
1196 struct backlight_device *bl;
1197
1198 bl = backlight_device_register(ch->cfg.bl_info.name, parent, ch,
1199 &sh_mobile_lcdc_bl_ops, NULL);
beee1f20
DC		 1200 if (IS_ERR(bl)) {
1201 dev_err(parent, "unable to register backlight device: %ld\n",
1202 PTR_ERR(bl));
3b0fd9d7
AC		 1203 return NULL;
1204 }
1205
1206 bl->props.max_brightness = ch->cfg.bl_info.max_brightness;
1207 bl->props.brightness = bl->props.max_brightness;
1208 backlight_update_status(bl);
1209
1210 return bl;
1211}
1212
1213static void sh_mobile_lcdc_bl_remove(struct backlight_device *bdev)
1214{
1215 backlight_device_unregister(bdev);
1216}
1217
53b50314
DHG		 1218static int sh_mobile_lcdc_set_bpp(struct fb_var_screeninfo *var, int bpp,
1219 int nonstd)
cfb4f5d1 1220{
53b50314
DHG		 1221 if (nonstd) {
1222 switch (bpp) {
1223 case 12:
1224 case 16:
1225 case 24:
1226 var->bits_per_pixel = bpp;
1227 var->nonstd = nonstd;
1228 return 0;
1229 default:
1230 return -EINVAL;
1231 }
1232 }
1233
cfb4f5d1
MD		 1234 switch (bpp) {
1235 case 16: /* PKF[4:0] = 00011 - RGB 565 */
1236 var->red.offset = 11;
1237 var->red.length = 5;
1238 var->green.offset = 5;
1239 var->green.length = 6;
1240 var->blue.offset = 0;
1241 var->blue.length = 5;
1242 var->transp.offset = 0;
1243 var->transp.length = 0;
1244 break;
1245
417d4827
MD		 1246 case 24: /* PKF[4:0] = 01011 - RGB 888 */
1247 var->red.offset = 16;
cfb4f5d1 1248 var->red.length = 8;
417d4827 1249 var->green.offset = 8;
cfb4f5d1 1250 var->green.length = 8;
417d4827 1251 var->blue.offset = 0;
cfb4f5d1
MD		 1252 var->blue.length = 8;
1253 var->transp.offset = 0;
1254 var->transp.length = 0;
1255 break;
417d4827
MD		 1256
1257 case 32: /* PKF[4:0] = 00000 - RGBA 888 */
1258 var->red.offset = 16;
1259 var->red.length = 8;
1260 var->green.offset = 8;
1261 var->green.length = 8;
1262 var->blue.offset = 0;
1263 var->blue.length = 8;
1264 var->transp.offset = 24;
1265 var->transp.length = 8;
1266 break;
cfb4f5d1
MD		 1267 default:
1268 return -EINVAL;
1269 }
1270 var->bits_per_pixel = bpp;
1271 var->red.msb_right = 0;
1272 var->green.msb_right = 0;
1273 var->blue.msb_right = 0;
1274 var->transp.msb_right = 0;
1275 return 0;
1276}
1277
2feb075a
MD		 1278static int sh_mobile_lcdc_suspend(struct device *dev)
1279{
1280 struct platform_device *pdev = to_platform_device(dev);
1281
1282 sh_mobile_lcdc_stop(platform_get_drvdata(pdev));
1283 return 0;
1284}
1285
1286static int sh_mobile_lcdc_resume(struct device *dev)
1287{
1288 struct platform_device *pdev = to_platform_device(dev);
1289
1290 return sh_mobile_lcdc_start(platform_get_drvdata(pdev));
1291}
1292
0246c471
MD		 1293static int sh_mobile_lcdc_runtime_suspend(struct device *dev)
1294{
1295 struct platform_device *pdev = to_platform_device(dev);
1296 struct sh_mobile_lcdc_priv *p = platform_get_drvdata(pdev);
1297 struct sh_mobile_lcdc_chan *ch;
1298 int k, n;
1299
1300 /* save per-channel registers */
1301 for (k = 0; k < ARRAY_SIZE(p->ch); k++) {
1302 ch = &p->ch[k];
1303 if (!ch->enabled)
1304 continue;
1305 for (n = 0; n < NR_CH_REGS; n++)
1306 ch->saved_ch_regs[n] = lcdc_read_chan(ch, n);
1307 }
1308
1309 /* save shared registers */
1310 for (n = 0; n < NR_SHARED_REGS; n++)
1311 p->saved_shared_regs[n] = lcdc_read(p, lcdc_shared_regs[n]);
1312
1313 /* turn off LCDC hardware */
1314 lcdc_write(p, _LDCNT1R, 0);
1315 return 0;
1316}
1317
1318static int sh_mobile_lcdc_runtime_resume(struct device *dev)
1319{
1320 struct platform_device *pdev = to_platform_device(dev);
1321 struct sh_mobile_lcdc_priv *p = platform_get_drvdata(pdev);
1322 struct sh_mobile_lcdc_chan *ch;
1323 int k, n;
1324
1325 /* restore per-channel registers */
1326 for (k = 0; k < ARRAY_SIZE(p->ch); k++) {
1327 ch = &p->ch[k];
1328 if (!ch->enabled)
1329 continue;
1330 for (n = 0; n < NR_CH_REGS; n++)
1331 lcdc_write_chan(ch, n, ch->saved_ch_regs[n]);
1332 }
1333
1334 /* restore shared registers */
1335 for (n = 0; n < NR_SHARED_REGS; n++)
1336 lcdc_write(p, lcdc_shared_regs[n], p->saved_shared_regs[n]);
1337
1338 return 0;
1339}
1340
47145210 1341static const struct dev_pm_ops sh_mobile_lcdc_dev_pm_ops = {
2feb075a
MD		 1342 .suspend = sh_mobile_lcdc_suspend,
1343 .resume = sh_mobile_lcdc_resume,
0246c471
MD		 1344 .runtime_suspend = sh_mobile_lcdc_runtime_suspend,
1345 .runtime_resume = sh_mobile_lcdc_runtime_resume,
2feb075a
MD		 1346};
1347
6de9edd5 1348/* locking: called with info->lock held */
6011bdea
GL		 1349static int sh_mobile_lcdc_notify(struct notifier_block *nb,
1350 unsigned long action, void *data)
1351{
1352 struct fb_event *event = data;
1353 struct fb_info *info = event->info;
1354 struct sh_mobile_lcdc_chan *ch = info->par;
1355 struct sh_mobile_lcdc_board_cfg *board_cfg = &ch->cfg.board_cfg;
6011bdea
GL		 1356
1357 if (&ch->lcdc->notifier != nb)
baf16374 1358 return NOTIFY_DONE;
6011bdea
GL		 1359
1360 dev_dbg(info->dev, "%s(): action = %lu, data = %p\n",
1361 __func__, action, event->data);
1362
1363 switch(action) {
1364 case FB_EVENT_SUSPEND:
247f9938 1365 if (board_cfg->display_off && try_module_get(board_cfg->owner)) {
6011bdea 1366 board_cfg->display_off(board_cfg->board_data);
6de9edd5
GL		 1367 module_put(board_cfg->owner);
1368 }
afe417c0 1369 sh_mobile_lcdc_stop(ch->lcdc);
6011bdea
GL		 1370 break;
1371 case FB_EVENT_RESUME:
dd210503
GL		 1372 mutex_lock(&ch->open_lock);
1373 sh_mobile_fb_reconfig(info);
1374 mutex_unlock(&ch->open_lock);
6011bdea
GL		 1375
1376 /* HDMI must be enabled before LCDC configuration */
247f9938 1377 if (board_cfg->display_on && try_module_get(board_cfg->owner)) {
dd210503 1378 board_cfg->display_on(board_cfg->board_data, info);
6de9edd5 1379 module_put(board_cfg->owner);
6011bdea
GL		 1380 }
1381
ebe5e12d 1382 sh_mobile_lcdc_start(ch->lcdc);
6011bdea
GL		 1383 }
1384
baf16374 1385 return NOTIFY_OK;
6011bdea
GL		 1386}
1387
cfb4f5d1
MD		 1388static int sh_mobile_lcdc_remove(struct platform_device *pdev);
1389
c2e13037 1390static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev)
cfb4f5d1
MD		 1391{
1392 struct fb_info *info;
1393 struct sh_mobile_lcdc_priv *priv;
01ac25b5 1394 struct sh_mobile_lcdc_info *pdata = pdev->dev.platform_data;
cfb4f5d1
MD		 1395 struct resource *res;
1396 int error;
1397 void *buf;
1398 int i, j;
1399
01ac25b5 1400 if (!pdata) {
cfb4f5d1 1401 dev_err(&pdev->dev, "no platform data defined\n");
8bed9055 1402 return -EINVAL;
cfb4f5d1
MD		 1403 }
1404
1405 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8564557a
MD		 1406 i = platform_get_irq(pdev, 0);
1407 if (!res || i < 0) {
1408 dev_err(&pdev->dev, "cannot get platform resources\n");
8bed9055 1409 return -ENOENT;
cfb4f5d1
MD		 1410 }
1411
1412 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1413 if (!priv) {
1414 dev_err(&pdev->dev, "cannot allocate device data\n");
8bed9055 1415 return -ENOMEM;
cfb4f5d1
MD		 1416 }
1417
8bed9055
GL		 1418 platform_set_drvdata(pdev, priv);
1419
8564557a 1420 error = request_irq(i, sh_mobile_lcdc_irq, IRQF_DISABLED,
7ad33e74 1421 dev_name(&pdev->dev), priv);
8564557a
MD		 1422 if (error) {
1423 dev_err(&pdev->dev, "unable to request irq\n");
1424 goto err1;
1425 }
1426
1427 priv->irq = i;
5ef6b505 1428 atomic_set(&priv->hw_usecnt, -1);
cfb4f5d1
MD		 1429
1430 j = 0;
1431 for (i = 0; i < ARRAY_SIZE(pdata->ch); i++) {
01ac25b5 1432 struct sh_mobile_lcdc_chan *ch = priv->ch + j;
cfb4f5d1 1433
01ac25b5
GL		 1434 ch->lcdc = priv;
1435 memcpy(&ch->cfg, &pdata->ch[i], sizeof(pdata->ch[i]));
cfb4f5d1 1436
01ac25b5 1437 error = sh_mobile_lcdc_check_interface(ch);
cfb4f5d1
MD		 1438 if (error) {
1439 dev_err(&pdev->dev, "unsupported interface type\n");
1440 goto err1;
1441 }
01ac25b5
GL		 1442 init_waitqueue_head(&ch->frame_end_wait);
1443 init_completion(&ch->vsync_completion);
1444 ch->pan_offset = 0;
cfb4f5d1 1445
3b0fd9d7
AC		 1446 /* probe the backlight is there is one defined */
1447 if (ch->cfg.bl_info.max_brightness)
1448 ch->bl = sh_mobile_lcdc_bl_probe(&pdev->dev, ch);
1449
cfb4f5d1
MD		 1450 switch (pdata->ch[i].chan) {
1451 case LCDC_CHAN_MAINLCD:
ce1c0b08 1452 ch->enabled = LDCNT2R_ME;
01ac25b5 1453 ch->reg_offs = lcdc_offs_mainlcd;
cfb4f5d1
MD		 1454 j++;
1455 break;
1456 case LCDC_CHAN_SUBLCD:
ce1c0b08 1457 ch->enabled = LDCNT2R_SE;
01ac25b5 1458 ch->reg_offs = lcdc_offs_sublcd;
cfb4f5d1
MD		 1459 j++;
1460 break;
1461 }
1462 }
1463
1464 if (!j) {
1465 dev_err(&pdev->dev, "no channels defined\n");
1466 error = -EINVAL;
1467 goto err1;
1468 }
1469
417d4827
MD		 1470 /* for dual channel LCDC (MAIN + SUB) force shared bpp setting */
1471 if (j == 2)
1472 priv->forced_bpp = pdata->ch[0].bpp;
1473
dba6f385
GL		 1474 priv->base = ioremap_nocache(res->start, resource_size(res));
1475 if (!priv->base)
1476 goto err1;
1477
b51339ff 1478 error = sh_mobile_lcdc_setup_clocks(pdev, pdata->clock_source, priv);
cfb4f5d1
MD		 1479 if (error) {
1480 dev_err(&pdev->dev, "unable to setup clocks\n");
1481 goto err1;
1482 }
1483
7caa4342
D		 1484 priv->meram_dev = pdata->meram_dev;
1485
cfb4f5d1 1486 for (i = 0; i < j; i++) {
6011bdea 1487 struct fb_var_screeninfo *var;
71d3b0fc 1488 const struct fb_videomode *lcd_cfg, *max_cfg = NULL;
01ac25b5 1489 struct sh_mobile_lcdc_chan *ch = priv->ch + i;
c44f9f76
GL		 1490 struct sh_mobile_lcdc_chan_cfg *cfg = &ch->cfg;
1491 const struct fb_videomode *mode = cfg->lcd_cfg;
71d3b0fc
GL		 1492 unsigned long max_size = 0;
1493 int k;
5fd284e6 1494 int num_cfg;
cfb4f5d1 1495
01ac25b5
GL		 1496 ch->info = framebuffer_alloc(0, &pdev->dev);
1497 if (!ch->info) {
e33afddc
PM		 1498 dev_err(&pdev->dev, "unable to allocate fb_info\n");
1499 error = -ENOMEM;
1500 break;
1501 }
1502
01ac25b5 1503 info = ch->info;
6011bdea 1504 var = &info->var;
cfb4f5d1 1505 info->fbops = &sh_mobile_lcdc_ops;
c44f9f76 1506 info->par = ch;
dd210503
GL		 1507
1508 mutex_init(&ch->open_lock);
1509
c44f9f76
GL		 1510 for (k = 0, lcd_cfg = mode;
1511 k < cfg->num_cfg && lcd_cfg;
71d3b0fc
GL		 1512 k++, lcd_cfg++) {
1513 unsigned long size = lcd_cfg->yres * lcd_cfg->xres;
53b50314
DHG		 1514 /* NV12 buffers must have even number of lines */
1515 if ((cfg->nonstd) && cfg->bpp == 12 &&
1516 (lcd_cfg->yres & 0x1)) {
1517 dev_err(&pdev->dev, "yres must be multiple of 2"
1518 " for YCbCr420 mode.\n");
1519 error = -EINVAL;
1520 goto err1;
1521 }
71d3b0fc
GL		 1522
1523 if (size > max_size) {
1524 max_cfg = lcd_cfg;
1525 max_size = size;
1526 }
1527 }
1528
c44f9f76 1529 if (!mode)
d2ecbab5 1530 max_size = MAX_XRES * MAX_YRES;
c44f9f76
GL		 1531 else if (max_cfg)
1532 dev_dbg(&pdev->dev, "Found largest videomode %ux%u\n",
1533 max_cfg->xres, max_cfg->yres);
71d3b0fc 1534
cfb4f5d1 1535 info->fix = sh_mobile_lcdc_fix;
53b50314
DHG		 1536 info->fix.smem_len = max_size * 2 * cfg->bpp / 8;
1537
1538 /* Only pan in 2 line steps for NV12 */
1539 if (cfg->nonstd && cfg->bpp == 12)
1540 info->fix.ypanstep = 2;
cfb4f5d1 1541
5fd284e6 1542 if (!mode) {
c44f9f76 1543 mode = &default_720p;
5fd284e6
GL		 1544 num_cfg = 1;
1545 } else {
e0b9fb26 1546 num_cfg = cfg->num_cfg;
5fd284e6
GL		 1547 }
1548
1549 fb_videomode_to_modelist(mode, num_cfg, &info->modelist);
c44f9f76
GL		 1550
1551 fb_videomode_to_var(var, mode);
e0b9fb26
GL		 1552 var->width = cfg->lcd_size_cfg.width;
1553 var->height = cfg->lcd_size_cfg.height;
9dd38819 1554 /* Default Y virtual resolution is 2x panel size */
6011bdea 1555 var->yres_virtual = var->yres * 2;
6011bdea 1556 var->activate = FB_ACTIVATE_NOW;
6011bdea 1557
53b50314 1558 error = sh_mobile_lcdc_set_bpp(var, cfg->bpp, cfg->nonstd);
cfb4f5d1
MD		 1559 if (error)
1560 break;
1561
cfb4f5d1 1562 buf = dma_alloc_coherent(&pdev->dev, info->fix.smem_len,
01ac25b5 1563 &ch->dma_handle, GFP_KERNEL);
cfb4f5d1
MD		 1564 if (!buf) {
1565 dev_err(&pdev->dev, "unable to allocate buffer\n");
1566 error = -ENOMEM;
1567 break;
1568 }
1569
01ac25b5 1570 info->pseudo_palette = &ch->pseudo_palette;
cfb4f5d1
MD		 1571 info->flags = FBINFO_FLAG_DEFAULT;
1572
1573 error = fb_alloc_cmap(&info->cmap, PALETTE_NR, 0);
1574 if (error < 0) {
1575 dev_err(&pdev->dev, "unable to allocate cmap\n");
1576 dma_free_coherent(&pdev->dev, info->fix.smem_len,
01ac25b5 1577 buf, ch->dma_handle);
cfb4f5d1
MD		 1578 break;
1579 }
1580
01ac25b5 1581 info->fix.smem_start = ch->dma_handle;
53b50314
DHG		 1582 if (var->nonstd)
1583 info->fix.line_length = var->xres;
1584 else
1585 info->fix.line_length = var->xres * (cfg->bpp / 8);
1586
cfb4f5d1
MD		 1587 info->screen_base = buf;
1588 info->device = &pdev->dev;
1c120deb 1589 ch->display_var = *var;
cfb4f5d1
MD		 1590 }
1591
1592 if (error)
1593 goto err1;
1594
1595 error = sh_mobile_lcdc_start(priv);
1596 if (error) {
1597 dev_err(&pdev->dev, "unable to start hardware\n");
1598 goto err1;
1599 }
1600
1601 for (i = 0; i < j; i++) {
1c6a307a
PM		 1602 struct sh_mobile_lcdc_chan *ch = priv->ch + i;
1603
e33afddc 1604 info = ch->info;
1c6a307a
PM		 1605
1606 if (info->fbdefio) {
8bed9055 1607 ch->sglist = vmalloc(sizeof(struct scatterlist) *
1c6a307a 1608 info->fix.smem_len >> PAGE_SHIFT);
8bed9055 1609 if (!ch->sglist) {
1c6a307a
PM		 1610 dev_err(&pdev->dev, "cannot allocate sglist\n");
1611 goto err1;
1612 }
1613 }
1614
3b0fd9d7
AC		 1615 info->bl_dev = ch->bl;
1616
1c6a307a 1617 error = register_framebuffer(info);
cfb4f5d1
MD		 1618 if (error < 0)
1619 goto err1;
cfb4f5d1 1620
cfb4f5d1
MD		 1621 dev_info(info->dev,
1622 "registered %s/%s as %dx%d %dbpp.\n",
1623 pdev->name,
1c6a307a 1624 (ch->cfg.chan == LCDC_CHAN_MAINLCD) ?
cfb4f5d1 1625 "mainlcd" : "sublcd",
c44f9f76 1626 info->var.xres, info->var.yres,
1c6a307a 1627 ch->cfg.bpp);
8564557a
MD		 1628
1629 /* deferred io mode: disable clock to save power */
6011bdea 1630 if (info->fbdefio || info->state == FBINFO_STATE_SUSPENDED)
8564557a 1631 sh_mobile_lcdc_clk_off(priv);
cfb4f5d1
MD		 1632 }
1633
6011bdea
GL		 1634 /* Failure ignored */
1635 priv->notifier.notifier_call = sh_mobile_lcdc_notify;
1636 fb_register_client(&priv->notifier);
1637
cfb4f5d1 1638 return 0;
8bed9055 1639err1:
cfb4f5d1 1640 sh_mobile_lcdc_remove(pdev);
8bed9055 1641
cfb4f5d1
MD		 1642 return error;
1643}
1644
1645static int sh_mobile_lcdc_remove(struct platform_device *pdev)
1646{
1647 struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
1648 struct fb_info *info;
1649 int i;
1650
6011bdea
GL		 1651 fb_unregister_client(&priv->notifier);
1652
cfb4f5d1 1653 for (i = 0; i < ARRAY_SIZE(priv->ch); i++)
8bed9055 1654 if (priv->ch[i].info && priv->ch[i].info->dev)
e33afddc 1655 unregister_framebuffer(priv->ch[i].info);
cfb4f5d1
MD		 1656
1657 sh_mobile_lcdc_stop(priv);
1658
1659 for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
e33afddc 1660 info = priv->ch[i].info;
cfb4f5d1 1661
e33afddc 1662 if (!info || !info->device)
cfb4f5d1
MD		 1663 continue;
1664
1c6a307a
PM		 1665 if (priv->ch[i].sglist)
1666 vfree(priv->ch[i].sglist);
1667
1ffbb037
MD		 1668 if (info->screen_base)
1669 dma_free_coherent(&pdev->dev, info->fix.smem_len,
1670 info->screen_base,
1671 priv->ch[i].dma_handle);
cfb4f5d1 1672 fb_dealloc_cmap(&info->cmap);
e33afddc 1673 framebuffer_release(info);
cfb4f5d1
MD		 1674 }
1675
3b0fd9d7
AC		 1676 for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
1677 if (priv->ch[i].bl)
1678 sh_mobile_lcdc_bl_remove(priv->ch[i].bl);
1679 }
1680
b51339ff
MD		 1681 if (priv->dot_clk)
1682 clk_put(priv->dot_clk);
0246c471 1683
8bed9055
GL		 1684 if (priv->dev)
1685 pm_runtime_disable(priv->dev);
cfb4f5d1
MD		 1686
1687 if (priv->base)
1688 iounmap(priv->base);
1689
8564557a
MD		 1690 if (priv->irq)
1691 free_irq(priv->irq, priv);
cfb4f5d1
MD		 1692 kfree(priv);
1693 return 0;
1694}
1695
1696static struct platform_driver sh_mobile_lcdc_driver = {
1697 .driver = {
1698 .name = "sh_mobile_lcdc_fb",
1699 .owner = THIS_MODULE,
2feb075a 1700 .pm = &sh_mobile_lcdc_dev_pm_ops,
cfb4f5d1
MD		 1701 },
1702 .probe = sh_mobile_lcdc_probe,
1703 .remove = sh_mobile_lcdc_remove,
1704};
1705
1706static int __init sh_mobile_lcdc_init(void)
1707{
1708 return platform_driver_register(&sh_mobile_lcdc_driver);
1709}
1710
1711static void __exit sh_mobile_lcdc_exit(void)
1712{
1713 platform_driver_unregister(&sh_mobile_lcdc_driver);
1714}
1715
1716module_init(sh_mobile_lcdc_init);
1717module_exit(sh_mobile_lcdc_exit);
1718
1719MODULE_DESCRIPTION("SuperH Mobile LCDC Framebuffer driver");
1720MODULE_AUTHOR("Magnus Damm <damm@opensource.se>");
1721MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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