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fbdev: sh_mobile_lcdc: Reorder code into sections
[deliverable/linux.git] / drivers / video / sh_mobile_lcdcfb.c
CommitLineData
cfb4f5d1
MD		 1/*
2 * SuperH Mobile LCDC Framebuffer
3 *
4 * Copyright (c) 2008 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
f1f60b5f
LP		 11#include <linux/atomic.h>
12#include <linux/backlight.h>
cfb4f5d1 13#include <linux/clk.h>
f1f60b5f 14#include <linux/console.h>
cfb4f5d1 15#include <linux/dma-mapping.h>
f1f60b5f
LP		 16#include <linux/delay.h>
17#include <linux/gpio.h>
18#include <linux/init.h>
8564557a 19#include <linux/interrupt.h>
40331b21 20#include <linux/ioctl.h>
f1f60b5f
LP		 21#include <linux/kernel.h>
22#include <linux/mm.h>
355b200b 23#include <linux/module.h>
f1f60b5f
LP		 24#include <linux/platform_device.h>
25#include <linux/pm_runtime.h>
26#include <linux/slab.h>
27#include <linux/videodev2.h>
28#include <linux/vmalloc.h>
29
225c9a8d 30#include <video/sh_mobile_lcdc.h>
8a20974f 31#include <video/sh_mobile_meram.h>
cfb4f5d1 32
6de9edd5
GL		 33#include "sh_mobile_lcdcfb.h"
34
a6f15ade
PE		 35#define SIDE_B_OFFSET 0x1000
36#define MIRROR_OFFSET 0x2000
cfb4f5d1 37
d2ecbab5
GL		 38#define MAX_XRES 1920
39#define MAX_YRES 1080
cfb4f5d1 40
f1f60b5f
LP		 41struct sh_mobile_lcdc_priv {
42 void __iomem *base;
43 int irq;
44 atomic_t hw_usecnt;
45 struct device *dev;
46 struct clk *dot_clk;
47 unsigned long lddckr;
48 struct sh_mobile_lcdc_chan ch[2];
49 struct notifier_block notifier;
50 int started;
51 int forced_fourcc; /* 2 channel LCDC must share fourcc setting */
52 struct sh_mobile_meram_info *meram_dev;
53};
54
55/* -----------------------------------------------------------------------------
56 * Registers access
57 */
58
0246c471 59static unsigned long lcdc_offs_mainlcd[NR_CH_REGS] = {
cfb4f5d1
MD		 60 [LDDCKPAT1R] = 0x400,
61 [LDDCKPAT2R] = 0x404,
62 [LDMT1R] = 0x418,
63 [LDMT2R] = 0x41c,
64 [LDMT3R] = 0x420,
65 [LDDFR] = 0x424,
66 [LDSM1R] = 0x428,
8564557a 67 [LDSM2R] = 0x42c,
cfb4f5d1 68 [LDSA1R] = 0x430,
53b50314 69 [LDSA2R] = 0x434,
cfb4f5d1
MD		 70 [LDMLSR] = 0x438,
71 [LDHCNR] = 0x448,
72 [LDHSYNR] = 0x44c,
73 [LDVLNR] = 0x450,
74 [LDVSYNR] = 0x454,
75 [LDPMR] = 0x460,
6011bdea 76 [LDHAJR] = 0x4a0,
cfb4f5d1
MD		 77};
78
0246c471 79static unsigned long lcdc_offs_sublcd[NR_CH_REGS] = {
cfb4f5d1
MD		 80 [LDDCKPAT1R] = 0x408,
81 [LDDCKPAT2R] = 0x40c,
82 [LDMT1R] = 0x600,
83 [LDMT2R] = 0x604,
84 [LDMT3R] = 0x608,
85 [LDDFR] = 0x60c,
86 [LDSM1R] = 0x610,
8564557a 87 [LDSM2R] = 0x614,
cfb4f5d1
MD		 88 [LDSA1R] = 0x618,
89 [LDMLSR] = 0x620,
90 [LDHCNR] = 0x624,
91 [LDHSYNR] = 0x628,
92 [LDVLNR] = 0x62c,
93 [LDVSYNR] = 0x630,
94 [LDPMR] = 0x63c,
95};
96
a6f15ade
PE		 97static bool banked(int reg_nr)
98{
99 switch (reg_nr) {
100 case LDMT1R:
101 case LDMT2R:
102 case LDMT3R:
103 case LDDFR:
104 case LDSM1R:
105 case LDSA1R:
53b50314 106 case LDSA2R:
a6f15ade
PE		 107 case LDMLSR:
108 case LDHCNR:
109 case LDHSYNR:
110 case LDVLNR:
111 case LDVSYNR:
112 return true;
113 }
114 return false;
115}
116
f1f60b5f
LP		 117static int lcdc_chan_is_sublcd(struct sh_mobile_lcdc_chan *chan)
118{
119 return chan->cfg.chan == LCDC_CHAN_SUBLCD;
120}
121
cfb4f5d1
MD		 122static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan,
123 int reg_nr, unsigned long data)
124{
125 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]);
a6f15ade
PE		 126 if (banked(reg_nr))
127 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
128 SIDE_B_OFFSET);
129}
130
131static void lcdc_write_chan_mirror(struct sh_mobile_lcdc_chan *chan,
132 int reg_nr, unsigned long data)
133{
134 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
135 MIRROR_OFFSET);
cfb4f5d1
MD		 136}
137
138static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan,
139 int reg_nr)
140{
141 return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]);
142}
143
144static void lcdc_write(struct sh_mobile_lcdc_priv *priv,
145 unsigned long reg_offs, unsigned long data)
146{
147 iowrite32(data, priv->base + reg_offs);
148}
149
150static unsigned long lcdc_read(struct sh_mobile_lcdc_priv *priv,
151 unsigned long reg_offs)
152{
153 return ioread32(priv->base + reg_offs);
154}
155
156static void lcdc_wait_bit(struct sh_mobile_lcdc_priv *priv,
157 unsigned long reg_offs,
158 unsigned long mask, unsigned long until)
159{
160 while ((lcdc_read(priv, reg_offs) & mask) != until)
161 cpu_relax();
162}
163
f1f60b5f
LP		 164/* -----------------------------------------------------------------------------
165 * Clock management
166 */
167
168static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv)
cfb4f5d1 169{
f1f60b5f
LP		 170 if (atomic_inc_and_test(&priv->hw_usecnt)) {
171 if (priv->dot_clk)
172 clk_enable(priv->dot_clk);
173 pm_runtime_get_sync(priv->dev);
174 if (priv->meram_dev && priv->meram_dev->pdev)
175 pm_runtime_get_sync(&priv->meram_dev->pdev->dev);
176 }
cfb4f5d1
MD		 177}
178
f1f60b5f
LP		 179static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv)
180{
181 if (atomic_sub_return(1, &priv->hw_usecnt) == -1) {
182 if (priv->meram_dev && priv->meram_dev->pdev)
183 pm_runtime_put_sync(&priv->meram_dev->pdev->dev);
184 pm_runtime_put(priv->dev);
185 if (priv->dot_clk)
186 clk_disable(priv->dot_clk);
187 }
188}
189
190static int sh_mobile_lcdc_setup_clocks(struct platform_device *pdev,
191 int clock_source,
192 struct sh_mobile_lcdc_priv *priv)
193{
194 char *str;
195
196 switch (clock_source) {
197 case LCDC_CLK_BUS:
198 str = "bus_clk";
199 priv->lddckr = LDDCKR_ICKSEL_BUS;
200 break;
201 case LCDC_CLK_PERIPHERAL:
202 str = "peripheral_clk";
203 priv->lddckr = LDDCKR_ICKSEL_MIPI;
204 break;
205 case LCDC_CLK_EXTERNAL:
206 str = NULL;
207 priv->lddckr = LDDCKR_ICKSEL_HDMI;
208 break;
209 default:
210 return -EINVAL;
211 }
212
213 if (str) {
214 priv->dot_clk = clk_get(&pdev->dev, str);
215 if (IS_ERR(priv->dot_clk)) {
216 dev_err(&pdev->dev, "cannot get dot clock %s\n", str);
217 return PTR_ERR(priv->dot_clk);
218 }
219 }
220
221 /* Runtime PM support involves two step for this driver:
222 * 1) Enable Runtime PM
223 * 2) Force Runtime PM Resume since hardware is accessed from probe()
224 */
225 priv->dev = &pdev->dev;
226 pm_runtime_enable(priv->dev);
227 pm_runtime_resume(priv->dev);
228 return 0;
229}
230
231/* -----------------------------------------------------------------------------
232 * Sys panel and deferred I/O
233 */
234
cfb4f5d1
MD		 235static void lcdc_sys_write_index(void *handle, unsigned long data)
236{
237 struct sh_mobile_lcdc_chan *ch = handle;
238
ce1c0b08
LP		 239 lcdc_write(ch->lcdc, _LDDWD0R, data | LDDWDxR_WDACT);
240 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
241 lcdc_write(ch->lcdc, _LDDWAR, LDDWAR_WA |
242 (lcdc_chan_is_sublcd(ch) ? 2 : 0));
243 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
cfb4f5d1
MD		 244}
245
246static void lcdc_sys_write_data(void *handle, unsigned long data)
247{
248 struct sh_mobile_lcdc_chan *ch = handle;
249
ce1c0b08
LP		 250 lcdc_write(ch->lcdc, _LDDWD0R, data | LDDWDxR_WDACT | LDDWDxR_RSW);
251 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
252 lcdc_write(ch->lcdc, _LDDWAR, LDDWAR_WA |
253 (lcdc_chan_is_sublcd(ch) ? 2 : 0));
254 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
cfb4f5d1
MD		 255}
256
257static unsigned long lcdc_sys_read_data(void *handle)
258{
259 struct sh_mobile_lcdc_chan *ch = handle;
260
ce1c0b08
LP		 261 lcdc_write(ch->lcdc, _LDDRDR, LDDRDR_RSR);
262 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
263 lcdc_write(ch->lcdc, _LDDRAR, LDDRAR_RA |
264 (lcdc_chan_is_sublcd(ch) ? 2 : 0));
cfb4f5d1 265 udelay(1);
ce1c0b08 266 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
cfb4f5d1 267
ce1c0b08 268 return lcdc_read(ch->lcdc, _LDDRDR) & LDDRDR_DRD_MASK;
cfb4f5d1
MD		 269}
270
271struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = {
272 lcdc_sys_write_index,
273 lcdc_sys_write_data,
274 lcdc_sys_read_data,
275};
276
1c6a307a
PM		 277static int sh_mobile_lcdc_sginit(struct fb_info *info,
278 struct list_head *pagelist)
279{
280 struct sh_mobile_lcdc_chan *ch = info->par;
281 unsigned int nr_pages_max = info->fix.smem_len >> PAGE_SHIFT;
282 struct page *page;
283 int nr_pages = 0;
284
285 sg_init_table(ch->sglist, nr_pages_max);
286
287 list_for_each_entry(page, pagelist, lru)
288 sg_set_page(&ch->sglist[nr_pages++], page, PAGE_SIZE, 0);
289
290 return nr_pages;
291}
292
8564557a
MD		 293static void sh_mobile_lcdc_deferred_io(struct fb_info *info,
294 struct list_head *pagelist)
295{
296 struct sh_mobile_lcdc_chan *ch = info->par;
ef61aae4 297 struct sh_mobile_lcdc_board_cfg *bcfg = &ch->cfg.board_cfg;
8564557a
MD		 298
299 /* enable clocks before accessing hardware */
300 sh_mobile_lcdc_clk_on(ch->lcdc);
301
5c1a56b5
PM		 302 /*
303 * It's possible to get here without anything on the pagelist via
304 * sh_mobile_lcdc_deferred_io_touch() or via a userspace fsync()
305 * invocation. In the former case, the acceleration routines are
306 * stepped in to when using the framebuffer console causing the
307 * workqueue to be scheduled without any dirty pages on the list.
308 *
309 * Despite this, a panel update is still needed given that the
310 * acceleration routines have their own methods for writing in
311 * that still need to be updated.
312 *
313 * The fsync() and empty pagelist case could be optimized for,
314 * but we don't bother, as any application exhibiting such
315 * behaviour is fundamentally broken anyways.
316 */
317 if (!list_empty(pagelist)) {
318 unsigned int nr_pages = sh_mobile_lcdc_sginit(info, pagelist);
319
320 /* trigger panel update */
321 dma_map_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
ef61aae4
MD		 322 if (bcfg->start_transfer)
323 bcfg->start_transfer(bcfg->board_data, ch,
324 &sh_mobile_lcdc_sys_bus_ops);
ce1c0b08 325 lcdc_write_chan(ch, LDSM2R, LDSM2R_OSTRG);
5c1a56b5 326 dma_unmap_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
ef61aae4
MD		 327 } else {
328 if (bcfg->start_transfer)
329 bcfg->start_transfer(bcfg->board_data, ch,
330 &sh_mobile_lcdc_sys_bus_ops);
ce1c0b08 331 lcdc_write_chan(ch, LDSM2R, LDSM2R_OSTRG);
ef61aae4 332 }
8564557a
MD		 333}
334
335static void sh_mobile_lcdc_deferred_io_touch(struct fb_info *info)
336{
337 struct fb_deferred_io *fbdefio = info->fbdefio;
338
339 if (fbdefio)
340 schedule_delayed_work(&info->deferred_work, fbdefio->delay);
341}
342
f1f60b5f
LP		 343/* -----------------------------------------------------------------------------
344 * Format helpers
345 */
346
347static int sh_mobile_format_fourcc(const struct fb_var_screeninfo *var)
348{
349 if (var->grayscale > 1)
350 return var->grayscale;
351
352 switch (var->bits_per_pixel) {
353 case 16:
354 return V4L2_PIX_FMT_RGB565;
355 case 24:
356 return V4L2_PIX_FMT_BGR24;
357 case 32:
358 return V4L2_PIX_FMT_BGR32;
359 default:
360 return 0;
361 }
362}
363
364static int sh_mobile_format_is_fourcc(const struct fb_var_screeninfo *var)
365{
366 return var->grayscale > 1;
367}
368
369static bool sh_mobile_format_is_yuv(const struct fb_var_screeninfo *var)
370{
371 if (var->grayscale <= 1)
372 return false;
373
374 switch (var->grayscale) {
375 case V4L2_PIX_FMT_NV12:
376 case V4L2_PIX_FMT_NV21:
377 case V4L2_PIX_FMT_NV16:
378 case V4L2_PIX_FMT_NV61:
379 case V4L2_PIX_FMT_NV24:
380 case V4L2_PIX_FMT_NV42:
381 return true;
382
383 default:
384 return false;
385 }
386}
387
388/* -----------------------------------------------------------------------------
389 * Start, stop and IRQ
390 */
391
8564557a
MD		 392static irqreturn_t sh_mobile_lcdc_irq(int irq, void *data)
393{
394 struct sh_mobile_lcdc_priv *priv = data;
2feb075a 395 struct sh_mobile_lcdc_chan *ch;
9dd38819 396 unsigned long ldintr;
2feb075a
MD		 397 int is_sub;
398 int k;
8564557a 399
dc48665f
LP		 400 /* Acknowledge interrupts and disable further VSYNC End IRQs. */
401 ldintr = lcdc_read(priv, _LDINTR);
402 lcdc_write(priv, _LDINTR, (ldintr ^ LDINTR_STATUS_MASK) & ~LDINTR_VEE);
8564557a 403
2feb075a 404 /* figure out if this interrupt is for main or sub lcd */
ce1c0b08 405 is_sub = (lcdc_read(priv, _LDSR) & LDSR_MSS) ? 1 : 0;
2feb075a 406
9dd38819 407 /* wake up channel and disable clocks */
2feb075a
MD		 408 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
409 ch = &priv->ch[k];
410
411 if (!ch->enabled)
412 continue;
413
dc48665f 414 /* Frame End */
9dd38819
PE		 415 if (ldintr & LDINTR_FS) {
416 if (is_sub == lcdc_chan_is_sublcd(ch)) {
417 ch->frame_end = 1;
418 wake_up(&ch->frame_end_wait);
2feb075a 419
9dd38819
PE		 420 sh_mobile_lcdc_clk_off(priv);
421 }
422 }
423
424 /* VSYNC End */
40331b21
PE		 425 if (ldintr & LDINTR_VES)
426 complete(&ch->vsync_completion);
2feb075a
MD		 427 }
428
8564557a
MD		 429 return IRQ_HANDLED;
430}
431
cfb4f5d1
MD		 432static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv *priv,
433 int start)
434{
435 unsigned long tmp = lcdc_read(priv, _LDCNT2R);
436 int k;
437
438 /* start or stop the lcdc */
439 if (start)
ce1c0b08 440 lcdc_write(priv, _LDCNT2R, tmp | LDCNT2R_DO);
cfb4f5d1 441 else
ce1c0b08 442 lcdc_write(priv, _LDCNT2R, tmp & ~LDCNT2R_DO);
cfb4f5d1
MD		 443
444 /* wait until power is applied/stopped on all channels */
445 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
446 if (lcdc_read(priv, _LDCNT2R) & priv->ch[k].enabled)
447 while (1) {
ce1c0b08
LP		 448 tmp = lcdc_read_chan(&priv->ch[k], LDPMR)
449 & LDPMR_LPS;
450 if (start && tmp == LDPMR_LPS)
cfb4f5d1
MD		 451 break;
452 if (!start && tmp == 0)
453 break;
454 cpu_relax();
455 }
456
457 if (!start)
458 lcdc_write(priv, _LDDCKSTPR, 1); /* stop dotclock */
459}
460
6011bdea
GL		 461static void sh_mobile_lcdc_geometry(struct sh_mobile_lcdc_chan *ch)
462{
1c120deb
GL		 463 struct fb_var_screeninfo *var = &ch->info->var, *display_var = &ch->display_var;
464 unsigned long h_total, hsync_pos, display_h_total;
6011bdea
GL		 465 u32 tmp;
466
467 tmp = ch->ldmt1r_value;
ce1c0b08
LP		 468 tmp |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : LDMT1R_VPOL;
469 tmp |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : LDMT1R_HPOL;
470 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWPOL) ? LDMT1R_DWPOL : 0;
471 tmp |= (ch->cfg.flags & LCDC_FLAGS_DIPOL) ? LDMT1R_DIPOL : 0;
472 tmp |= (ch->cfg.flags & LCDC_FLAGS_DAPOL) ? LDMT1R_DAPOL : 0;
473 tmp |= (ch->cfg.flags & LCDC_FLAGS_HSCNT) ? LDMT1R_HSCNT : 0;
474 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWCNT) ? LDMT1R_DWCNT : 0;
6011bdea
GL		 475 lcdc_write_chan(ch, LDMT1R, tmp);
476
477 /* setup SYS bus */
478 lcdc_write_chan(ch, LDMT2R, ch->cfg.sys_bus_cfg.ldmt2r);
479 lcdc_write_chan(ch, LDMT3R, ch->cfg.sys_bus_cfg.ldmt3r);
480
481 /* horizontal configuration */
1c120deb
GL		 482 h_total = display_var->xres + display_var->hsync_len +
483 display_var->left_margin + display_var->right_margin;
6011bdea 484 tmp = h_total / 8; /* HTCN */
1c120deb 485 tmp |= (min(display_var->xres, var->xres) / 8) << 16; /* HDCN */
6011bdea
GL		 486 lcdc_write_chan(ch, LDHCNR, tmp);
487
1c120deb 488 hsync_pos = display_var->xres + display_var->right_margin;
6011bdea 489 tmp = hsync_pos / 8; /* HSYNP */
1c120deb 490 tmp |= (display_var->hsync_len / 8) << 16; /* HSYNW */
6011bdea
GL		 491 lcdc_write_chan(ch, LDHSYNR, tmp);
492
493 /* vertical configuration */
1c120deb
GL		 494 tmp = display_var->yres + display_var->vsync_len +
495 display_var->upper_margin + display_var->lower_margin; /* VTLN */
496 tmp |= min(display_var->yres, var->yres) << 16; /* VDLN */
6011bdea
GL		 497 lcdc_write_chan(ch, LDVLNR, tmp);
498
1c120deb
GL		 499 tmp = display_var->yres + display_var->lower_margin; /* VSYNP */
500 tmp |= display_var->vsync_len << 16; /* VSYNW */
6011bdea
GL		 501 lcdc_write_chan(ch, LDVSYNR, tmp);
502
503 /* Adjust horizontal synchronisation for HDMI */
1c120deb
GL		 504 display_h_total = display_var->xres + display_var->hsync_len +
505 display_var->left_margin + display_var->right_margin;
506 tmp = ((display_var->xres & 7) << 24) |
507 ((display_h_total & 7) << 16) |
508 ((display_var->hsync_len & 7) << 8) |
41e583c2 509 (hsync_pos & 7);
6011bdea
GL		 510 lcdc_write_chan(ch, LDHAJR, tmp);
511}
512
9a217e34
LP		 513/*
514 * __sh_mobile_lcdc_start - Configure and tart the LCDC
515 * @priv: LCDC device
516 *
517 * Configure all enabled channels and start the LCDC device. All external
518 * devices (clocks, MERAM, panels, ...) are not touched by this function.
519 */
520static void __sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
cfb4f5d1
MD		 521{
522 struct sh_mobile_lcdc_chan *ch;
cfb4f5d1 523 unsigned long tmp;
9a217e34 524 int k, m;
8564557a 525
9a217e34
LP		 526 /* Enable LCDC channels. Read data from external memory, avoid using the
527 * BEU for now.
528 */
529 lcdc_write(priv, _LDCNT2R, priv->ch[0].enabled | priv->ch[1].enabled);
cfb4f5d1 530
9a217e34 531 /* Stop the LCDC first and disable all interrupts. */
cfb4f5d1 532 sh_mobile_lcdc_start_stop(priv, 0);
9a217e34 533 lcdc_write(priv, _LDINTR, 0);
cfb4f5d1 534
9a217e34 535 /* Configure power supply, dot clocks and start them. */
cfb4f5d1
MD		 536 tmp = priv->lddckr;
537 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
538 ch = &priv->ch[k];
9a217e34 539 if (!ch->enabled)
cfb4f5d1
MD		 540 continue;
541
9a217e34
LP		 542 /* Power supply */
543 lcdc_write_chan(ch, LDPMR, 0);
544
cfb4f5d1
MD		 545 m = ch->cfg.clock_divider;
546 if (!m)
547 continue;
548
505c7de5
LP		 549 /* FIXME: sh7724 can only use 42, 48, 54 and 60 for the divider
550 * denominator.
551 */
552 lcdc_write_chan(ch, LDDCKPAT1R, 0);
553 lcdc_write_chan(ch, LDDCKPAT2R, (1 << (m/2)) - 1);
554
cfb4f5d1 555 if (m == 1)
ce1c0b08 556 m = LDDCKR_MOSEL;
cfb4f5d1 557 tmp |= m << (lcdc_chan_is_sublcd(ch) ? 8 : 0);
cfb4f5d1
MD		 558 }
559
560 lcdc_write(priv, _LDDCKR, tmp);
cfb4f5d1
MD		 561 lcdc_write(priv, _LDDCKSTPR, 0);
562 lcdc_wait_bit(priv, _LDDCKSTPR, ~0, 0);
563
9a217e34 564 /* Setup geometry, format, frame buffer memory and operation mode. */
cfb4f5d1
MD		 565 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
566 ch = &priv->ch[k];
cfb4f5d1
MD		 567 if (!ch->enabled)
568 continue;
569
6011bdea 570 sh_mobile_lcdc_geometry(ch);
cfb4f5d1 571
edd153a3
LP		 572 switch (sh_mobile_format_fourcc(&ch->info->var)) {
573 case V4L2_PIX_FMT_RGB565:
574 tmp = LDDFR_PKF_RGB16;
575 break;
576 case V4L2_PIX_FMT_BGR24:
577 tmp = LDDFR_PKF_RGB24;
578 break;
579 case V4L2_PIX_FMT_BGR32:
580 tmp = LDDFR_PKF_ARGB32;
581 break;
582 case V4L2_PIX_FMT_NV12:
583 case V4L2_PIX_FMT_NV21:
584 tmp = LDDFR_CC | LDDFR_YF_420;
585 break;
586 case V4L2_PIX_FMT_NV16:
587 case V4L2_PIX_FMT_NV61:
588 tmp = LDDFR_CC | LDDFR_YF_422;
589 break;
590 case V4L2_PIX_FMT_NV24:
591 case V4L2_PIX_FMT_NV42:
592 tmp = LDDFR_CC | LDDFR_YF_444;
593 break;
594 }
595
596 if (sh_mobile_format_is_yuv(&ch->info->var)) {
597 switch (ch->info->var.colorspace) {
598 case V4L2_COLORSPACE_REC709:
599 tmp |= LDDFR_CF1;
53b50314 600 break;
edd153a3
LP		 601 case V4L2_COLORSPACE_JPEG:
602 tmp |= LDDFR_CF0;
53b50314
DHG		 603 break;
604 }
417d4827 605 }
7caa4342 606
9a217e34
LP		 607 lcdc_write_chan(ch, LDDFR, tmp);
608 lcdc_write_chan(ch, LDMLSR, ch->pitch);
609 lcdc_write_chan(ch, LDSA1R, ch->base_addr_y);
edd153a3 610 if (sh_mobile_format_is_yuv(&ch->info->var))
9a217e34 611 lcdc_write_chan(ch, LDSA2R, ch->base_addr_c);
7caa4342 612
9a217e34
LP		 613 /* When using deferred I/O mode, configure the LCDC for one-shot
614 * operation and enable the frame end interrupt. Otherwise use
615 * continuous read mode.
616 */
617 if (ch->ldmt1r_value & LDMT1R_IFM &&
618 ch->cfg.sys_bus_cfg.deferred_io_msec) {
619 lcdc_write_chan(ch, LDSM1R, LDSM1R_OS);
620 lcdc_write(priv, _LDINTR, LDINTR_FE);
621 } else {
622 lcdc_write_chan(ch, LDSM1R, 0);
623 }
624 }
7caa4342 625
9a217e34 626 /* Word and long word swap. */
edd153a3
LP		 627 switch (sh_mobile_format_fourcc(&priv->ch[0].info->var)) {
628 case V4L2_PIX_FMT_RGB565:
629 case V4L2_PIX_FMT_NV21:
630 case V4L2_PIX_FMT_NV61:
631 case V4L2_PIX_FMT_NV42:
632 tmp = LDDDSR_LS | LDDDSR_WS;
633 break;
634 case V4L2_PIX_FMT_BGR24:
635 case V4L2_PIX_FMT_NV12:
636 case V4L2_PIX_FMT_NV16:
637 case V4L2_PIX_FMT_NV24:
9a217e34 638 tmp = LDDDSR_LS | LDDDSR_WS | LDDDSR_BS;
edd153a3
LP		 639 break;
640 case V4L2_PIX_FMT_BGR32:
641 default:
642 tmp = LDDDSR_LS;
643 break;
9a217e34
LP		 644 }
645 lcdc_write(priv, _LDDDSR, tmp);
7caa4342 646
9a217e34
LP		 647 /* Enable the display output. */
648 lcdc_write(priv, _LDCNT1R, LDCNT1R_DE);
649 sh_mobile_lcdc_start_stop(priv, 1);
650 priv->started = 1;
651}
cfb4f5d1 652
9a217e34
LP		 653static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
654{
655 struct sh_mobile_meram_info *mdev = priv->meram_dev;
656 struct sh_mobile_lcdc_board_cfg *board_cfg;
657 struct sh_mobile_lcdc_chan *ch;
658 unsigned long tmp;
659 int ret;
660 int k;
cfb4f5d1 661
9a217e34
LP		 662 /* enable clocks before accessing the hardware */
663 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
664 if (priv->ch[k].enabled)
665 sh_mobile_lcdc_clk_on(priv);
666 }
8564557a 667
9a217e34
LP		 668 /* reset */
669 lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LDCNT2R_BR);
670 lcdc_wait_bit(priv, _LDCNT2R, LDCNT2R_BR, 0);
8564557a 671
9a217e34
LP		 672 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
673 ch = &priv->ch[k];
8564557a 674
9a217e34
LP		 675 if (!ch->enabled)
676 continue;
677
678 board_cfg = &ch->cfg.board_cfg;
679 if (board_cfg->setup_sys) {
680 ret = board_cfg->setup_sys(board_cfg->board_data, ch,
681 &sh_mobile_lcdc_sys_bus_ops);
682 if (ret)
683 return ret;
8564557a 684 }
cfb4f5d1
MD		 685 }
686
9a217e34
LP		 687 /* Compute frame buffer base address and pitch for each channel. */
688 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
689 struct sh_mobile_meram_cfg *cfg;
690 int pixelformat;
cfb4f5d1 691
9a217e34
LP		 692 ch = &priv->ch[k];
693 if (!ch->enabled)
694 continue;
cfb4f5d1 695
9a217e34
LP		 696 ch->base_addr_y = ch->info->fix.smem_start;
697 ch->base_addr_c = ch->base_addr_y
698 + ch->info->var.xres
699 * ch->info->var.yres_virtual;
700 ch->pitch = ch->info->fix.line_length;
701
702 /* Enable MERAM if possible. */
703 cfg = ch->cfg.meram_cfg;
704 if (mdev == NULL || mdev->ops == NULL || cfg == NULL)
705 continue;
706
707 /* we need to de-init configured ICBs before we can
708 * re-initialize them.
709 */
710 if (ch->meram_enabled) {
711 mdev->ops->meram_unregister(mdev, cfg);
712 ch->meram_enabled = 0;
713 }
714
edd153a3
LP		 715 switch (sh_mobile_format_fourcc(&ch->info->var)) {
716 case V4L2_PIX_FMT_NV12:
717 case V4L2_PIX_FMT_NV21:
718 case V4L2_PIX_FMT_NV16:
719 case V4L2_PIX_FMT_NV61:
9a217e34 720 pixelformat = SH_MOBILE_MERAM_PF_NV;
edd153a3
LP		 721 break;
722 case V4L2_PIX_FMT_NV24:
723 case V4L2_PIX_FMT_NV42:
724 pixelformat = SH_MOBILE_MERAM_PF_NV24;
725 break;
726 case V4L2_PIX_FMT_RGB565:
727 case V4L2_PIX_FMT_BGR24:
728 case V4L2_PIX_FMT_BGR32:
729 default:
730 pixelformat = SH_MOBILE_MERAM_PF_RGB;
731 break;
732 }
9a217e34
LP		 733
734 ret = mdev->ops->meram_register(mdev, cfg, ch->pitch,
735 ch->info->var.yres, pixelformat,
736 ch->base_addr_y, ch->base_addr_c,
737 &ch->base_addr_y, &ch->base_addr_c,
738 &ch->pitch);
739 if (!ret)
740 ch->meram_enabled = 1;
741 }
742
743 /* Start the LCDC. */
744 __sh_mobile_lcdc_start(priv);
745
746 /* Setup deferred I/O, tell the board code to enable the panels, and
747 * turn backlight on.
748 */
cfb4f5d1
MD		 749 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
750 ch = &priv->ch[k];
21bc1f02
MD		 751 if (!ch->enabled)
752 continue;
753
9a217e34
LP		 754 tmp = ch->cfg.sys_bus_cfg.deferred_io_msec;
755 if (ch->ldmt1r_value & LDMT1R_IFM && tmp) {
756 ch->defio.deferred_io = sh_mobile_lcdc_deferred_io;
757 ch->defio.delay = msecs_to_jiffies(tmp);
758 ch->info->fbdefio = &ch->defio;
759 fb_deferred_io_init(ch->info);
760 }
761
cfb4f5d1 762 board_cfg = &ch->cfg.board_cfg;
247f9938 763 if (board_cfg->display_on && try_module_get(board_cfg->owner)) {
c2439398 764 board_cfg->display_on(board_cfg->board_data, ch->info);
6de9edd5
GL		 765 module_put(board_cfg->owner);
766 }
3b0fd9d7
AC		 767
768 if (ch->bl) {
769 ch->bl->props.power = FB_BLANK_UNBLANK;
770 backlight_update_status(ch->bl);
771 }
cfb4f5d1
MD		 772 }
773
774 return 0;
775}
776
777static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
778{
779 struct sh_mobile_lcdc_chan *ch;
780 struct sh_mobile_lcdc_board_cfg *board_cfg;
781 int k;
782
2feb075a 783 /* clean up deferred io and ask board code to disable panel */
cfb4f5d1
MD		 784 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
785 ch = &priv->ch[k];
21bc1f02
MD		 786 if (!ch->enabled)
787 continue;
8564557a 788
2feb075a
MD		 789 /* deferred io mode:
790 * flush frame, and wait for frame end interrupt
791 * clean up deferred io and enable clock
792 */
5ef6b505 793 if (ch->info && ch->info->fbdefio) {
2feb075a 794 ch->frame_end = 0;
e33afddc 795 schedule_delayed_work(&ch->info->deferred_work, 0);
2feb075a 796 wait_event(ch->frame_end_wait, ch->frame_end);
e33afddc
PM		 797 fb_deferred_io_cleanup(ch->info);
798 ch->info->fbdefio = NULL;
2feb075a 799 sh_mobile_lcdc_clk_on(priv);
8564557a 800 }
2feb075a 801
3b0fd9d7
AC		 802 if (ch->bl) {
803 ch->bl->props.power = FB_BLANK_POWERDOWN;
804 backlight_update_status(ch->bl);
805 }
806
2feb075a 807 board_cfg = &ch->cfg.board_cfg;
247f9938 808 if (board_cfg->display_off && try_module_get(board_cfg->owner)) {
2feb075a 809 board_cfg->display_off(board_cfg->board_data);
6de9edd5
GL		 810 module_put(board_cfg->owner);
811 }
7caa4342
D		 812
813 /* disable the meram */
814 if (ch->meram_enabled) {
815 struct sh_mobile_meram_cfg *cfg;
816 struct sh_mobile_meram_info *mdev;
817 cfg = ch->cfg.meram_cfg;
818 mdev = priv->meram_dev;
819 mdev->ops->meram_unregister(mdev, cfg);
820 ch->meram_enabled = 0;
821 }
822
cfb4f5d1
MD		 823 }
824
825 /* stop the lcdc */
8e9bb19e
MD		 826 if (priv->started) {
827 sh_mobile_lcdc_start_stop(priv, 0);
828 priv->started = 0;
829 }
b51339ff 830
8564557a
MD		 831 /* stop clocks */
832 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
833 if (priv->ch[k].enabled)
834 sh_mobile_lcdc_clk_off(priv);
cfb4f5d1
MD		 835}
836
f1f60b5f
LP		 837/* -----------------------------------------------------------------------------
838 * Frame buffer operations
839 */
cfb4f5d1
MD		 840
841static int sh_mobile_lcdc_setcolreg(u_int regno,
842 u_int red, u_int green, u_int blue,
843 u_int transp, struct fb_info *info)
844{
845 u32 *palette = info->pseudo_palette;
846
847 if (regno >= PALETTE_NR)
848 return -EINVAL;
849
850 /* only FB_VISUAL_TRUECOLOR supported */
851
852 red >>= 16 - info->var.red.length;
853 green >>= 16 - info->var.green.length;
854 blue >>= 16 - info->var.blue.length;
855 transp >>= 16 - info->var.transp.length;
856
857 palette[regno] = (red << info->var.red.offset) |
858 (green << info->var.green.offset) |
859 (blue << info->var.blue.offset) |
860 (transp << info->var.transp.offset);
861
862 return 0;
863}
864
865static struct fb_fix_screeninfo sh_mobile_lcdc_fix = {
866 .id = "SH Mobile LCDC",
867 .type = FB_TYPE_PACKED_PIXELS,
868 .visual = FB_VISUAL_TRUECOLOR,
869 .accel = FB_ACCEL_NONE,
9dd38819
PE		 870 .xpanstep = 0,
871 .ypanstep = 1,
872 .ywrapstep = 0,
edd153a3 873 .capabilities = FB_CAP_FOURCC,
cfb4f5d1
MD		 874};
875
8564557a
MD		 876static void sh_mobile_lcdc_fillrect(struct fb_info *info,
877 const struct fb_fillrect *rect)
878{
879 sys_fillrect(info, rect);
880 sh_mobile_lcdc_deferred_io_touch(info);
881}
882
883static void sh_mobile_lcdc_copyarea(struct fb_info *info,
884 const struct fb_copyarea *area)
885{
886 sys_copyarea(info, area);
887 sh_mobile_lcdc_deferred_io_touch(info);
888}
889
890static void sh_mobile_lcdc_imageblit(struct fb_info *info,
891 const struct fb_image *image)
892{
893 sys_imageblit(info, image);
894 sh_mobile_lcdc_deferred_io_touch(info);
895}
896
9dd38819
PE		 897static int sh_mobile_fb_pan_display(struct fb_var_screeninfo *var,
898 struct fb_info *info)
899{
900 struct sh_mobile_lcdc_chan *ch = info->par;
92e1f9a7
PE		 901 struct sh_mobile_lcdc_priv *priv = ch->lcdc;
902 unsigned long ldrcntr;
903 unsigned long new_pan_offset;
53b50314
DHG		 904 unsigned long base_addr_y, base_addr_c;
905 unsigned long c_offset;
edd153a3 906 bool yuv = sh_mobile_format_is_yuv(&info->var);
92e1f9a7 907
edd153a3 908 if (!yuv)
dc1d5ada
LP		 909 new_pan_offset = var->yoffset * info->fix.line_length
910 + var->xoffset * (info->var.bits_per_pixel / 8);
53b50314 911 else
dc1d5ada
LP		 912 new_pan_offset = var->yoffset * info->fix.line_length
913 + var->xoffset;
9dd38819 914
92e1f9a7 915 if (new_pan_offset == ch->pan_offset)
9dd38819
PE		 916 return 0; /* No change, do nothing */
917
92e1f9a7 918 ldrcntr = lcdc_read(priv, _LDRCNTR);
9dd38819 919
92e1f9a7 920 /* Set the source address for the next refresh */
53b50314 921 base_addr_y = ch->dma_handle + new_pan_offset;
edd153a3 922 if (yuv) {
53b50314 923 /* Set y offset */
dc1d5ada
LP		 924 c_offset = var->yoffset * info->fix.line_length
925 * (info->var.bits_per_pixel - 8) / 8;
926 base_addr_c = ch->dma_handle
927 + info->var.xres * info->var.yres_virtual
928 + c_offset;
53b50314 929 /* Set x offset */
edd153a3 930 if (sh_mobile_format_fourcc(&info->var) == V4L2_PIX_FMT_NV24)
53b50314
DHG		 931 base_addr_c += 2 * var->xoffset;
932 else
933 base_addr_c += var->xoffset;
49d79ba2 934 }
53b50314 935
49d79ba2 936 if (ch->meram_enabled) {
7caa4342
D		 937 struct sh_mobile_meram_cfg *cfg;
938 struct sh_mobile_meram_info *mdev;
7caa4342
D		 939 int ret;
940
941 cfg = ch->cfg.meram_cfg;
942 mdev = priv->meram_dev;
943 ret = mdev->ops->meram_update(mdev, cfg,
944 base_addr_y, base_addr_c,
49d79ba2 945 &base_addr_y, &base_addr_c);
7caa4342
D		 946 if (ret)
947 return ret;
49d79ba2 948 }
7caa4342 949
49d79ba2
LP		 950 ch->base_addr_y = base_addr_y;
951 ch->base_addr_c = base_addr_c;
7caa4342 952
49d79ba2 953 lcdc_write_chan_mirror(ch, LDSA1R, base_addr_y);
edd153a3 954 if (yuv)
49d79ba2 955 lcdc_write_chan_mirror(ch, LDSA2R, base_addr_c);
53b50314 956
92e1f9a7
PE		 957 if (lcdc_chan_is_sublcd(ch))
958 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_SRS);
959 else
960 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_MRS);
961
962 ch->pan_offset = new_pan_offset;
963
964 sh_mobile_lcdc_deferred_io_touch(info);
9dd38819
PE		 965
966 return 0;
967}
968
40331b21
PE		 969static int sh_mobile_wait_for_vsync(struct fb_info *info)
970{
971 struct sh_mobile_lcdc_chan *ch = info->par;
972 unsigned long ldintr;
973 int ret;
974
dc48665f
LP		 975 /* Enable VSync End interrupt and be careful not to acknowledge any
976 * pending interrupt.
977 */
40331b21 978 ldintr = lcdc_read(ch->lcdc, _LDINTR);
dc48665f 979 ldintr |= LDINTR_VEE | LDINTR_STATUS_MASK;
40331b21
PE		 980 lcdc_write(ch->lcdc, _LDINTR, ldintr);
981
982 ret = wait_for_completion_interruptible_timeout(&ch->vsync_completion,
983 msecs_to_jiffies(100));
984 if (!ret)
985 return -ETIMEDOUT;
986
987 return 0;
988}
989
990static int sh_mobile_ioctl(struct fb_info *info, unsigned int cmd,
991 unsigned long arg)
992{
993 int retval;
994
995 switch (cmd) {
996 case FBIO_WAITFORVSYNC:
997 retval = sh_mobile_wait_for_vsync(info);
998 break;
999
1000 default:
1001 retval = -ENOIOCTLCMD;
1002 break;
1003 }
1004 return retval;
1005}
1006
dd210503
GL		 1007static void sh_mobile_fb_reconfig(struct fb_info *info)
1008{
1009 struct sh_mobile_lcdc_chan *ch = info->par;
1010 struct fb_videomode mode1, mode2;
1011 struct fb_event event;
1012 int evnt = FB_EVENT_MODE_CHANGE_ALL;
1013
1014 if (ch->use_count > 1 || (ch->use_count == 1 && !info->fbcon_par))
1015 /* More framebuffer users are active */
1016 return;
1017
1018 fb_var_to_videomode(&mode1, &ch->display_var);
1019 fb_var_to_videomode(&mode2, &info->var);
1020
1021 if (fb_mode_is_equal(&mode1, &mode2))
1022 return;
1023
1024 /* Display has been re-plugged, framebuffer is free now, reconfigure */
1025 if (fb_set_var(info, &ch->display_var) < 0)
1026 /* Couldn't reconfigure, hopefully, can continue as before */
1027 return;
1028
dd210503
GL		 1029 /*
1030 * fb_set_var() calls the notifier change internally, only if
1031 * FBINFO_MISC_USEREVENT flag is set. Since we do not want to fake a
1032 * user event, we have to call the chain ourselves.
1033 */
1034 event.info = info;
cc267ec5 1035 event.data = &mode1;
dd210503
GL		 1036 fb_notifier_call_chain(evnt, &event);
1037}
1038
1039/*
1040 * Locking: both .fb_release() and .fb_open() are called with info->lock held if
1041 * user == 1, or with console sem held, if user == 0.
1042 */
1043static int sh_mobile_release(struct fb_info *info, int user)
1044{
1045 struct sh_mobile_lcdc_chan *ch = info->par;
1046
1047 mutex_lock(&ch->open_lock);
1048 dev_dbg(info->dev, "%s(): %d users\n", __func__, ch->use_count);
1049
1050 ch->use_count--;
1051
1052 /* Nothing to reconfigure, when called from fbcon */
1053 if (user) {
ac751efa 1054 console_lock();
dd210503 1055 sh_mobile_fb_reconfig(info);
ac751efa 1056 console_unlock();
dd210503
GL		 1057 }
1058
1059 mutex_unlock(&ch->open_lock);
1060
1061 return 0;
1062}
1063
1064static int sh_mobile_open(struct fb_info *info, int user)
1065{
1066 struct sh_mobile_lcdc_chan *ch = info->par;
1067
1068 mutex_lock(&ch->open_lock);
1069 ch->use_count++;
1070
1071 dev_dbg(info->dev, "%s(): %d users\n", __func__, ch->use_count);
1072 mutex_unlock(&ch->open_lock);
1073
1074 return 0;
1075}
1076
1077static int sh_mobile_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1078{
1079 struct sh_mobile_lcdc_chan *ch = info->par;
417d4827 1080 struct sh_mobile_lcdc_priv *p = ch->lcdc;
03862194
LP		 1081 unsigned int best_dist = (unsigned int)-1;
1082 unsigned int best_xres = 0;
1083 unsigned int best_yres = 0;
1084 unsigned int i;
dd210503 1085
03862194 1086 if (var->xres > MAX_XRES || var->yres > MAX_YRES)
dd210503 1087 return -EINVAL;
03862194
LP		 1088
1089 /* If board code provides us with a list of available modes, make sure
1090 * we use one of them. Find the mode closest to the requested one. The
1091 * distance between two modes is defined as the size of the
1092 * non-overlapping parts of the two rectangles.
1093 */
1094 for (i = 0; i < ch->cfg.num_cfg; ++i) {
1095 const struct fb_videomode *mode = &ch->cfg.lcd_cfg[i];
1096 unsigned int dist;
1097
1098 /* We can only round up. */
1099 if (var->xres > mode->xres || var->yres > mode->yres)
1100 continue;
1101
1102 dist = var->xres * var->yres + mode->xres * mode->yres
1103 - 2 * min(var->xres, mode->xres)
1104 * min(var->yres, mode->yres);
1105
1106 if (dist < best_dist) {
1107 best_xres = mode->xres;
1108 best_yres = mode->yres;
1109 best_dist = dist;
1110 }
dd210503 1111 }
417d4827 1112
03862194
LP		 1113 /* If no available mode can be used, return an error. */
1114 if (ch->cfg.num_cfg != 0) {
1115 if (best_dist == (unsigned int)-1)
1116 return -EINVAL;
1117
1118 var->xres = best_xres;
1119 var->yres = best_yres;
1120 }
1121
1122 /* Make sure the virtual resolution is at least as big as the visible
1123 * resolution.
1124 */
1125 if (var->xres_virtual < var->xres)
1126 var->xres_virtual = var->xres;
1127 if (var->yres_virtual < var->yres)
1128 var->yres_virtual = var->yres;
1129
edd153a3
LP		 1130 if (sh_mobile_format_is_fourcc(var)) {
1131 switch (var->grayscale) {
1132 case V4L2_PIX_FMT_NV12:
1133 case V4L2_PIX_FMT_NV21:
1134 var->bits_per_pixel = 12;
1135 break;
1136 case V4L2_PIX_FMT_RGB565:
1137 case V4L2_PIX_FMT_NV16:
1138 case V4L2_PIX_FMT_NV61:
1139 var->bits_per_pixel = 16;
1140 break;
1141 case V4L2_PIX_FMT_BGR24:
1142 case V4L2_PIX_FMT_NV24:
1143 case V4L2_PIX_FMT_NV42:
1144 var->bits_per_pixel = 24;
1145 break;
1146 case V4L2_PIX_FMT_BGR32:
1147 var->bits_per_pixel = 32;
1148 break;
1149 default:
1150 return -EINVAL;
1151 }
1152
1153 /* Default to RGB and JPEG color-spaces for RGB and YUV formats
1154 * respectively.
1155 */
1156 if (!sh_mobile_format_is_yuv(var))
1157 var->colorspace = V4L2_COLORSPACE_SRGB;
1158 else if (var->colorspace != V4L2_COLORSPACE_REC709)
1159 var->colorspace = V4L2_COLORSPACE_JPEG;
1160 } else {
1161 if (var->bits_per_pixel <= 16) { /* RGB 565 */
1162 var->bits_per_pixel = 16;
1163 var->red.offset = 11;
1164 var->red.length = 5;
1165 var->green.offset = 5;
1166 var->green.length = 6;
1167 var->blue.offset = 0;
1168 var->blue.length = 5;
1169 var->transp.offset = 0;
1170 var->transp.length = 0;
1171 } else if (var->bits_per_pixel <= 24) { /* RGB 888 */
1172 var->bits_per_pixel = 24;
1173 var->red.offset = 16;
1174 var->red.length = 8;
1175 var->green.offset = 8;
1176 var->green.length = 8;
1177 var->blue.offset = 0;
1178 var->blue.length = 8;
1179 var->transp.offset = 0;
1180 var->transp.length = 0;
1181 } else if (var->bits_per_pixel <= 32) { /* RGBA 888 */
1182 var->bits_per_pixel = 32;
1183 var->red.offset = 16;
1184 var->red.length = 8;
1185 var->green.offset = 8;
1186 var->green.length = 8;
1187 var->blue.offset = 0;
1188 var->blue.length = 8;
1189 var->transp.offset = 24;
1190 var->transp.length = 8;
1191 } else
1192 return -EINVAL;
417d4827 1193
edd153a3
LP		 1194 var->red.msb_right = 0;
1195 var->green.msb_right = 0;
1196 var->blue.msb_right = 0;
1197 var->transp.msb_right = 0;
1198 }
03862194
LP		 1199
1200 /* Make sure we don't exceed our allocated memory. */
1201 if (var->xres_virtual * var->yres_virtual * var->bits_per_pixel / 8 >
1202 info->fix.smem_len)
1203 return -EINVAL;
1204
edd153a3
LP		 1205 /* only accept the forced_fourcc for dual channel configurations */
1206 if (p->forced_fourcc &&
1207 p->forced_fourcc != sh_mobile_format_fourcc(var))
417d4827 1208 return -EINVAL;
417d4827 1209
dd210503
GL		 1210 return 0;
1211}
40331b21 1212
ed5bebf2
LP		 1213static int sh_mobile_set_par(struct fb_info *info)
1214{
1215 struct sh_mobile_lcdc_chan *ch = info->par;
91fba48d 1216 u32 line_length = info->fix.line_length;
ed5bebf2
LP		 1217 int ret;
1218
1219 sh_mobile_lcdc_stop(ch->lcdc);
91fba48d 1220
edd153a3 1221 if (sh_mobile_format_is_yuv(&info->var))
91fba48d
LP		 1222 info->fix.line_length = info->var.xres;
1223 else
1224 info->fix.line_length = info->var.xres
1225 * info->var.bits_per_pixel / 8;
1226
ed5bebf2 1227 ret = sh_mobile_lcdc_start(ch->lcdc);
91fba48d 1228 if (ret < 0) {
ed5bebf2 1229 dev_err(info->dev, "%s: unable to restart LCDC\n", __func__);
91fba48d
LP		 1230 info->fix.line_length = line_length;
1231 }
ed5bebf2 1232
edd153a3
LP		 1233 if (sh_mobile_format_is_fourcc(&info->var)) {
1234 info->fix.type = FB_TYPE_FOURCC;
1235 info->fix.visual = FB_VISUAL_FOURCC;
1236 } else {
1237 info->fix.type = FB_TYPE_PACKED_PIXELS;
1238 info->fix.visual = FB_VISUAL_TRUECOLOR;
1239 }
1240
ed5bebf2
LP		 1241 return ret;
1242}
1243
8857b9aa
AC		 1244/*
1245 * Screen blanking. Behavior is as follows:
1246 * FB_BLANK_UNBLANK: screen unblanked, clocks enabled
1247 * FB_BLANK_NORMAL: screen blanked, clocks enabled
1248 * FB_BLANK_VSYNC,
1249 * FB_BLANK_HSYNC,
1250 * FB_BLANK_POWEROFF: screen blanked, clocks disabled
1251 */
1252static int sh_mobile_lcdc_blank(int blank, struct fb_info *info)
1253{
1254 struct sh_mobile_lcdc_chan *ch = info->par;
1255 struct sh_mobile_lcdc_priv *p = ch->lcdc;
1256
1257 /* blank the screen? */
1258 if (blank > FB_BLANK_UNBLANK && ch->blank_status == FB_BLANK_UNBLANK) {
1259 struct fb_fillrect rect = {
1260 .width = info->var.xres,
1261 .height = info->var.yres,
1262 };
1263 sh_mobile_lcdc_fillrect(info, &rect);
1264 }
1265 /* turn clocks on? */
1266 if (blank <= FB_BLANK_NORMAL && ch->blank_status > FB_BLANK_NORMAL) {
1267 sh_mobile_lcdc_clk_on(p);
1268 }
1269 /* turn clocks off? */
1270 if (blank > FB_BLANK_NORMAL && ch->blank_status <= FB_BLANK_NORMAL) {
1271 /* make sure the screen is updated with the black fill before
1272 * switching the clocks off. one vsync is not enough since
1273 * blanking may occur in the middle of a refresh. deferred io
1274 * mode will reenable the clocks and update the screen in time,
1275 * so it does not need this. */
1276 if (!info->fbdefio) {
1277 sh_mobile_wait_for_vsync(info);
1278 sh_mobile_wait_for_vsync(info);
1279 }
1280 sh_mobile_lcdc_clk_off(p);
1281 }
1282
1283 ch->blank_status = blank;
1284 return 0;
1285}
1286
cfb4f5d1 1287static struct fb_ops sh_mobile_lcdc_ops = {
9dd38819 1288 .owner = THIS_MODULE,
cfb4f5d1 1289 .fb_setcolreg = sh_mobile_lcdc_setcolreg,
2540c111
MD		 1290 .fb_read = fb_sys_read,
1291 .fb_write = fb_sys_write,
8564557a
MD		 1292 .fb_fillrect = sh_mobile_lcdc_fillrect,
1293 .fb_copyarea = sh_mobile_lcdc_copyarea,
1294 .fb_imageblit = sh_mobile_lcdc_imageblit,
8857b9aa 1295 .fb_blank = sh_mobile_lcdc_blank,
9dd38819 1296 .fb_pan_display = sh_mobile_fb_pan_display,
40331b21 1297 .fb_ioctl = sh_mobile_ioctl,
dd210503
GL		 1298 .fb_open = sh_mobile_open,
1299 .fb_release = sh_mobile_release,
1300 .fb_check_var = sh_mobile_check_var,
ed5bebf2 1301 .fb_set_par = sh_mobile_set_par,
cfb4f5d1
MD		 1302};
1303
f1f60b5f
LP		 1304/* -----------------------------------------------------------------------------
1305 * Backlight
1306 */
1307
3b0fd9d7
AC		 1308static int sh_mobile_lcdc_update_bl(struct backlight_device *bdev)
1309{
1310 struct sh_mobile_lcdc_chan *ch = bl_get_data(bdev);
1311 struct sh_mobile_lcdc_board_cfg *cfg = &ch->cfg.board_cfg;
1312 int brightness = bdev->props.brightness;
1313
1314 if (bdev->props.power != FB_BLANK_UNBLANK ||
1315 bdev->props.state & (BL_CORE_SUSPENDED | BL_CORE_FBBLANK))
1316 brightness = 0;
1317
1318 return cfg->set_brightness(cfg->board_data, brightness);
1319}
1320
1321static int sh_mobile_lcdc_get_brightness(struct backlight_device *bdev)
1322{
1323 struct sh_mobile_lcdc_chan *ch = bl_get_data(bdev);
1324 struct sh_mobile_lcdc_board_cfg *cfg = &ch->cfg.board_cfg;
1325
1326 return cfg->get_brightness(cfg->board_data);
1327}
1328
1329static int sh_mobile_lcdc_check_fb(struct backlight_device *bdev,
1330 struct fb_info *info)
1331{
1332 return (info->bl_dev == bdev);
1333}
1334
1335static struct backlight_ops sh_mobile_lcdc_bl_ops = {
1336 .options = BL_CORE_SUSPENDRESUME,
1337 .update_status = sh_mobile_lcdc_update_bl,
1338 .get_brightness = sh_mobile_lcdc_get_brightness,
1339 .check_fb = sh_mobile_lcdc_check_fb,
1340};
1341
1342static struct backlight_device *sh_mobile_lcdc_bl_probe(struct device *parent,
1343 struct sh_mobile_lcdc_chan *ch)
1344{
1345 struct backlight_device *bl;
1346
1347 bl = backlight_device_register(ch->cfg.bl_info.name, parent, ch,
1348 &sh_mobile_lcdc_bl_ops, NULL);
beee1f20
DC		 1349 if (IS_ERR(bl)) {
1350 dev_err(parent, "unable to register backlight device: %ld\n",
1351 PTR_ERR(bl));
3b0fd9d7
AC		 1352 return NULL;
1353 }
1354
1355 bl->props.max_brightness = ch->cfg.bl_info.max_brightness;
1356 bl->props.brightness = bl->props.max_brightness;
1357 backlight_update_status(bl);
1358
1359 return bl;
1360}
1361
1362static void sh_mobile_lcdc_bl_remove(struct backlight_device *bdev)
1363{
1364 backlight_device_unregister(bdev);
1365}
1366
f1f60b5f
LP		 1367/* -----------------------------------------------------------------------------
1368 * Power management
1369 */
1370
2feb075a
MD		 1371static int sh_mobile_lcdc_suspend(struct device *dev)
1372{
1373 struct platform_device *pdev = to_platform_device(dev);
1374
1375 sh_mobile_lcdc_stop(platform_get_drvdata(pdev));
1376 return 0;
1377}
1378
1379static int sh_mobile_lcdc_resume(struct device *dev)
1380{
1381 struct platform_device *pdev = to_platform_device(dev);
1382
1383 return sh_mobile_lcdc_start(platform_get_drvdata(pdev));
1384}
1385
0246c471
MD		 1386static int sh_mobile_lcdc_runtime_suspend(struct device *dev)
1387{
1388 struct platform_device *pdev = to_platform_device(dev);
2427bb24 1389 struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
0246c471
MD		 1390
1391 /* turn off LCDC hardware */
2427bb24
LP		 1392 lcdc_write(priv, _LDCNT1R, 0);
1393
0246c471
MD		 1394 return 0;
1395}
1396
1397static int sh_mobile_lcdc_runtime_resume(struct device *dev)
1398{
1399 struct platform_device *pdev = to_platform_device(dev);
2427bb24 1400 struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
0246c471 1401
2427bb24 1402 __sh_mobile_lcdc_start(priv);
0246c471
MD		 1403
1404 return 0;
1405}
1406
47145210 1407static const struct dev_pm_ops sh_mobile_lcdc_dev_pm_ops = {
2feb075a
MD		 1408 .suspend = sh_mobile_lcdc_suspend,
1409 .resume = sh_mobile_lcdc_resume,
0246c471
MD		 1410 .runtime_suspend = sh_mobile_lcdc_runtime_suspend,
1411 .runtime_resume = sh_mobile_lcdc_runtime_resume,
2feb075a
MD		 1412};
1413
f1f60b5f
LP		 1414/* -----------------------------------------------------------------------------
1415 * Framebuffer notifier
1416 */
1417
6de9edd5 1418/* locking: called with info->lock held */
6011bdea
GL		 1419static int sh_mobile_lcdc_notify(struct notifier_block *nb,
1420 unsigned long action, void *data)
1421{
1422 struct fb_event *event = data;
1423 struct fb_info *info = event->info;
1424 struct sh_mobile_lcdc_chan *ch = info->par;
1425 struct sh_mobile_lcdc_board_cfg *board_cfg = &ch->cfg.board_cfg;
6011bdea
GL		 1426
1427 if (&ch->lcdc->notifier != nb)
baf16374 1428 return NOTIFY_DONE;
6011bdea
GL		 1429
1430 dev_dbg(info->dev, "%s(): action = %lu, data = %p\n",
1431 __func__, action, event->data);
1432
1433 switch(action) {
1434 case FB_EVENT_SUSPEND:
247f9938 1435 if (board_cfg->display_off && try_module_get(board_cfg->owner)) {
6011bdea 1436 board_cfg->display_off(board_cfg->board_data);
6de9edd5
GL		 1437 module_put(board_cfg->owner);
1438 }
afe417c0 1439 sh_mobile_lcdc_stop(ch->lcdc);
6011bdea
GL		 1440 break;
1441 case FB_EVENT_RESUME:
dd210503
GL		 1442 mutex_lock(&ch->open_lock);
1443 sh_mobile_fb_reconfig(info);
1444 mutex_unlock(&ch->open_lock);
6011bdea
GL		 1445
1446 /* HDMI must be enabled before LCDC configuration */
247f9938 1447 if (board_cfg->display_on && try_module_get(board_cfg->owner)) {
dd210503 1448 board_cfg->display_on(board_cfg->board_data, info);
6de9edd5 1449 module_put(board_cfg->owner);
6011bdea
GL		 1450 }
1451
ebe5e12d 1452 sh_mobile_lcdc_start(ch->lcdc);
6011bdea
GL		 1453 }
1454
baf16374 1455 return NOTIFY_OK;
6011bdea
GL		 1456}
1457
f1f60b5f
LP		 1458/* -----------------------------------------------------------------------------
1459 * Probe/remove and driver init/exit
1460 */
1461
1462static const struct fb_videomode default_720p = {
1463 .name = "HDMI 720p",
1464 .xres = 1280,
1465 .yres = 720,
1466
1467 .left_margin = 220,
1468 .right_margin = 110,
1469 .hsync_len = 40,
1470
1471 .upper_margin = 20,
1472 .lower_margin = 5,
1473 .vsync_len = 5,
1474
1475 .pixclock = 13468,
1476 .refresh = 60,
1477 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
1478};
1479
b4bee692
LP		 1480static int sh_mobile_lcdc_remove(struct platform_device *pdev)
1481{
1482 struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
1483 struct fb_info *info;
1484 int i;
1485
1486 fb_unregister_client(&priv->notifier);
1487
1488 for (i = 0; i < ARRAY_SIZE(priv->ch); i++)
1489 if (priv->ch[i].info && priv->ch[i].info->dev)
1490 unregister_framebuffer(priv->ch[i].info);
1491
1492 sh_mobile_lcdc_stop(priv);
1493
1494 for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
1495 info = priv->ch[i].info;
1496
1497 if (!info || !info->device)
1498 continue;
1499
1500 if (priv->ch[i].sglist)
1501 vfree(priv->ch[i].sglist);
1502
1503 if (info->screen_base)
1504 dma_free_coherent(&pdev->dev, info->fix.smem_len,
1505 info->screen_base,
1506 priv->ch[i].dma_handle);
1507 fb_dealloc_cmap(&info->cmap);
1508 framebuffer_release(info);
1509 }
1510
1511 for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
1512 if (priv->ch[i].bl)
1513 sh_mobile_lcdc_bl_remove(priv->ch[i].bl);
1514 }
1515
1516 if (priv->dot_clk)
1517 clk_put(priv->dot_clk);
1518
1519 if (priv->dev)
1520 pm_runtime_disable(priv->dev);
1521
1522 if (priv->base)
1523 iounmap(priv->base);
1524
1525 if (priv->irq)
1526 free_irq(priv->irq, priv);
1527 kfree(priv);
1528 return 0;
1529}
cfb4f5d1 1530
f1f60b5f
LP		 1531static int sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan *ch)
1532{
1533 int interface_type = ch->cfg.interface_type;
1534
1535 switch (interface_type) {
1536 case RGB8:
1537 case RGB9:
1538 case RGB12A:
1539 case RGB12B:
1540 case RGB16:
1541 case RGB18:
1542 case RGB24:
1543 case SYS8A:
1544 case SYS8B:
1545 case SYS8C:
1546 case SYS8D:
1547 case SYS9:
1548 case SYS12:
1549 case SYS16A:
1550 case SYS16B:
1551 case SYS16C:
1552 case SYS18:
1553 case SYS24:
1554 break;
1555 default:
1556 return -EINVAL;
1557 }
1558
1559 /* SUBLCD only supports SYS interface */
1560 if (lcdc_chan_is_sublcd(ch)) {
1561 if (!(interface_type & LDMT1R_IFM))
1562 return -EINVAL;
1563
1564 interface_type &= ~LDMT1R_IFM;
1565 }
1566
1567 ch->ldmt1r_value = interface_type;
1568 return 0;
1569}
1570
3ce05599
LP		 1571static int __devinit sh_mobile_lcdc_channel_init(struct sh_mobile_lcdc_chan *ch,
1572 struct device *dev)
cfb4f5d1 1573{
3ce05599
LP		 1574 struct sh_mobile_lcdc_chan_cfg *cfg = &ch->cfg;
1575 const struct fb_videomode *max_mode;
1576 const struct fb_videomode *mode;
1577 struct fb_var_screeninfo *var;
cfb4f5d1 1578 struct fb_info *info;
3ce05599
LP		 1579 unsigned int max_size;
1580 int num_cfg;
1581 void *buf;
1582 int ret;
1583 int i;
1584
a67472ad
LP		 1585 mutex_init(&ch->open_lock);
1586
1587 /* Allocate the frame buffer device. */
3ce05599
LP		 1588 ch->info = framebuffer_alloc(0, dev);
1589 if (!ch->info) {
1590 dev_err(dev, "unable to allocate fb_info\n");
1591 return -ENOMEM;
1592 }
1593
1594 info = ch->info;
3ce05599
LP		 1595 info->fbops = &sh_mobile_lcdc_ops;
1596 info->par = ch;
a67472ad
LP		 1597 info->pseudo_palette = &ch->pseudo_palette;
1598 info->flags = FBINFO_FLAG_DEFAULT;
3ce05599
LP		 1599
1600 /* Iterate through the modes to validate them and find the highest
1601 * resolution.
1602 */
1603 max_mode = NULL;
1604 max_size = 0;
1605
1606 for (i = 0, mode = cfg->lcd_cfg; i < cfg->num_cfg; i++, mode++) {
1607 unsigned int size = mode->yres * mode->xres;
1608
edd153a3
LP		 1609 /* NV12/NV21 buffers must have even number of lines */
1610 if ((cfg->fourcc == V4L2_PIX_FMT_NV12 ||
1611 cfg->fourcc == V4L2_PIX_FMT_NV21) && (mode->yres & 0x1)) {
3ce05599
LP		 1612 dev_err(dev, "yres must be multiple of 2 for YCbCr420 "
1613 "mode.\n");
1614 return -EINVAL;
1615 }
1616
1617 if (size > max_size) {
1618 max_mode = mode;
1619 max_size = size;
1620 }
1621 }
1622
1623 if (!max_size)
1624 max_size = MAX_XRES * MAX_YRES;
1625 else
1626 dev_dbg(dev, "Found largest videomode %ux%u\n",
1627 max_mode->xres, max_mode->yres);
1628
a67472ad 1629 /* Create the mode list. */
3ce05599
LP		 1630 if (cfg->lcd_cfg == NULL) {
1631 mode = &default_720p;
1632 num_cfg = 1;
1633 } else {
1634 mode = cfg->lcd_cfg;
1635 num_cfg = cfg->num_cfg;
1636 }
1637
1638 fb_videomode_to_modelist(mode, num_cfg, &info->modelist);
1639
a67472ad
LP		 1640 /* Initialize variable screen information using the first mode as
1641 * default. The default Y virtual resolution is twice the panel size to
1642 * allow for double-buffering.
1643 */
1644 var = &info->var;
3ce05599
LP		 1645 fb_videomode_to_var(var, mode);
1646 var->width = cfg->lcd_size_cfg.width;
1647 var->height = cfg->lcd_size_cfg.height;
3ce05599
LP		 1648 var->yres_virtual = var->yres * 2;
1649 var->activate = FB_ACTIVATE_NOW;
1650
edd153a3
LP		 1651 switch (cfg->fourcc) {
1652 case V4L2_PIX_FMT_RGB565:
1653 var->bits_per_pixel = 16;
1654 break;
1655 case V4L2_PIX_FMT_BGR24:
1656 var->bits_per_pixel = 24;
1657 break;
1658 case V4L2_PIX_FMT_BGR32:
1659 var->bits_per_pixel = 32;
1660 break;
1661 default:
1662 var->grayscale = cfg->fourcc;
1663 break;
1664 }
1665
1666 /* Make sure the memory size check won't fail. smem_len is initialized
1667 * later based on var.
1668 */
1669 info->fix.smem_len = UINT_MAX;
a67472ad 1670 ret = sh_mobile_check_var(var, info);
3ce05599
LP		 1671 if (ret)
1672 return ret;
1673
edd153a3
LP		 1674 max_size = max_size * var->bits_per_pixel / 8 * 2;
1675
a67472ad 1676 /* Allocate frame buffer memory and color map. */
edd153a3 1677 buf = dma_alloc_coherent(dev, max_size, &ch->dma_handle, GFP_KERNEL);
3ce05599
LP		 1678 if (!buf) {
1679 dev_err(dev, "unable to allocate buffer\n");
1680 return -ENOMEM;
1681 }
1682
3ce05599
LP		 1683 ret = fb_alloc_cmap(&info->cmap, PALETTE_NR, 0);
1684 if (ret < 0) {
1685 dev_err(dev, "unable to allocate cmap\n");
edd153a3 1686 dma_free_coherent(dev, max_size, buf, ch->dma_handle);
3ce05599
LP		 1687 return ret;
1688 }
1689
edd153a3
LP		 1690 /* Initialize fixed screen information. Restrict pan to 2 lines steps
1691 * for NV12 and NV21.
1692 */
1693 info->fix = sh_mobile_lcdc_fix;
3ce05599 1694 info->fix.smem_start = ch->dma_handle;
edd153a3
LP		 1695 info->fix.smem_len = max_size;
1696 if (cfg->fourcc == V4L2_PIX_FMT_NV12 ||
1697 cfg->fourcc == V4L2_PIX_FMT_NV21)
1698 info->fix.ypanstep = 2;
1699
1700 if (sh_mobile_format_is_yuv(var)) {
3ce05599 1701 info->fix.line_length = var->xres;
edd153a3
LP		 1702 info->fix.visual = FB_VISUAL_FOURCC;
1703 } else {
1704 info->fix.line_length = var->xres * var->bits_per_pixel / 8;
1705 info->fix.visual = FB_VISUAL_TRUECOLOR;
1706 }
3ce05599
LP		 1707
1708 info->screen_base = buf;
1709 info->device = dev;
1710 ch->display_var = *var;
1711
1712 return 0;
1713}
1714
1715static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev)
1716{
01ac25b5 1717 struct sh_mobile_lcdc_info *pdata = pdev->dev.platform_data;
3ce05599 1718 struct sh_mobile_lcdc_priv *priv;
cfb4f5d1 1719 struct resource *res;
3ce05599 1720 int num_channels;
cfb4f5d1 1721 int error;
3ce05599 1722 int i;
cfb4f5d1 1723
01ac25b5 1724 if (!pdata) {
cfb4f5d1 1725 dev_err(&pdev->dev, "no platform data defined\n");
8bed9055 1726 return -EINVAL;
cfb4f5d1
MD		 1727 }
1728
1729 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8564557a
MD		 1730 i = platform_get_irq(pdev, 0);
1731 if (!res || i < 0) {
1732 dev_err(&pdev->dev, "cannot get platform resources\n");
8bed9055 1733 return -ENOENT;
cfb4f5d1
MD		 1734 }
1735
1736 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1737 if (!priv) {
1738 dev_err(&pdev->dev, "cannot allocate device data\n");
8bed9055 1739 return -ENOMEM;
cfb4f5d1
MD		 1740 }
1741
8bed9055
GL		 1742 platform_set_drvdata(pdev, priv);
1743
f8798ccb 1744 error = request_irq(i, sh_mobile_lcdc_irq, 0,
7ad33e74 1745 dev_name(&pdev->dev), priv);
8564557a
MD		 1746 if (error) {
1747 dev_err(&pdev->dev, "unable to request irq\n");
1748 goto err1;
1749 }
1750
1751 priv->irq = i;
5ef6b505 1752 atomic_set(&priv->hw_usecnt, -1);
cfb4f5d1 1753
3ce05599
LP		 1754 for (i = 0, num_channels = 0; i < ARRAY_SIZE(pdata->ch); i++) {
1755 struct sh_mobile_lcdc_chan *ch = priv->ch + num_channels;
cfb4f5d1 1756
01ac25b5
GL		 1757 ch->lcdc = priv;
1758 memcpy(&ch->cfg, &pdata->ch[i], sizeof(pdata->ch[i]));
cfb4f5d1 1759
01ac25b5 1760 error = sh_mobile_lcdc_check_interface(ch);
cfb4f5d1
MD		 1761 if (error) {
1762 dev_err(&pdev->dev, "unsupported interface type\n");
1763 goto err1;
1764 }
01ac25b5
GL		 1765 init_waitqueue_head(&ch->frame_end_wait);
1766 init_completion(&ch->vsync_completion);
1767 ch->pan_offset = 0;
cfb4f5d1 1768
3b0fd9d7
AC		 1769 /* probe the backlight is there is one defined */
1770 if (ch->cfg.bl_info.max_brightness)
1771 ch->bl = sh_mobile_lcdc_bl_probe(&pdev->dev, ch);
1772
cfb4f5d1
MD		 1773 switch (pdata->ch[i].chan) {
1774 case LCDC_CHAN_MAINLCD:
ce1c0b08 1775 ch->enabled = LDCNT2R_ME;
01ac25b5 1776 ch->reg_offs = lcdc_offs_mainlcd;
3ce05599 1777 num_channels++;
cfb4f5d1
MD		 1778 break;
1779 case LCDC_CHAN_SUBLCD:
ce1c0b08 1780 ch->enabled = LDCNT2R_SE;
01ac25b5 1781 ch->reg_offs = lcdc_offs_sublcd;
3ce05599 1782 num_channels++;
cfb4f5d1
MD		 1783 break;
1784 }
1785 }
1786
3ce05599 1787 if (!num_channels) {
cfb4f5d1
MD		 1788 dev_err(&pdev->dev, "no channels defined\n");
1789 error = -EINVAL;
1790 goto err1;
1791 }
1792
edd153a3 1793 /* for dual channel LCDC (MAIN + SUB) force shared format setting */
3ce05599 1794 if (num_channels == 2)
edd153a3 1795 priv->forced_fourcc = pdata->ch[0].fourcc;
417d4827 1796
dba6f385
GL		 1797 priv->base = ioremap_nocache(res->start, resource_size(res));
1798 if (!priv->base)
1799 goto err1;
1800
b51339ff 1801 error = sh_mobile_lcdc_setup_clocks(pdev, pdata->clock_source, priv);
cfb4f5d1
MD		 1802 if (error) {
1803 dev_err(&pdev->dev, "unable to setup clocks\n");
1804 goto err1;
1805 }
1806
7caa4342
D		 1807 priv->meram_dev = pdata->meram_dev;
1808
3ce05599 1809 for (i = 0; i < num_channels; i++) {
01ac25b5 1810 struct sh_mobile_lcdc_chan *ch = priv->ch + i;
c44f9f76 1811
3ce05599 1812 error = sh_mobile_lcdc_channel_init(ch, &pdev->dev);
cfb4f5d1 1813 if (error)
3ce05599 1814 goto err1;
cfb4f5d1
MD		 1815 }
1816
cfb4f5d1
MD		 1817 error = sh_mobile_lcdc_start(priv);
1818 if (error) {
1819 dev_err(&pdev->dev, "unable to start hardware\n");
1820 goto err1;
1821 }
1822
3ce05599 1823 for (i = 0; i < num_channels; i++) {
1c6a307a 1824 struct sh_mobile_lcdc_chan *ch = priv->ch + i;
3ce05599 1825 struct fb_info *info = ch->info;
1c6a307a
PM		 1826
1827 if (info->fbdefio) {
8bed9055 1828 ch->sglist = vmalloc(sizeof(struct scatterlist) *
1c6a307a 1829 info->fix.smem_len >> PAGE_SHIFT);
8bed9055 1830 if (!ch->sglist) {
1c6a307a
PM		 1831 dev_err(&pdev->dev, "cannot allocate sglist\n");
1832 goto err1;
1833 }
1834 }
1835
3b0fd9d7
AC		 1836 info->bl_dev = ch->bl;
1837
1c6a307a 1838 error = register_framebuffer(info);
cfb4f5d1
MD		 1839 if (error < 0)
1840 goto err1;
cfb4f5d1 1841
edd153a3
LP		 1842 dev_info(info->dev, "registered %s/%s as %dx%d %dbpp.\n",
1843 pdev->name, (ch->cfg.chan == LCDC_CHAN_MAINLCD) ?
1844 "mainlcd" : "sublcd", info->var.xres, info->var.yres,
1845 info->var.bits_per_pixel);
8564557a
MD		 1846
1847 /* deferred io mode: disable clock to save power */
6011bdea 1848 if (info->fbdefio || info->state == FBINFO_STATE_SUSPENDED)
8564557a 1849 sh_mobile_lcdc_clk_off(priv);
cfb4f5d1
MD		 1850 }
1851
6011bdea
GL		 1852 /* Failure ignored */
1853 priv->notifier.notifier_call = sh_mobile_lcdc_notify;
1854 fb_register_client(&priv->notifier);
1855
cfb4f5d1 1856 return 0;
8bed9055 1857err1:
cfb4f5d1 1858 sh_mobile_lcdc_remove(pdev);
8bed9055 1859
cfb4f5d1
MD		 1860 return error;
1861}
1862
cfb4f5d1
MD		 1863static struct platform_driver sh_mobile_lcdc_driver = {
1864 .driver = {
1865 .name = "sh_mobile_lcdc_fb",
1866 .owner = THIS_MODULE,
2feb075a 1867 .pm = &sh_mobile_lcdc_dev_pm_ops,
cfb4f5d1
MD		 1868 },
1869 .probe = sh_mobile_lcdc_probe,
1870 .remove = sh_mobile_lcdc_remove,
1871};
1872
4277f2c4 1873module_platform_driver(sh_mobile_lcdc_driver);
cfb4f5d1
MD		 1874
1875MODULE_DESCRIPTION("SuperH Mobile LCDC Framebuffer driver");
1876MODULE_AUTHOR("Magnus Damm <damm@opensource.se>");
1877MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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