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fbdev: sh_mobile_lcdc: Store the format in struct sh_mobile_lcdc_chan
[deliverable/linux.git] / drivers / video / sh_mobile_lcdcfb.c
CommitLineData
cfb4f5d1
MD		 1/*
2 * SuperH Mobile LCDC Framebuffer
3 *
4 * Copyright (c) 2008 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
f1f60b5f
LP		 11#include <linux/atomic.h>
12#include <linux/backlight.h>
cfb4f5d1 13#include <linux/clk.h>
f1f60b5f 14#include <linux/console.h>
cfb4f5d1 15#include <linux/dma-mapping.h>
f1f60b5f
LP		 16#include <linux/delay.h>
17#include <linux/gpio.h>
18#include <linux/init.h>
8564557a 19#include <linux/interrupt.h>
40331b21 20#include <linux/ioctl.h>
f1f60b5f
LP		 21#include <linux/kernel.h>
22#include <linux/mm.h>
355b200b 23#include <linux/module.h>
f1f60b5f
LP		 24#include <linux/platform_device.h>
25#include <linux/pm_runtime.h>
26#include <linux/slab.h>
27#include <linux/videodev2.h>
28#include <linux/vmalloc.h>
29
225c9a8d 30#include <video/sh_mobile_lcdc.h>
8a20974f 31#include <video/sh_mobile_meram.h>
cfb4f5d1 32
6de9edd5
GL		 33#include "sh_mobile_lcdcfb.h"
34
a6f15ade
PE		 35#define SIDE_B_OFFSET 0x1000
36#define MIRROR_OFFSET 0x2000
cfb4f5d1 37
d2ecbab5
GL		 38#define MAX_XRES 1920
39#define MAX_YRES 1080
cfb4f5d1 40
f1f60b5f
LP		 41struct sh_mobile_lcdc_priv {
42 void __iomem *base;
43 int irq;
44 atomic_t hw_usecnt;
45 struct device *dev;
46 struct clk *dot_clk;
47 unsigned long lddckr;
48 struct sh_mobile_lcdc_chan ch[2];
49 struct notifier_block notifier;
50 int started;
51 int forced_fourcc; /* 2 channel LCDC must share fourcc setting */
52 struct sh_mobile_meram_info *meram_dev;
53};
54
55/* -----------------------------------------------------------------------------
56 * Registers access
57 */
58
0246c471 59static unsigned long lcdc_offs_mainlcd[NR_CH_REGS] = {
cfb4f5d1
MD		 60 [LDDCKPAT1R] = 0x400,
61 [LDDCKPAT2R] = 0x404,
62 [LDMT1R] = 0x418,
63 [LDMT2R] = 0x41c,
64 [LDMT3R] = 0x420,
65 [LDDFR] = 0x424,
66 [LDSM1R] = 0x428,
8564557a 67 [LDSM2R] = 0x42c,
cfb4f5d1 68 [LDSA1R] = 0x430,
53b50314 69 [LDSA2R] = 0x434,
cfb4f5d1
MD		 70 [LDMLSR] = 0x438,
71 [LDHCNR] = 0x448,
72 [LDHSYNR] = 0x44c,
73 [LDVLNR] = 0x450,
74 [LDVSYNR] = 0x454,
75 [LDPMR] = 0x460,
6011bdea 76 [LDHAJR] = 0x4a0,
cfb4f5d1
MD		 77};
78
0246c471 79static unsigned long lcdc_offs_sublcd[NR_CH_REGS] = {
cfb4f5d1
MD		 80 [LDDCKPAT1R] = 0x408,
81 [LDDCKPAT2R] = 0x40c,
82 [LDMT1R] = 0x600,
83 [LDMT2R] = 0x604,
84 [LDMT3R] = 0x608,
85 [LDDFR] = 0x60c,
86 [LDSM1R] = 0x610,
8564557a 87 [LDSM2R] = 0x614,
cfb4f5d1
MD		 88 [LDSA1R] = 0x618,
89 [LDMLSR] = 0x620,
90 [LDHCNR] = 0x624,
91 [LDHSYNR] = 0x628,
92 [LDVLNR] = 0x62c,
93 [LDVSYNR] = 0x630,
94 [LDPMR] = 0x63c,
95};
96
a6f15ade
PE		 97static bool banked(int reg_nr)
98{
99 switch (reg_nr) {
100 case LDMT1R:
101 case LDMT2R:
102 case LDMT3R:
103 case LDDFR:
104 case LDSM1R:
105 case LDSA1R:
53b50314 106 case LDSA2R:
a6f15ade
PE		 107 case LDMLSR:
108 case LDHCNR:
109 case LDHSYNR:
110 case LDVLNR:
111 case LDVSYNR:
112 return true;
113 }
114 return false;
115}
116
f1f60b5f
LP		 117static int lcdc_chan_is_sublcd(struct sh_mobile_lcdc_chan *chan)
118{
119 return chan->cfg.chan == LCDC_CHAN_SUBLCD;
120}
121
cfb4f5d1
MD		 122static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan,
123 int reg_nr, unsigned long data)
124{
125 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]);
a6f15ade
PE		 126 if (banked(reg_nr))
127 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
128 SIDE_B_OFFSET);
129}
130
131static void lcdc_write_chan_mirror(struct sh_mobile_lcdc_chan *chan,
132 int reg_nr, unsigned long data)
133{
134 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
135 MIRROR_OFFSET);
cfb4f5d1
MD		 136}
137
138static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan,
139 int reg_nr)
140{
141 return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]);
142}
143
144static void lcdc_write(struct sh_mobile_lcdc_priv *priv,
145 unsigned long reg_offs, unsigned long data)
146{
147 iowrite32(data, priv->base + reg_offs);
148}
149
150static unsigned long lcdc_read(struct sh_mobile_lcdc_priv *priv,
151 unsigned long reg_offs)
152{
153 return ioread32(priv->base + reg_offs);
154}
155
156static void lcdc_wait_bit(struct sh_mobile_lcdc_priv *priv,
157 unsigned long reg_offs,
158 unsigned long mask, unsigned long until)
159{
160 while ((lcdc_read(priv, reg_offs) & mask) != until)
161 cpu_relax();
162}
163
f1f60b5f
LP		 164/* -----------------------------------------------------------------------------
165 * Clock management
166 */
167
168static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv)
cfb4f5d1 169{
f1f60b5f
LP		 170 if (atomic_inc_and_test(&priv->hw_usecnt)) {
171 if (priv->dot_clk)
172 clk_enable(priv->dot_clk);
173 pm_runtime_get_sync(priv->dev);
174 if (priv->meram_dev && priv->meram_dev->pdev)
175 pm_runtime_get_sync(&priv->meram_dev->pdev->dev);
176 }
cfb4f5d1
MD		 177}
178
f1f60b5f
LP		 179static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv)
180{
181 if (atomic_sub_return(1, &priv->hw_usecnt) == -1) {
182 if (priv->meram_dev && priv->meram_dev->pdev)
183 pm_runtime_put_sync(&priv->meram_dev->pdev->dev);
184 pm_runtime_put(priv->dev);
185 if (priv->dot_clk)
186 clk_disable(priv->dot_clk);
187 }
188}
189
0a7f17aa
LP		 190static int sh_mobile_lcdc_setup_clocks(struct sh_mobile_lcdc_priv *priv,
191 int clock_source)
f1f60b5f 192{
4774c12a 193 struct clk *clk;
f1f60b5f
LP		 194 char *str;
195
196 switch (clock_source) {
197 case LCDC_CLK_BUS:
198 str = "bus_clk";
199 priv->lddckr = LDDCKR_ICKSEL_BUS;
200 break;
201 case LCDC_CLK_PERIPHERAL:
202 str = "peripheral_clk";
203 priv->lddckr = LDDCKR_ICKSEL_MIPI;
204 break;
205 case LCDC_CLK_EXTERNAL:
206 str = NULL;
207 priv->lddckr = LDDCKR_ICKSEL_HDMI;
208 break;
209 default:
210 return -EINVAL;
211 }
212
4774c12a
LP		 213 if (str == NULL)
214 return 0;
215
0a7f17aa 216 clk = clk_get(priv->dev, str);
4774c12a 217 if (IS_ERR(clk)) {
0a7f17aa 218 dev_err(priv->dev, "cannot get dot clock %s\n", str);
4774c12a 219 return PTR_ERR(clk);
f1f60b5f
LP		 220 }
221
4774c12a 222 priv->dot_clk = clk;
f1f60b5f
LP		 223 return 0;
224}
225
226/* -----------------------------------------------------------------------------
37c5dcc2 227 * Display, panel and deferred I/O
f1f60b5f
LP		 228 */
229
cfb4f5d1
MD		 230static void lcdc_sys_write_index(void *handle, unsigned long data)
231{
232 struct sh_mobile_lcdc_chan *ch = handle;
233
ce1c0b08
LP		 234 lcdc_write(ch->lcdc, _LDDWD0R, data | LDDWDxR_WDACT);
235 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
236 lcdc_write(ch->lcdc, _LDDWAR, LDDWAR_WA |
237 (lcdc_chan_is_sublcd(ch) ? 2 : 0));
238 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
cfb4f5d1
MD		 239}
240
241static void lcdc_sys_write_data(void *handle, unsigned long data)
242{
243 struct sh_mobile_lcdc_chan *ch = handle;
244
ce1c0b08
LP		 245 lcdc_write(ch->lcdc, _LDDWD0R, data | LDDWDxR_WDACT | LDDWDxR_RSW);
246 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
247 lcdc_write(ch->lcdc, _LDDWAR, LDDWAR_WA |
248 (lcdc_chan_is_sublcd(ch) ? 2 : 0));
249 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
cfb4f5d1
MD		 250}
251
252static unsigned long lcdc_sys_read_data(void *handle)
253{
254 struct sh_mobile_lcdc_chan *ch = handle;
255
ce1c0b08
LP		 256 lcdc_write(ch->lcdc, _LDDRDR, LDDRDR_RSR);
257 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
258 lcdc_write(ch->lcdc, _LDDRAR, LDDRAR_RA |
259 (lcdc_chan_is_sublcd(ch) ? 2 : 0));
cfb4f5d1 260 udelay(1);
ce1c0b08 261 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
cfb4f5d1 262
ce1c0b08 263 return lcdc_read(ch->lcdc, _LDDRDR) & LDDRDR_DRD_MASK;
cfb4f5d1
MD		 264}
265
266struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = {
267 lcdc_sys_write_index,
268 lcdc_sys_write_data,
269 lcdc_sys_read_data,
270};
271
1c6a307a
PM		 272static int sh_mobile_lcdc_sginit(struct fb_info *info,
273 struct list_head *pagelist)
274{
275 struct sh_mobile_lcdc_chan *ch = info->par;
276 unsigned int nr_pages_max = info->fix.smem_len >> PAGE_SHIFT;
277 struct page *page;
278 int nr_pages = 0;
279
280 sg_init_table(ch->sglist, nr_pages_max);
281
282 list_for_each_entry(page, pagelist, lru)
283 sg_set_page(&ch->sglist[nr_pages++], page, PAGE_SIZE, 0);
284
285 return nr_pages;
286}
287
8564557a
MD		 288static void sh_mobile_lcdc_deferred_io(struct fb_info *info,
289 struct list_head *pagelist)
290{
291 struct sh_mobile_lcdc_chan *ch = info->par;
afaad83b 292 struct sh_mobile_lcdc_panel_cfg *panel = &ch->cfg.panel_cfg;
8564557a
MD		 293
294 /* enable clocks before accessing hardware */
295 sh_mobile_lcdc_clk_on(ch->lcdc);
296
5c1a56b5
PM		 297 /*
298 * It's possible to get here without anything on the pagelist via
299 * sh_mobile_lcdc_deferred_io_touch() or via a userspace fsync()
300 * invocation. In the former case, the acceleration routines are
301 * stepped in to when using the framebuffer console causing the
302 * workqueue to be scheduled without any dirty pages on the list.
303 *
304 * Despite this, a panel update is still needed given that the
305 * acceleration routines have their own methods for writing in
306 * that still need to be updated.
307 *
308 * The fsync() and empty pagelist case could be optimized for,
309 * but we don't bother, as any application exhibiting such
310 * behaviour is fundamentally broken anyways.
311 */
312 if (!list_empty(pagelist)) {
313 unsigned int nr_pages = sh_mobile_lcdc_sginit(info, pagelist);
314
315 /* trigger panel update */
316 dma_map_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
afaad83b
LP		 317 if (panel->start_transfer)
318 panel->start_transfer(ch, &sh_mobile_lcdc_sys_bus_ops);
ce1c0b08 319 lcdc_write_chan(ch, LDSM2R, LDSM2R_OSTRG);
5c1a56b5 320 dma_unmap_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
ef61aae4 321 } else {
afaad83b
LP		 322 if (panel->start_transfer)
323 panel->start_transfer(ch, &sh_mobile_lcdc_sys_bus_ops);
ce1c0b08 324 lcdc_write_chan(ch, LDSM2R, LDSM2R_OSTRG);
ef61aae4 325 }
8564557a
MD		 326}
327
328static void sh_mobile_lcdc_deferred_io_touch(struct fb_info *info)
329{
330 struct fb_deferred_io *fbdefio = info->fbdefio;
331
332 if (fbdefio)
333 schedule_delayed_work(&info->deferred_work, fbdefio->delay);
334}
335
37c5dcc2
LP		 336static void sh_mobile_lcdc_display_on(struct sh_mobile_lcdc_chan *ch)
337{
afaad83b 338 struct sh_mobile_lcdc_panel_cfg *panel = &ch->cfg.panel_cfg;
37c5dcc2 339
9a2985e7 340 if (ch->tx_dev) {
458981c3
LP		 341 int ret;
342
343 ret = ch->tx_dev->ops->display_on(ch->tx_dev);
344 if (ret < 0)
9a2985e7 345 return;
458981c3
LP		 346
347 if (ret == SH_MOBILE_LCDC_DISPLAY_DISCONNECTED)
348 ch->info->state = FBINFO_STATE_SUSPENDED;
9a2985e7
LP		 349 }
350
37c5dcc2 351 /* HDMI must be enabled before LCDC configuration */
afaad83b
LP		 352 if (panel->display_on)
353 panel->display_on();
37c5dcc2
LP		 354}
355
356static void sh_mobile_lcdc_display_off(struct sh_mobile_lcdc_chan *ch)
357{
afaad83b 358 struct sh_mobile_lcdc_panel_cfg *panel = &ch->cfg.panel_cfg;
37c5dcc2 359
afaad83b
LP		 360 if (panel->display_off)
361 panel->display_off();
9a2985e7
LP		 362
363 if (ch->tx_dev)
364 ch->tx_dev->ops->display_off(ch->tx_dev);
37c5dcc2
LP		 365}
366
ecd29947
LP		 367static bool
368sh_mobile_lcdc_must_reconfigure(struct sh_mobile_lcdc_chan *ch,
e0c8601a 369 const struct fb_videomode *new_mode)
ecd29947 370{
ecd29947 371 dev_dbg(ch->info->dev, "Old %ux%u, new %ux%u\n",
2d04559d
LP		 372 ch->display.mode.xres, ch->display.mode.yres,
373 new_mode->xres, new_mode->yres);
ecd29947 374
e0c8601a 375 /* It can be a different monitor with an equal video-mode */
2d04559d 376 if (fb_mode_is_equal(&ch->display.mode, new_mode))
ecd29947 377 return false;
ecd29947
LP		 378
379 dev_dbg(ch->info->dev, "Switching %u -> %u lines\n",
2d04559d
LP		 380 ch->display.mode.yres, new_mode->yres);
381 ch->display.mode = *new_mode;
ecd29947
LP		 382
383 return true;
384}
385
386static int sh_mobile_check_var(struct fb_var_screeninfo *var,
387 struct fb_info *info);
388
389static int sh_mobile_lcdc_display_notify(struct sh_mobile_lcdc_chan *ch,
390 enum sh_mobile_lcdc_entity_event event,
e0c8601a
LP		 391 const struct fb_videomode *mode,
392 const struct fb_monspecs *monspec)
ecd29947
LP		 393{
394 struct fb_info *info = ch->info;
e0c8601a 395 struct fb_var_screeninfo var;
ecd29947
LP		 396 int ret = 0;
397
398 switch (event) {
399 case SH_MOBILE_LCDC_EVENT_DISPLAY_CONNECT:
400 /* HDMI plug in */
401 if (lock_fb_info(info)) {
402 console_lock();
403
2d04559d
LP		 404 ch->display.width = monspec->max_x * 10;
405 ch->display.height = monspec->max_y * 10;
e0c8601a
LP		 406
407 if (!sh_mobile_lcdc_must_reconfigure(ch, mode) &&
ecd29947
LP		 408 info->state == FBINFO_STATE_RUNNING) {
409 /* First activation with the default monitor.
410 * Just turn on, if we run a resume here, the
411 * logo disappears.
412 */
e0c8601a
LP		 413 info->var.width = monspec->max_x * 10;
414 info->var.height = monspec->max_y * 10;
ecd29947
LP		 415 sh_mobile_lcdc_display_on(ch);
416 } else {
417 /* New monitor or have to wake up */
418 fb_set_suspend(info, 0);
419 }
420
421 console_unlock();
422 unlock_fb_info(info);
423 }
424 break;
425
426 case SH_MOBILE_LCDC_EVENT_DISPLAY_DISCONNECT:
427 /* HDMI disconnect */
428 if (lock_fb_info(info)) {
429 console_lock();
430 fb_set_suspend(info, 1);
431 console_unlock();
432 unlock_fb_info(info);
433 }
434 break;
435
436 case SH_MOBILE_LCDC_EVENT_DISPLAY_MODE:
437 /* Validate a proposed new mode */
e0c8601a
LP		 438 fb_videomode_to_var(&var, mode);
439 var.bits_per_pixel = info->var.bits_per_pixel;
440 var.grayscale = info->var.grayscale;
441 ret = sh_mobile_check_var(&var, info);
ecd29947
LP		 442 break;
443 }
444
445 return ret;
446}
447
f1f60b5f
LP		 448/* -----------------------------------------------------------------------------
449 * Format helpers
450 */
451
105784bb
LP		 452struct sh_mobile_lcdc_format_info {
453 u32 fourcc;
454 unsigned int bpp;
455 bool yuv;
456 u32 lddfr;
457};
458
459static const struct sh_mobile_lcdc_format_info sh_mobile_format_infos[] = {
460 {
461 .fourcc = V4L2_PIX_FMT_RGB565,
462 .bpp = 16,
463 .yuv = false,
464 .lddfr = LDDFR_PKF_RGB16,
465 }, {
466 .fourcc = V4L2_PIX_FMT_BGR24,
467 .bpp = 24,
468 .yuv = false,
469 .lddfr = LDDFR_PKF_RGB24,
470 }, {
471 .fourcc = V4L2_PIX_FMT_BGR32,
472 .bpp = 32,
473 .yuv = false,
474 .lddfr = LDDFR_PKF_ARGB32,
475 }, {
476 .fourcc = V4L2_PIX_FMT_NV12,
477 .bpp = 12,
478 .yuv = true,
479 .lddfr = LDDFR_CC | LDDFR_YF_420,
480 }, {
481 .fourcc = V4L2_PIX_FMT_NV21,
482 .bpp = 12,
483 .yuv = true,
484 .lddfr = LDDFR_CC | LDDFR_YF_420,
485 }, {
486 .fourcc = V4L2_PIX_FMT_NV16,
487 .bpp = 16,
488 .yuv = true,
489 .lddfr = LDDFR_CC | LDDFR_YF_422,
490 }, {
491 .fourcc = V4L2_PIX_FMT_NV61,
492 .bpp = 16,
493 .yuv = true,
494 .lddfr = LDDFR_CC | LDDFR_YF_422,
495 }, {
496 .fourcc = V4L2_PIX_FMT_NV24,
497 .bpp = 24,
498 .yuv = true,
499 .lddfr = LDDFR_CC | LDDFR_YF_444,
500 }, {
501 .fourcc = V4L2_PIX_FMT_NV42,
502 .bpp = 24,
503 .yuv = true,
504 .lddfr = LDDFR_CC | LDDFR_YF_444,
505 },
506};
507
508static const struct sh_mobile_lcdc_format_info *
509sh_mobile_format_info(u32 fourcc)
510{
511 unsigned int i;
512
513 for (i = 0; i < ARRAY_SIZE(sh_mobile_format_infos); ++i) {
514 if (sh_mobile_format_infos[i].fourcc == fourcc)
515 return &sh_mobile_format_infos[i];
516 }
517
518 return NULL;
519}
520
f1f60b5f
LP		 521static int sh_mobile_format_fourcc(const struct fb_var_screeninfo *var)
522{
523 if (var->grayscale > 1)
524 return var->grayscale;
525
526 switch (var->bits_per_pixel) {
527 case 16:
528 return V4L2_PIX_FMT_RGB565;
529 case 24:
530 return V4L2_PIX_FMT_BGR24;
531 case 32:
532 return V4L2_PIX_FMT_BGR32;
533 default:
534 return 0;
535 }
536}
537
538static int sh_mobile_format_is_fourcc(const struct fb_var_screeninfo *var)
539{
540 return var->grayscale > 1;
541}
542
543static bool sh_mobile_format_is_yuv(const struct fb_var_screeninfo *var)
544{
105784bb
LP		 545 const struct sh_mobile_lcdc_format_info *format;
546
f1f60b5f
LP		 547 if (var->grayscale <= 1)
548 return false;
549
105784bb
LP		 550 format = sh_mobile_format_info(var->grayscale);
551 return format ? format->yuv : false;
f1f60b5f
LP		 552}
553
554/* -----------------------------------------------------------------------------
555 * Start, stop and IRQ
556 */
557
8564557a
MD		 558static irqreturn_t sh_mobile_lcdc_irq(int irq, void *data)
559{
560 struct sh_mobile_lcdc_priv *priv = data;
2feb075a 561 struct sh_mobile_lcdc_chan *ch;
9dd38819 562 unsigned long ldintr;
2feb075a
MD		 563 int is_sub;
564 int k;
8564557a 565
dc48665f
LP		 566 /* Acknowledge interrupts and disable further VSYNC End IRQs. */
567 ldintr = lcdc_read(priv, _LDINTR);
568 lcdc_write(priv, _LDINTR, (ldintr ^ LDINTR_STATUS_MASK) & ~LDINTR_VEE);
8564557a 569
2feb075a 570 /* figure out if this interrupt is for main or sub lcd */
ce1c0b08 571 is_sub = (lcdc_read(priv, _LDSR) & LDSR_MSS) ? 1 : 0;
2feb075a 572
9dd38819 573 /* wake up channel and disable clocks */
2feb075a
MD		 574 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
575 ch = &priv->ch[k];
576
577 if (!ch->enabled)
578 continue;
579
dc48665f 580 /* Frame End */
9dd38819
PE		 581 if (ldintr & LDINTR_FS) {
582 if (is_sub == lcdc_chan_is_sublcd(ch)) {
583 ch->frame_end = 1;
584 wake_up(&ch->frame_end_wait);
2feb075a 585
9dd38819
PE		 586 sh_mobile_lcdc_clk_off(priv);
587 }
588 }
589
590 /* VSYNC End */
40331b21
PE		 591 if (ldintr & LDINTR_VES)
592 complete(&ch->vsync_completion);
2feb075a
MD		 593 }
594
8564557a
MD		 595 return IRQ_HANDLED;
596}
597
cfb4f5d1
MD		 598static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv *priv,
599 int start)
600{
601 unsigned long tmp = lcdc_read(priv, _LDCNT2R);
602 int k;
603
604 /* start or stop the lcdc */
605 if (start)
ce1c0b08 606 lcdc_write(priv, _LDCNT2R, tmp | LDCNT2R_DO);
cfb4f5d1 607 else
ce1c0b08 608 lcdc_write(priv, _LDCNT2R, tmp & ~LDCNT2R_DO);
cfb4f5d1
MD		 609
610 /* wait until power is applied/stopped on all channels */
611 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
612 if (lcdc_read(priv, _LDCNT2R) & priv->ch[k].enabled)
613 while (1) {
ce1c0b08
LP		 614 tmp = lcdc_read_chan(&priv->ch[k], LDPMR)
615 & LDPMR_LPS;
616 if (start && tmp == LDPMR_LPS)
cfb4f5d1
MD		 617 break;
618 if (!start && tmp == 0)
619 break;
620 cpu_relax();
621 }
622
623 if (!start)
624 lcdc_write(priv, _LDDCKSTPR, 1); /* stop dotclock */
625}
626
6011bdea
GL		 627static void sh_mobile_lcdc_geometry(struct sh_mobile_lcdc_chan *ch)
628{
2d04559d
LP		 629 const struct fb_var_screeninfo *var = &ch->info->var;
630 const struct fb_videomode *mode = &ch->display.mode;
1c120deb 631 unsigned long h_total, hsync_pos, display_h_total;
6011bdea
GL		 632 u32 tmp;
633
634 tmp = ch->ldmt1r_value;
ce1c0b08
LP		 635 tmp |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : LDMT1R_VPOL;
636 tmp |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : LDMT1R_HPOL;
637 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWPOL) ? LDMT1R_DWPOL : 0;
638 tmp |= (ch->cfg.flags & LCDC_FLAGS_DIPOL) ? LDMT1R_DIPOL : 0;
639 tmp |= (ch->cfg.flags & LCDC_FLAGS_DAPOL) ? LDMT1R_DAPOL : 0;
640 tmp |= (ch->cfg.flags & LCDC_FLAGS_HSCNT) ? LDMT1R_HSCNT : 0;
641 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWCNT) ? LDMT1R_DWCNT : 0;
6011bdea
GL		 642 lcdc_write_chan(ch, LDMT1R, tmp);
643
644 /* setup SYS bus */
645 lcdc_write_chan(ch, LDMT2R, ch->cfg.sys_bus_cfg.ldmt2r);
646 lcdc_write_chan(ch, LDMT3R, ch->cfg.sys_bus_cfg.ldmt3r);
647
648 /* horizontal configuration */
2d04559d
LP		 649 h_total = mode->xres + mode->hsync_len + mode->left_margin
650 + mode->right_margin;
6011bdea 651 tmp = h_total / 8; /* HTCN */
2d04559d 652 tmp |= (min(mode->xres, var->xres) / 8) << 16; /* HDCN */
6011bdea
GL		 653 lcdc_write_chan(ch, LDHCNR, tmp);
654
2d04559d 655 hsync_pos = mode->xres + mode->right_margin;
6011bdea 656 tmp = hsync_pos / 8; /* HSYNP */
2d04559d 657 tmp |= (mode->hsync_len / 8) << 16; /* HSYNW */
6011bdea
GL		 658 lcdc_write_chan(ch, LDHSYNR, tmp);
659
660 /* vertical configuration */
2d04559d
LP		 661 tmp = mode->yres + mode->vsync_len + mode->upper_margin
662 + mode->lower_margin; /* VTLN */
663 tmp |= min(mode->yres, var->yres) << 16; /* VDLN */
6011bdea
GL		 664 lcdc_write_chan(ch, LDVLNR, tmp);
665
2d04559d
LP		 666 tmp = mode->yres + mode->lower_margin; /* VSYNP */
667 tmp |= mode->vsync_len << 16; /* VSYNW */
6011bdea
GL		 668 lcdc_write_chan(ch, LDVSYNR, tmp);
669
670 /* Adjust horizontal synchronisation for HDMI */
2d04559d
LP		 671 display_h_total = mode->xres + mode->hsync_len + mode->left_margin
672 + mode->right_margin;
673 tmp = ((mode->xres & 7) << 24) | ((display_h_total & 7) << 16)
674 | ((mode->hsync_len & 7) << 8) | (hsync_pos & 7);
6011bdea
GL		 675 lcdc_write_chan(ch, LDHAJR, tmp);
676}
677
9a217e34
LP		 678/*
679 * __sh_mobile_lcdc_start - Configure and tart the LCDC
680 * @priv: LCDC device
681 *
682 * Configure all enabled channels and start the LCDC device. All external
683 * devices (clocks, MERAM, panels, ...) are not touched by this function.
684 */
685static void __sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
cfb4f5d1
MD		 686{
687 struct sh_mobile_lcdc_chan *ch;
cfb4f5d1 688 unsigned long tmp;
9a217e34 689 int k, m;
8564557a 690
9a217e34
LP		 691 /* Enable LCDC channels. Read data from external memory, avoid using the
692 * BEU for now.
693 */
694 lcdc_write(priv, _LDCNT2R, priv->ch[0].enabled | priv->ch[1].enabled);
cfb4f5d1 695
9a217e34 696 /* Stop the LCDC first and disable all interrupts. */
cfb4f5d1 697 sh_mobile_lcdc_start_stop(priv, 0);
9a217e34 698 lcdc_write(priv, _LDINTR, 0);
cfb4f5d1 699
9a217e34 700 /* Configure power supply, dot clocks and start them. */
cfb4f5d1
MD		 701 tmp = priv->lddckr;
702 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
703 ch = &priv->ch[k];
9a217e34 704 if (!ch->enabled)
cfb4f5d1
MD		 705 continue;
706
9a217e34
LP		 707 /* Power supply */
708 lcdc_write_chan(ch, LDPMR, 0);
709
cfb4f5d1
MD		 710 m = ch->cfg.clock_divider;
711 if (!m)
712 continue;
713
505c7de5
LP		 714 /* FIXME: sh7724 can only use 42, 48, 54 and 60 for the divider
715 * denominator.
716 */
717 lcdc_write_chan(ch, LDDCKPAT1R, 0);
718 lcdc_write_chan(ch, LDDCKPAT2R, (1 << (m/2)) - 1);
719
cfb4f5d1 720 if (m == 1)
ce1c0b08 721 m = LDDCKR_MOSEL;
cfb4f5d1 722 tmp |= m << (lcdc_chan_is_sublcd(ch) ? 8 : 0);
cfb4f5d1
MD		 723 }
724
725 lcdc_write(priv, _LDDCKR, tmp);
cfb4f5d1
MD		 726 lcdc_write(priv, _LDDCKSTPR, 0);
727 lcdc_wait_bit(priv, _LDDCKSTPR, ~0, 0);
728
9a217e34 729 /* Setup geometry, format, frame buffer memory and operation mode. */
cfb4f5d1
MD		 730 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
731 ch = &priv->ch[k];
cfb4f5d1
MD		 732 if (!ch->enabled)
733 continue;
734
6011bdea 735 sh_mobile_lcdc_geometry(ch);
cfb4f5d1 736
fc9e78e6 737 tmp = ch->format->lddfr;
edd153a3 738
fc9e78e6 739 if (ch->format->yuv) {
edd153a3
LP		 740 switch (ch->info->var.colorspace) {
741 case V4L2_COLORSPACE_REC709:
742 tmp |= LDDFR_CF1;
53b50314 743 break;
edd153a3
LP		 744 case V4L2_COLORSPACE_JPEG:
745 tmp |= LDDFR_CF0;
53b50314
DHG		 746 break;
747 }
417d4827 748 }
7caa4342 749
9a217e34
LP		 750 lcdc_write_chan(ch, LDDFR, tmp);
751 lcdc_write_chan(ch, LDMLSR, ch->pitch);
752 lcdc_write_chan(ch, LDSA1R, ch->base_addr_y);
fc9e78e6 753 if (ch->format->yuv)
9a217e34 754 lcdc_write_chan(ch, LDSA2R, ch->base_addr_c);
7caa4342 755
9a217e34
LP		 756 /* When using deferred I/O mode, configure the LCDC for one-shot
757 * operation and enable the frame end interrupt. Otherwise use
758 * continuous read mode.
759 */
760 if (ch->ldmt1r_value & LDMT1R_IFM &&
761 ch->cfg.sys_bus_cfg.deferred_io_msec) {
762 lcdc_write_chan(ch, LDSM1R, LDSM1R_OS);
763 lcdc_write(priv, _LDINTR, LDINTR_FE);
764 } else {
765 lcdc_write_chan(ch, LDSM1R, 0);
766 }
767 }
7caa4342 768
9a217e34 769 /* Word and long word swap. */
fc9e78e6 770 switch (priv->ch[0].format->fourcc) {
edd153a3
LP		 771 case V4L2_PIX_FMT_RGB565:
772 case V4L2_PIX_FMT_NV21:
773 case V4L2_PIX_FMT_NV61:
774 case V4L2_PIX_FMT_NV42:
775 tmp = LDDDSR_LS | LDDDSR_WS;
776 break;
777 case V4L2_PIX_FMT_BGR24:
778 case V4L2_PIX_FMT_NV12:
779 case V4L2_PIX_FMT_NV16:
780 case V4L2_PIX_FMT_NV24:
9a217e34 781 tmp = LDDDSR_LS | LDDDSR_WS | LDDDSR_BS;
edd153a3
LP		 782 break;
783 case V4L2_PIX_FMT_BGR32:
784 default:
785 tmp = LDDDSR_LS;
786 break;
9a217e34
LP		 787 }
788 lcdc_write(priv, _LDDDSR, tmp);
7caa4342 789
9a217e34
LP		 790 /* Enable the display output. */
791 lcdc_write(priv, _LDCNT1R, LDCNT1R_DE);
792 sh_mobile_lcdc_start_stop(priv, 1);
793 priv->started = 1;
794}
cfb4f5d1 795
9a217e34
LP		 796static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
797{
798 struct sh_mobile_meram_info *mdev = priv->meram_dev;
9a217e34
LP		 799 struct sh_mobile_lcdc_chan *ch;
800 unsigned long tmp;
801 int ret;
802 int k;
cfb4f5d1 803
9a217e34
LP		 804 /* enable clocks before accessing the hardware */
805 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
806 if (priv->ch[k].enabled)
807 sh_mobile_lcdc_clk_on(priv);
808 }
8564557a 809
9a217e34
LP		 810 /* reset */
811 lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LDCNT2R_BR);
812 lcdc_wait_bit(priv, _LDCNT2R, LDCNT2R_BR, 0);
8564557a 813
9a217e34 814 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
afaad83b 815 struct sh_mobile_lcdc_panel_cfg *panel;
8564557a 816
37c5dcc2 817 ch = &priv->ch[k];
9a217e34
LP		 818 if (!ch->enabled)
819 continue;
820
afaad83b
LP		 821 panel = &ch->cfg.panel_cfg;
822 if (panel->setup_sys) {
823 ret = panel->setup_sys(ch, &sh_mobile_lcdc_sys_bus_ops);
9a217e34
LP		 824 if (ret)
825 return ret;
8564557a 826 }
cfb4f5d1
MD		 827 }
828
9a217e34
LP		 829 /* Compute frame buffer base address and pitch for each channel. */
830 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
831 struct sh_mobile_meram_cfg *cfg;
832 int pixelformat;
cfb4f5d1 833
9a217e34
LP		 834 ch = &priv->ch[k];
835 if (!ch->enabled)
836 continue;
cfb4f5d1 837
9a217e34
LP		 838 ch->base_addr_y = ch->info->fix.smem_start;
839 ch->base_addr_c = ch->base_addr_y
840 + ch->info->var.xres
841 * ch->info->var.yres_virtual;
842 ch->pitch = ch->info->fix.line_length;
843
844 /* Enable MERAM if possible. */
845 cfg = ch->cfg.meram_cfg;
846 if (mdev == NULL || mdev->ops == NULL || cfg == NULL)
847 continue;
848
849 /* we need to de-init configured ICBs before we can
850 * re-initialize them.
851 */
852 if (ch->meram_enabled) {
853 mdev->ops->meram_unregister(mdev, cfg);
854 ch->meram_enabled = 0;
855 }
856
fc9e78e6 857 switch (ch->format->fourcc) {
edd153a3
LP		 858 case V4L2_PIX_FMT_NV12:
859 case V4L2_PIX_FMT_NV21:
860 case V4L2_PIX_FMT_NV16:
861 case V4L2_PIX_FMT_NV61:
9a217e34 862 pixelformat = SH_MOBILE_MERAM_PF_NV;
edd153a3
LP		 863 break;
864 case V4L2_PIX_FMT_NV24:
865 case V4L2_PIX_FMT_NV42:
866 pixelformat = SH_MOBILE_MERAM_PF_NV24;
867 break;
868 case V4L2_PIX_FMT_RGB565:
869 case V4L2_PIX_FMT_BGR24:
870 case V4L2_PIX_FMT_BGR32:
871 default:
872 pixelformat = SH_MOBILE_MERAM_PF_RGB;
873 break;
874 }
9a217e34
LP		 875
876 ret = mdev->ops->meram_register(mdev, cfg, ch->pitch,
877 ch->info->var.yres, pixelformat,
878 ch->base_addr_y, ch->base_addr_c,
879 &ch->base_addr_y, &ch->base_addr_c,
880 &ch->pitch);
881 if (!ret)
882 ch->meram_enabled = 1;
883 }
884
885 /* Start the LCDC. */
886 __sh_mobile_lcdc_start(priv);
887
888 /* Setup deferred I/O, tell the board code to enable the panels, and
889 * turn backlight on.
890 */
cfb4f5d1
MD		 891 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
892 ch = &priv->ch[k];
21bc1f02
MD		 893 if (!ch->enabled)
894 continue;
895
9a217e34
LP		 896 tmp = ch->cfg.sys_bus_cfg.deferred_io_msec;
897 if (ch->ldmt1r_value & LDMT1R_IFM && tmp) {
898 ch->defio.deferred_io = sh_mobile_lcdc_deferred_io;
899 ch->defio.delay = msecs_to_jiffies(tmp);
900 ch->info->fbdefio = &ch->defio;
901 fb_deferred_io_init(ch->info);
902 }
903
37c5dcc2 904 sh_mobile_lcdc_display_on(ch);
3b0fd9d7
AC		 905
906 if (ch->bl) {
907 ch->bl->props.power = FB_BLANK_UNBLANK;
908 backlight_update_status(ch->bl);
909 }
cfb4f5d1
MD		 910 }
911
912 return 0;
913}
914
915static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
916{
917 struct sh_mobile_lcdc_chan *ch;
cfb4f5d1
MD		 918 int k;
919
2feb075a 920 /* clean up deferred io and ask board code to disable panel */
cfb4f5d1
MD		 921 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
922 ch = &priv->ch[k];
21bc1f02
MD		 923 if (!ch->enabled)
924 continue;
8564557a 925
2feb075a
MD		 926 /* deferred io mode:
927 * flush frame, and wait for frame end interrupt
928 * clean up deferred io and enable clock
929 */
5ef6b505 930 if (ch->info && ch->info->fbdefio) {
2feb075a 931 ch->frame_end = 0;
e33afddc 932 schedule_delayed_work(&ch->info->deferred_work, 0);
2feb075a 933 wait_event(ch->frame_end_wait, ch->frame_end);
e33afddc
PM		 934 fb_deferred_io_cleanup(ch->info);
935 ch->info->fbdefio = NULL;
2feb075a 936 sh_mobile_lcdc_clk_on(priv);
8564557a 937 }
2feb075a 938
3b0fd9d7
AC		 939 if (ch->bl) {
940 ch->bl->props.power = FB_BLANK_POWERDOWN;
941 backlight_update_status(ch->bl);
942 }
943
37c5dcc2 944 sh_mobile_lcdc_display_off(ch);
7caa4342
D		 945
946 /* disable the meram */
947 if (ch->meram_enabled) {
948 struct sh_mobile_meram_cfg *cfg;
949 struct sh_mobile_meram_info *mdev;
950 cfg = ch->cfg.meram_cfg;
951 mdev = priv->meram_dev;
952 mdev->ops->meram_unregister(mdev, cfg);
953 ch->meram_enabled = 0;
954 }
955
cfb4f5d1
MD		 956 }
957
958 /* stop the lcdc */
8e9bb19e
MD		 959 if (priv->started) {
960 sh_mobile_lcdc_start_stop(priv, 0);
961 priv->started = 0;
962 }
b51339ff 963
8564557a
MD		 964 /* stop clocks */
965 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
966 if (priv->ch[k].enabled)
967 sh_mobile_lcdc_clk_off(priv);
cfb4f5d1
MD		 968}
969
f1f60b5f
LP		 970/* -----------------------------------------------------------------------------
971 * Frame buffer operations
972 */
cfb4f5d1
MD		 973
974static int sh_mobile_lcdc_setcolreg(u_int regno,
975 u_int red, u_int green, u_int blue,
976 u_int transp, struct fb_info *info)
977{
978 u32 *palette = info->pseudo_palette;
979
980 if (regno >= PALETTE_NR)
981 return -EINVAL;
982
983 /* only FB_VISUAL_TRUECOLOR supported */
984
985 red >>= 16 - info->var.red.length;
986 green >>= 16 - info->var.green.length;
987 blue >>= 16 - info->var.blue.length;
988 transp >>= 16 - info->var.transp.length;
989
990 palette[regno] = (red << info->var.red.offset) |
991 (green << info->var.green.offset) |
992 (blue << info->var.blue.offset) |
993 (transp << info->var.transp.offset);
994
995 return 0;
996}
997
998static struct fb_fix_screeninfo sh_mobile_lcdc_fix = {
999 .id = "SH Mobile LCDC",
1000 .type = FB_TYPE_PACKED_PIXELS,
1001 .visual = FB_VISUAL_TRUECOLOR,
1002 .accel = FB_ACCEL_NONE,
9dd38819
PE		 1003 .xpanstep = 0,
1004 .ypanstep = 1,
1005 .ywrapstep = 0,
edd153a3 1006 .capabilities = FB_CAP_FOURCC,
cfb4f5d1
MD		 1007};
1008
8564557a
MD		 1009static void sh_mobile_lcdc_fillrect(struct fb_info *info,
1010 const struct fb_fillrect *rect)
1011{
1012 sys_fillrect(info, rect);
1013 sh_mobile_lcdc_deferred_io_touch(info);
1014}
1015
1016static void sh_mobile_lcdc_copyarea(struct fb_info *info,
1017 const struct fb_copyarea *area)
1018{
1019 sys_copyarea(info, area);
1020 sh_mobile_lcdc_deferred_io_touch(info);
1021}
1022
1023static void sh_mobile_lcdc_imageblit(struct fb_info *info,
1024 const struct fb_image *image)
1025{
1026 sys_imageblit(info, image);
1027 sh_mobile_lcdc_deferred_io_touch(info);
1028}
1029
9dd38819
PE		 1030static int sh_mobile_fb_pan_display(struct fb_var_screeninfo *var,
1031 struct fb_info *info)
1032{
1033 struct sh_mobile_lcdc_chan *ch = info->par;
92e1f9a7
PE		 1034 struct sh_mobile_lcdc_priv *priv = ch->lcdc;
1035 unsigned long ldrcntr;
1036 unsigned long new_pan_offset;
53b50314
DHG		 1037 unsigned long base_addr_y, base_addr_c;
1038 unsigned long c_offset;
edd153a3 1039 bool yuv = sh_mobile_format_is_yuv(&info->var);
92e1f9a7 1040
edd153a3 1041 if (!yuv)
dc1d5ada
LP		 1042 new_pan_offset = var->yoffset * info->fix.line_length
1043 + var->xoffset * (info->var.bits_per_pixel / 8);
53b50314 1044 else
dc1d5ada
LP		 1045 new_pan_offset = var->yoffset * info->fix.line_length
1046 + var->xoffset;
9dd38819 1047
92e1f9a7 1048 if (new_pan_offset == ch->pan_offset)
9dd38819
PE		 1049 return 0; /* No change, do nothing */
1050
92e1f9a7 1051 ldrcntr = lcdc_read(priv, _LDRCNTR);
9dd38819 1052
92e1f9a7 1053 /* Set the source address for the next refresh */
53b50314 1054 base_addr_y = ch->dma_handle + new_pan_offset;
edd153a3 1055 if (yuv) {
53b50314 1056 /* Set y offset */
dc1d5ada
LP		 1057 c_offset = var->yoffset * info->fix.line_length
1058 * (info->var.bits_per_pixel - 8) / 8;
1059 base_addr_c = ch->dma_handle
1060 + info->var.xres * info->var.yres_virtual
1061 + c_offset;
53b50314 1062 /* Set x offset */
fc9e78e6 1063 if (ch->format->fourcc == V4L2_PIX_FMT_NV24)
53b50314
DHG		 1064 base_addr_c += 2 * var->xoffset;
1065 else
1066 base_addr_c += var->xoffset;
49d79ba2 1067 }
53b50314 1068
49d79ba2 1069 if (ch->meram_enabled) {
7caa4342
D		 1070 struct sh_mobile_meram_cfg *cfg;
1071 struct sh_mobile_meram_info *mdev;
7caa4342
D		 1072 int ret;
1073
1074 cfg = ch->cfg.meram_cfg;
1075 mdev = priv->meram_dev;
1076 ret = mdev->ops->meram_update(mdev, cfg,
1077 base_addr_y, base_addr_c,
49d79ba2 1078 &base_addr_y, &base_addr_c);
7caa4342
D		 1079 if (ret)
1080 return ret;
49d79ba2 1081 }
7caa4342 1082
49d79ba2
LP		 1083 ch->base_addr_y = base_addr_y;
1084 ch->base_addr_c = base_addr_c;
7caa4342 1085
49d79ba2 1086 lcdc_write_chan_mirror(ch, LDSA1R, base_addr_y);
edd153a3 1087 if (yuv)
49d79ba2 1088 lcdc_write_chan_mirror(ch, LDSA2R, base_addr_c);
53b50314 1089
92e1f9a7
PE		 1090 if (lcdc_chan_is_sublcd(ch))
1091 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_SRS);
1092 else
1093 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_MRS);
1094
1095 ch->pan_offset = new_pan_offset;
1096
1097 sh_mobile_lcdc_deferred_io_touch(info);
9dd38819
PE		 1098
1099 return 0;
1100}
1101
40331b21
PE		 1102static int sh_mobile_wait_for_vsync(struct fb_info *info)
1103{
1104 struct sh_mobile_lcdc_chan *ch = info->par;
1105 unsigned long ldintr;
1106 int ret;
1107
dc48665f
LP		 1108 /* Enable VSync End interrupt and be careful not to acknowledge any
1109 * pending interrupt.
1110 */
40331b21 1111 ldintr = lcdc_read(ch->lcdc, _LDINTR);
dc48665f 1112 ldintr |= LDINTR_VEE | LDINTR_STATUS_MASK;
40331b21
PE		 1113 lcdc_write(ch->lcdc, _LDINTR, ldintr);
1114
1115 ret = wait_for_completion_interruptible_timeout(&ch->vsync_completion,
1116 msecs_to_jiffies(100));
1117 if (!ret)
1118 return -ETIMEDOUT;
1119
1120 return 0;
1121}
1122
1123static int sh_mobile_ioctl(struct fb_info *info, unsigned int cmd,
1124 unsigned long arg)
1125{
1126 int retval;
1127
1128 switch (cmd) {
1129 case FBIO_WAITFORVSYNC:
1130 retval = sh_mobile_wait_for_vsync(info);
1131 break;
1132
1133 default:
1134 retval = -ENOIOCTLCMD;
1135 break;
1136 }
1137 return retval;
1138}
1139
dd210503
GL		 1140static void sh_mobile_fb_reconfig(struct fb_info *info)
1141{
1142 struct sh_mobile_lcdc_chan *ch = info->par;
2d04559d
LP		 1143 struct fb_var_screeninfo var;
1144 struct fb_videomode mode;
dd210503
GL		 1145 struct fb_event event;
1146 int evnt = FB_EVENT_MODE_CHANGE_ALL;
1147
1148 if (ch->use_count > 1 || (ch->use_count == 1 && !info->fbcon_par))
1149 /* More framebuffer users are active */
1150 return;
1151
2d04559d 1152 fb_var_to_videomode(&mode, &info->var);
dd210503 1153
2d04559d 1154 if (fb_mode_is_equal(&ch->display.mode, &mode))
dd210503
GL		 1155 return;
1156
1157 /* Display has been re-plugged, framebuffer is free now, reconfigure */
2d04559d
LP		 1158 var = info->var;
1159 fb_videomode_to_var(&var, &ch->display.mode);
1160 var.width = ch->display.width;
1161 var.height = ch->display.height;
1162 var.activate = FB_ACTIVATE_NOW;
1163
1164 if (fb_set_var(info, &var) < 0)
dd210503
GL		 1165 /* Couldn't reconfigure, hopefully, can continue as before */
1166 return;
1167
dd210503
GL		 1168 /*
1169 * fb_set_var() calls the notifier change internally, only if
1170 * FBINFO_MISC_USEREVENT flag is set. Since we do not want to fake a
1171 * user event, we have to call the chain ourselves.
1172 */
1173 event.info = info;
2d04559d 1174 event.data = &ch->display.mode;
dd210503
GL		 1175 fb_notifier_call_chain(evnt, &event);
1176}
1177
1178/*
1179 * Locking: both .fb_release() and .fb_open() are called with info->lock held if
1180 * user == 1, or with console sem held, if user == 0.
1181 */
1182static int sh_mobile_release(struct fb_info *info, int user)
1183{
1184 struct sh_mobile_lcdc_chan *ch = info->par;
1185
1186 mutex_lock(&ch->open_lock);
1187 dev_dbg(info->dev, "%s(): %d users\n", __func__, ch->use_count);
1188
1189 ch->use_count--;
1190
1191 /* Nothing to reconfigure, when called from fbcon */
1192 if (user) {
ac751efa 1193 console_lock();
dd210503 1194 sh_mobile_fb_reconfig(info);
ac751efa 1195 console_unlock();
dd210503
GL		 1196 }
1197
1198 mutex_unlock(&ch->open_lock);
1199
1200 return 0;
1201}
1202
1203static int sh_mobile_open(struct fb_info *info, int user)
1204{
1205 struct sh_mobile_lcdc_chan *ch = info->par;
1206
1207 mutex_lock(&ch->open_lock);
1208 ch->use_count++;
1209
1210 dev_dbg(info->dev, "%s(): %d users\n", __func__, ch->use_count);
1211 mutex_unlock(&ch->open_lock);
1212
1213 return 0;
1214}
1215
1216static int sh_mobile_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1217{
1218 struct sh_mobile_lcdc_chan *ch = info->par;
417d4827 1219 struct sh_mobile_lcdc_priv *p = ch->lcdc;
03862194
LP		 1220 unsigned int best_dist = (unsigned int)-1;
1221 unsigned int best_xres = 0;
1222 unsigned int best_yres = 0;
1223 unsigned int i;
dd210503 1224
03862194 1225 if (var->xres > MAX_XRES || var->yres > MAX_YRES)
dd210503 1226 return -EINVAL;
03862194
LP		 1227
1228 /* If board code provides us with a list of available modes, make sure
1229 * we use one of them. Find the mode closest to the requested one. The
1230 * distance between two modes is defined as the size of the
1231 * non-overlapping parts of the two rectangles.
1232 */
93ff2598
LP		 1233 for (i = 0; i < ch->cfg.num_modes; ++i) {
1234 const struct fb_videomode *mode = &ch->cfg.lcd_modes[i];
03862194
LP		 1235 unsigned int dist;
1236
1237 /* We can only round up. */
1238 if (var->xres > mode->xres || var->yres > mode->yres)
1239 continue;
1240
1241 dist = var->xres * var->yres + mode->xres * mode->yres
1242 - 2 * min(var->xres, mode->xres)
1243 * min(var->yres, mode->yres);
1244
1245 if (dist < best_dist) {
1246 best_xres = mode->xres;
1247 best_yres = mode->yres;
1248 best_dist = dist;
1249 }
dd210503 1250 }
417d4827 1251
03862194 1252 /* If no available mode can be used, return an error. */
93ff2598 1253 if (ch->cfg.num_modes != 0) {
03862194
LP		 1254 if (best_dist == (unsigned int)-1)
1255 return -EINVAL;
1256
1257 var->xres = best_xres;
1258 var->yres = best_yres;
1259 }
1260
1261 /* Make sure the virtual resolution is at least as big as the visible
1262 * resolution.
1263 */
1264 if (var->xres_virtual < var->xres)
1265 var->xres_virtual = var->xres;
1266 if (var->yres_virtual < var->yres)
1267 var->yres_virtual = var->yres;
1268
edd153a3 1269 if (sh_mobile_format_is_fourcc(var)) {
105784bb
LP		 1270 const struct sh_mobile_lcdc_format_info *format;
1271
1272 format = sh_mobile_format_info(var->grayscale);
1273 if (format == NULL)
edd153a3 1274 return -EINVAL;
105784bb 1275 var->bits_per_pixel = format->bpp;
edd153a3
LP		 1276
1277 /* Default to RGB and JPEG color-spaces for RGB and YUV formats
1278 * respectively.
1279 */
105784bb 1280 if (!format->yuv)
edd153a3
LP		 1281 var->colorspace = V4L2_COLORSPACE_SRGB;
1282 else if (var->colorspace != V4L2_COLORSPACE_REC709)
1283 var->colorspace = V4L2_COLORSPACE_JPEG;
1284 } else {
1285 if (var->bits_per_pixel <= 16) { /* RGB 565 */
1286 var->bits_per_pixel = 16;
1287 var->red.offset = 11;
1288 var->red.length = 5;
1289 var->green.offset = 5;
1290 var->green.length = 6;
1291 var->blue.offset = 0;
1292 var->blue.length = 5;
1293 var->transp.offset = 0;
1294 var->transp.length = 0;
1295 } else if (var->bits_per_pixel <= 24) { /* RGB 888 */
1296 var->bits_per_pixel = 24;
1297 var->red.offset = 16;
1298 var->red.length = 8;
1299 var->green.offset = 8;
1300 var->green.length = 8;
1301 var->blue.offset = 0;
1302 var->blue.length = 8;
1303 var->transp.offset = 0;
1304 var->transp.length = 0;
1305 } else if (var->bits_per_pixel <= 32) { /* RGBA 888 */
1306 var->bits_per_pixel = 32;
1307 var->red.offset = 16;
1308 var->red.length = 8;
1309 var->green.offset = 8;
1310 var->green.length = 8;
1311 var->blue.offset = 0;
1312 var->blue.length = 8;
1313 var->transp.offset = 24;
1314 var->transp.length = 8;
1315 } else
1316 return -EINVAL;
417d4827 1317
edd153a3
LP		 1318 var->red.msb_right = 0;
1319 var->green.msb_right = 0;
1320 var->blue.msb_right = 0;
1321 var->transp.msb_right = 0;
1322 }
03862194
LP		 1323
1324 /* Make sure we don't exceed our allocated memory. */
1325 if (var->xres_virtual * var->yres_virtual * var->bits_per_pixel / 8 >
1326 info->fix.smem_len)
1327 return -EINVAL;
1328
edd153a3
LP		 1329 /* only accept the forced_fourcc for dual channel configurations */
1330 if (p->forced_fourcc &&
1331 p->forced_fourcc != sh_mobile_format_fourcc(var))
417d4827 1332 return -EINVAL;
417d4827 1333
dd210503
GL		 1334 return 0;
1335}
40331b21 1336
ed5bebf2
LP		 1337static int sh_mobile_set_par(struct fb_info *info)
1338{
1339 struct sh_mobile_lcdc_chan *ch = info->par;
91fba48d 1340 u32 line_length = info->fix.line_length;
ed5bebf2
LP		 1341 int ret;
1342
1343 sh_mobile_lcdc_stop(ch->lcdc);
91fba48d 1344
edd153a3 1345 if (sh_mobile_format_is_yuv(&info->var))
91fba48d
LP		 1346 info->fix.line_length = info->var.xres;
1347 else
1348 info->fix.line_length = info->var.xres
1349 * info->var.bits_per_pixel / 8;
1350
fc9e78e6
LP		 1351 ch->format = sh_mobile_format_info(sh_mobile_format_fourcc(&info->var));
1352
ed5bebf2 1353 ret = sh_mobile_lcdc_start(ch->lcdc);
91fba48d 1354 if (ret < 0) {
ed5bebf2 1355 dev_err(info->dev, "%s: unable to restart LCDC\n", __func__);
91fba48d
LP		 1356 info->fix.line_length = line_length;
1357 }
ed5bebf2 1358
edd153a3
LP		 1359 if (sh_mobile_format_is_fourcc(&info->var)) {
1360 info->fix.type = FB_TYPE_FOURCC;
1361 info->fix.visual = FB_VISUAL_FOURCC;
1362 } else {
1363 info->fix.type = FB_TYPE_PACKED_PIXELS;
1364 info->fix.visual = FB_VISUAL_TRUECOLOR;
1365 }
1366
ed5bebf2
LP		 1367 return ret;
1368}
1369
8857b9aa
AC		 1370/*
1371 * Screen blanking. Behavior is as follows:
1372 * FB_BLANK_UNBLANK: screen unblanked, clocks enabled
1373 * FB_BLANK_NORMAL: screen blanked, clocks enabled
1374 * FB_BLANK_VSYNC,
1375 * FB_BLANK_HSYNC,
1376 * FB_BLANK_POWEROFF: screen blanked, clocks disabled
1377 */
1378static int sh_mobile_lcdc_blank(int blank, struct fb_info *info)
1379{
1380 struct sh_mobile_lcdc_chan *ch = info->par;
1381 struct sh_mobile_lcdc_priv *p = ch->lcdc;
1382
1383 /* blank the screen? */
1384 if (blank > FB_BLANK_UNBLANK && ch->blank_status == FB_BLANK_UNBLANK) {
1385 struct fb_fillrect rect = {
1386 .width = info->var.xres,
1387 .height = info->var.yres,
1388 };
1389 sh_mobile_lcdc_fillrect(info, &rect);
1390 }
1391 /* turn clocks on? */
1392 if (blank <= FB_BLANK_NORMAL && ch->blank_status > FB_BLANK_NORMAL) {
1393 sh_mobile_lcdc_clk_on(p);
1394 }
1395 /* turn clocks off? */
1396 if (blank > FB_BLANK_NORMAL && ch->blank_status <= FB_BLANK_NORMAL) {
1397 /* make sure the screen is updated with the black fill before
1398 * switching the clocks off. one vsync is not enough since
1399 * blanking may occur in the middle of a refresh. deferred io
1400 * mode will reenable the clocks and update the screen in time,
1401 * so it does not need this. */
1402 if (!info->fbdefio) {
1403 sh_mobile_wait_for_vsync(info);
1404 sh_mobile_wait_for_vsync(info);
1405 }
1406 sh_mobile_lcdc_clk_off(p);
1407 }
1408
1409 ch->blank_status = blank;
1410 return 0;
1411}
1412
cfb4f5d1 1413static struct fb_ops sh_mobile_lcdc_ops = {
9dd38819 1414 .owner = THIS_MODULE,
cfb4f5d1 1415 .fb_setcolreg = sh_mobile_lcdc_setcolreg,
2540c111
MD		 1416 .fb_read = fb_sys_read,
1417 .fb_write = fb_sys_write,
8564557a
MD		 1418 .fb_fillrect = sh_mobile_lcdc_fillrect,
1419 .fb_copyarea = sh_mobile_lcdc_copyarea,
1420 .fb_imageblit = sh_mobile_lcdc_imageblit,
8857b9aa 1421 .fb_blank = sh_mobile_lcdc_blank,
9dd38819 1422 .fb_pan_display = sh_mobile_fb_pan_display,
40331b21 1423 .fb_ioctl = sh_mobile_ioctl,
dd210503
GL		 1424 .fb_open = sh_mobile_open,
1425 .fb_release = sh_mobile_release,
1426 .fb_check_var = sh_mobile_check_var,
ed5bebf2 1427 .fb_set_par = sh_mobile_set_par,
cfb4f5d1
MD		 1428};
1429
f1f60b5f
LP		 1430/* -----------------------------------------------------------------------------
1431 * Backlight
1432 */
1433
3b0fd9d7
AC		 1434static int sh_mobile_lcdc_update_bl(struct backlight_device *bdev)
1435{
1436 struct sh_mobile_lcdc_chan *ch = bl_get_data(bdev);
3b0fd9d7
AC		 1437 int brightness = bdev->props.brightness;
1438
1439 if (bdev->props.power != FB_BLANK_UNBLANK ||
1440 bdev->props.state & (BL_CORE_SUSPENDED | BL_CORE_FBBLANK))
1441 brightness = 0;
1442
43059b0f 1443 return ch->cfg.bl_info.set_brightness(brightness);
3b0fd9d7
AC		 1444}
1445
1446static int sh_mobile_lcdc_get_brightness(struct backlight_device *bdev)
1447{
1448 struct sh_mobile_lcdc_chan *ch = bl_get_data(bdev);
3b0fd9d7 1449
43059b0f 1450 return ch->cfg.bl_info.get_brightness();
3b0fd9d7
AC		 1451}
1452
1453static int sh_mobile_lcdc_check_fb(struct backlight_device *bdev,
1454 struct fb_info *info)
1455{
1456 return (info->bl_dev == bdev);
1457}
1458
1459static struct backlight_ops sh_mobile_lcdc_bl_ops = {
1460 .options = BL_CORE_SUSPENDRESUME,
1461 .update_status = sh_mobile_lcdc_update_bl,
1462 .get_brightness = sh_mobile_lcdc_get_brightness,
1463 .check_fb = sh_mobile_lcdc_check_fb,
1464};
1465
1466static struct backlight_device *sh_mobile_lcdc_bl_probe(struct device *parent,
1467 struct sh_mobile_lcdc_chan *ch)
1468{
1469 struct backlight_device *bl;
1470
1471 bl = backlight_device_register(ch->cfg.bl_info.name, parent, ch,
1472 &sh_mobile_lcdc_bl_ops, NULL);
beee1f20
DC		 1473 if (IS_ERR(bl)) {
1474 dev_err(parent, "unable to register backlight device: %ld\n",
1475 PTR_ERR(bl));
3b0fd9d7
AC		 1476 return NULL;
1477 }
1478
1479 bl->props.max_brightness = ch->cfg.bl_info.max_brightness;
1480 bl->props.brightness = bl->props.max_brightness;
1481 backlight_update_status(bl);
1482
1483 return bl;
1484}
1485
1486static void sh_mobile_lcdc_bl_remove(struct backlight_device *bdev)
1487{
1488 backlight_device_unregister(bdev);
1489}
1490
f1f60b5f
LP		 1491/* -----------------------------------------------------------------------------
1492 * Power management
1493 */
1494
2feb075a
MD		 1495static int sh_mobile_lcdc_suspend(struct device *dev)
1496{
1497 struct platform_device *pdev = to_platform_device(dev);
1498
1499 sh_mobile_lcdc_stop(platform_get_drvdata(pdev));
1500 return 0;
1501}
1502
1503static int sh_mobile_lcdc_resume(struct device *dev)
1504{
1505 struct platform_device *pdev = to_platform_device(dev);
1506
1507 return sh_mobile_lcdc_start(platform_get_drvdata(pdev));
1508}
1509
0246c471
MD		 1510static int sh_mobile_lcdc_runtime_suspend(struct device *dev)
1511{
1512 struct platform_device *pdev = to_platform_device(dev);
2427bb24 1513 struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
0246c471
MD		 1514
1515 /* turn off LCDC hardware */
2427bb24
LP		 1516 lcdc_write(priv, _LDCNT1R, 0);
1517
0246c471
MD		 1518 return 0;
1519}
1520
1521static int sh_mobile_lcdc_runtime_resume(struct device *dev)
1522{
1523 struct platform_device *pdev = to_platform_device(dev);
2427bb24 1524 struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
0246c471 1525
2427bb24 1526 __sh_mobile_lcdc_start(priv);
0246c471
MD		 1527
1528 return 0;
1529}
1530
47145210 1531static const struct dev_pm_ops sh_mobile_lcdc_dev_pm_ops = {
2feb075a
MD		 1532 .suspend = sh_mobile_lcdc_suspend,
1533 .resume = sh_mobile_lcdc_resume,
0246c471
MD		 1534 .runtime_suspend = sh_mobile_lcdc_runtime_suspend,
1535 .runtime_resume = sh_mobile_lcdc_runtime_resume,
2feb075a
MD		 1536};
1537
f1f60b5f
LP		 1538/* -----------------------------------------------------------------------------
1539 * Framebuffer notifier
1540 */
1541
6de9edd5 1542/* locking: called with info->lock held */
6011bdea
GL		 1543static int sh_mobile_lcdc_notify(struct notifier_block *nb,
1544 unsigned long action, void *data)
1545{
1546 struct fb_event *event = data;
1547 struct fb_info *info = event->info;
1548 struct sh_mobile_lcdc_chan *ch = info->par;
6011bdea
GL		 1549
1550 if (&ch->lcdc->notifier != nb)
baf16374 1551 return NOTIFY_DONE;
6011bdea
GL		 1552
1553 dev_dbg(info->dev, "%s(): action = %lu, data = %p\n",
1554 __func__, action, event->data);
1555
1556 switch(action) {
1557 case FB_EVENT_SUSPEND:
37c5dcc2 1558 sh_mobile_lcdc_display_off(ch);
afe417c0 1559 sh_mobile_lcdc_stop(ch->lcdc);
6011bdea
GL		 1560 break;
1561 case FB_EVENT_RESUME:
dd210503
GL		 1562 mutex_lock(&ch->open_lock);
1563 sh_mobile_fb_reconfig(info);
1564 mutex_unlock(&ch->open_lock);
6011bdea 1565
37c5dcc2 1566 sh_mobile_lcdc_display_on(ch);
ebe5e12d 1567 sh_mobile_lcdc_start(ch->lcdc);
6011bdea
GL		 1568 }
1569
baf16374 1570 return NOTIFY_OK;
6011bdea
GL		 1571}
1572
f1f60b5f
LP		 1573/* -----------------------------------------------------------------------------
1574 * Probe/remove and driver init/exit
1575 */
1576
217e9c43 1577static const struct fb_videomode default_720p __devinitconst = {
f1f60b5f
LP		 1578 .name = "HDMI 720p",
1579 .xres = 1280,
1580 .yres = 720,
1581
1582 .left_margin = 220,
1583 .right_margin = 110,
1584 .hsync_len = 40,
1585
1586 .upper_margin = 20,
1587 .lower_margin = 5,
1588 .vsync_len = 5,
1589
1590 .pixclock = 13468,
1591 .refresh = 60,
1592 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
1593};
1594
b4bee692
LP		 1595static int sh_mobile_lcdc_remove(struct platform_device *pdev)
1596{
1597 struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
1598 struct fb_info *info;
1599 int i;
1600
1601 fb_unregister_client(&priv->notifier);
1602
1603 for (i = 0; i < ARRAY_SIZE(priv->ch); i++)
1604 if (priv->ch[i].info && priv->ch[i].info->dev)
1605 unregister_framebuffer(priv->ch[i].info);
1606
1607 sh_mobile_lcdc_stop(priv);
1608
1609 for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
9a2985e7 1610 struct sh_mobile_lcdc_chan *ch = &priv->ch[i];
b4bee692 1611
9a2985e7 1612 info = ch->info;
b4bee692
LP		 1613 if (!info || !info->device)
1614 continue;
1615
e34d0bbb
LP		 1616 if (ch->tx_dev) {
1617 ch->tx_dev->lcdc = NULL;
9a2985e7 1618 module_put(ch->cfg.tx_dev->dev.driver->owner);
e34d0bbb 1619 }
9a2985e7
LP		 1620
1621 if (ch->sglist)
1622 vfree(ch->sglist);
b4bee692
LP		 1623
1624 if (info->screen_base)
1625 dma_free_coherent(&pdev->dev, info->fix.smem_len,
9a2985e7 1626 info->screen_base, ch->dma_handle);
b4bee692
LP		 1627 fb_dealloc_cmap(&info->cmap);
1628 framebuffer_release(info);
1629 }
1630
1631 for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
1632 if (priv->ch[i].bl)
1633 sh_mobile_lcdc_bl_remove(priv->ch[i].bl);
1634 }
1635
4774c12a
LP		 1636 if (priv->dot_clk) {
1637 pm_runtime_disable(&pdev->dev);
b4bee692 1638 clk_put(priv->dot_clk);
4774c12a 1639 }
b4bee692
LP		 1640
1641 if (priv->base)
1642 iounmap(priv->base);
1643
1644 if (priv->irq)
1645 free_irq(priv->irq, priv);
1646 kfree(priv);
1647 return 0;
1648}
cfb4f5d1 1649
217e9c43 1650static int __devinit sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan *ch)
f1f60b5f
LP		 1651{
1652 int interface_type = ch->cfg.interface_type;
1653
1654 switch (interface_type) {
1655 case RGB8:
1656 case RGB9:
1657 case RGB12A:
1658 case RGB12B:
1659 case RGB16:
1660 case RGB18:
1661 case RGB24:
1662 case SYS8A:
1663 case SYS8B:
1664 case SYS8C:
1665 case SYS8D:
1666 case SYS9:
1667 case SYS12:
1668 case SYS16A:
1669 case SYS16B:
1670 case SYS16C:
1671 case SYS18:
1672 case SYS24:
1673 break;
1674 default:
1675 return -EINVAL;
1676 }
1677
1678 /* SUBLCD only supports SYS interface */
1679 if (lcdc_chan_is_sublcd(ch)) {
1680 if (!(interface_type & LDMT1R_IFM))
1681 return -EINVAL;
1682
1683 interface_type &= ~LDMT1R_IFM;
1684 }
1685
1686 ch->ldmt1r_value = interface_type;
1687 return 0;
1688}
1689
0a7f17aa
LP		 1690static int __devinit
1691sh_mobile_lcdc_channel_init(struct sh_mobile_lcdc_priv *priv,
1692 struct sh_mobile_lcdc_chan *ch)
cfb4f5d1 1693{
105784bb 1694 const struct sh_mobile_lcdc_format_info *format;
3ce05599
LP		 1695 struct sh_mobile_lcdc_chan_cfg *cfg = &ch->cfg;
1696 const struct fb_videomode *max_mode;
1697 const struct fb_videomode *mode;
1698 struct fb_var_screeninfo *var;
cfb4f5d1 1699 struct fb_info *info;
3ce05599 1700 unsigned int max_size;
93ff2598 1701 int num_modes;
3ce05599
LP		 1702 void *buf;
1703 int ret;
1704 int i;
1705
a67472ad 1706 mutex_init(&ch->open_lock);
ecd29947 1707 ch->notify = sh_mobile_lcdc_display_notify;
a67472ad 1708
105784bb
LP		 1709 /* Validate the format. */
1710 format = sh_mobile_format_info(cfg->fourcc);
1711 if (format == NULL) {
1712 dev_err(priv->dev, "Invalid FOURCC %08x.\n", cfg->fourcc);
1713 return -EINVAL;
1714 }
1715
fc9e78e6
LP		 1716 ch->format = format;
1717
a67472ad 1718 /* Allocate the frame buffer device. */
0a7f17aa 1719 ch->info = framebuffer_alloc(0, priv->dev);
3ce05599 1720 if (!ch->info) {
0a7f17aa 1721 dev_err(priv->dev, "unable to allocate fb_info\n");
3ce05599
LP		 1722 return -ENOMEM;
1723 }
1724
1725 info = ch->info;
3ce05599
LP		 1726 info->fbops = &sh_mobile_lcdc_ops;
1727 info->par = ch;
a67472ad
LP		 1728 info->pseudo_palette = &ch->pseudo_palette;
1729 info->flags = FBINFO_FLAG_DEFAULT;
3ce05599
LP		 1730
1731 /* Iterate through the modes to validate them and find the highest
1732 * resolution.
1733 */
1734 max_mode = NULL;
1735 max_size = 0;
1736
93ff2598 1737 for (i = 0, mode = cfg->lcd_modes; i < cfg->num_modes; i++, mode++) {
3ce05599
LP		 1738 unsigned int size = mode->yres * mode->xres;
1739
edd153a3
LP		 1740 /* NV12/NV21 buffers must have even number of lines */
1741 if ((cfg->fourcc == V4L2_PIX_FMT_NV12 ||
1742 cfg->fourcc == V4L2_PIX_FMT_NV21) && (mode->yres & 0x1)) {
0a7f17aa
LP		 1743 dev_err(priv->dev, "yres must be multiple of 2 for "
1744 "YCbCr420 mode.\n");
3ce05599
LP		 1745 return -EINVAL;
1746 }
1747
1748 if (size > max_size) {
1749 max_mode = mode;
1750 max_size = size;
1751 }
1752 }
1753
1754 if (!max_size)
1755 max_size = MAX_XRES * MAX_YRES;
1756 else
0a7f17aa 1757 dev_dbg(priv->dev, "Found largest videomode %ux%u\n",
3ce05599
LP		 1758 max_mode->xres, max_mode->yres);
1759
a67472ad 1760 /* Create the mode list. */
93ff2598 1761 if (cfg->lcd_modes == NULL) {
3ce05599 1762 mode = &default_720p;
93ff2598 1763 num_modes = 1;
3ce05599 1764 } else {
93ff2598
LP		 1765 mode = cfg->lcd_modes;
1766 num_modes = cfg->num_modes;
3ce05599
LP		 1767 }
1768
93ff2598 1769 fb_videomode_to_modelist(mode, num_modes, &info->modelist);
3ce05599 1770
13f80eea
LP		 1771 /* Initialize the transmitter device if present. */
1772 if (cfg->tx_dev) {
1773 if (!cfg->tx_dev->dev.driver ||
1774 !try_module_get(cfg->tx_dev->dev.driver->owner)) {
1775 dev_warn(priv->dev,
1776 "unable to get transmitter device\n");
1777 return -EINVAL;
1778 }
1779 ch->tx_dev = platform_get_drvdata(cfg->tx_dev);
1780 ch->tx_dev->lcdc = ch;
1781 ch->tx_dev->def_mode = *mode;
1782 }
1783
a67472ad
LP		 1784 /* Initialize variable screen information using the first mode as
1785 * default. The default Y virtual resolution is twice the panel size to
1786 * allow for double-buffering.
1787 */
1788 var = &info->var;
3ce05599 1789 fb_videomode_to_var(var, mode);
afaad83b
LP		 1790 var->width = cfg->panel_cfg.width;
1791 var->height = cfg->panel_cfg.height;
3ce05599
LP		 1792 var->yres_virtual = var->yres * 2;
1793 var->activate = FB_ACTIVATE_NOW;
1794
105784bb
LP		 1795 /* Use the legacy API by default for RGB formats, and the FOURCC API
1796 * for YUV formats.
1797 */
1798 if (!format->yuv)
1799 var->bits_per_pixel = format->bpp;
1800 else
edd153a3 1801 var->grayscale = cfg->fourcc;
edd153a3
LP		 1802
1803 /* Make sure the memory size check won't fail. smem_len is initialized
1804 * later based on var.
1805 */
1806 info->fix.smem_len = UINT_MAX;
a67472ad 1807 ret = sh_mobile_check_var(var, info);
3ce05599
LP		 1808 if (ret)
1809 return ret;
1810
edd153a3
LP		 1811 max_size = max_size * var->bits_per_pixel / 8 * 2;
1812
a67472ad 1813 /* Allocate frame buffer memory and color map. */
0a7f17aa
LP		 1814 buf = dma_alloc_coherent(priv->dev, max_size, &ch->dma_handle,
1815 GFP_KERNEL);
3ce05599 1816 if (!buf) {
0a7f17aa 1817 dev_err(priv->dev, "unable to allocate buffer\n");
3ce05599
LP		 1818 return -ENOMEM;
1819 }
1820
3ce05599
LP		 1821 ret = fb_alloc_cmap(&info->cmap, PALETTE_NR, 0);
1822 if (ret < 0) {
0a7f17aa
LP		 1823 dev_err(priv->dev, "unable to allocate cmap\n");
1824 dma_free_coherent(priv->dev, max_size, buf, ch->dma_handle);
3ce05599
LP		 1825 return ret;
1826 }
1827
edd153a3
LP		 1828 /* Initialize fixed screen information. Restrict pan to 2 lines steps
1829 * for NV12 and NV21.
1830 */
1831 info->fix = sh_mobile_lcdc_fix;
3ce05599 1832 info->fix.smem_start = ch->dma_handle;
edd153a3
LP		 1833 info->fix.smem_len = max_size;
1834 if (cfg->fourcc == V4L2_PIX_FMT_NV12 ||
1835 cfg->fourcc == V4L2_PIX_FMT_NV21)
1836 info->fix.ypanstep = 2;
1837
105784bb 1838 if (format->yuv) {
3ce05599 1839 info->fix.line_length = var->xres;
edd153a3
LP		 1840 info->fix.visual = FB_VISUAL_FOURCC;
1841 } else {
1842 info->fix.line_length = var->xres * var->bits_per_pixel / 8;
1843 info->fix.visual = FB_VISUAL_TRUECOLOR;
1844 }
3ce05599
LP		 1845
1846 info->screen_base = buf;
0a7f17aa 1847 info->device = priv->dev;
2d04559d
LP		 1848
1849 ch->display.width = cfg->panel_cfg.width;
1850 ch->display.height = cfg->panel_cfg.height;
1851 ch->display.mode = *mode;
3ce05599
LP		 1852
1853 return 0;
1854}
1855
1856static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev)
1857{
01ac25b5 1858 struct sh_mobile_lcdc_info *pdata = pdev->dev.platform_data;
3ce05599 1859 struct sh_mobile_lcdc_priv *priv;
cfb4f5d1 1860 struct resource *res;
3ce05599 1861 int num_channels;
cfb4f5d1 1862 int error;
3ce05599 1863 int i;
cfb4f5d1 1864
01ac25b5 1865 if (!pdata) {
cfb4f5d1 1866 dev_err(&pdev->dev, "no platform data defined\n");
8bed9055 1867 return -EINVAL;
cfb4f5d1
MD		 1868 }
1869
1870 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8564557a
MD		 1871 i = platform_get_irq(pdev, 0);
1872 if (!res || i < 0) {
1873 dev_err(&pdev->dev, "cannot get platform resources\n");
8bed9055 1874 return -ENOENT;
cfb4f5d1
MD		 1875 }
1876
1877 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1878 if (!priv) {
1879 dev_err(&pdev->dev, "cannot allocate device data\n");
8bed9055 1880 return -ENOMEM;
cfb4f5d1
MD		 1881 }
1882
4774c12a
LP		 1883 priv->dev = &pdev->dev;
1884 priv->meram_dev = pdata->meram_dev;
8bed9055
GL		 1885 platform_set_drvdata(pdev, priv);
1886
f8798ccb 1887 error = request_irq(i, sh_mobile_lcdc_irq, 0,
7ad33e74 1888 dev_name(&pdev->dev), priv);
8564557a
MD		 1889 if (error) {
1890 dev_err(&pdev->dev, "unable to request irq\n");
1891 goto err1;
1892 }
1893
1894 priv->irq = i;
5ef6b505 1895 atomic_set(&priv->hw_usecnt, -1);
cfb4f5d1 1896
3ce05599
LP		 1897 for (i = 0, num_channels = 0; i < ARRAY_SIZE(pdata->ch); i++) {
1898 struct sh_mobile_lcdc_chan *ch = priv->ch + num_channels;
cfb4f5d1 1899
01ac25b5
GL		 1900 ch->lcdc = priv;
1901 memcpy(&ch->cfg, &pdata->ch[i], sizeof(pdata->ch[i]));
cfb4f5d1 1902
01ac25b5 1903 error = sh_mobile_lcdc_check_interface(ch);
cfb4f5d1
MD		 1904 if (error) {
1905 dev_err(&pdev->dev, "unsupported interface type\n");
1906 goto err1;
1907 }
01ac25b5
GL		 1908 init_waitqueue_head(&ch->frame_end_wait);
1909 init_completion(&ch->vsync_completion);
1910 ch->pan_offset = 0;
cfb4f5d1 1911
3b0fd9d7
AC		 1912 /* probe the backlight is there is one defined */
1913 if (ch->cfg.bl_info.max_brightness)
1914 ch->bl = sh_mobile_lcdc_bl_probe(&pdev->dev, ch);
1915
cfb4f5d1
MD		 1916 switch (pdata->ch[i].chan) {
1917 case LCDC_CHAN_MAINLCD:
ce1c0b08 1918 ch->enabled = LDCNT2R_ME;
01ac25b5 1919 ch->reg_offs = lcdc_offs_mainlcd;
3ce05599 1920 num_channels++;
cfb4f5d1
MD		 1921 break;
1922 case LCDC_CHAN_SUBLCD:
ce1c0b08 1923 ch->enabled = LDCNT2R_SE;
01ac25b5 1924 ch->reg_offs = lcdc_offs_sublcd;
3ce05599 1925 num_channels++;
cfb4f5d1
MD		 1926 break;
1927 }
1928 }
1929
3ce05599 1930 if (!num_channels) {
cfb4f5d1
MD		 1931 dev_err(&pdev->dev, "no channels defined\n");
1932 error = -EINVAL;
1933 goto err1;
1934 }
1935
edd153a3 1936 /* for dual channel LCDC (MAIN + SUB) force shared format setting */
3ce05599 1937 if (num_channels == 2)
edd153a3 1938 priv->forced_fourcc = pdata->ch[0].fourcc;
417d4827 1939
dba6f385
GL		 1940 priv->base = ioremap_nocache(res->start, resource_size(res));
1941 if (!priv->base)
1942 goto err1;
1943
0a7f17aa 1944 error = sh_mobile_lcdc_setup_clocks(priv, pdata->clock_source);
cfb4f5d1
MD		 1945 if (error) {
1946 dev_err(&pdev->dev, "unable to setup clocks\n");
1947 goto err1;
1948 }
1949
4774c12a
LP		 1950 /* Enable runtime PM. */
1951 pm_runtime_enable(&pdev->dev);
7caa4342 1952
3ce05599 1953 for (i = 0; i < num_channels; i++) {
01ac25b5 1954 struct sh_mobile_lcdc_chan *ch = priv->ch + i;
c44f9f76 1955
0a7f17aa 1956 error = sh_mobile_lcdc_channel_init(priv, ch);
cfb4f5d1 1957 if (error)
3ce05599 1958 goto err1;
cfb4f5d1
MD		 1959 }
1960
cfb4f5d1
MD		 1961 error = sh_mobile_lcdc_start(priv);
1962 if (error) {
1963 dev_err(&pdev->dev, "unable to start hardware\n");
1964 goto err1;
1965 }
1966
3ce05599 1967 for (i = 0; i < num_channels; i++) {
1c6a307a 1968 struct sh_mobile_lcdc_chan *ch = priv->ch + i;
3ce05599 1969 struct fb_info *info = ch->info;
1c6a307a
PM		 1970
1971 if (info->fbdefio) {
8bed9055 1972 ch->sglist = vmalloc(sizeof(struct scatterlist) *
1c6a307a 1973 info->fix.smem_len >> PAGE_SHIFT);
8bed9055 1974 if (!ch->sglist) {
1c6a307a
PM		 1975 dev_err(&pdev->dev, "cannot allocate sglist\n");
1976 goto err1;
1977 }
1978 }
1979
3b0fd9d7
AC		 1980 info->bl_dev = ch->bl;
1981
1c6a307a 1982 error = register_framebuffer(info);
cfb4f5d1
MD		 1983 if (error < 0)
1984 goto err1;
cfb4f5d1 1985
0a7f17aa 1986 dev_info(&pdev->dev, "registered %s/%s as %dx%d %dbpp.\n",
edd153a3
LP		 1987 pdev->name, (ch->cfg.chan == LCDC_CHAN_MAINLCD) ?
1988 "mainlcd" : "sublcd", info->var.xres, info->var.yres,
1989 info->var.bits_per_pixel);
8564557a
MD		 1990
1991 /* deferred io mode: disable clock to save power */
6011bdea 1992 if (info->fbdefio || info->state == FBINFO_STATE_SUSPENDED)
8564557a 1993 sh_mobile_lcdc_clk_off(priv);
cfb4f5d1
MD		 1994 }
1995
6011bdea
GL		 1996 /* Failure ignored */
1997 priv->notifier.notifier_call = sh_mobile_lcdc_notify;
1998 fb_register_client(&priv->notifier);
1999
cfb4f5d1 2000 return 0;
8bed9055 2001err1:
cfb4f5d1 2002 sh_mobile_lcdc_remove(pdev);
8bed9055 2003
cfb4f5d1
MD		 2004 return error;
2005}
2006
cfb4f5d1
MD		 2007static struct platform_driver sh_mobile_lcdc_driver = {
2008 .driver = {
2009 .name = "sh_mobile_lcdc_fb",
2010 .owner = THIS_MODULE,
2feb075a 2011 .pm = &sh_mobile_lcdc_dev_pm_ops,
cfb4f5d1
MD		 2012 },
2013 .probe = sh_mobile_lcdc_probe,
2014 .remove = sh_mobile_lcdc_remove,
2015};
2016
4277f2c4 2017module_platform_driver(sh_mobile_lcdc_driver);
cfb4f5d1
MD		 2018
2019MODULE_DESCRIPTION("SuperH Mobile LCDC Framebuffer driver");
2020MODULE_AUTHOR("Magnus Damm <damm@opensource.se>");
2021MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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