tridentfb: move global flat panel variable into structure
[deliverable/linux.git] / drivers / video / tridentfb.c
CommitLineData
1da177e4
LT
1/*
2 * Frame buffer driver for Trident Blade and Image series
3 *
245a2c2c 4 * Copyright 2001, 2002 - Jani Monoses <jani@iv.ro>
1da177e4
LT
5 *
6 *
7 * CREDITS:(in order of appearance)
245a2c2c
KH
8 * skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video
9 * Special thanks ;) to Mattia Crivellini <tia@mclink.it>
10 * much inspired by the XFree86 4.x Trident driver sources
11 * by Alan Hourihane the FreeVGA project
12 * Francesco Salvestrini <salvestrini@users.sf.net> XP support,
13 * code, suggestions
1da177e4 14 * TODO:
245a2c2c
KH
15 * timing value tweaking so it looks good on every monitor in every mode
16 * TGUI acceleration
1da177e4
LT
17 */
18
1da177e4
LT
19#include <linux/module.h>
20#include <linux/fb.h>
21#include <linux/init.h>
22#include <linux/pci.h>
23
24#include <linux/delay.h>
25#include <video/trident.h>
26
122e8ad3 27#define VERSION "0.7.9-NEWAPI"
1da177e4
LT
28
29struct tridentfb_par {
245a2c2c 30 void __iomem *io_virt; /* iospace virtual memory address */
ea8ee55c 31 u32 pseudo_pal[16];
122e8ad3 32 int chip_id;
6eed8e1e 33 int flatpanel;
1da177e4
LT
34};
35
245a2c2c 36static unsigned char eng_oper; /* engine operation... */
1da177e4
LT
37static struct fb_ops tridentfb_ops;
38
1da177e4 39static struct fb_fix_screeninfo tridentfb_fix = {
245a2c2c 40 .id = "Trident",
1da177e4
LT
41 .type = FB_TYPE_PACKED_PIXELS,
42 .ypanstep = 1,
43 .visual = FB_VISUAL_PSEUDOCOLOR,
44 .accel = FB_ACCEL_NONE,
45};
46
1da177e4
LT
47/* defaults which are normally overriden by user values */
48
49/* video mode */
07f41e45 50static char *mode_option __devinitdata = "640x480";
6eed8e1e 51static int bpp __devinitdata = 8;
1da177e4 52
6eed8e1e 53static int noaccel __devinitdata;
1da177e4
LT
54
55static int center;
56static int stretch;
57
6eed8e1e
KH
58static int fp __devinitdata;
59static int crt __devinitdata;
1da177e4 60
6eed8e1e
KH
61static int memsize __devinitdata;
62static int memdiff __devinitdata;
1da177e4
LT
63static int nativex;
64
07f41e45
KH
65module_param(mode_option, charp, 0);
66MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
9e3f0ca8
KH
67module_param_named(mode, mode_option, charp, 0);
68MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)");
1da177e4
LT
69module_param(bpp, int, 0);
70module_param(center, int, 0);
71module_param(stretch, int, 0);
72module_param(noaccel, int, 0);
73module_param(memsize, int, 0);
74module_param(memdiff, int, 0);
75module_param(nativex, int, 0);
76module_param(fp, int, 0);
6eed8e1e 77MODULE_PARM_DESC(fp, "Define if flatpanel is connected");
1da177e4 78module_param(crt, int, 0);
6eed8e1e 79MODULE_PARM_DESC(crt, "Define if CRT is connected");
1da177e4 80
1da177e4
LT
81static int is3Dchip(int id)
82{
245a2c2c
KH
83 return ((id == BLADE3D) || (id == CYBERBLADEE4) ||
84 (id == CYBERBLADEi7) || (id == CYBERBLADEi7D) ||
85 (id == CYBER9397) || (id == CYBER9397DVD) ||
86 (id == CYBER9520) || (id == CYBER9525DVD) ||
87 (id == IMAGE975) || (id == IMAGE985) ||
88 (id == CYBERBLADEi1) || (id == CYBERBLADEi1D) ||
89 (id == CYBERBLADEAi1) || (id == CYBERBLADEAi1D) ||
90 (id == CYBERBLADEXPm8) || (id == CYBERBLADEXPm16) ||
91 (id == CYBERBLADEXPAi1));
1da177e4
LT
92}
93
94static int iscyber(int id)
95{
96 switch (id) {
245a2c2c
KH
97 case CYBER9388:
98 case CYBER9382:
99 case CYBER9385:
100 case CYBER9397:
101 case CYBER9397DVD:
102 case CYBER9520:
103 case CYBER9525DVD:
104 case CYBERBLADEE4:
105 case CYBERBLADEi7D:
106 case CYBERBLADEi1:
107 case CYBERBLADEi1D:
108 case CYBERBLADEAi1:
109 case CYBERBLADEAi1D:
110 case CYBERBLADEXPAi1:
111 return 1;
1da177e4 112
245a2c2c
KH
113 case CYBER9320:
114 case TGUI9660:
115 case IMAGE975:
116 case IMAGE985:
117 case BLADE3D:
118 case CYBERBLADEi7: /* VIA MPV4 integrated version */
119
120 default:
121 /* case CYBERBLDAEXPm8: Strange */
122 /* case CYBERBLDAEXPm16: Strange */
123 return 0;
1da177e4
LT
124 }
125}
126
245a2c2c 127#define CRT 0x3D0 /* CRTC registers offset for color display */
1da177e4 128
306fa6f6
KH
129static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg)
130{
131 fb_writeb(val, p->io_virt + reg);
132}
1da177e4 133
306fa6f6
KH
134static inline u8 t_inb(struct tridentfb_par *p, u16 reg)
135{
136 return fb_readb(p->io_virt + reg);
137}
1da177e4
LT
138
139static struct accel_switch {
306fa6f6
KH
140 void (*init_accel) (struct tridentfb_par *, int, int);
141 void (*wait_engine) (struct tridentfb_par *);
142 void (*fill_rect)
143 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
144 void (*copy_rect)
145 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
1da177e4
LT
146} *acc;
147
306fa6f6
KH
148static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v)
149{
150 fb_writel(v, par->io_virt + r);
151}
152
153static inline u32 readmmr(struct tridentfb_par *par, u16 r)
154{
155 return fb_readl(par->io_virt + r);
156}
1da177e4 157
1da177e4
LT
158/*
159 * Blade specific acceleration.
160 */
161
245a2c2c 162#define point(x, y) ((y) << 16 | (x))
1da177e4
LT
163#define STA 0x2120
164#define CMD 0x2144
165#define ROP 0x2148
166#define CLR 0x2160
167#define SR1 0x2100
168#define SR2 0x2104
169#define DR1 0x2108
170#define DR2 0x210C
171
172#define ROP_S 0xCC
173
306fa6f6 174static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp)
1da177e4 175{
245a2c2c
KH
176 int v1 = (pitch >> 3) << 20;
177 int tmp = 0, v2;
1da177e4 178 switch (bpp) {
245a2c2c
KH
179 case 8:
180 tmp = 0;
181 break;
182 case 15:
183 tmp = 5;
184 break;
185 case 16:
186 tmp = 1;
187 break;
188 case 24:
189 case 32:
190 tmp = 2;
191 break;
1da177e4 192 }
245a2c2c 193 v2 = v1 | (tmp << 29);
306fa6f6
KH
194 writemmr(par, 0x21C0, v2);
195 writemmr(par, 0x21C4, v2);
196 writemmr(par, 0x21B8, v2);
197 writemmr(par, 0x21BC, v2);
198 writemmr(par, 0x21D0, v1);
199 writemmr(par, 0x21D4, v1);
200 writemmr(par, 0x21C8, v1);
201 writemmr(par, 0x21CC, v1);
202 writemmr(par, 0x216C, 0);
1da177e4
LT
203}
204
306fa6f6 205static void blade_wait_engine(struct tridentfb_par *par)
1da177e4 206{
306fa6f6 207 while (readmmr(par, STA) & 0xFA800000) ;
1da177e4
LT
208}
209
306fa6f6
KH
210static void blade_fill_rect(struct tridentfb_par *par,
211 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
1da177e4 212{
306fa6f6
KH
213 writemmr(par, CLR, c);
214 writemmr(par, ROP, rop ? 0x66 : ROP_S);
215 writemmr(par, CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2);
1da177e4 216
306fa6f6
KH
217 writemmr(par, DR1, point(x, y));
218 writemmr(par, DR2, point(x + w - 1, y + h - 1));
1da177e4
LT
219}
220
306fa6f6
KH
221static void blade_copy_rect(struct tridentfb_par *par,
222 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
1da177e4 223{
245a2c2c 224 u32 s1, s2, d1, d2;
1da177e4 225 int direction = 2;
245a2c2c
KH
226 s1 = point(x1, y1);
227 s2 = point(x1 + w - 1, y1 + h - 1);
228 d1 = point(x2, y2);
229 d2 = point(x2 + w - 1, y2 + h - 1);
1da177e4
LT
230
231 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
245a2c2c 232 direction = 0;
1da177e4 233
306fa6f6
KH
234 writemmr(par, ROP, ROP_S);
235 writemmr(par, CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction);
1da177e4 236
306fa6f6
KH
237 writemmr(par, SR1, direction ? s2 : s1);
238 writemmr(par, SR2, direction ? s1 : s2);
239 writemmr(par, DR1, direction ? d2 : d1);
240 writemmr(par, DR2, direction ? d1 : d2);
1da177e4
LT
241}
242
243static struct accel_switch accel_blade = {
244 blade_init_accel,
245 blade_wait_engine,
246 blade_fill_rect,
247 blade_copy_rect,
248};
249
1da177e4
LT
250/*
251 * BladeXP specific acceleration functions
252 */
253
254#define ROP_P 0xF0
245a2c2c 255#define masked_point(x, y) ((y & 0xffff)<<16|(x & 0xffff))
1da177e4 256
306fa6f6 257static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp)
1da177e4 258{
245a2c2c 259 int tmp = 0, v1;
1da177e4
LT
260 unsigned char x = 0;
261
262 switch (bpp) {
245a2c2c
KH
263 case 8:
264 x = 0;
265 break;
266 case 16:
267 x = 1;
268 break;
269 case 24:
270 x = 3;
271 break;
272 case 32:
273 x = 2;
274 break;
1da177e4
LT
275 }
276
277 switch (pitch << (bpp >> 3)) {
245a2c2c
KH
278 case 8192:
279 case 512:
280 x |= 0x00;
281 break;
282 case 1024:
283 x |= 0x04;
284 break;
285 case 2048:
286 x |= 0x08;
287 break;
288 case 4096:
289 x |= 0x0C;
290 break;
1da177e4
LT
291 }
292
306fa6f6 293 t_outb(par, x, 0x2125);
1da177e4
LT
294
295 eng_oper = x | 0x40;
296
297 switch (bpp) {
245a2c2c
KH
298 case 8:
299 tmp = 18;
300 break;
301 case 15:
302 case 16:
303 tmp = 19;
304 break;
305 case 24:
306 case 32:
307 tmp = 20;
308 break;
1da177e4
LT
309 }
310
311 v1 = pitch << tmp;
312
306fa6f6
KH
313 writemmr(par, 0x2154, v1);
314 writemmr(par, 0x2150, v1);
315 t_outb(par, 3, 0x2126);
1da177e4
LT
316}
317
306fa6f6 318static void xp_wait_engine(struct tridentfb_par *par)
1da177e4
LT
319{
320 int busy;
321 int count, timeout;
322
323 count = 0;
324 timeout = 0;
325 for (;;) {
306fa6f6 326 busy = t_inb(par, STA) & 0x80;
1da177e4
LT
327 if (busy != 0x80)
328 return;
329 count++;
330 if (count == 10000000) {
331 /* Timeout */
332 count = 9990000;
333 timeout++;
334 if (timeout == 8) {
335 /* Reset engine */
306fa6f6 336 t_outb(par, 0x00, 0x2120);
1da177e4
LT
337 return;
338 }
339 }
340 }
341}
342
306fa6f6
KH
343static void xp_fill_rect(struct tridentfb_par *par,
344 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
1da177e4 345{
306fa6f6
KH
346 writemmr(par, 0x2127, ROP_P);
347 writemmr(par, 0x2158, c);
348 writemmr(par, 0x2128, 0x4000);
349 writemmr(par, 0x2140, masked_point(h, w));
350 writemmr(par, 0x2138, masked_point(y, x));
351 t_outb(par, 0x01, 0x2124);
352 t_outb(par, eng_oper, 0x2125);
1da177e4
LT
353}
354
306fa6f6
KH
355static void xp_copy_rect(struct tridentfb_par *par,
356 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
1da177e4
LT
357{
358 int direction;
245a2c2c 359 u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
1da177e4
LT
360
361 direction = 0x0004;
245a2c2c 362
1da177e4
LT
363 if ((x1 < x2) && (y1 == y2)) {
364 direction |= 0x0200;
365 x1_tmp = x1 + w - 1;
366 x2_tmp = x2 + w - 1;
367 } else {
368 x1_tmp = x1;
369 x2_tmp = x2;
370 }
245a2c2c 371
1da177e4
LT
372 if (y1 < y2) {
373 direction |= 0x0100;
374 y1_tmp = y1 + h - 1;
375 y2_tmp = y2 + h - 1;
245a2c2c 376 } else {
1da177e4
LT
377 y1_tmp = y1;
378 y2_tmp = y2;
379 }
380
306fa6f6
KH
381 writemmr(par, 0x2128, direction);
382 t_outb(par, ROP_S, 0x2127);
383 writemmr(par, 0x213C, masked_point(y1_tmp, x1_tmp));
384 writemmr(par, 0x2138, masked_point(y2_tmp, x2_tmp));
385 writemmr(par, 0x2140, masked_point(h, w));
386 t_outb(par, 0x01, 0x2124);
1da177e4
LT
387}
388
389static struct accel_switch accel_xp = {
245a2c2c 390 xp_init_accel,
1da177e4
LT
391 xp_wait_engine,
392 xp_fill_rect,
393 xp_copy_rect,
394};
395
1da177e4
LT
396/*
397 * Image specific acceleration functions
398 */
306fa6f6 399static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp)
1da177e4
LT
400{
401 int tmp = 0;
245a2c2c
KH
402 switch (bpp) {
403 case 8:
404 tmp = 0;
405 break;
406 case 15:
407 tmp = 5;
408 break;
409 case 16:
410 tmp = 1;
411 break;
412 case 24:
413 case 32:
414 tmp = 2;
415 break;
1da177e4 416 }
306fa6f6
KH
417 writemmr(par, 0x2120, 0xF0000000);
418 writemmr(par, 0x2120, 0x40000000 | tmp);
419 writemmr(par, 0x2120, 0x80000000);
420 writemmr(par, 0x2144, 0x00000000);
421 writemmr(par, 0x2148, 0x00000000);
422 writemmr(par, 0x2150, 0x00000000);
423 writemmr(par, 0x2154, 0x00000000);
424 writemmr(par, 0x2120, 0x60000000 | (pitch << 16) | pitch);
425 writemmr(par, 0x216C, 0x00000000);
426 writemmr(par, 0x2170, 0x00000000);
427 writemmr(par, 0x217C, 0x00000000);
428 writemmr(par, 0x2120, 0x10000000);
429 writemmr(par, 0x2130, (2047 << 16) | 2047);
1da177e4
LT
430}
431
306fa6f6 432static void image_wait_engine(struct tridentfb_par *par)
1da177e4 433{
306fa6f6 434 while (readmmr(par, 0x2164) & 0xF0000000) ;
1da177e4
LT
435}
436
306fa6f6
KH
437static void image_fill_rect(struct tridentfb_par *par,
438 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
1da177e4 439{
306fa6f6
KH
440 writemmr(par, 0x2120, 0x80000000);
441 writemmr(par, 0x2120, 0x90000000 | ROP_S);
1da177e4 442
306fa6f6 443 writemmr(par, 0x2144, c);
1da177e4 444
306fa6f6
KH
445 writemmr(par, DR1, point(x, y));
446 writemmr(par, DR2, point(x + w - 1, y + h - 1));
1da177e4 447
306fa6f6 448 writemmr(par, 0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9);
1da177e4
LT
449}
450
306fa6f6
KH
451static void image_copy_rect(struct tridentfb_par *par,
452 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
1da177e4 453{
245a2c2c 454 u32 s1, s2, d1, d2;
1da177e4 455 int direction = 2;
245a2c2c
KH
456 s1 = point(x1, y1);
457 s2 = point(x1 + w - 1, y1 + h - 1);
458 d1 = point(x2, y2);
459 d2 = point(x2 + w - 1, y2 + h - 1);
1da177e4 460
245a2c2c
KH
461 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
462 direction = 0;
463
306fa6f6
KH
464 writemmr(par, 0x2120, 0x80000000);
465 writemmr(par, 0x2120, 0x90000000 | ROP_S);
245a2c2c 466
306fa6f6
KH
467 writemmr(par, SR1, direction ? s2 : s1);
468 writemmr(par, SR2, direction ? s1 : s2);
469 writemmr(par, DR1, direction ? d2 : d1);
470 writemmr(par, DR2, direction ? d1 : d2);
471 writemmr(par, 0x2124,
472 0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction);
245a2c2c 473}
1da177e4
LT
474
475static struct accel_switch accel_image = {
476 image_init_accel,
477 image_wait_engine,
478 image_fill_rect,
479 image_copy_rect,
480};
481
482/*
483 * Accel functions called by the upper layers
484 */
485#ifdef CONFIG_FB_TRIDENT_ACCEL
245a2c2c
KH
486static void tridentfb_fillrect(struct fb_info *info,
487 const struct fb_fillrect *fr)
1da177e4 488{
306fa6f6 489 struct tridentfb_par *par = info->par;
1da177e4 490 int bpp = info->var.bits_per_pixel;
8dad46cf 491 int col = 0;
245a2c2c 492
1da177e4 493 switch (bpp) {
245a2c2c
KH
494 default:
495 case 8:
496 col |= fr->color;
497 col |= col << 8;
498 col |= col << 16;
499 break;
500 case 16:
501 col = ((u32 *)(info->pseudo_palette))[fr->color];
502 break;
503 case 32:
504 col = ((u32 *)(info->pseudo_palette))[fr->color];
505 break;
506 }
507
306fa6f6
KH
508 acc->fill_rect(par, fr->dx, fr->dy, fr->width,
509 fr->height, col, fr->rop);
510 acc->wait_engine(par);
1da177e4 511}
245a2c2c
KH
512static void tridentfb_copyarea(struct fb_info *info,
513 const struct fb_copyarea *ca)
1da177e4 514{
306fa6f6
KH
515 struct tridentfb_par *par = info->par;
516
517 acc->copy_rect(par, ca->sx, ca->sy, ca->dx, ca->dy,
518 ca->width, ca->height);
519 acc->wait_engine(par);
1da177e4
LT
520}
521#else /* !CONFIG_FB_TRIDENT_ACCEL */
522#define tridentfb_fillrect cfb_fillrect
523#define tridentfb_copyarea cfb_copyarea
524#endif /* CONFIG_FB_TRIDENT_ACCEL */
525
526
527/*
528 * Hardware access functions
529 */
530
306fa6f6 531static inline unsigned char read3X4(struct tridentfb_par *par, int reg)
1da177e4 532{
1da177e4 533 writeb(reg, par->io_virt + CRT + 4);
245a2c2c 534 return readb(par->io_virt + CRT + 5);
1da177e4
LT
535}
536
306fa6f6
KH
537static inline void write3X4(struct tridentfb_par *par, int reg,
538 unsigned char val)
1da177e4 539{
1da177e4
LT
540 writeb(reg, par->io_virt + CRT + 4);
541 writeb(val, par->io_virt + CRT + 5);
542}
543
306fa6f6 544static inline unsigned char read3C4(struct tridentfb_par *par, int reg)
1da177e4 545{
306fa6f6
KH
546 t_outb(par, reg, 0x3C4);
547 return t_inb(par, 0x3C5);
1da177e4
LT
548}
549
306fa6f6
KH
550static inline void write3C4(struct tridentfb_par *par, int reg,
551 unsigned char val)
1da177e4 552{
306fa6f6
KH
553 t_outb(par, reg, 0x3C4);
554 t_outb(par, val, 0x3C5);
1da177e4
LT
555}
556
306fa6f6 557static inline unsigned char read3CE(struct tridentfb_par *par, int reg)
1da177e4 558{
306fa6f6
KH
559 t_outb(par, reg, 0x3CE);
560 return t_inb(par, 0x3CF);
1da177e4
LT
561}
562
306fa6f6
KH
563static inline void writeAttr(struct tridentfb_par *par, int reg,
564 unsigned char val)
1da177e4 565{
306fa6f6
KH
566 fb_readb(par->io_virt + CRT + 0x0A); /* flip-flop to index */
567 t_outb(par, reg, 0x3C0);
568 t_outb(par, val, 0x3C0);
1da177e4
LT
569}
570
306fa6f6
KH
571static inline void write3CE(struct tridentfb_par *par, int reg,
572 unsigned char val)
1da177e4 573{
306fa6f6
KH
574 t_outb(par, reg, 0x3CE);
575 t_outb(par, val, 0x3CF);
1da177e4
LT
576}
577
e8ed857c 578static void enable_mmio(void)
1da177e4
LT
579{
580 /* Goto New Mode */
581 outb(0x0B, 0x3C4);
582 inb(0x3C5);
583
584 /* Unprotect registers */
585 outb(NewMode1, 0x3C4);
586 outb(0x80, 0x3C5);
245a2c2c 587
1da177e4 588 /* Enable MMIO */
245a2c2c 589 outb(PCIReg, 0x3D4);
1da177e4 590 outb(inb(0x3D5) | 0x01, 0x3D5);
e8ed857c
KH
591}
592
306fa6f6 593static void disable_mmio(struct tridentfb_par *par)
e8ed857c 594{
e8ed857c 595 /* Goto New Mode */
306fa6f6
KH
596 t_outb(par, 0x0B, 0x3C4);
597 t_inb(par, 0x3C5);
e8ed857c
KH
598
599 /* Unprotect registers */
306fa6f6
KH
600 t_outb(par, NewMode1, 0x3C4);
601 t_outb(par, 0x80, 0x3C5);
e8ed857c
KH
602
603 /* Disable MMIO */
306fa6f6
KH
604 t_outb(par, PCIReg, 0x3D4);
605 t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5);
1da177e4
LT
606}
607
306fa6f6
KH
608static void crtc_unlock(struct tridentfb_par *par)
609{
610 write3X4(par, CRTVSyncEnd, read3X4(par, CRTVSyncEnd) & 0x7F);
611}
1da177e4
LT
612
613/* Return flat panel's maximum x resolution */
306fa6f6 614static int __devinit get_nativex(struct tridentfb_par *par)
1da177e4 615{
245a2c2c 616 int x, y, tmp;
1da177e4
LT
617
618 if (nativex)
619 return nativex;
620
306fa6f6 621 tmp = (read3CE(par, VertStretch) >> 4) & 3;
1da177e4
LT
622
623 switch (tmp) {
245a2c2c
KH
624 case 0:
625 x = 1280; y = 1024;
626 break;
627 case 2:
628 x = 1024; y = 768;
629 break;
630 case 3:
631 x = 800; y = 600;
632 break;
633 case 4:
634 x = 1400; y = 1050;
635 break;
636 case 1:
637 default:
638 x = 640; y = 480;
639 break;
1da177e4
LT
640 }
641
642 output("%dx%d flat panel found\n", x, y);
643 return x;
644}
645
646/* Set pitch */
306fa6f6 647static void set_lwidth(struct tridentfb_par *par, int width)
1da177e4 648{
306fa6f6
KH
649 write3X4(par, Offset, width & 0xFF);
650 write3X4(par, AddColReg,
651 (read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4));
1da177e4
LT
652}
653
654/* For resolutions smaller than FP resolution stretch */
306fa6f6 655static void screen_stretch(struct tridentfb_par *par)
1da177e4 656{
122e8ad3 657 if (par->chip_id != CYBERBLADEXPAi1)
306fa6f6 658 write3CE(par, BiosReg, 0);
245a2c2c 659 else
306fa6f6
KH
660 write3CE(par, BiosReg, 8);
661 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 1);
662 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 1);
1da177e4
LT
663}
664
665/* For resolutions smaller than FP resolution center */
306fa6f6 666static void screen_center(struct tridentfb_par *par)
1da177e4 667{
306fa6f6
KH
668 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 0x80);
669 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 0x80);
1da177e4
LT
670}
671
672/* Address of first shown pixel in display memory */
306fa6f6 673static void set_screen_start(struct tridentfb_par *par, int base)
1da177e4 674{
306fa6f6
KH
675 u8 tmp;
676 write3X4(par, StartAddrLow, base & 0xFF);
677 write3X4(par, StartAddrHigh, (base & 0xFF00) >> 8);
678 tmp = read3X4(par, CRTCModuleTest) & 0xDF;
679 write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11));
680 tmp = read3X4(par, CRTHiOrd) & 0xF8;
681 write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17));
1da177e4
LT
682}
683
1da177e4 684/* Set dotclock frequency */
306fa6f6 685static void set_vclk(struct tridentfb_par *par, unsigned long freq)
1da177e4 686{
245a2c2c 687 int m, n, k;
3f275ea3 688 unsigned long f, fi, d, di;
245a2c2c 689 unsigned char lo = 0, hi = 0;
1da177e4 690
3f275ea3 691 d = 20000;
245a2c2c
KH
692 for (k = 2; k >= 0; k--)
693 for (m = 0; m < 63; m++)
694 for (n = 0; n < 128; n++) {
3f275ea3 695 fi = ((14318l * (n + 8)) / (m + 2)) >> k;
245a2c2c
KH
696 if ((di = abs(fi - freq)) < d) {
697 d = di;
698 f = fi;
699 lo = n;
700 hi = (k << 6) | m;
701 }
3f275ea3
KH
702 if (fi > freq)
703 break;
245a2c2c 704 }
122e8ad3 705 if (is3Dchip(par->chip_id)) {
306fa6f6
KH
706 write3C4(par, ClockHigh, hi);
707 write3C4(par, ClockLow, lo);
1da177e4 708 } else {
245a2c2c
KH
709 outb(lo, 0x43C8);
710 outb(hi, 0x43C9);
1da177e4 711 }
245a2c2c 712 debug("VCLK = %X %X\n", hi, lo);
1da177e4
LT
713}
714
715/* Set number of lines for flat panels*/
306fa6f6 716static void set_number_of_lines(struct tridentfb_par *par, int lines)
1da177e4 717{
306fa6f6 718 int tmp = read3CE(par, CyberEnhance) & 0x8F;
1da177e4
LT
719 if (lines > 1024)
720 tmp |= 0x50;
721 else if (lines > 768)
722 tmp |= 0x30;
723 else if (lines > 600)
724 tmp |= 0x20;
725 else if (lines > 480)
726 tmp |= 0x10;
306fa6f6 727 write3CE(par, CyberEnhance, tmp);
1da177e4
LT
728}
729
730/*
731 * If we see that FP is active we assume we have one.
6eed8e1e 732 * Otherwise we have a CRT display. User can override.
1da177e4 733 */
6eed8e1e 734static int __devinit is_flatpanel(struct tridentfb_par *par)
1da177e4
LT
735{
736 if (fp)
6eed8e1e 737 return 1;
122e8ad3 738 if (crt || !iscyber(par->chip_id))
6eed8e1e
KH
739 return 0;
740 return (read3CE(par, FPConfig) & 0x10) ? 1 : 0;
1da177e4
LT
741}
742
743/* Try detecting the video memory size */
306fa6f6 744static unsigned int __devinit get_memsize(struct tridentfb_par *par)
1da177e4
LT
745{
746 unsigned char tmp, tmp2;
747 unsigned int k;
748
749 /* If memory size provided by user */
750 if (memsize)
751 k = memsize * Kb;
752 else
122e8ad3 753 switch (par->chip_id) {
245a2c2c
KH
754 case CYBER9525DVD:
755 k = 2560 * Kb;
756 break;
1da177e4 757 default:
306fa6f6 758 tmp = read3X4(par, SPR) & 0x0F;
1da177e4
LT
759 switch (tmp) {
760
245a2c2c 761 case 0x01:
b614ce8b 762 k = 512 * Kb;
245a2c2c
KH
763 break;
764 case 0x02:
765 k = 6 * Mb; /* XP */
766 break;
767 case 0x03:
768 k = 1 * Mb;
769 break;
770 case 0x04:
771 k = 8 * Mb;
772 break;
773 case 0x06:
774 k = 10 * Mb; /* XP */
775 break;
776 case 0x07:
777 k = 2 * Mb;
778 break;
779 case 0x08:
780 k = 12 * Mb; /* XP */
781 break;
782 case 0x0A:
783 k = 14 * Mb; /* XP */
784 break;
785 case 0x0C:
786 k = 16 * Mb; /* XP */
787 break;
788 case 0x0E: /* XP */
789
306fa6f6 790 tmp2 = read3C4(par, 0xC1);
245a2c2c
KH
791 switch (tmp2) {
792 case 0x00:
793 k = 20 * Mb;
794 break;
795 case 0x01:
796 k = 24 * Mb;
797 break;
798 case 0x10:
799 k = 28 * Mb;
800 break;
801 case 0x11:
802 k = 32 * Mb;
803 break;
804 default:
805 k = 1 * Mb;
806 break;
807 }
808 break;
809
810 case 0x0F:
811 k = 4 * Mb;
812 break;
813 default:
814 k = 1 * Mb;
1da177e4 815 break;
1da177e4 816 }
245a2c2c 817 }
1da177e4
LT
818
819 k -= memdiff * Kb;
245a2c2c 820 output("framebuffer size = %d Kb\n", k / Kb);
1da177e4
LT
821 return k;
822}
823
824/* See if we can handle the video mode described in var */
245a2c2c
KH
825static int tridentfb_check_var(struct fb_var_screeninfo *var,
826 struct fb_info *info)
1da177e4 827{
6eed8e1e 828 struct tridentfb_par *par = info->par;
1da177e4
LT
829 int bpp = var->bits_per_pixel;
830 debug("enter\n");
831
832 /* check color depth */
245a2c2c 833 if (bpp == 24)
1da177e4 834 bpp = var->bits_per_pixel = 32;
245a2c2c 835 /* check whether resolution fits on panel and in memory */
6eed8e1e 836 if (par->flatpanel && nativex && var->xres > nativex)
1da177e4 837 return -EINVAL;
245a2c2c 838 if (var->xres * var->yres_virtual * bpp / 8 > info->fix.smem_len)
1da177e4
LT
839 return -EINVAL;
840
841 switch (bpp) {
245a2c2c
KH
842 case 8:
843 var->red.offset = 0;
844 var->green.offset = 0;
845 var->blue.offset = 0;
846 var->red.length = 6;
847 var->green.length = 6;
848 var->blue.length = 6;
849 break;
850 case 16:
851 var->red.offset = 11;
852 var->green.offset = 5;
853 var->blue.offset = 0;
854 var->red.length = 5;
855 var->green.length = 6;
856 var->blue.length = 5;
857 break;
858 case 32:
859 var->red.offset = 16;
860 var->green.offset = 8;
861 var->blue.offset = 0;
862 var->red.length = 8;
863 var->green.length = 8;
864 var->blue.length = 8;
865 break;
866 default:
867 return -EINVAL;
1da177e4
LT
868 }
869 debug("exit\n");
870
871 return 0;
872
873}
245a2c2c 874
1da177e4
LT
875/* Pan the display */
876static int tridentfb_pan_display(struct fb_var_screeninfo *var,
245a2c2c 877 struct fb_info *info)
1da177e4 878{
306fa6f6 879 struct tridentfb_par *par = info->par;
1da177e4
LT
880 unsigned int offset;
881
882 debug("enter\n");
883 offset = (var->xoffset + (var->yoffset * var->xres))
245a2c2c 884 * var->bits_per_pixel / 32;
1da177e4
LT
885 info->var.xoffset = var->xoffset;
886 info->var.yoffset = var->yoffset;
306fa6f6 887 set_screen_start(par, offset);
1da177e4
LT
888 debug("exit\n");
889 return 0;
890}
891
306fa6f6
KH
892static void shadowmode_on(struct tridentfb_par *par)
893{
894 write3CE(par, CyberControl, read3CE(par, CyberControl) | 0x81);
895}
896
897static void shadowmode_off(struct tridentfb_par *par)
898{
899 write3CE(par, CyberControl, read3CE(par, CyberControl) & 0x7E);
900}
1da177e4
LT
901
902/* Set the hardware to the requested video mode */
903static int tridentfb_set_par(struct fb_info *info)
904{
245a2c2c
KH
905 struct tridentfb_par *par = (struct tridentfb_par *)(info->par);
906 u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend;
907 u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend;
908 struct fb_var_screeninfo *var = &info->var;
1da177e4
LT
909 int bpp = var->bits_per_pixel;
910 unsigned char tmp;
3f275ea3
KH
911 unsigned long vclk;
912
1da177e4 913 debug("enter\n");
245a2c2c
KH
914 hdispend = var->xres / 8 - 1;
915 hsyncstart = (var->xres + var->right_margin) / 8;
916 hsyncend = var->hsync_len / 8;
917 htotal =
918 (var->xres + var->left_margin + var->right_margin +
919 var->hsync_len) / 8 - 10;
1da177e4
LT
920 hblankstart = hdispend + 1;
921 hblankend = htotal + 5;
922
1da177e4
LT
923 vdispend = var->yres - 1;
924 vsyncstart = var->yres + var->lower_margin;
925 vsyncend = var->vsync_len;
245a2c2c 926 vtotal = var->upper_margin + vsyncstart + vsyncend - 2;
1da177e4
LT
927 vblankstart = var->yres;
928 vblankend = vtotal + 2;
929
306fa6f6
KH
930 crtc_unlock(par);
931 write3CE(par, CyberControl, 8);
1da177e4 932
6eed8e1e 933 if (par->flatpanel && var->xres < nativex) {
1da177e4
LT
934 /*
935 * on flat panels with native size larger
936 * than requested resolution decide whether
937 * we stretch or center
938 */
306fa6f6 939 t_outb(par, 0xEB, 0x3C2);
1da177e4 940
306fa6f6 941 shadowmode_on(par);
1da177e4 942
245a2c2c 943 if (center)
306fa6f6 944 screen_center(par);
1da177e4 945 else if (stretch)
306fa6f6 946 screen_stretch(par);
1da177e4
LT
947
948 } else {
306fa6f6
KH
949 t_outb(par, 0x2B, 0x3C2);
950 write3CE(par, CyberControl, 8);
1da177e4
LT
951 }
952
953 /* vertical timing values */
306fa6f6
KH
954 write3X4(par, CRTVTotal, vtotal & 0xFF);
955 write3X4(par, CRTVDispEnd, vdispend & 0xFF);
956 write3X4(par, CRTVSyncStart, vsyncstart & 0xFF);
957 write3X4(par, CRTVSyncEnd, (vsyncend & 0x0F));
958 write3X4(par, CRTVBlankStart, vblankstart & 0xFF);
959 write3X4(par, CRTVBlankEnd, 0 /* p->vblankend & 0xFF */);
1da177e4
LT
960
961 /* horizontal timing values */
306fa6f6
KH
962 write3X4(par, CRTHTotal, htotal & 0xFF);
963 write3X4(par, CRTHDispEnd, hdispend & 0xFF);
964 write3X4(par, CRTHSyncStart, hsyncstart & 0xFF);
965 write3X4(par, CRTHSyncEnd,
966 (hsyncend & 0x1F) | ((hblankend & 0x20) << 2));
967 write3X4(par, CRTHBlankStart, hblankstart & 0xFF);
968 write3X4(par, CRTHBlankEnd, 0 /* (p->hblankend & 0x1F) */);
1da177e4
LT
969
970 /* higher bits of vertical timing values */
971 tmp = 0x10;
972 if (vtotal & 0x100) tmp |= 0x01;
973 if (vdispend & 0x100) tmp |= 0x02;
974 if (vsyncstart & 0x100) tmp |= 0x04;
975 if (vblankstart & 0x100) tmp |= 0x08;
976
977 if (vtotal & 0x200) tmp |= 0x20;
978 if (vdispend & 0x200) tmp |= 0x40;
979 if (vsyncstart & 0x200) tmp |= 0x80;
306fa6f6 980 write3X4(par, CRTOverflow, tmp);
1da177e4 981
306fa6f6 982 tmp = read3X4(par, CRTHiOrd) | 0x08; /* line compare bit 10 */
1da177e4
LT
983 if (vtotal & 0x400) tmp |= 0x80;
984 if (vblankstart & 0x400) tmp |= 0x40;
985 if (vsyncstart & 0x400) tmp |= 0x20;
986 if (vdispend & 0x400) tmp |= 0x10;
306fa6f6 987 write3X4(par, CRTHiOrd, tmp);
1da177e4
LT
988
989 tmp = 0;
990 if (htotal & 0x800) tmp |= 0x800 >> 11;
991 if (hblankstart & 0x800) tmp |= 0x800 >> 7;
306fa6f6 992 write3X4(par, HorizOverflow, tmp);
245a2c2c 993
1da177e4
LT
994 tmp = 0x40;
995 if (vblankstart & 0x200) tmp |= 0x20;
245a2c2c 996//FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */
306fa6f6 997 write3X4(par, CRTMaxScanLine, tmp);
1da177e4 998
306fa6f6
KH
999 write3X4(par, CRTLineCompare, 0xFF);
1000 write3X4(par, CRTPRowScan, 0);
1001 write3X4(par, CRTModeControl, 0xC3);
1da177e4 1002
306fa6f6 1003 write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */
1da177e4 1004
245a2c2c 1005 tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80;
306fa6f6
KH
1006 /* enable access extended memory */
1007 write3X4(par, CRTCModuleTest, tmp);
1da177e4 1008
306fa6f6
KH
1009 /* enable GE for text acceleration */
1010 write3X4(par, GraphEngReg, 0x80);
1da177e4 1011
245a2c2c 1012#ifdef CONFIG_FB_TRIDENT_ACCEL
306fa6f6 1013 acc->init_accel(par, info->var.xres, bpp);
8dad46cf 1014#endif
245a2c2c 1015
1da177e4 1016 switch (bpp) {
245a2c2c
KH
1017 case 8:
1018 tmp = 0x00;
1019 break;
1020 case 16:
1021 tmp = 0x05;
1022 break;
1023 case 24:
1024 tmp = 0x29;
1025 break;
1026 case 32:
1027 tmp = 0x09;
1028 break;
1da177e4
LT
1029 }
1030
306fa6f6 1031 write3X4(par, PixelBusReg, tmp);
1da177e4
LT
1032
1033 tmp = 0x10;
122e8ad3 1034 if (iscyber(par->chip_id))
245a2c2c 1035 tmp |= 0x20;
306fa6f6 1036 write3X4(par, DRAMControl, tmp); /* both IO, linear enable */
1da177e4 1037
306fa6f6
KH
1038 write3X4(par, InterfaceSel, read3X4(par, InterfaceSel) | 0x40);
1039 write3X4(par, Performance, 0x92);
1040 /* MMIO & PCI read and write burst enable */
1041 write3X4(par, PCIReg, 0x07);
1da177e4 1042
3f275ea3
KH
1043 /* convert from picoseconds to kHz */
1044 vclk = PICOS2KHZ(info->var.pixclock);
1da177e4 1045 if (bpp == 32)
3f275ea3 1046 vclk *= 2;
306fa6f6 1047 set_vclk(par, vclk);
1da177e4 1048
306fa6f6
KH
1049 write3C4(par, 0, 3);
1050 write3C4(par, 1, 1); /* set char clock 8 dots wide */
1051 /* enable 4 maps because needed in chain4 mode */
1052 write3C4(par, 2, 0x0F);
1053 write3C4(par, 3, 0);
1054 write3C4(par, 4, 0x0E); /* memory mode enable bitmaps ?? */
1da177e4 1055
306fa6f6
KH
1056 /* divide clock by 2 if 32bpp chain4 mode display and CPU path */
1057 write3CE(par, MiscExtFunc, (bpp == 32) ? 0x1A : 0x12);
1058 write3CE(par, 0x5, 0x40); /* no CGA compat, allow 256 col */
1059 write3CE(par, 0x6, 0x05); /* graphics mode */
1060 write3CE(par, 0x7, 0x0F); /* planes? */
1da177e4 1061
122e8ad3 1062 if (par->chip_id == CYBERBLADEXPAi1) {
1da177e4 1063 /* This fixes snow-effect in 32 bpp */
306fa6f6 1064 write3X4(par, CRTHSyncStart, 0x84);
1da177e4
LT
1065 }
1066
306fa6f6
KH
1067 /* graphics mode and support 256 color modes */
1068 writeAttr(par, 0x10, 0x41);
1069 writeAttr(par, 0x12, 0x0F); /* planes */
1070 writeAttr(par, 0x13, 0); /* horizontal pel panning */
1da177e4 1071
245a2c2c
KH
1072 /* colors */
1073 for (tmp = 0; tmp < 0x10; tmp++)
306fa6f6
KH
1074 writeAttr(par, tmp, tmp);
1075 fb_readb(par->io_virt + CRT + 0x0A); /* flip-flop to index */
1076 t_outb(par, 0x20, 0x3C0); /* enable attr */
1da177e4
LT
1077
1078 switch (bpp) {
245a2c2c
KH
1079 case 8:
1080 tmp = 0;
1081 break;
1082 case 15:
1083 tmp = 0x10;
1084 break;
1085 case 16:
1086 tmp = 0x30;
1087 break;
1088 case 24:
1089 case 32:
1090 tmp = 0xD0;
1091 break;
1da177e4
LT
1092 }
1093
306fa6f6
KH
1094 t_inb(par, 0x3C8);
1095 t_inb(par, 0x3C6);
1096 t_inb(par, 0x3C6);
1097 t_inb(par, 0x3C6);
1098 t_inb(par, 0x3C6);
1099 t_outb(par, tmp, 0x3C6);
1100 t_inb(par, 0x3C8);
1da177e4 1101
6eed8e1e 1102 if (par->flatpanel)
306fa6f6
KH
1103 set_number_of_lines(par, info->var.yres);
1104 set_lwidth(par, info->var.xres * bpp / (4 * 16));
1da177e4 1105 info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
245a2c2c
KH
1106 info->fix.line_length = info->var.xres * (bpp >> 3);
1107 info->cmap.len = (bpp == 8) ? 256 : 16;
1da177e4
LT
1108 debug("exit\n");
1109 return 0;
1110}
1111
1112/* Set one color register */
1113static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green,
245a2c2c
KH
1114 unsigned blue, unsigned transp,
1115 struct fb_info *info)
1da177e4
LT
1116{
1117 int bpp = info->var.bits_per_pixel;
306fa6f6 1118 struct tridentfb_par *par = info->par;
1da177e4
LT
1119
1120 if (regno >= info->cmap.len)
1121 return 1;
1122
973d9ab2 1123 if (bpp == 8) {
306fa6f6
KH
1124 t_outb(par, 0xFF, 0x3C6);
1125 t_outb(par, regno, 0x3C8);
1da177e4 1126
306fa6f6
KH
1127 t_outb(par, red >> 10, 0x3C9);
1128 t_outb(par, green >> 10, 0x3C9);
1129 t_outb(par, blue >> 10, 0x3C9);
1da177e4 1130
973d9ab2
AD
1131 } else if (regno < 16) {
1132 if (bpp == 16) { /* RGB 565 */
1133 u32 col;
1134
1135 col = (red & 0xF800) | ((green & 0xFC00) >> 5) |
1136 ((blue & 0xF800) >> 11);
1137 col |= col << 16;
1138 ((u32 *)(info->pseudo_palette))[regno] = col;
1139 } else if (bpp == 32) /* ARGB 8888 */
1140 ((u32*)info->pseudo_palette)[regno] =
245a2c2c
KH
1141 ((transp & 0xFF00) << 16) |
1142 ((red & 0xFF00) << 8) |
973d9ab2 1143 ((green & 0xFF00)) |
245a2c2c 1144 ((blue & 0xFF00) >> 8);
973d9ab2 1145 }
1da177e4 1146
245a2c2c 1147/* debug("exit\n"); */
1da177e4
LT
1148 return 0;
1149}
1150
1151/* Try blanking the screen.For flat panels it does nothing */
1152static int tridentfb_blank(int blank_mode, struct fb_info *info)
1153{
245a2c2c 1154 unsigned char PMCont, DPMSCont;
306fa6f6 1155 struct tridentfb_par *par = info->par;
1da177e4
LT
1156
1157 debug("enter\n");
6eed8e1e 1158 if (par->flatpanel)
1da177e4 1159 return 0;
306fa6f6
KH
1160 t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */
1161 PMCont = t_inb(par, 0x83C6) & 0xFC;
1162 DPMSCont = read3CE(par, PowerStatus) & 0xFC;
245a2c2c 1163 switch (blank_mode) {
1da177e4
LT
1164 case FB_BLANK_UNBLANK:
1165 /* Screen: On, HSync: On, VSync: On */
1166 case FB_BLANK_NORMAL:
1167 /* Screen: Off, HSync: On, VSync: On */
1168 PMCont |= 0x03;
1169 DPMSCont |= 0x00;
1170 break;
1171 case FB_BLANK_HSYNC_SUSPEND:
1172 /* Screen: Off, HSync: Off, VSync: On */
1173 PMCont |= 0x02;
1174 DPMSCont |= 0x01;
1175 break;
1176 case FB_BLANK_VSYNC_SUSPEND:
1177 /* Screen: Off, HSync: On, VSync: Off */
1178 PMCont |= 0x02;
1179 DPMSCont |= 0x02;
1180 break;
1181 case FB_BLANK_POWERDOWN:
1182 /* Screen: Off, HSync: Off, VSync: Off */
1183 PMCont |= 0x00;
1184 DPMSCont |= 0x03;
1185 break;
245a2c2c 1186 }
1da177e4 1187
306fa6f6
KH
1188 write3CE(par, PowerStatus, DPMSCont);
1189 t_outb(par, 4, 0x83C8);
1190 t_outb(par, PMCont, 0x83C6);
1da177e4
LT
1191
1192 debug("exit\n");
1193
1194 /* let fbcon do a softblank for us */
1195 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1196}
1197
245a2c2c
KH
1198static struct fb_ops tridentfb_ops = {
1199 .owner = THIS_MODULE,
1200 .fb_setcolreg = tridentfb_setcolreg,
1201 .fb_pan_display = tridentfb_pan_display,
1202 .fb_blank = tridentfb_blank,
1203 .fb_check_var = tridentfb_check_var,
1204 .fb_set_par = tridentfb_set_par,
1205 .fb_fillrect = tridentfb_fillrect,
1206 .fb_copyarea = tridentfb_copyarea,
1207 .fb_imageblit = cfb_imageblit,
1208};
1209
e09ed099
KH
1210static int __devinit trident_pci_probe(struct pci_dev *dev,
1211 const struct pci_device_id *id)
1da177e4
LT
1212{
1213 int err;
1214 unsigned char revision;
e09ed099
KH
1215 struct fb_info *info;
1216 struct tridentfb_par *default_par;
122e8ad3
KH
1217 int defaultaccel;
1218 int chip3D;
1219 int chip_id;
1da177e4
LT
1220
1221 err = pci_enable_device(dev);
1222 if (err)
1223 return err;
1224
e09ed099
KH
1225 info = framebuffer_alloc(sizeof(struct tridentfb_par), &dev->dev);
1226 if (!info)
1227 return -ENOMEM;
1228 default_par = info->par;
1229
1da177e4
LT
1230 chip_id = id->device;
1231
245a2c2c 1232 if (chip_id == CYBERBLADEi1)
9fa68eae
KP
1233 output("*** Please do use cyblafb, Cyberblade/i1 support "
1234 "will soon be removed from tridentfb!\n");
1235
1236
1da177e4 1237 /* If PCI id is 0x9660 then further detect chip type */
245a2c2c 1238
1da177e4 1239 if (chip_id == TGUI9660) {
245a2c2c
KH
1240 outb(RevisionID, 0x3C4);
1241 revision = inb(0x3C5);
1242
1da177e4 1243 switch (revision) {
245a2c2c
KH
1244 case 0x22:
1245 case 0x23:
1246 chip_id = CYBER9397;
1247 break;
1248 case 0x2A:
1249 chip_id = CYBER9397DVD;
1250 break;
1251 case 0x30:
1252 case 0x33:
1253 case 0x34:
1254 case 0x35:
1255 case 0x38:
1256 case 0x3A:
1257 case 0xB3:
1258 chip_id = CYBER9385;
1259 break;
1260 case 0x40 ... 0x43:
1261 chip_id = CYBER9382;
1262 break;
1263 case 0x4A:
1264 chip_id = CYBER9388;
1265 break;
1266 default:
1267 break;
1da177e4
LT
1268 }
1269 }
1270
1271 chip3D = is3Dchip(chip_id);
1da177e4
LT
1272
1273 if (is_xp(chip_id)) {
1274 acc = &accel_xp;
245a2c2c 1275 } else if (is_blade(chip_id)) {
1da177e4
LT
1276 acc = &accel_blade;
1277 } else {
1278 acc = &accel_image;
1279 }
1280
122e8ad3
KH
1281 default_par->chip_id = chip_id;
1282
1da177e4
LT
1283 /* acceleration is on by default for 3D chips */
1284 defaultaccel = chip3D && !noaccel;
1285
1da177e4 1286 /* setup MMIO region */
245a2c2c
KH
1287 tridentfb_fix.mmio_start = pci_resource_start(dev, 1);
1288 tridentfb_fix.mmio_len = chip3D ? 0x20000 : 0x10000;
1da177e4
LT
1289
1290 if (!request_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len, "tridentfb")) {
1291 debug("request_region failed!\n");
1292 return -1;
1293 }
1294
e09ed099
KH
1295 default_par->io_virt = ioremap_nocache(tridentfb_fix.mmio_start,
1296 tridentfb_fix.mmio_len);
1da177e4 1297
e09ed099 1298 if (!default_par->io_virt) {
1da177e4 1299 debug("ioremap failed\n");
e8ed857c
KH
1300 err = -1;
1301 goto out_unmap1;
1da177e4
LT
1302 }
1303
1304 enable_mmio();
245a2c2c 1305
1da177e4 1306 /* setup framebuffer memory */
245a2c2c 1307 tridentfb_fix.smem_start = pci_resource_start(dev, 0);
e09ed099 1308 tridentfb_fix.smem_len = get_memsize(default_par);
245a2c2c 1309
1da177e4
LT
1310 if (!request_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len, "tridentfb")) {
1311 debug("request_mem_region failed!\n");
e09ed099 1312 disable_mmio(info->par);
a02f6402 1313 err = -1;
e8ed857c 1314 goto out_unmap1;
1da177e4
LT
1315 }
1316
e09ed099
KH
1317 info->screen_base = ioremap_nocache(tridentfb_fix.smem_start,
1318 tridentfb_fix.smem_len);
1da177e4 1319
e09ed099 1320 if (!info->screen_base) {
1da177e4 1321 debug("ioremap failed\n");
a02f6402 1322 err = -1;
e8ed857c 1323 goto out_unmap2;
1da177e4
LT
1324 }
1325
1326 output("%s board found\n", pci_name(dev));
6eed8e1e 1327 default_par->flatpanel = is_flatpanel(default_par);
1da177e4 1328
6eed8e1e 1329 if (default_par->flatpanel)
e09ed099 1330 nativex = get_nativex(default_par);
1da177e4 1331
e09ed099
KH
1332 info->fix = tridentfb_fix;
1333 info->fbops = &tridentfb_ops;
1da177e4
LT
1334
1335
e09ed099 1336 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1da177e4 1337#ifdef CONFIG_FB_TRIDENT_ACCEL
e09ed099 1338 info->flags |= FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT;
1da177e4 1339#endif
ea8ee55c 1340 if (!fb_find_mode(&info->var, info,
07f41e45 1341 mode_option, NULL, 0, NULL, bpp)) {
a02f6402 1342 err = -EINVAL;
e8ed857c 1343 goto out_unmap2;
a02f6402 1344 }
e09ed099 1345 err = fb_alloc_cmap(&info->cmap, 256, 0);
e8ed857c
KH
1346 if (err < 0)
1347 goto out_unmap2;
1348
1da177e4 1349 if (defaultaccel && acc)
ea8ee55c 1350 info->var.accel_flags |= FB_ACCELF_TEXT;
1da177e4 1351 else
ea8ee55c
KH
1352 info->var.accel_flags &= ~FB_ACCELF_TEXT;
1353 info->var.activate |= FB_ACTIVATE_NOW;
e09ed099
KH
1354 info->device = &dev->dev;
1355 if (register_framebuffer(info) < 0) {
1da177e4 1356 printk(KERN_ERR "tridentfb: could not register Trident framebuffer\n");
e09ed099 1357 fb_dealloc_cmap(&info->cmap);
a02f6402 1358 err = -EINVAL;
e8ed857c 1359 goto out_unmap2;
1da177e4
LT
1360 }
1361 output("fb%d: %s frame buffer device %dx%d-%dbpp\n",
ea8ee55c
KH
1362 info->node, info->fix.id, info->var.xres,
1363 info->var.yres, info->var.bits_per_pixel);
e09ed099
KH
1364
1365 pci_set_drvdata(dev, info);
1da177e4 1366 return 0;
a02f6402 1367
e8ed857c 1368out_unmap2:
e09ed099
KH
1369 if (info->screen_base)
1370 iounmap(info->screen_base);
e8ed857c 1371 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
e09ed099 1372 disable_mmio(info->par);
e8ed857c 1373out_unmap1:
e09ed099
KH
1374 if (default_par->io_virt)
1375 iounmap(default_par->io_virt);
e8ed857c 1376 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
e09ed099 1377 framebuffer_release(info);
a02f6402 1378 return err;
1da177e4
LT
1379}
1380
245a2c2c 1381static void __devexit trident_pci_remove(struct pci_dev *dev)
1da177e4 1382{
e09ed099
KH
1383 struct fb_info *info = pci_get_drvdata(dev);
1384 struct tridentfb_par *par = info->par;
1385
1386 unregister_framebuffer(info);
1da177e4 1387 iounmap(par->io_virt);
e09ed099 1388 iounmap(info->screen_base);
1da177e4 1389 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
e8ed857c 1390 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
e09ed099
KH
1391 pci_set_drvdata(dev, NULL);
1392 framebuffer_release(info);
1da177e4
LT
1393}
1394
1395/* List of boards that we are trying to support */
1396static struct pci_device_id trident_devices[] = {
245a2c2c
KH
1397 {PCI_VENDOR_ID_TRIDENT, BLADE3D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1398 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1399 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1400 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1401 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1402 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1403 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1404 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1405 {PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1406 {PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1407 {PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1408 {PCI_VENDOR_ID_TRIDENT, CYBER9320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1409 {PCI_VENDOR_ID_TRIDENT, CYBER9388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1410 {PCI_VENDOR_ID_TRIDENT, CYBER9520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1411 {PCI_VENDOR_ID_TRIDENT, CYBER9525DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1412 {PCI_VENDOR_ID_TRIDENT, CYBER9397, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1413 {PCI_VENDOR_ID_TRIDENT, CYBER9397DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1414 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1415 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1416 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm16, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1da177e4 1417 {0,}
245a2c2c
KH
1418};
1419
1420MODULE_DEVICE_TABLE(pci, trident_devices);
1da177e4
LT
1421
1422static struct pci_driver tridentfb_pci_driver = {
245a2c2c
KH
1423 .name = "tridentfb",
1424 .id_table = trident_devices,
1425 .probe = trident_pci_probe,
1426 .remove = __devexit_p(trident_pci_remove)
1da177e4
LT
1427};
1428
1429/*
1430 * Parse user specified options (`video=trident:')
1431 * example:
245a2c2c 1432 * video=trident:800x600,bpp=16,noaccel
1da177e4
LT
1433 */
1434#ifndef MODULE
07f41e45 1435static int __init tridentfb_setup(char *options)
1da177e4 1436{
245a2c2c 1437 char *opt;
1da177e4
LT
1438 if (!options || !*options)
1439 return 0;
245a2c2c
KH
1440 while ((opt = strsep(&options, ",")) != NULL) {
1441 if (!*opt)
1442 continue;
1443 if (!strncmp(opt, "noaccel", 7))
1da177e4 1444 noaccel = 1;
245a2c2c 1445 else if (!strncmp(opt, "fp", 2))
6eed8e1e 1446 fp = 1;
245a2c2c 1447 else if (!strncmp(opt, "crt", 3))
6eed8e1e 1448 fp = 0;
245a2c2c
KH
1449 else if (!strncmp(opt, "bpp=", 4))
1450 bpp = simple_strtoul(opt + 4, NULL, 0);
1451 else if (!strncmp(opt, "center", 6))
1da177e4 1452 center = 1;
245a2c2c 1453 else if (!strncmp(opt, "stretch", 7))
1da177e4 1454 stretch = 1;
245a2c2c
KH
1455 else if (!strncmp(opt, "memsize=", 8))
1456 memsize = simple_strtoul(opt + 8, NULL, 0);
1457 else if (!strncmp(opt, "memdiff=", 8))
1458 memdiff = simple_strtoul(opt + 8, NULL, 0);
1459 else if (!strncmp(opt, "nativex=", 8))
1460 nativex = simple_strtoul(opt + 8, NULL, 0);
1da177e4 1461 else
07f41e45 1462 mode_option = opt;
1da177e4
LT
1463 }
1464 return 0;
1465}
1466#endif
1467
1468static int __init tridentfb_init(void)
1469{
1470#ifndef MODULE
1471 char *option = NULL;
1472
1473 if (fb_get_options("tridentfb", &option))
1474 return -ENODEV;
1475 tridentfb_setup(option);
1476#endif
1477 output("Trident framebuffer %s initializing\n", VERSION);
1478 return pci_register_driver(&tridentfb_pci_driver);
1479}
1480
1481static void __exit tridentfb_exit(void)
1482{
1483 pci_unregister_driver(&tridentfb_pci_driver);
1484}
1485
1da177e4
LT
1486module_init(tridentfb_init);
1487module_exit(tridentfb_exit);
1488
1489MODULE_AUTHOR("Jani Monoses <jani@iv.ro>");
1490MODULE_DESCRIPTION("Framebuffer driver for Trident cards");
1491MODULE_LICENSE("GPL");
1492
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