Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Frame buffer driver for Trident Blade and Image series | |
3 | * | |
245a2c2c | 4 | * Copyright 2001, 2002 - Jani Monoses <jani@iv.ro> |
1da177e4 LT |
5 | * |
6 | * | |
7 | * CREDITS:(in order of appearance) | |
245a2c2c KH |
8 | * skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video |
9 | * Special thanks ;) to Mattia Crivellini <tia@mclink.it> | |
10 | * much inspired by the XFree86 4.x Trident driver sources | |
11 | * by Alan Hourihane the FreeVGA project | |
12 | * Francesco Salvestrini <salvestrini@users.sf.net> XP support, | |
13 | * code, suggestions | |
1da177e4 | 14 | * TODO: |
245a2c2c KH |
15 | * timing value tweaking so it looks good on every monitor in every mode |
16 | * TGUI acceleration | |
1da177e4 LT |
17 | */ |
18 | ||
1da177e4 LT |
19 | #include <linux/module.h> |
20 | #include <linux/fb.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/pci.h> | |
23 | ||
24 | #include <linux/delay.h> | |
10172ed6 | 25 | #include <video/vga.h> |
1da177e4 LT |
26 | #include <video/trident.h> |
27 | ||
122e8ad3 | 28 | #define VERSION "0.7.9-NEWAPI" |
1da177e4 LT |
29 | |
30 | struct tridentfb_par { | |
245a2c2c | 31 | void __iomem *io_virt; /* iospace virtual memory address */ |
ea8ee55c | 32 | u32 pseudo_pal[16]; |
122e8ad3 | 33 | int chip_id; |
6eed8e1e | 34 | int flatpanel; |
d9cad04b KH |
35 | void (*init_accel) (struct tridentfb_par *, int, int); |
36 | void (*wait_engine) (struct tridentfb_par *); | |
37 | void (*fill_rect) | |
38 | (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32); | |
39 | void (*copy_rect) | |
40 | (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32); | |
1da177e4 LT |
41 | }; |
42 | ||
245a2c2c | 43 | static unsigned char eng_oper; /* engine operation... */ |
1da177e4 LT |
44 | static struct fb_ops tridentfb_ops; |
45 | ||
1da177e4 | 46 | static struct fb_fix_screeninfo tridentfb_fix = { |
245a2c2c | 47 | .id = "Trident", |
1da177e4 LT |
48 | .type = FB_TYPE_PACKED_PIXELS, |
49 | .ypanstep = 1, | |
50 | .visual = FB_VISUAL_PSEUDOCOLOR, | |
51 | .accel = FB_ACCEL_NONE, | |
52 | }; | |
53 | ||
1da177e4 LT |
54 | /* defaults which are normally overriden by user values */ |
55 | ||
56 | /* video mode */ | |
07f41e45 | 57 | static char *mode_option __devinitdata = "640x480"; |
6eed8e1e | 58 | static int bpp __devinitdata = 8; |
1da177e4 | 59 | |
6eed8e1e | 60 | static int noaccel __devinitdata; |
1da177e4 LT |
61 | |
62 | static int center; | |
63 | static int stretch; | |
64 | ||
6eed8e1e KH |
65 | static int fp __devinitdata; |
66 | static int crt __devinitdata; | |
1da177e4 | 67 | |
6eed8e1e KH |
68 | static int memsize __devinitdata; |
69 | static int memdiff __devinitdata; | |
1da177e4 LT |
70 | static int nativex; |
71 | ||
07f41e45 KH |
72 | module_param(mode_option, charp, 0); |
73 | MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'"); | |
9e3f0ca8 KH |
74 | module_param_named(mode, mode_option, charp, 0); |
75 | MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)"); | |
1da177e4 LT |
76 | module_param(bpp, int, 0); |
77 | module_param(center, int, 0); | |
78 | module_param(stretch, int, 0); | |
79 | module_param(noaccel, int, 0); | |
80 | module_param(memsize, int, 0); | |
81 | module_param(memdiff, int, 0); | |
82 | module_param(nativex, int, 0); | |
83 | module_param(fp, int, 0); | |
6eed8e1e | 84 | MODULE_PARM_DESC(fp, "Define if flatpanel is connected"); |
1da177e4 | 85 | module_param(crt, int, 0); |
6eed8e1e | 86 | MODULE_PARM_DESC(crt, "Define if CRT is connected"); |
1da177e4 | 87 | |
6bdf1035 KH |
88 | static int is_oldclock(int id) |
89 | { | |
a0d92256 KH |
90 | return (id == TGUI9440) || |
91 | (id == TGUI9660) || | |
0e73a47f KH |
92 | (id == CYBER9320); |
93 | } | |
94 | ||
95 | static int is_oldprotect(int id) | |
96 | { | |
a0d92256 KH |
97 | return (id == TGUI9440) || |
98 | (id == TGUI9660) || | |
0e73a47f KH |
99 | (id == PROVIDIA9685) || |
100 | (id == CYBER9320) || | |
101 | (id == CYBER9382) || | |
102 | (id == CYBER9385); | |
6bdf1035 KH |
103 | } |
104 | ||
e0759a5f KH |
105 | static int is_blade(int id) |
106 | { | |
107 | return (id == BLADE3D) || | |
108 | (id == CYBERBLADEE4) || | |
109 | (id == CYBERBLADEi7) || | |
110 | (id == CYBERBLADEi7D) || | |
111 | (id == CYBERBLADEi1) || | |
112 | (id == CYBERBLADEi1D) || | |
113 | (id == CYBERBLADEAi1) || | |
114 | (id == CYBERBLADEAi1D); | |
115 | } | |
116 | ||
117 | static int is_xp(int id) | |
118 | { | |
119 | return (id == CYBERBLADEXPAi1) || | |
120 | (id == CYBERBLADEXPm8) || | |
121 | (id == CYBERBLADEXPm16); | |
122 | } | |
123 | ||
1da177e4 LT |
124 | static int is3Dchip(int id) |
125 | { | |
245a2c2c KH |
126 | return ((id == BLADE3D) || (id == CYBERBLADEE4) || |
127 | (id == CYBERBLADEi7) || (id == CYBERBLADEi7D) || | |
128 | (id == CYBER9397) || (id == CYBER9397DVD) || | |
129 | (id == CYBER9520) || (id == CYBER9525DVD) || | |
130 | (id == IMAGE975) || (id == IMAGE985) || | |
131 | (id == CYBERBLADEi1) || (id == CYBERBLADEi1D) || | |
132 | (id == CYBERBLADEAi1) || (id == CYBERBLADEAi1D) || | |
133 | (id == CYBERBLADEXPm8) || (id == CYBERBLADEXPm16) || | |
134 | (id == CYBERBLADEXPAi1)); | |
1da177e4 LT |
135 | } |
136 | ||
137 | static int iscyber(int id) | |
138 | { | |
139 | switch (id) { | |
245a2c2c KH |
140 | case CYBER9388: |
141 | case CYBER9382: | |
142 | case CYBER9385: | |
143 | case CYBER9397: | |
144 | case CYBER9397DVD: | |
145 | case CYBER9520: | |
146 | case CYBER9525DVD: | |
147 | case CYBERBLADEE4: | |
148 | case CYBERBLADEi7D: | |
149 | case CYBERBLADEi1: | |
150 | case CYBERBLADEi1D: | |
151 | case CYBERBLADEAi1: | |
152 | case CYBERBLADEAi1D: | |
153 | case CYBERBLADEXPAi1: | |
154 | return 1; | |
1da177e4 | 155 | |
245a2c2c KH |
156 | case CYBER9320: |
157 | case TGUI9660: | |
0e73a47f | 158 | case PROVIDIA9685: |
245a2c2c KH |
159 | case IMAGE975: |
160 | case IMAGE985: | |
161 | case BLADE3D: | |
162 | case CYBERBLADEi7: /* VIA MPV4 integrated version */ | |
163 | ||
164 | default: | |
165 | /* case CYBERBLDAEXPm8: Strange */ | |
166 | /* case CYBERBLDAEXPm16: Strange */ | |
167 | return 0; | |
1da177e4 LT |
168 | } |
169 | } | |
170 | ||
306fa6f6 KH |
171 | static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg) |
172 | { | |
173 | fb_writeb(val, p->io_virt + reg); | |
174 | } | |
1da177e4 | 175 | |
306fa6f6 KH |
176 | static inline u8 t_inb(struct tridentfb_par *p, u16 reg) |
177 | { | |
178 | return fb_readb(p->io_virt + reg); | |
179 | } | |
1da177e4 | 180 | |
306fa6f6 KH |
181 | static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v) |
182 | { | |
183 | fb_writel(v, par->io_virt + r); | |
184 | } | |
185 | ||
186 | static inline u32 readmmr(struct tridentfb_par *par, u16 r) | |
187 | { | |
188 | return fb_readl(par->io_virt + r); | |
189 | } | |
1da177e4 | 190 | |
1da177e4 LT |
191 | /* |
192 | * Blade specific acceleration. | |
193 | */ | |
194 | ||
245a2c2c | 195 | #define point(x, y) ((y) << 16 | (x)) |
1da177e4 LT |
196 | #define STA 0x2120 |
197 | #define CMD 0x2144 | |
198 | #define ROP 0x2148 | |
199 | #define CLR 0x2160 | |
200 | #define SR1 0x2100 | |
201 | #define SR2 0x2104 | |
202 | #define DR1 0x2108 | |
203 | #define DR2 0x210C | |
204 | ||
205 | #define ROP_S 0xCC | |
206 | ||
306fa6f6 | 207 | static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp) |
1da177e4 | 208 | { |
245a2c2c KH |
209 | int v1 = (pitch >> 3) << 20; |
210 | int tmp = 0, v2; | |
1da177e4 | 211 | switch (bpp) { |
245a2c2c KH |
212 | case 8: |
213 | tmp = 0; | |
214 | break; | |
215 | case 15: | |
216 | tmp = 5; | |
217 | break; | |
218 | case 16: | |
219 | tmp = 1; | |
220 | break; | |
221 | case 24: | |
222 | case 32: | |
223 | tmp = 2; | |
224 | break; | |
1da177e4 | 225 | } |
245a2c2c | 226 | v2 = v1 | (tmp << 29); |
306fa6f6 KH |
227 | writemmr(par, 0x21C0, v2); |
228 | writemmr(par, 0x21C4, v2); | |
229 | writemmr(par, 0x21B8, v2); | |
230 | writemmr(par, 0x21BC, v2); | |
231 | writemmr(par, 0x21D0, v1); | |
232 | writemmr(par, 0x21D4, v1); | |
233 | writemmr(par, 0x21C8, v1); | |
234 | writemmr(par, 0x21CC, v1); | |
235 | writemmr(par, 0x216C, 0); | |
1da177e4 LT |
236 | } |
237 | ||
306fa6f6 | 238 | static void blade_wait_engine(struct tridentfb_par *par) |
1da177e4 | 239 | { |
306fa6f6 | 240 | while (readmmr(par, STA) & 0xFA800000) ; |
1da177e4 LT |
241 | } |
242 | ||
306fa6f6 KH |
243 | static void blade_fill_rect(struct tridentfb_par *par, |
244 | u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop) | |
1da177e4 | 245 | { |
306fa6f6 KH |
246 | writemmr(par, CLR, c); |
247 | writemmr(par, ROP, rop ? 0x66 : ROP_S); | |
248 | writemmr(par, CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2); | |
1da177e4 | 249 | |
306fa6f6 KH |
250 | writemmr(par, DR1, point(x, y)); |
251 | writemmr(par, DR2, point(x + w - 1, y + h - 1)); | |
1da177e4 LT |
252 | } |
253 | ||
306fa6f6 KH |
254 | static void blade_copy_rect(struct tridentfb_par *par, |
255 | u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h) | |
1da177e4 | 256 | { |
245a2c2c | 257 | u32 s1, s2, d1, d2; |
1da177e4 | 258 | int direction = 2; |
245a2c2c KH |
259 | s1 = point(x1, y1); |
260 | s2 = point(x1 + w - 1, y1 + h - 1); | |
261 | d1 = point(x2, y2); | |
262 | d2 = point(x2 + w - 1, y2 + h - 1); | |
1da177e4 LT |
263 | |
264 | if ((y1 > y2) || ((y1 == y2) && (x1 > x2))) | |
245a2c2c | 265 | direction = 0; |
1da177e4 | 266 | |
306fa6f6 KH |
267 | writemmr(par, ROP, ROP_S); |
268 | writemmr(par, CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction); | |
1da177e4 | 269 | |
306fa6f6 KH |
270 | writemmr(par, SR1, direction ? s2 : s1); |
271 | writemmr(par, SR2, direction ? s1 : s2); | |
272 | writemmr(par, DR1, direction ? d2 : d1); | |
273 | writemmr(par, DR2, direction ? d1 : d2); | |
1da177e4 LT |
274 | } |
275 | ||
1da177e4 LT |
276 | /* |
277 | * BladeXP specific acceleration functions | |
278 | */ | |
279 | ||
280 | #define ROP_P 0xF0 | |
245a2c2c | 281 | #define masked_point(x, y) ((y & 0xffff)<<16|(x & 0xffff)) |
1da177e4 | 282 | |
306fa6f6 | 283 | static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp) |
1da177e4 | 284 | { |
245a2c2c | 285 | int tmp = 0, v1; |
1da177e4 LT |
286 | unsigned char x = 0; |
287 | ||
288 | switch (bpp) { | |
245a2c2c KH |
289 | case 8: |
290 | x = 0; | |
291 | break; | |
292 | case 16: | |
293 | x = 1; | |
294 | break; | |
295 | case 24: | |
296 | x = 3; | |
297 | break; | |
298 | case 32: | |
299 | x = 2; | |
300 | break; | |
1da177e4 LT |
301 | } |
302 | ||
303 | switch (pitch << (bpp >> 3)) { | |
245a2c2c KH |
304 | case 8192: |
305 | case 512: | |
306 | x |= 0x00; | |
307 | break; | |
308 | case 1024: | |
309 | x |= 0x04; | |
310 | break; | |
311 | case 2048: | |
312 | x |= 0x08; | |
313 | break; | |
314 | case 4096: | |
315 | x |= 0x0C; | |
316 | break; | |
1da177e4 LT |
317 | } |
318 | ||
306fa6f6 | 319 | t_outb(par, x, 0x2125); |
1da177e4 LT |
320 | |
321 | eng_oper = x | 0x40; | |
322 | ||
323 | switch (bpp) { | |
245a2c2c KH |
324 | case 8: |
325 | tmp = 18; | |
326 | break; | |
327 | case 15: | |
328 | case 16: | |
329 | tmp = 19; | |
330 | break; | |
331 | case 24: | |
332 | case 32: | |
333 | tmp = 20; | |
334 | break; | |
1da177e4 LT |
335 | } |
336 | ||
337 | v1 = pitch << tmp; | |
338 | ||
306fa6f6 KH |
339 | writemmr(par, 0x2154, v1); |
340 | writemmr(par, 0x2150, v1); | |
341 | t_outb(par, 3, 0x2126); | |
1da177e4 LT |
342 | } |
343 | ||
306fa6f6 | 344 | static void xp_wait_engine(struct tridentfb_par *par) |
1da177e4 LT |
345 | { |
346 | int busy; | |
347 | int count, timeout; | |
348 | ||
349 | count = 0; | |
350 | timeout = 0; | |
351 | for (;;) { | |
306fa6f6 | 352 | busy = t_inb(par, STA) & 0x80; |
1da177e4 LT |
353 | if (busy != 0x80) |
354 | return; | |
355 | count++; | |
356 | if (count == 10000000) { | |
357 | /* Timeout */ | |
358 | count = 9990000; | |
359 | timeout++; | |
360 | if (timeout == 8) { | |
361 | /* Reset engine */ | |
306fa6f6 | 362 | t_outb(par, 0x00, 0x2120); |
1da177e4 LT |
363 | return; |
364 | } | |
365 | } | |
366 | } | |
367 | } | |
368 | ||
306fa6f6 KH |
369 | static void xp_fill_rect(struct tridentfb_par *par, |
370 | u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop) | |
1da177e4 | 371 | { |
306fa6f6 KH |
372 | writemmr(par, 0x2127, ROP_P); |
373 | writemmr(par, 0x2158, c); | |
374 | writemmr(par, 0x2128, 0x4000); | |
375 | writemmr(par, 0x2140, masked_point(h, w)); | |
376 | writemmr(par, 0x2138, masked_point(y, x)); | |
377 | t_outb(par, 0x01, 0x2124); | |
378 | t_outb(par, eng_oper, 0x2125); | |
1da177e4 LT |
379 | } |
380 | ||
306fa6f6 KH |
381 | static void xp_copy_rect(struct tridentfb_par *par, |
382 | u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h) | |
1da177e4 LT |
383 | { |
384 | int direction; | |
245a2c2c | 385 | u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp; |
1da177e4 LT |
386 | |
387 | direction = 0x0004; | |
245a2c2c | 388 | |
1da177e4 LT |
389 | if ((x1 < x2) && (y1 == y2)) { |
390 | direction |= 0x0200; | |
391 | x1_tmp = x1 + w - 1; | |
392 | x2_tmp = x2 + w - 1; | |
393 | } else { | |
394 | x1_tmp = x1; | |
395 | x2_tmp = x2; | |
396 | } | |
245a2c2c | 397 | |
1da177e4 LT |
398 | if (y1 < y2) { |
399 | direction |= 0x0100; | |
400 | y1_tmp = y1 + h - 1; | |
401 | y2_tmp = y2 + h - 1; | |
245a2c2c | 402 | } else { |
1da177e4 LT |
403 | y1_tmp = y1; |
404 | y2_tmp = y2; | |
405 | } | |
406 | ||
306fa6f6 KH |
407 | writemmr(par, 0x2128, direction); |
408 | t_outb(par, ROP_S, 0x2127); | |
409 | writemmr(par, 0x213C, masked_point(y1_tmp, x1_tmp)); | |
410 | writemmr(par, 0x2138, masked_point(y2_tmp, x2_tmp)); | |
411 | writemmr(par, 0x2140, masked_point(h, w)); | |
412 | t_outb(par, 0x01, 0x2124); | |
1da177e4 LT |
413 | } |
414 | ||
1da177e4 LT |
415 | /* |
416 | * Image specific acceleration functions | |
417 | */ | |
306fa6f6 | 418 | static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp) |
1da177e4 LT |
419 | { |
420 | int tmp = 0; | |
245a2c2c KH |
421 | switch (bpp) { |
422 | case 8: | |
423 | tmp = 0; | |
424 | break; | |
425 | case 15: | |
426 | tmp = 5; | |
427 | break; | |
428 | case 16: | |
429 | tmp = 1; | |
430 | break; | |
431 | case 24: | |
432 | case 32: | |
433 | tmp = 2; | |
434 | break; | |
1da177e4 | 435 | } |
306fa6f6 KH |
436 | writemmr(par, 0x2120, 0xF0000000); |
437 | writemmr(par, 0x2120, 0x40000000 | tmp); | |
438 | writemmr(par, 0x2120, 0x80000000); | |
439 | writemmr(par, 0x2144, 0x00000000); | |
440 | writemmr(par, 0x2148, 0x00000000); | |
441 | writemmr(par, 0x2150, 0x00000000); | |
442 | writemmr(par, 0x2154, 0x00000000); | |
443 | writemmr(par, 0x2120, 0x60000000 | (pitch << 16) | pitch); | |
444 | writemmr(par, 0x216C, 0x00000000); | |
445 | writemmr(par, 0x2170, 0x00000000); | |
446 | writemmr(par, 0x217C, 0x00000000); | |
447 | writemmr(par, 0x2120, 0x10000000); | |
448 | writemmr(par, 0x2130, (2047 << 16) | 2047); | |
1da177e4 LT |
449 | } |
450 | ||
306fa6f6 | 451 | static void image_wait_engine(struct tridentfb_par *par) |
1da177e4 | 452 | { |
306fa6f6 | 453 | while (readmmr(par, 0x2164) & 0xF0000000) ; |
1da177e4 LT |
454 | } |
455 | ||
306fa6f6 KH |
456 | static void image_fill_rect(struct tridentfb_par *par, |
457 | u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop) | |
1da177e4 | 458 | { |
306fa6f6 KH |
459 | writemmr(par, 0x2120, 0x80000000); |
460 | writemmr(par, 0x2120, 0x90000000 | ROP_S); | |
1da177e4 | 461 | |
306fa6f6 | 462 | writemmr(par, 0x2144, c); |
1da177e4 | 463 | |
306fa6f6 KH |
464 | writemmr(par, DR1, point(x, y)); |
465 | writemmr(par, DR2, point(x + w - 1, y + h - 1)); | |
1da177e4 | 466 | |
306fa6f6 | 467 | writemmr(par, 0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9); |
1da177e4 LT |
468 | } |
469 | ||
306fa6f6 KH |
470 | static void image_copy_rect(struct tridentfb_par *par, |
471 | u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h) | |
1da177e4 | 472 | { |
245a2c2c | 473 | u32 s1, s2, d1, d2; |
1da177e4 | 474 | int direction = 2; |
245a2c2c KH |
475 | s1 = point(x1, y1); |
476 | s2 = point(x1 + w - 1, y1 + h - 1); | |
477 | d1 = point(x2, y2); | |
478 | d2 = point(x2 + w - 1, y2 + h - 1); | |
1da177e4 | 479 | |
245a2c2c KH |
480 | if ((y1 > y2) || ((y1 == y2) && (x1 > x2))) |
481 | direction = 0; | |
482 | ||
306fa6f6 KH |
483 | writemmr(par, 0x2120, 0x80000000); |
484 | writemmr(par, 0x2120, 0x90000000 | ROP_S); | |
245a2c2c | 485 | |
306fa6f6 KH |
486 | writemmr(par, SR1, direction ? s2 : s1); |
487 | writemmr(par, SR2, direction ? s1 : s2); | |
488 | writemmr(par, DR1, direction ? d2 : d1); | |
489 | writemmr(par, DR2, direction ? d1 : d2); | |
490 | writemmr(par, 0x2124, | |
491 | 0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction); | |
245a2c2c | 492 | } |
1da177e4 | 493 | |
1da177e4 LT |
494 | /* |
495 | * Accel functions called by the upper layers | |
496 | */ | |
497 | #ifdef CONFIG_FB_TRIDENT_ACCEL | |
245a2c2c KH |
498 | static void tridentfb_fillrect(struct fb_info *info, |
499 | const struct fb_fillrect *fr) | |
1da177e4 | 500 | { |
306fa6f6 | 501 | struct tridentfb_par *par = info->par; |
1da177e4 | 502 | int bpp = info->var.bits_per_pixel; |
8dad46cf | 503 | int col = 0; |
245a2c2c | 504 | |
1da177e4 | 505 | switch (bpp) { |
245a2c2c KH |
506 | default: |
507 | case 8: | |
508 | col |= fr->color; | |
509 | col |= col << 8; | |
510 | col |= col << 16; | |
511 | break; | |
512 | case 16: | |
513 | col = ((u32 *)(info->pseudo_palette))[fr->color]; | |
514 | break; | |
515 | case 32: | |
516 | col = ((u32 *)(info->pseudo_palette))[fr->color]; | |
517 | break; | |
518 | } | |
519 | ||
d9cad04b | 520 | par->fill_rect(par, fr->dx, fr->dy, fr->width, |
306fa6f6 | 521 | fr->height, col, fr->rop); |
d9cad04b | 522 | par->wait_engine(par); |
1da177e4 | 523 | } |
245a2c2c KH |
524 | static void tridentfb_copyarea(struct fb_info *info, |
525 | const struct fb_copyarea *ca) | |
1da177e4 | 526 | { |
306fa6f6 KH |
527 | struct tridentfb_par *par = info->par; |
528 | ||
d9cad04b | 529 | par->copy_rect(par, ca->sx, ca->sy, ca->dx, ca->dy, |
306fa6f6 | 530 | ca->width, ca->height); |
d9cad04b | 531 | par->wait_engine(par); |
1da177e4 LT |
532 | } |
533 | #else /* !CONFIG_FB_TRIDENT_ACCEL */ | |
534 | #define tridentfb_fillrect cfb_fillrect | |
535 | #define tridentfb_copyarea cfb_copyarea | |
536 | #endif /* CONFIG_FB_TRIDENT_ACCEL */ | |
537 | ||
538 | ||
539 | /* | |
540 | * Hardware access functions | |
541 | */ | |
542 | ||
306fa6f6 | 543 | static inline unsigned char read3X4(struct tridentfb_par *par, int reg) |
1da177e4 | 544 | { |
10172ed6 | 545 | return vga_mm_rcrt(par->io_virt, reg); |
1da177e4 LT |
546 | } |
547 | ||
306fa6f6 KH |
548 | static inline void write3X4(struct tridentfb_par *par, int reg, |
549 | unsigned char val) | |
1da177e4 | 550 | { |
10172ed6 | 551 | vga_mm_wcrt(par->io_virt, reg, val); |
1da177e4 LT |
552 | } |
553 | ||
10172ed6 KH |
554 | static inline unsigned char read3CE(struct tridentfb_par *par, |
555 | unsigned char reg) | |
1da177e4 | 556 | { |
10172ed6 | 557 | return vga_mm_rgfx(par->io_virt, reg); |
1da177e4 LT |
558 | } |
559 | ||
306fa6f6 KH |
560 | static inline void writeAttr(struct tridentfb_par *par, int reg, |
561 | unsigned char val) | |
1da177e4 | 562 | { |
10172ed6 KH |
563 | fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */ |
564 | vga_mm_wattr(par->io_virt, reg, val); | |
1da177e4 LT |
565 | } |
566 | ||
306fa6f6 KH |
567 | static inline void write3CE(struct tridentfb_par *par, int reg, |
568 | unsigned char val) | |
1da177e4 | 569 | { |
10172ed6 | 570 | vga_mm_wgfx(par->io_virt, reg, val); |
1da177e4 LT |
571 | } |
572 | ||
e8ed857c | 573 | static void enable_mmio(void) |
1da177e4 LT |
574 | { |
575 | /* Goto New Mode */ | |
10172ed6 | 576 | vga_io_rseq(0x0B); |
1da177e4 LT |
577 | |
578 | /* Unprotect registers */ | |
10172ed6 | 579 | vga_io_wseq(NewMode1, 0x80); |
245a2c2c | 580 | |
1da177e4 | 581 | /* Enable MMIO */ |
245a2c2c | 582 | outb(PCIReg, 0x3D4); |
1da177e4 | 583 | outb(inb(0x3D5) | 0x01, 0x3D5); |
e8ed857c KH |
584 | } |
585 | ||
306fa6f6 | 586 | static void disable_mmio(struct tridentfb_par *par) |
e8ed857c | 587 | { |
e8ed857c | 588 | /* Goto New Mode */ |
10172ed6 | 589 | vga_mm_rseq(par->io_virt, 0x0B); |
e8ed857c KH |
590 | |
591 | /* Unprotect registers */ | |
10172ed6 | 592 | vga_mm_wseq(par->io_virt, NewMode1, 0x80); |
e8ed857c KH |
593 | |
594 | /* Disable MMIO */ | |
306fa6f6 KH |
595 | t_outb(par, PCIReg, 0x3D4); |
596 | t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5); | |
1da177e4 LT |
597 | } |
598 | ||
306fa6f6 KH |
599 | static void crtc_unlock(struct tridentfb_par *par) |
600 | { | |
10172ed6 KH |
601 | write3X4(par, VGA_CRTC_V_SYNC_END, |
602 | read3X4(par, VGA_CRTC_V_SYNC_END) & 0x7F); | |
306fa6f6 | 603 | } |
1da177e4 LT |
604 | |
605 | /* Return flat panel's maximum x resolution */ | |
306fa6f6 | 606 | static int __devinit get_nativex(struct tridentfb_par *par) |
1da177e4 | 607 | { |
245a2c2c | 608 | int x, y, tmp; |
1da177e4 LT |
609 | |
610 | if (nativex) | |
611 | return nativex; | |
612 | ||
306fa6f6 | 613 | tmp = (read3CE(par, VertStretch) >> 4) & 3; |
1da177e4 LT |
614 | |
615 | switch (tmp) { | |
245a2c2c KH |
616 | case 0: |
617 | x = 1280; y = 1024; | |
618 | break; | |
619 | case 2: | |
620 | x = 1024; y = 768; | |
621 | break; | |
622 | case 3: | |
623 | x = 800; y = 600; | |
624 | break; | |
625 | case 4: | |
626 | x = 1400; y = 1050; | |
627 | break; | |
628 | case 1: | |
629 | default: | |
630 | x = 640; y = 480; | |
631 | break; | |
1da177e4 LT |
632 | } |
633 | ||
634 | output("%dx%d flat panel found\n", x, y); | |
635 | return x; | |
636 | } | |
637 | ||
638 | /* Set pitch */ | |
306fa6f6 | 639 | static void set_lwidth(struct tridentfb_par *par, int width) |
1da177e4 | 640 | { |
10172ed6 | 641 | write3X4(par, VGA_CRTC_OFFSET, width & 0xFF); |
306fa6f6 KH |
642 | write3X4(par, AddColReg, |
643 | (read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4)); | |
1da177e4 LT |
644 | } |
645 | ||
646 | /* For resolutions smaller than FP resolution stretch */ | |
306fa6f6 | 647 | static void screen_stretch(struct tridentfb_par *par) |
1da177e4 | 648 | { |
122e8ad3 | 649 | if (par->chip_id != CYBERBLADEXPAi1) |
306fa6f6 | 650 | write3CE(par, BiosReg, 0); |
245a2c2c | 651 | else |
306fa6f6 KH |
652 | write3CE(par, BiosReg, 8); |
653 | write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 1); | |
654 | write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 1); | |
1da177e4 LT |
655 | } |
656 | ||
657 | /* For resolutions smaller than FP resolution center */ | |
306fa6f6 | 658 | static void screen_center(struct tridentfb_par *par) |
1da177e4 | 659 | { |
306fa6f6 KH |
660 | write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 0x80); |
661 | write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 0x80); | |
1da177e4 LT |
662 | } |
663 | ||
664 | /* Address of first shown pixel in display memory */ | |
306fa6f6 | 665 | static void set_screen_start(struct tridentfb_par *par, int base) |
1da177e4 | 666 | { |
306fa6f6 | 667 | u8 tmp; |
10172ed6 KH |
668 | write3X4(par, VGA_CRTC_START_LO, base & 0xFF); |
669 | write3X4(par, VGA_CRTC_START_HI, (base & 0xFF00) >> 8); | |
306fa6f6 KH |
670 | tmp = read3X4(par, CRTCModuleTest) & 0xDF; |
671 | write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11)); | |
672 | tmp = read3X4(par, CRTHiOrd) & 0xF8; | |
673 | write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17)); | |
1da177e4 LT |
674 | } |
675 | ||
1da177e4 | 676 | /* Set dotclock frequency */ |
306fa6f6 | 677 | static void set_vclk(struct tridentfb_par *par, unsigned long freq) |
1da177e4 | 678 | { |
245a2c2c | 679 | int m, n, k; |
6bdf1035 KH |
680 | unsigned long fi, d, di; |
681 | unsigned char best_m = 0, best_n = 0, best_k = 0; | |
682 | unsigned char hi, lo; | |
1da177e4 | 683 | |
3f275ea3 | 684 | d = 20000; |
6bdf1035 KH |
685 | for (k = 1; k >= 0; k--) |
686 | for (m = 0; m < 32; m++) | |
687 | for (n = 0; n < 122; n++) { | |
3f275ea3 | 688 | fi = ((14318l * (n + 8)) / (m + 2)) >> k; |
245a2c2c KH |
689 | if ((di = abs(fi - freq)) < d) { |
690 | d = di; | |
6bdf1035 KH |
691 | best_n = n; |
692 | best_m = m; | |
693 | best_k = k; | |
245a2c2c | 694 | } |
3f275ea3 KH |
695 | if (fi > freq) |
696 | break; | |
245a2c2c | 697 | } |
6bdf1035 KH |
698 | |
699 | if (is_oldclock(par->chip_id)) { | |
700 | lo = best_n | (best_m << 7); | |
701 | hi = (best_m >> 1) | (best_k << 4); | |
702 | } else { | |
703 | lo = best_n; | |
704 | hi = best_m | (best_k << 6); | |
705 | } | |
706 | ||
122e8ad3 | 707 | if (is3Dchip(par->chip_id)) { |
10172ed6 KH |
708 | vga_mm_wseq(par->io_virt, ClockHigh, hi); |
709 | vga_mm_wseq(par->io_virt, ClockLow, lo); | |
1da177e4 | 710 | } else { |
c1724fec KH |
711 | t_outb(par, lo, 0x43C8); |
712 | t_outb(par, hi, 0x43C9); | |
1da177e4 | 713 | } |
245a2c2c | 714 | debug("VCLK = %X %X\n", hi, lo); |
1da177e4 LT |
715 | } |
716 | ||
717 | /* Set number of lines for flat panels*/ | |
306fa6f6 | 718 | static void set_number_of_lines(struct tridentfb_par *par, int lines) |
1da177e4 | 719 | { |
306fa6f6 | 720 | int tmp = read3CE(par, CyberEnhance) & 0x8F; |
1da177e4 LT |
721 | if (lines > 1024) |
722 | tmp |= 0x50; | |
723 | else if (lines > 768) | |
724 | tmp |= 0x30; | |
725 | else if (lines > 600) | |
726 | tmp |= 0x20; | |
727 | else if (lines > 480) | |
728 | tmp |= 0x10; | |
306fa6f6 | 729 | write3CE(par, CyberEnhance, tmp); |
1da177e4 LT |
730 | } |
731 | ||
732 | /* | |
733 | * If we see that FP is active we assume we have one. | |
6eed8e1e | 734 | * Otherwise we have a CRT display. User can override. |
1da177e4 | 735 | */ |
6eed8e1e | 736 | static int __devinit is_flatpanel(struct tridentfb_par *par) |
1da177e4 LT |
737 | { |
738 | if (fp) | |
6eed8e1e | 739 | return 1; |
122e8ad3 | 740 | if (crt || !iscyber(par->chip_id)) |
6eed8e1e KH |
741 | return 0; |
742 | return (read3CE(par, FPConfig) & 0x10) ? 1 : 0; | |
1da177e4 LT |
743 | } |
744 | ||
745 | /* Try detecting the video memory size */ | |
306fa6f6 | 746 | static unsigned int __devinit get_memsize(struct tridentfb_par *par) |
1da177e4 LT |
747 | { |
748 | unsigned char tmp, tmp2; | |
749 | unsigned int k; | |
750 | ||
751 | /* If memory size provided by user */ | |
752 | if (memsize) | |
753 | k = memsize * Kb; | |
754 | else | |
122e8ad3 | 755 | switch (par->chip_id) { |
245a2c2c KH |
756 | case CYBER9525DVD: |
757 | k = 2560 * Kb; | |
758 | break; | |
1da177e4 | 759 | default: |
306fa6f6 | 760 | tmp = read3X4(par, SPR) & 0x0F; |
1da177e4 LT |
761 | switch (tmp) { |
762 | ||
245a2c2c | 763 | case 0x01: |
b614ce8b | 764 | k = 512 * Kb; |
245a2c2c KH |
765 | break; |
766 | case 0x02: | |
767 | k = 6 * Mb; /* XP */ | |
768 | break; | |
769 | case 0x03: | |
770 | k = 1 * Mb; | |
771 | break; | |
772 | case 0x04: | |
773 | k = 8 * Mb; | |
774 | break; | |
775 | case 0x06: | |
776 | k = 10 * Mb; /* XP */ | |
777 | break; | |
778 | case 0x07: | |
779 | k = 2 * Mb; | |
780 | break; | |
781 | case 0x08: | |
782 | k = 12 * Mb; /* XP */ | |
783 | break; | |
784 | case 0x0A: | |
785 | k = 14 * Mb; /* XP */ | |
786 | break; | |
787 | case 0x0C: | |
788 | k = 16 * Mb; /* XP */ | |
789 | break; | |
790 | case 0x0E: /* XP */ | |
791 | ||
10172ed6 | 792 | tmp2 = vga_mm_rseq(par->io_virt, 0xC1); |
245a2c2c KH |
793 | switch (tmp2) { |
794 | case 0x00: | |
795 | k = 20 * Mb; | |
796 | break; | |
797 | case 0x01: | |
798 | k = 24 * Mb; | |
799 | break; | |
800 | case 0x10: | |
801 | k = 28 * Mb; | |
802 | break; | |
803 | case 0x11: | |
804 | k = 32 * Mb; | |
805 | break; | |
806 | default: | |
807 | k = 1 * Mb; | |
808 | break; | |
809 | } | |
810 | break; | |
811 | ||
812 | case 0x0F: | |
813 | k = 4 * Mb; | |
814 | break; | |
815 | default: | |
816 | k = 1 * Mb; | |
1da177e4 | 817 | break; |
1da177e4 | 818 | } |
245a2c2c | 819 | } |
1da177e4 LT |
820 | |
821 | k -= memdiff * Kb; | |
245a2c2c | 822 | output("framebuffer size = %d Kb\n", k / Kb); |
1da177e4 LT |
823 | return k; |
824 | } | |
825 | ||
826 | /* See if we can handle the video mode described in var */ | |
245a2c2c KH |
827 | static int tridentfb_check_var(struct fb_var_screeninfo *var, |
828 | struct fb_info *info) | |
1da177e4 | 829 | { |
6eed8e1e | 830 | struct tridentfb_par *par = info->par; |
1da177e4 | 831 | int bpp = var->bits_per_pixel; |
74a933fe | 832 | int ramdac = 230000; /* 230MHz for most 3D chips */ |
1da177e4 LT |
833 | debug("enter\n"); |
834 | ||
835 | /* check color depth */ | |
245a2c2c | 836 | if (bpp == 24) |
1da177e4 | 837 | bpp = var->bits_per_pixel = 32; |
245a2c2c | 838 | /* check whether resolution fits on panel and in memory */ |
6eed8e1e | 839 | if (par->flatpanel && nativex && var->xres > nativex) |
1da177e4 | 840 | return -EINVAL; |
74a933fe KH |
841 | /* various resolution checks */ |
842 | var->xres = (var->xres + 7) & ~0x7; | |
843 | if (var->xres != var->xres_virtual) | |
844 | var->xres_virtual = var->xres; | |
845 | if (var->yres > var->yres_virtual) | |
846 | var->yres_virtual = var->yres; | |
245a2c2c | 847 | if (var->xres * var->yres_virtual * bpp / 8 > info->fix.smem_len) |
1da177e4 LT |
848 | return -EINVAL; |
849 | ||
850 | switch (bpp) { | |
245a2c2c KH |
851 | case 8: |
852 | var->red.offset = 0; | |
853 | var->green.offset = 0; | |
854 | var->blue.offset = 0; | |
855 | var->red.length = 6; | |
856 | var->green.length = 6; | |
857 | var->blue.length = 6; | |
858 | break; | |
859 | case 16: | |
860 | var->red.offset = 11; | |
861 | var->green.offset = 5; | |
862 | var->blue.offset = 0; | |
863 | var->red.length = 5; | |
864 | var->green.length = 6; | |
865 | var->blue.length = 5; | |
866 | break; | |
867 | case 32: | |
868 | var->red.offset = 16; | |
869 | var->green.offset = 8; | |
870 | var->blue.offset = 0; | |
871 | var->red.length = 8; | |
872 | var->green.length = 8; | |
873 | var->blue.length = 8; | |
874 | break; | |
875 | default: | |
876 | return -EINVAL; | |
1da177e4 | 877 | } |
74a933fe KH |
878 | |
879 | if (is_xp(par->chip_id)) | |
880 | ramdac = 350000; | |
881 | ||
882 | switch (par->chip_id) { | |
883 | case TGUI9440: | |
884 | ramdac = 90000; | |
885 | break; | |
886 | case CYBER9320: | |
887 | case TGUI9660: | |
888 | ramdac = 135000; | |
889 | break; | |
890 | case PROVIDIA9685: | |
891 | case CYBER9388: | |
892 | case CYBER9382: | |
893 | case CYBER9385: | |
894 | ramdac = 170000; | |
895 | break; | |
896 | } | |
897 | ||
898 | /* The clock is doubled for 32 bpp */ | |
899 | if (bpp == 32) | |
900 | ramdac /= 2; | |
901 | ||
902 | if (PICOS2KHZ(var->pixclock) > ramdac) | |
903 | return -EINVAL; | |
904 | ||
1da177e4 LT |
905 | debug("exit\n"); |
906 | ||
907 | return 0; | |
908 | ||
909 | } | |
245a2c2c | 910 | |
1da177e4 LT |
911 | /* Pan the display */ |
912 | static int tridentfb_pan_display(struct fb_var_screeninfo *var, | |
245a2c2c | 913 | struct fb_info *info) |
1da177e4 | 914 | { |
306fa6f6 | 915 | struct tridentfb_par *par = info->par; |
1da177e4 LT |
916 | unsigned int offset; |
917 | ||
918 | debug("enter\n"); | |
919 | offset = (var->xoffset + (var->yoffset * var->xres)) | |
245a2c2c | 920 | * var->bits_per_pixel / 32; |
1da177e4 LT |
921 | info->var.xoffset = var->xoffset; |
922 | info->var.yoffset = var->yoffset; | |
306fa6f6 | 923 | set_screen_start(par, offset); |
1da177e4 LT |
924 | debug("exit\n"); |
925 | return 0; | |
926 | } | |
927 | ||
306fa6f6 KH |
928 | static void shadowmode_on(struct tridentfb_par *par) |
929 | { | |
930 | write3CE(par, CyberControl, read3CE(par, CyberControl) | 0x81); | |
931 | } | |
932 | ||
933 | static void shadowmode_off(struct tridentfb_par *par) | |
934 | { | |
935 | write3CE(par, CyberControl, read3CE(par, CyberControl) & 0x7E); | |
936 | } | |
1da177e4 LT |
937 | |
938 | /* Set the hardware to the requested video mode */ | |
939 | static int tridentfb_set_par(struct fb_info *info) | |
940 | { | |
245a2c2c KH |
941 | struct tridentfb_par *par = (struct tridentfb_par *)(info->par); |
942 | u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend; | |
943 | u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend; | |
944 | struct fb_var_screeninfo *var = &info->var; | |
1da177e4 LT |
945 | int bpp = var->bits_per_pixel; |
946 | unsigned char tmp; | |
3f275ea3 KH |
947 | unsigned long vclk; |
948 | ||
1da177e4 | 949 | debug("enter\n"); |
245a2c2c | 950 | hdispend = var->xres / 8 - 1; |
7f762d23 KH |
951 | hsyncstart = (var->xres + var->right_margin) / 8 - 1; |
952 | hsyncend = (var->xres + var->right_margin + var->hsync_len) / 8 - 1; | |
953 | htotal = (var->xres + var->left_margin + var->right_margin + | |
954 | var->hsync_len) / 8 - 5; | |
0e73a47f | 955 | hblankstart = hdispend + 1; |
7f762d23 | 956 | hblankend = htotal + 3; |
1da177e4 | 957 | |
1da177e4 LT |
958 | vdispend = var->yres - 1; |
959 | vsyncstart = var->yres + var->lower_margin; | |
7f762d23 KH |
960 | vsyncend = vsyncstart + var->vsync_len; |
961 | vtotal = var->upper_margin + vsyncend - 2; | |
0e73a47f | 962 | vblankstart = vdispend + 1; |
7f762d23 | 963 | vblankend = vtotal; |
1da177e4 | 964 | |
306fa6f6 KH |
965 | crtc_unlock(par); |
966 | write3CE(par, CyberControl, 8); | |
1da177e4 | 967 | |
6eed8e1e | 968 | if (par->flatpanel && var->xres < nativex) { |
1da177e4 LT |
969 | /* |
970 | * on flat panels with native size larger | |
971 | * than requested resolution decide whether | |
972 | * we stretch or center | |
973 | */ | |
10172ed6 | 974 | t_outb(par, 0xEB, VGA_MIS_W); |
1da177e4 | 975 | |
306fa6f6 | 976 | shadowmode_on(par); |
1da177e4 | 977 | |
245a2c2c | 978 | if (center) |
306fa6f6 | 979 | screen_center(par); |
1da177e4 | 980 | else if (stretch) |
306fa6f6 | 981 | screen_stretch(par); |
1da177e4 LT |
982 | |
983 | } else { | |
10172ed6 | 984 | t_outb(par, 0x2B, VGA_MIS_W); |
306fa6f6 | 985 | write3CE(par, CyberControl, 8); |
1da177e4 LT |
986 | } |
987 | ||
988 | /* vertical timing values */ | |
10172ed6 KH |
989 | write3X4(par, VGA_CRTC_V_TOTAL, vtotal & 0xFF); |
990 | write3X4(par, VGA_CRTC_V_DISP_END, vdispend & 0xFF); | |
991 | write3X4(par, VGA_CRTC_V_SYNC_START, vsyncstart & 0xFF); | |
992 | write3X4(par, VGA_CRTC_V_SYNC_END, (vsyncend & 0x0F)); | |
993 | write3X4(par, VGA_CRTC_V_BLANK_START, vblankstart & 0xFF); | |
7f762d23 | 994 | write3X4(par, VGA_CRTC_V_BLANK_END, vblankend & 0xFF); |
1da177e4 LT |
995 | |
996 | /* horizontal timing values */ | |
10172ed6 KH |
997 | write3X4(par, VGA_CRTC_H_TOTAL, htotal & 0xFF); |
998 | write3X4(par, VGA_CRTC_H_DISP, hdispend & 0xFF); | |
999 | write3X4(par, VGA_CRTC_H_SYNC_START, hsyncstart & 0xFF); | |
1000 | write3X4(par, VGA_CRTC_H_SYNC_END, | |
306fa6f6 | 1001 | (hsyncend & 0x1F) | ((hblankend & 0x20) << 2)); |
10172ed6 | 1002 | write3X4(par, VGA_CRTC_H_BLANK_START, hblankstart & 0xFF); |
7f762d23 | 1003 | write3X4(par, VGA_CRTC_H_BLANK_END, hblankend & 0x1F); |
1da177e4 LT |
1004 | |
1005 | /* higher bits of vertical timing values */ | |
1006 | tmp = 0x10; | |
1007 | if (vtotal & 0x100) tmp |= 0x01; | |
1008 | if (vdispend & 0x100) tmp |= 0x02; | |
1009 | if (vsyncstart & 0x100) tmp |= 0x04; | |
1010 | if (vblankstart & 0x100) tmp |= 0x08; | |
1011 | ||
1012 | if (vtotal & 0x200) tmp |= 0x20; | |
1013 | if (vdispend & 0x200) tmp |= 0x40; | |
1014 | if (vsyncstart & 0x200) tmp |= 0x80; | |
10172ed6 | 1015 | write3X4(par, VGA_CRTC_OVERFLOW, tmp); |
1da177e4 | 1016 | |
7f762d23 KH |
1017 | tmp = read3X4(par, CRTHiOrd) & 0x07; |
1018 | tmp |= 0x08; /* line compare bit 10 */ | |
1da177e4 LT |
1019 | if (vtotal & 0x400) tmp |= 0x80; |
1020 | if (vblankstart & 0x400) tmp |= 0x40; | |
1021 | if (vsyncstart & 0x400) tmp |= 0x20; | |
1022 | if (vdispend & 0x400) tmp |= 0x10; | |
306fa6f6 | 1023 | write3X4(par, CRTHiOrd, tmp); |
1da177e4 | 1024 | |
7f762d23 KH |
1025 | tmp = (htotal >> 8) & 0x01; |
1026 | tmp |= (hdispend >> 7) & 0x02; | |
1027 | tmp |= (hsyncstart >> 5) & 0x08; | |
1028 | tmp |= (hblankstart >> 4) & 0x10; | |
306fa6f6 | 1029 | write3X4(par, HorizOverflow, tmp); |
245a2c2c | 1030 | |
1da177e4 LT |
1031 | tmp = 0x40; |
1032 | if (vblankstart & 0x200) tmp |= 0x20; | |
245a2c2c | 1033 | //FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */ |
10172ed6 | 1034 | write3X4(par, VGA_CRTC_MAX_SCAN, tmp); |
1da177e4 | 1035 | |
10172ed6 KH |
1036 | write3X4(par, VGA_CRTC_LINE_COMPARE, 0xFF); |
1037 | write3X4(par, VGA_CRTC_PRESET_ROW, 0); | |
1038 | write3X4(par, VGA_CRTC_MODE, 0xC3); | |
1da177e4 | 1039 | |
306fa6f6 | 1040 | write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */ |
1da177e4 | 1041 | |
245a2c2c | 1042 | tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80; |
306fa6f6 KH |
1043 | /* enable access extended memory */ |
1044 | write3X4(par, CRTCModuleTest, tmp); | |
1da177e4 | 1045 | |
306fa6f6 KH |
1046 | /* enable GE for text acceleration */ |
1047 | write3X4(par, GraphEngReg, 0x80); | |
1da177e4 | 1048 | |
245a2c2c | 1049 | #ifdef CONFIG_FB_TRIDENT_ACCEL |
d9cad04b | 1050 | par->init_accel(par, info->var.xres, bpp); |
8dad46cf | 1051 | #endif |
245a2c2c | 1052 | |
1da177e4 | 1053 | switch (bpp) { |
245a2c2c KH |
1054 | case 8: |
1055 | tmp = 0x00; | |
1056 | break; | |
1057 | case 16: | |
1058 | tmp = 0x05; | |
1059 | break; | |
1060 | case 24: | |
1061 | tmp = 0x29; | |
1062 | break; | |
1063 | case 32: | |
1064 | tmp = 0x09; | |
1065 | break; | |
1da177e4 LT |
1066 | } |
1067 | ||
306fa6f6 | 1068 | write3X4(par, PixelBusReg, tmp); |
1da177e4 | 1069 | |
0e73a47f KH |
1070 | tmp = read3X4(par, DRAMControl); |
1071 | if (!is_oldprotect(par->chip_id)) | |
1072 | tmp |= 0x10; | |
122e8ad3 | 1073 | if (iscyber(par->chip_id)) |
245a2c2c | 1074 | tmp |= 0x20; |
306fa6f6 | 1075 | write3X4(par, DRAMControl, tmp); /* both IO, linear enable */ |
1da177e4 | 1076 | |
306fa6f6 | 1077 | write3X4(par, InterfaceSel, read3X4(par, InterfaceSel) | 0x40); |
0e73a47f KH |
1078 | if (!is_xp(par->chip_id)) |
1079 | write3X4(par, Performance, read3X4(par, Performance) | 0x10); | |
306fa6f6 | 1080 | /* MMIO & PCI read and write burst enable */ |
a0d92256 KH |
1081 | if (par->chip_id != TGUI9440) |
1082 | write3X4(par, PCIReg, read3X4(par, PCIReg) | 0x06); | |
1da177e4 | 1083 | |
3f275ea3 KH |
1084 | /* convert from picoseconds to kHz */ |
1085 | vclk = PICOS2KHZ(info->var.pixclock); | |
1da177e4 | 1086 | if (bpp == 32) |
3f275ea3 | 1087 | vclk *= 2; |
306fa6f6 | 1088 | set_vclk(par, vclk); |
1da177e4 | 1089 | |
10172ed6 KH |
1090 | vga_mm_wseq(par->io_virt, 0, 3); |
1091 | vga_mm_wseq(par->io_virt, 1, 1); /* set char clock 8 dots wide */ | |
306fa6f6 | 1092 | /* enable 4 maps because needed in chain4 mode */ |
10172ed6 KH |
1093 | vga_mm_wseq(par->io_virt, 2, 0x0F); |
1094 | vga_mm_wseq(par->io_virt, 3, 0); | |
1095 | vga_mm_wseq(par->io_virt, 4, 0x0E); /* memory mode enable bitmaps ?? */ | |
1da177e4 | 1096 | |
306fa6f6 KH |
1097 | /* divide clock by 2 if 32bpp chain4 mode display and CPU path */ |
1098 | write3CE(par, MiscExtFunc, (bpp == 32) ? 0x1A : 0x12); | |
1099 | write3CE(par, 0x5, 0x40); /* no CGA compat, allow 256 col */ | |
1100 | write3CE(par, 0x6, 0x05); /* graphics mode */ | |
1101 | write3CE(par, 0x7, 0x0F); /* planes? */ | |
1da177e4 | 1102 | |
122e8ad3 | 1103 | if (par->chip_id == CYBERBLADEXPAi1) { |
1da177e4 | 1104 | /* This fixes snow-effect in 32 bpp */ |
10172ed6 | 1105 | write3X4(par, VGA_CRTC_H_SYNC_START, 0x84); |
1da177e4 LT |
1106 | } |
1107 | ||
306fa6f6 KH |
1108 | /* graphics mode and support 256 color modes */ |
1109 | writeAttr(par, 0x10, 0x41); | |
1110 | writeAttr(par, 0x12, 0x0F); /* planes */ | |
1111 | writeAttr(par, 0x13, 0); /* horizontal pel panning */ | |
1da177e4 | 1112 | |
245a2c2c KH |
1113 | /* colors */ |
1114 | for (tmp = 0; tmp < 0x10; tmp++) | |
306fa6f6 | 1115 | writeAttr(par, tmp, tmp); |
10172ed6 KH |
1116 | fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */ |
1117 | t_outb(par, 0x20, VGA_ATT_W); /* enable attr */ | |
1da177e4 LT |
1118 | |
1119 | switch (bpp) { | |
245a2c2c KH |
1120 | case 8: |
1121 | tmp = 0; | |
1122 | break; | |
1123 | case 15: | |
1124 | tmp = 0x10; | |
1125 | break; | |
1126 | case 16: | |
1127 | tmp = 0x30; | |
1128 | break; | |
1129 | case 24: | |
1130 | case 32: | |
1131 | tmp = 0xD0; | |
1132 | break; | |
1da177e4 LT |
1133 | } |
1134 | ||
10172ed6 KH |
1135 | t_inb(par, VGA_PEL_IW); |
1136 | t_inb(par, VGA_PEL_MSK); | |
1137 | t_inb(par, VGA_PEL_MSK); | |
1138 | t_inb(par, VGA_PEL_MSK); | |
1139 | t_inb(par, VGA_PEL_MSK); | |
1140 | t_outb(par, tmp, VGA_PEL_MSK); | |
1141 | t_inb(par, VGA_PEL_IW); | |
1da177e4 | 1142 | |
6eed8e1e | 1143 | if (par->flatpanel) |
306fa6f6 KH |
1144 | set_number_of_lines(par, info->var.yres); |
1145 | set_lwidth(par, info->var.xres * bpp / (4 * 16)); | |
1da177e4 | 1146 | info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; |
245a2c2c KH |
1147 | info->fix.line_length = info->var.xres * (bpp >> 3); |
1148 | info->cmap.len = (bpp == 8) ? 256 : 16; | |
1da177e4 LT |
1149 | debug("exit\n"); |
1150 | return 0; | |
1151 | } | |
1152 | ||
1153 | /* Set one color register */ | |
1154 | static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green, | |
245a2c2c KH |
1155 | unsigned blue, unsigned transp, |
1156 | struct fb_info *info) | |
1da177e4 LT |
1157 | { |
1158 | int bpp = info->var.bits_per_pixel; | |
306fa6f6 | 1159 | struct tridentfb_par *par = info->par; |
1da177e4 LT |
1160 | |
1161 | if (regno >= info->cmap.len) | |
1162 | return 1; | |
1163 | ||
973d9ab2 | 1164 | if (bpp == 8) { |
10172ed6 KH |
1165 | t_outb(par, 0xFF, VGA_PEL_MSK); |
1166 | t_outb(par, regno, VGA_PEL_IW); | |
1da177e4 | 1167 | |
10172ed6 KH |
1168 | t_outb(par, red >> 10, VGA_PEL_D); |
1169 | t_outb(par, green >> 10, VGA_PEL_D); | |
1170 | t_outb(par, blue >> 10, VGA_PEL_D); | |
1da177e4 | 1171 | |
973d9ab2 AD |
1172 | } else if (regno < 16) { |
1173 | if (bpp == 16) { /* RGB 565 */ | |
1174 | u32 col; | |
1175 | ||
1176 | col = (red & 0xF800) | ((green & 0xFC00) >> 5) | | |
1177 | ((blue & 0xF800) >> 11); | |
1178 | col |= col << 16; | |
1179 | ((u32 *)(info->pseudo_palette))[regno] = col; | |
1180 | } else if (bpp == 32) /* ARGB 8888 */ | |
1181 | ((u32*)info->pseudo_palette)[regno] = | |
245a2c2c KH |
1182 | ((transp & 0xFF00) << 16) | |
1183 | ((red & 0xFF00) << 8) | | |
973d9ab2 | 1184 | ((green & 0xFF00)) | |
245a2c2c | 1185 | ((blue & 0xFF00) >> 8); |
973d9ab2 | 1186 | } |
1da177e4 | 1187 | |
245a2c2c | 1188 | /* debug("exit\n"); */ |
1da177e4 LT |
1189 | return 0; |
1190 | } | |
1191 | ||
1192 | /* Try blanking the screen.For flat panels it does nothing */ | |
1193 | static int tridentfb_blank(int blank_mode, struct fb_info *info) | |
1194 | { | |
245a2c2c | 1195 | unsigned char PMCont, DPMSCont; |
306fa6f6 | 1196 | struct tridentfb_par *par = info->par; |
1da177e4 LT |
1197 | |
1198 | debug("enter\n"); | |
6eed8e1e | 1199 | if (par->flatpanel) |
1da177e4 | 1200 | return 0; |
306fa6f6 KH |
1201 | t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */ |
1202 | PMCont = t_inb(par, 0x83C6) & 0xFC; | |
1203 | DPMSCont = read3CE(par, PowerStatus) & 0xFC; | |
245a2c2c | 1204 | switch (blank_mode) { |
1da177e4 LT |
1205 | case FB_BLANK_UNBLANK: |
1206 | /* Screen: On, HSync: On, VSync: On */ | |
1207 | case FB_BLANK_NORMAL: | |
1208 | /* Screen: Off, HSync: On, VSync: On */ | |
1209 | PMCont |= 0x03; | |
1210 | DPMSCont |= 0x00; | |
1211 | break; | |
1212 | case FB_BLANK_HSYNC_SUSPEND: | |
1213 | /* Screen: Off, HSync: Off, VSync: On */ | |
1214 | PMCont |= 0x02; | |
1215 | DPMSCont |= 0x01; | |
1216 | break; | |
1217 | case FB_BLANK_VSYNC_SUSPEND: | |
1218 | /* Screen: Off, HSync: On, VSync: Off */ | |
1219 | PMCont |= 0x02; | |
1220 | DPMSCont |= 0x02; | |
1221 | break; | |
1222 | case FB_BLANK_POWERDOWN: | |
1223 | /* Screen: Off, HSync: Off, VSync: Off */ | |
1224 | PMCont |= 0x00; | |
1225 | DPMSCont |= 0x03; | |
1226 | break; | |
245a2c2c | 1227 | } |
1da177e4 | 1228 | |
306fa6f6 KH |
1229 | write3CE(par, PowerStatus, DPMSCont); |
1230 | t_outb(par, 4, 0x83C8); | |
1231 | t_outb(par, PMCont, 0x83C6); | |
1da177e4 LT |
1232 | |
1233 | debug("exit\n"); | |
1234 | ||
1235 | /* let fbcon do a softblank for us */ | |
1236 | return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0; | |
1237 | } | |
1238 | ||
245a2c2c KH |
1239 | static struct fb_ops tridentfb_ops = { |
1240 | .owner = THIS_MODULE, | |
1241 | .fb_setcolreg = tridentfb_setcolreg, | |
1242 | .fb_pan_display = tridentfb_pan_display, | |
1243 | .fb_blank = tridentfb_blank, | |
1244 | .fb_check_var = tridentfb_check_var, | |
1245 | .fb_set_par = tridentfb_set_par, | |
1246 | .fb_fillrect = tridentfb_fillrect, | |
1247 | .fb_copyarea = tridentfb_copyarea, | |
1248 | .fb_imageblit = cfb_imageblit, | |
1249 | }; | |
1250 | ||
e09ed099 KH |
1251 | static int __devinit trident_pci_probe(struct pci_dev *dev, |
1252 | const struct pci_device_id *id) | |
1da177e4 LT |
1253 | { |
1254 | int err; | |
1255 | unsigned char revision; | |
e09ed099 KH |
1256 | struct fb_info *info; |
1257 | struct tridentfb_par *default_par; | |
122e8ad3 KH |
1258 | int defaultaccel; |
1259 | int chip3D; | |
1260 | int chip_id; | |
1da177e4 LT |
1261 | |
1262 | err = pci_enable_device(dev); | |
1263 | if (err) | |
1264 | return err; | |
1265 | ||
e09ed099 KH |
1266 | info = framebuffer_alloc(sizeof(struct tridentfb_par), &dev->dev); |
1267 | if (!info) | |
1268 | return -ENOMEM; | |
1269 | default_par = info->par; | |
1270 | ||
1da177e4 LT |
1271 | chip_id = id->device; |
1272 | ||
245a2c2c | 1273 | if (chip_id == CYBERBLADEi1) |
9fa68eae KP |
1274 | output("*** Please do use cyblafb, Cyberblade/i1 support " |
1275 | "will soon be removed from tridentfb!\n"); | |
1276 | ||
1277 | ||
1da177e4 | 1278 | /* If PCI id is 0x9660 then further detect chip type */ |
245a2c2c | 1279 | |
1da177e4 | 1280 | if (chip_id == TGUI9660) { |
10172ed6 | 1281 | revision = vga_io_rseq(RevisionID); |
245a2c2c | 1282 | |
1da177e4 | 1283 | switch (revision) { |
0e73a47f KH |
1284 | case 0x21: |
1285 | chip_id = PROVIDIA9685; | |
1286 | break; | |
245a2c2c KH |
1287 | case 0x22: |
1288 | case 0x23: | |
1289 | chip_id = CYBER9397; | |
1290 | break; | |
1291 | case 0x2A: | |
1292 | chip_id = CYBER9397DVD; | |
1293 | break; | |
1294 | case 0x30: | |
1295 | case 0x33: | |
1296 | case 0x34: | |
1297 | case 0x35: | |
1298 | case 0x38: | |
1299 | case 0x3A: | |
1300 | case 0xB3: | |
1301 | chip_id = CYBER9385; | |
1302 | break; | |
1303 | case 0x40 ... 0x43: | |
1304 | chip_id = CYBER9382; | |
1305 | break; | |
1306 | case 0x4A: | |
1307 | chip_id = CYBER9388; | |
1308 | break; | |
1309 | default: | |
1310 | break; | |
1da177e4 LT |
1311 | } |
1312 | } | |
1313 | ||
1314 | chip3D = is3Dchip(chip_id); | |
1da177e4 LT |
1315 | |
1316 | if (is_xp(chip_id)) { | |
d9cad04b KH |
1317 | default_par->init_accel = xp_init_accel; |
1318 | default_par->wait_engine = xp_wait_engine; | |
1319 | default_par->fill_rect = xp_fill_rect; | |
1320 | default_par->copy_rect = xp_copy_rect; | |
245a2c2c | 1321 | } else if (is_blade(chip_id)) { |
d9cad04b KH |
1322 | default_par->init_accel = blade_init_accel; |
1323 | default_par->wait_engine = blade_wait_engine; | |
1324 | default_par->fill_rect = blade_fill_rect; | |
1325 | default_par->copy_rect = blade_copy_rect; | |
1da177e4 | 1326 | } else { |
d9cad04b KH |
1327 | default_par->init_accel = image_init_accel; |
1328 | default_par->wait_engine = image_wait_engine; | |
1329 | default_par->fill_rect = image_fill_rect; | |
1330 | default_par->copy_rect = image_copy_rect; | |
1da177e4 LT |
1331 | } |
1332 | ||
122e8ad3 KH |
1333 | default_par->chip_id = chip_id; |
1334 | ||
1da177e4 LT |
1335 | /* acceleration is on by default for 3D chips */ |
1336 | defaultaccel = chip3D && !noaccel; | |
1337 | ||
1da177e4 | 1338 | /* setup MMIO region */ |
245a2c2c KH |
1339 | tridentfb_fix.mmio_start = pci_resource_start(dev, 1); |
1340 | tridentfb_fix.mmio_len = chip3D ? 0x20000 : 0x10000; | |
1da177e4 LT |
1341 | |
1342 | if (!request_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len, "tridentfb")) { | |
1343 | debug("request_region failed!\n"); | |
3876ae8b | 1344 | framebuffer_release(info); |
1da177e4 LT |
1345 | return -1; |
1346 | } | |
1347 | ||
e09ed099 KH |
1348 | default_par->io_virt = ioremap_nocache(tridentfb_fix.mmio_start, |
1349 | tridentfb_fix.mmio_len); | |
1da177e4 | 1350 | |
e09ed099 | 1351 | if (!default_par->io_virt) { |
1da177e4 | 1352 | debug("ioremap failed\n"); |
e8ed857c KH |
1353 | err = -1; |
1354 | goto out_unmap1; | |
1da177e4 LT |
1355 | } |
1356 | ||
1da177e4 | 1357 | /* setup framebuffer memory */ |
245a2c2c | 1358 | tridentfb_fix.smem_start = pci_resource_start(dev, 0); |
e09ed099 | 1359 | tridentfb_fix.smem_len = get_memsize(default_par); |
245a2c2c | 1360 | |
1da177e4 LT |
1361 | if (!request_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len, "tridentfb")) { |
1362 | debug("request_mem_region failed!\n"); | |
e09ed099 | 1363 | disable_mmio(info->par); |
a02f6402 | 1364 | err = -1; |
e8ed857c | 1365 | goto out_unmap1; |
1da177e4 LT |
1366 | } |
1367 | ||
3876ae8b KH |
1368 | enable_mmio(); |
1369 | ||
e09ed099 KH |
1370 | info->screen_base = ioremap_nocache(tridentfb_fix.smem_start, |
1371 | tridentfb_fix.smem_len); | |
1da177e4 | 1372 | |
e09ed099 | 1373 | if (!info->screen_base) { |
1da177e4 | 1374 | debug("ioremap failed\n"); |
a02f6402 | 1375 | err = -1; |
e8ed857c | 1376 | goto out_unmap2; |
1da177e4 LT |
1377 | } |
1378 | ||
1379 | output("%s board found\n", pci_name(dev)); | |
6eed8e1e | 1380 | default_par->flatpanel = is_flatpanel(default_par); |
1da177e4 | 1381 | |
6eed8e1e | 1382 | if (default_par->flatpanel) |
e09ed099 | 1383 | nativex = get_nativex(default_par); |
1da177e4 | 1384 | |
e09ed099 KH |
1385 | info->fix = tridentfb_fix; |
1386 | info->fbops = &tridentfb_ops; | |
aa0aa8ab | 1387 | info->pseudo_palette = default_par->pseudo_pal; |
1da177e4 | 1388 | |
e09ed099 | 1389 | info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN; |
1da177e4 | 1390 | #ifdef CONFIG_FB_TRIDENT_ACCEL |
e09ed099 | 1391 | info->flags |= FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT; |
1da177e4 | 1392 | #endif |
ea8ee55c | 1393 | if (!fb_find_mode(&info->var, info, |
07f41e45 | 1394 | mode_option, NULL, 0, NULL, bpp)) { |
a02f6402 | 1395 | err = -EINVAL; |
e8ed857c | 1396 | goto out_unmap2; |
a02f6402 | 1397 | } |
e09ed099 | 1398 | err = fb_alloc_cmap(&info->cmap, 256, 0); |
e8ed857c KH |
1399 | if (err < 0) |
1400 | goto out_unmap2; | |
1401 | ||
d9cad04b | 1402 | if (defaultaccel && default_par->init_accel) |
ea8ee55c | 1403 | info->var.accel_flags |= FB_ACCELF_TEXT; |
1da177e4 | 1404 | else |
ea8ee55c KH |
1405 | info->var.accel_flags &= ~FB_ACCELF_TEXT; |
1406 | info->var.activate |= FB_ACTIVATE_NOW; | |
e09ed099 KH |
1407 | info->device = &dev->dev; |
1408 | if (register_framebuffer(info) < 0) { | |
1da177e4 | 1409 | printk(KERN_ERR "tridentfb: could not register Trident framebuffer\n"); |
e09ed099 | 1410 | fb_dealloc_cmap(&info->cmap); |
a02f6402 | 1411 | err = -EINVAL; |
e8ed857c | 1412 | goto out_unmap2; |
1da177e4 LT |
1413 | } |
1414 | output("fb%d: %s frame buffer device %dx%d-%dbpp\n", | |
ea8ee55c KH |
1415 | info->node, info->fix.id, info->var.xres, |
1416 | info->var.yres, info->var.bits_per_pixel); | |
e09ed099 KH |
1417 | |
1418 | pci_set_drvdata(dev, info); | |
1da177e4 | 1419 | return 0; |
a02f6402 | 1420 | |
e8ed857c | 1421 | out_unmap2: |
e09ed099 KH |
1422 | if (info->screen_base) |
1423 | iounmap(info->screen_base); | |
e8ed857c | 1424 | release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len); |
e09ed099 | 1425 | disable_mmio(info->par); |
e8ed857c | 1426 | out_unmap1: |
e09ed099 KH |
1427 | if (default_par->io_virt) |
1428 | iounmap(default_par->io_virt); | |
e8ed857c | 1429 | release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len); |
e09ed099 | 1430 | framebuffer_release(info); |
a02f6402 | 1431 | return err; |
1da177e4 LT |
1432 | } |
1433 | ||
245a2c2c | 1434 | static void __devexit trident_pci_remove(struct pci_dev *dev) |
1da177e4 | 1435 | { |
e09ed099 KH |
1436 | struct fb_info *info = pci_get_drvdata(dev); |
1437 | struct tridentfb_par *par = info->par; | |
1438 | ||
1439 | unregister_framebuffer(info); | |
1da177e4 | 1440 | iounmap(par->io_virt); |
e09ed099 | 1441 | iounmap(info->screen_base); |
1da177e4 | 1442 | release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len); |
e8ed857c | 1443 | release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len); |
e09ed099 KH |
1444 | pci_set_drvdata(dev, NULL); |
1445 | framebuffer_release(info); | |
1da177e4 LT |
1446 | } |
1447 | ||
1448 | /* List of boards that we are trying to support */ | |
1449 | static struct pci_device_id trident_devices[] = { | |
245a2c2c KH |
1450 | {PCI_VENDOR_ID_TRIDENT, BLADE3D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, |
1451 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1452 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1453 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1454 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1455 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1456 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1457 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
a0d92256 | 1458 | {PCI_VENDOR_ID_TRIDENT, TGUI9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, |
245a2c2c KH |
1459 | {PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, |
1460 | {PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1461 | {PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1462 | {PCI_VENDOR_ID_TRIDENT, CYBER9320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1463 | {PCI_VENDOR_ID_TRIDENT, CYBER9388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1464 | {PCI_VENDOR_ID_TRIDENT, CYBER9520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1465 | {PCI_VENDOR_ID_TRIDENT, CYBER9525DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1466 | {PCI_VENDOR_ID_TRIDENT, CYBER9397, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1467 | {PCI_VENDOR_ID_TRIDENT, CYBER9397DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1468 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1469 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1470 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm16, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1da177e4 | 1471 | {0,} |
245a2c2c KH |
1472 | }; |
1473 | ||
1474 | MODULE_DEVICE_TABLE(pci, trident_devices); | |
1da177e4 LT |
1475 | |
1476 | static struct pci_driver tridentfb_pci_driver = { | |
245a2c2c KH |
1477 | .name = "tridentfb", |
1478 | .id_table = trident_devices, | |
1479 | .probe = trident_pci_probe, | |
1480 | .remove = __devexit_p(trident_pci_remove) | |
1da177e4 LT |
1481 | }; |
1482 | ||
1483 | /* | |
1484 | * Parse user specified options (`video=trident:') | |
1485 | * example: | |
245a2c2c | 1486 | * video=trident:800x600,bpp=16,noaccel |
1da177e4 LT |
1487 | */ |
1488 | #ifndef MODULE | |
07f41e45 | 1489 | static int __init tridentfb_setup(char *options) |
1da177e4 | 1490 | { |
245a2c2c | 1491 | char *opt; |
1da177e4 LT |
1492 | if (!options || !*options) |
1493 | return 0; | |
245a2c2c KH |
1494 | while ((opt = strsep(&options, ",")) != NULL) { |
1495 | if (!*opt) | |
1496 | continue; | |
1497 | if (!strncmp(opt, "noaccel", 7)) | |
1da177e4 | 1498 | noaccel = 1; |
245a2c2c | 1499 | else if (!strncmp(opt, "fp", 2)) |
6eed8e1e | 1500 | fp = 1; |
245a2c2c | 1501 | else if (!strncmp(opt, "crt", 3)) |
6eed8e1e | 1502 | fp = 0; |
245a2c2c KH |
1503 | else if (!strncmp(opt, "bpp=", 4)) |
1504 | bpp = simple_strtoul(opt + 4, NULL, 0); | |
1505 | else if (!strncmp(opt, "center", 6)) | |
1da177e4 | 1506 | center = 1; |
245a2c2c | 1507 | else if (!strncmp(opt, "stretch", 7)) |
1da177e4 | 1508 | stretch = 1; |
245a2c2c KH |
1509 | else if (!strncmp(opt, "memsize=", 8)) |
1510 | memsize = simple_strtoul(opt + 8, NULL, 0); | |
1511 | else if (!strncmp(opt, "memdiff=", 8)) | |
1512 | memdiff = simple_strtoul(opt + 8, NULL, 0); | |
1513 | else if (!strncmp(opt, "nativex=", 8)) | |
1514 | nativex = simple_strtoul(opt + 8, NULL, 0); | |
1da177e4 | 1515 | else |
07f41e45 | 1516 | mode_option = opt; |
1da177e4 LT |
1517 | } |
1518 | return 0; | |
1519 | } | |
1520 | #endif | |
1521 | ||
1522 | static int __init tridentfb_init(void) | |
1523 | { | |
1524 | #ifndef MODULE | |
1525 | char *option = NULL; | |
1526 | ||
1527 | if (fb_get_options("tridentfb", &option)) | |
1528 | return -ENODEV; | |
1529 | tridentfb_setup(option); | |
1530 | #endif | |
1531 | output("Trident framebuffer %s initializing\n", VERSION); | |
1532 | return pci_register_driver(&tridentfb_pci_driver); | |
1533 | } | |
1534 | ||
1535 | static void __exit tridentfb_exit(void) | |
1536 | { | |
1537 | pci_unregister_driver(&tridentfb_pci_driver); | |
1538 | } | |
1539 | ||
1da177e4 LT |
1540 | module_init(tridentfb_init); |
1541 | module_exit(tridentfb_exit); | |
1542 | ||
1543 | MODULE_AUTHOR("Jani Monoses <jani@iv.ro>"); | |
1544 | MODULE_DESCRIPTION("Framebuffer driver for Trident cards"); | |
1545 | MODULE_LICENSE("GPL"); | |
1546 |