[deliverable/linux.git] / drivers / video / via / accel.c

/*
 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.

 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public
 * License as published by the Free Software Foundation;
 * either version 2, or (at your option) any later version.

 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
 * the implied warranty of MERCHANTABILITY or FITNESS FOR
 * A PARTICULAR PURPOSE.See the GNU General Public License
 * for more details.

 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc.,
 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 */
#include "global.h"

/*
 * Figure out an appropriate bytes-per-pixel setting.
 */
static int viafb_set_bpp(void __iomem *engine, u8 bpp)
{
	u32 gemode;

	/* Preserve the reserved bits */
	/* Lowest 2 bits to zero gives us no rotation */
	gemode = readl(engine + VIA_REG_GEMODE) & 0xfffffcfc;
	switch (bpp) {
	case 8:
		gemode |= VIA_GEM_8bpp;
		break;
	case 16:
		gemode |= VIA_GEM_16bpp;
		break;
	case 32:
		gemode |= VIA_GEM_32bpp;
		break;
	default:
		printk(KERN_WARNING "viafb_set_bpp: Unsupported bpp %d\n", bpp);
		return -EINVAL;
	}
	writel(gemode, engine + VIA_REG_GEMODE);
	return 0;
}


static int hw_bitblt_1(void __iomem *engine, u8 op, u32 width, u32 height,
	u8 dst_bpp, u32 dst_addr, u32 dst_pitch, u32 dst_x, u32 dst_y,
	u32 *src_mem, u32 src_addr, u32 src_pitch, u32 src_x, u32 src_y,
	u32 fg_color, u32 bg_color, u8 fill_rop)
{
	u32 ge_cmd = 0, tmp, i;
	int ret;

	if (!op || op > 3) {
		printk(KERN_WARNING "hw_bitblt_1: Invalid operation: %d\n", op);
		return -EINVAL;
	}

	if (op != VIA_BITBLT_FILL && !src_mem && src_addr == dst_addr) {
		if (src_x < dst_x) {
			ge_cmd |= 0x00008000;
			src_x += width - 1;
			dst_x += width - 1;
		}
		if (src_y < dst_y) {
			ge_cmd |= 0x00004000;
			src_y += height - 1;
			dst_y += height - 1;
		}
	}

	if (op == VIA_BITBLT_FILL) {
		switch (fill_rop) {
		case 0x00: /* blackness */
		case 0x5A: /* pattern inversion */
		case 0xF0: /* pattern copy */
		case 0xFF: /* whiteness */
			break;
		default:
			printk(KERN_WARNING "hw_bitblt_1: Invalid fill rop: "
				"%u\n", fill_rop);
			return -EINVAL;
		}
	}

	ret = viafb_set_bpp(engine, dst_bpp);
	if (ret)
		return ret;

	if (op != VIA_BITBLT_FILL) {
		if (src_x & (op == VIA_BITBLT_MONO ? 0xFFFF8000 : 0xFFFFF000)
			|| src_y & 0xFFFFF000) {
			printk(KERN_WARNING "hw_bitblt_1: Unsupported source "
				"x/y %d %d\n", src_x, src_y);
			return -EINVAL;
		}
		tmp = src_x | (src_y << 16);
		writel(tmp, engine + 0x08);
	}

	if (dst_x & 0xFFFFF000 || dst_y & 0xFFFFF000) {
		printk(KERN_WARNING "hw_bitblt_1: Unsupported destination x/y "
			"%d %d\n", dst_x, dst_y);
		return -EINVAL;
	}
	tmp = dst_x | (dst_y << 16);
	writel(tmp, engine + 0x0C);

	if ((width - 1) & 0xFFFFF000 || (height - 1) & 0xFFFFF000) {
		printk(KERN_WARNING "hw_bitblt_1: Unsupported width/height "
			"%d %d\n", width, height);
		return -EINVAL;
	}
	tmp = (width - 1) | ((height - 1) << 16);
	writel(tmp, engine + 0x10);

	if (op != VIA_BITBLT_COLOR)
		writel(fg_color, engine + 0x18);

	if (op == VIA_BITBLT_MONO)
		writel(bg_color, engine + 0x1C);

	if (op != VIA_BITBLT_FILL) {
		tmp = src_mem ? 0 : src_addr;
		if (dst_addr & 0xE0000007) {
			printk(KERN_WARNING "hw_bitblt_1: Unsupported source "
				"address %X\n", tmp);
			return -EINVAL;
		}
		tmp >>= 3;
		writel(tmp, engine + 0x30);
	}

	if (dst_addr & 0xE0000007) {
		printk(KERN_WARNING "hw_bitblt_1: Unsupported destination "
			"address %X\n", dst_addr);
		return -EINVAL;
	}
	tmp = dst_addr >> 3;
	writel(tmp, engine + 0x34);

	if (op == VIA_BITBLT_FILL)
		tmp = 0;
	else
		tmp = src_pitch;
	if (tmp & 0xFFFFC007 || dst_pitch & 0xFFFFC007) {
		printk(KERN_WARNING "hw_bitblt_1: Unsupported pitch %X %X\n",
			tmp, dst_pitch);
		return -EINVAL;
	}
	tmp = VIA_PITCH_ENABLE | (tmp >> 3) | (dst_pitch << (16 - 3));
	writel(tmp, engine + 0x38);

	if (op == VIA_BITBLT_FILL)
		ge_cmd |= fill_rop << 24 | 0x00002000 | 0x00000001;
	else {
		ge_cmd |= 0xCC000000; /* ROP=SRCCOPY */
		if (src_mem)
			ge_cmd |= 0x00000040;
		if (op == VIA_BITBLT_MONO)
			ge_cmd |= 0x00000002 | 0x00000100 | 0x00020000;
		else
			ge_cmd |= 0x00000001;
	}
	writel(ge_cmd, engine);

	if (op == VIA_BITBLT_FILL || !src_mem)
		return 0;

	tmp = (width * height * (op == VIA_BITBLT_MONO ? 1 : (dst_bpp >> 3)) +
		3) >> 2;

	for (i = 0; i < tmp; i++)
		writel(src_mem[i], engine + VIA_MMIO_BLTBASE);

	return 0;
}

static int hw_bitblt_2(void __iomem *engine, u8 op, u32 width, u32 height,
	u8 dst_bpp, u32 dst_addr, u32 dst_pitch, u32 dst_x, u32 dst_y,
	u32 *src_mem, u32 src_addr, u32 src_pitch, u32 src_x, u32 src_y,
	u32 fg_color, u32 bg_color, u8 fill_rop)
{
	u32 ge_cmd = 0, tmp, i;
	int ret;

	if (!op || op > 3) {
		printk(KERN_WARNING "hw_bitblt_2: Invalid operation: %d\n", op);
		return -EINVAL;
	}

	if (op != VIA_BITBLT_FILL && !src_mem && src_addr == dst_addr) {
		if (src_x < dst_x) {
			ge_cmd |= 0x00008000;
			src_x += width - 1;
			dst_x += width - 1;
		}
		if (src_y < dst_y) {
			ge_cmd |= 0x00004000;
			src_y += height - 1;
			dst_y += height - 1;
		}
	}

	if (op == VIA_BITBLT_FILL) {
		switch (fill_rop) {
		case 0x00: /* blackness */
		case 0x5A: /* pattern inversion */
		case 0xF0: /* pattern copy */
		case 0xFF: /* whiteness */
			break;
		default:
			printk(KERN_WARNING "hw_bitblt_2: Invalid fill rop: "
				"%u\n", fill_rop);
			return -EINVAL;
		}
	}

	ret = viafb_set_bpp(engine, dst_bpp);
	if (ret)
		return ret;

	if (op == VIA_BITBLT_FILL)
		tmp = 0;
	else
		tmp = src_pitch;
	if (tmp & 0xFFFFC007 || dst_pitch & 0xFFFFC007) {
		printk(KERN_WARNING "hw_bitblt_2: Unsupported pitch %X %X\n",
			tmp, dst_pitch);
		return -EINVAL;
	}
	tmp = (tmp >> 3) | (dst_pitch << (16 - 3));
	writel(tmp, engine + 0x08);

	if ((width - 1) & 0xFFFFF000 || (height - 1) & 0xFFFFF000) {
		printk(KERN_WARNING "hw_bitblt_2: Unsupported width/height "
			"%d %d\n", width, height);
		return -EINVAL;
	}
	tmp = (width - 1) | ((height - 1) << 16);
	writel(tmp, engine + 0x0C);

	if (dst_x & 0xFFFFF000 || dst_y & 0xFFFFF000) {
		printk(KERN_WARNING "hw_bitblt_2: Unsupported destination x/y "
			"%d %d\n", dst_x, dst_y);
		return -EINVAL;
	}
	tmp = dst_x | (dst_y << 16);
	writel(tmp, engine + 0x10);

	if (dst_addr & 0xE0000007) {
		printk(KERN_WARNING "hw_bitblt_2: Unsupported destination "
			"address %X\n", dst_addr);
		return -EINVAL;
	}
	tmp = dst_addr >> 3;
	writel(tmp, engine + 0x14);

	if (op != VIA_BITBLT_FILL) {
		if (src_x & (op == VIA_BITBLT_MONO ? 0xFFFF8000 : 0xFFFFF000)
			|| src_y & 0xFFFFF000) {
			printk(KERN_WARNING "hw_bitblt_2: Unsupported source "
				"x/y %d %d\n", src_x, src_y);
			return -EINVAL;
		}
		tmp = src_x | (src_y << 16);
		writel(tmp, engine + 0x18);

		tmp = src_mem ? 0 : src_addr;
		if (dst_addr & 0xE0000007) {
			printk(KERN_WARNING "hw_bitblt_2: Unsupported source "
				"address %X\n", tmp);
			return -EINVAL;
		}
		tmp >>= 3;
		writel(tmp, engine + 0x1C);
	}

	if (op != VIA_BITBLT_COLOR)
		writel(fg_color, engine + 0x4C);

	if (op == VIA_BITBLT_MONO)
		writel(bg_color, engine + 0x50);

	if (op == VIA_BITBLT_FILL)
		ge_cmd |= fill_rop << 24 | 0x00002000 | 0x00000001;
	else {
		ge_cmd |= 0xCC000000; /* ROP=SRCCOPY */
		if (src_mem)
			ge_cmd |= 0x00000040;
		if (op == VIA_BITBLT_MONO)
			ge_cmd |= 0x00000002 | 0x00000100 | 0x00020000;
		else
			ge_cmd |= 0x00000001;
	}
	writel(ge_cmd, engine);

	if (op == VIA_BITBLT_FILL || !src_mem)
		return 0;

	tmp = (width * height * (op == VIA_BITBLT_MONO ? 1 : (dst_bpp >> 3)) +
		3) >> 2;

	for (i = 0; i < tmp; i++)
		writel(src_mem[i], engine + VIA_MMIO_BLTBASE);

	return 0;
}

int viafb_init_engine(struct fb_info *info)
{
	struct viafb_par *viapar = info->par;
	void __iomem *engine;
	int highest_reg, i;
	u32 vq_start_addr, vq_end_addr, vq_start_low, vq_end_low, vq_high,
		vq_len, chip_name = viapar->shared->chip_info.gfx_chip_name;

	engine = ioremap_nocache(info->fix.mmio_start, info->fix.mmio_len);
	viapar->shared->engine_mmio = engine;
	if (!engine) {
		printk(KERN_WARNING "viafb_init_accel: ioremap failed, "
			"hardware acceleration disabled\n");
		return -ENOMEM;
	}

	/* Initialize registers to reset the 2D engine */
	switch (viapar->shared->chip_info.twod_engine) {
	case VIA_2D_ENG_M1:
		highest_reg = 0x5c;
		break;
	default:
		highest_reg = 0x40;
		break;
	}
	for (i = 0; i <= highest_reg; i += 4)
		writel(0x0, engine + i);

	switch (chip_name) {
	case UNICHROME_CLE266:
	case UNICHROME_K400:
	case UNICHROME_K800:
	case UNICHROME_PM800:
	case UNICHROME_CN700:
	case UNICHROME_CX700:
	case UNICHROME_CN750:
	case UNICHROME_K8M890:
	case UNICHROME_P4M890:
	case UNICHROME_P4M900:
		viapar->shared->hw_bitblt = hw_bitblt_1;
		break;
	case UNICHROME_VX800:
	case UNICHROME_VX855:
		viapar->shared->hw_bitblt = hw_bitblt_2;
		break;
	default:
		viapar->shared->hw_bitblt = NULL;
	}

	viapar->fbmem_free -= CURSOR_SIZE;
	viapar->shared->cursor_vram_addr = viapar->fbmem_free;
	viapar->fbmem_used += CURSOR_SIZE;

	viapar->fbmem_free -= VQ_SIZE;
	viapar->shared->vq_vram_addr = viapar->fbmem_free;
	viapar->fbmem_used += VQ_SIZE;

	/* Init AGP and VQ regs */
	switch (chip_name) {
	case UNICHROME_K8M890:
	case UNICHROME_P4M900:
	case UNICHROME_VX800:
	case UNICHROME_VX855:
		writel(0x00100000, engine + VIA_REG_CR_TRANSET);
		writel(0x680A0000, engine + VIA_REG_CR_TRANSPACE);
		writel(0x02000000, engine + VIA_REG_CR_TRANSPACE);
		break;

	default:
		writel(0x00100000, engine + VIA_REG_TRANSET);
		writel(0x00000000, engine + VIA_REG_TRANSPACE);
		writel(0x00333004, engine + VIA_REG_TRANSPACE);
		writel(0x60000000, engine + VIA_REG_TRANSPACE);
		writel(0x61000000, engine + VIA_REG_TRANSPACE);
		writel(0x62000000, engine + VIA_REG_TRANSPACE);
		writel(0x63000000, engine + VIA_REG_TRANSPACE);
		writel(0x64000000, engine + VIA_REG_TRANSPACE);
		writel(0x7D000000, engine + VIA_REG_TRANSPACE);

		writel(0xFE020000, engine + VIA_REG_TRANSET);
		writel(0x00000000, engine + VIA_REG_TRANSPACE);
		break;
	}

	/* Enable VQ */
	vq_start_addr = viapar->shared->vq_vram_addr;
	vq_end_addr = viapar->shared->vq_vram_addr + VQ_SIZE - 1;

	vq_start_low = 0x50000000 | (vq_start_addr & 0xFFFFFF);
	vq_end_low = 0x51000000 | (vq_end_addr & 0xFFFFFF);
	vq_high = 0x52000000 | ((vq_start_addr & 0xFF000000) >> 24) |
		((vq_end_addr & 0xFF000000) >> 16);
	vq_len = 0x53000000 | (VQ_SIZE >> 3);

	switch (chip_name) {
	case UNICHROME_K8M890:
	case UNICHROME_P4M900:
	case UNICHROME_VX800:
	case UNICHROME_VX855:
		vq_start_low |= 0x20000000;
		vq_end_low |= 0x20000000;
		vq_high |= 0x20000000;
		vq_len |= 0x20000000;

		writel(0x00100000, engine + VIA_REG_CR_TRANSET);
		writel(vq_high, engine + VIA_REG_CR_TRANSPACE);
		writel(vq_start_low, engine + VIA_REG_CR_TRANSPACE);
		writel(vq_end_low, engine + VIA_REG_CR_TRANSPACE);
		writel(vq_len, engine + VIA_REG_CR_TRANSPACE);
		writel(0x74301001, engine + VIA_REG_CR_TRANSPACE);
		writel(0x00000000, engine + VIA_REG_CR_TRANSPACE);
		break;
	default:
		writel(0x00FE0000, engine + VIA_REG_TRANSET);
		writel(0x080003FE, engine + VIA_REG_TRANSPACE);
		writel(0x0A00027C, engine + VIA_REG_TRANSPACE);
		writel(0x0B000260, engine + VIA_REG_TRANSPACE);
		writel(0x0C000274, engine + VIA_REG_TRANSPACE);
		writel(0x0D000264, engine + VIA_REG_TRANSPACE);
		writel(0x0E000000, engine + VIA_REG_TRANSPACE);
		writel(0x0F000020, engine + VIA_REG_TRANSPACE);
		writel(0x1000027E, engine + VIA_REG_TRANSPACE);
		writel(0x110002FE, engine + VIA_REG_TRANSPACE);
		writel(0x200F0060, engine + VIA_REG_TRANSPACE);

		writel(0x00000006, engine + VIA_REG_TRANSPACE);
		writel(0x40008C0F, engine + VIA_REG_TRANSPACE);
		writel(0x44000000, engine + VIA_REG_TRANSPACE);
		writel(0x45080C04, engine + VIA_REG_TRANSPACE);
		writel(0x46800408, engine + VIA_REG_TRANSPACE);

		writel(vq_high, engine + VIA_REG_TRANSPACE);
		writel(vq_start_low, engine + VIA_REG_TRANSPACE);
		writel(vq_end_low, engine + VIA_REG_TRANSPACE);
		writel(vq_len, engine + VIA_REG_TRANSPACE);
		break;
	}

	/* Set Cursor Image Base Address */
	writel(viapar->shared->cursor_vram_addr, engine + VIA_REG_CURSOR_MODE);
	writel(0x0, engine + VIA_REG_CURSOR_POS);
	writel(0x0, engine + VIA_REG_CURSOR_ORG);
	writel(0x0, engine + VIA_REG_CURSOR_BG);
	writel(0x0, engine + VIA_REG_CURSOR_FG);
	return 0;
}

void viafb_show_hw_cursor(struct fb_info *info, int Status)
{
	struct viafb_par *viapar = info->par;
	u32 temp, iga_path = viapar->iga_path;

	temp = readl(viapar->shared->engine_mmio + VIA_REG_CURSOR_MODE);
	switch (Status) {
	case HW_Cursor_ON:
		temp |= 0x1;
		break;
	case HW_Cursor_OFF:
		temp &= 0xFFFFFFFE;
		break;
	}
	switch (iga_path) {
	case IGA2:
		temp |= 0x80000000;
		break;
	case IGA1:
	default:
		temp &= 0x7FFFFFFF;
	}
	writel(temp, viapar->shared->engine_mmio + VIA_REG_CURSOR_MODE);
}

void viafb_wait_engine_idle(struct fb_info *info)
{
	struct viafb_par *viapar = info->par;
	int loop = 0;
	u32 mask;

	switch (viapar->shared->chip_info.twod_engine) {
	case VIA_2D_ENG_H5:
	case VIA_2D_ENG_M1:
		mask = VIA_CMD_RGTR_BUSY_M1 | VIA_2D_ENG_BUSY_M1 |
			      VIA_3D_ENG_BUSY_M1;
		break;
	default:
		while (!(readl(viapar->shared->engine_mmio + VIA_REG_STATUS) &
				VIA_VR_QUEUE_BUSY) && (loop < MAXLOOP)) {
			loop++;
			cpu_relax();
		}
		mask = VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY | VIA_3D_ENG_BUSY;
		break;
	}

	while ((readl(viapar->shared->engine_mmio + VIA_REG_STATUS) & mask) &&
		    (loop < MAXLOOP)) {
		loop++;
		cpu_relax();
	}

	if (loop >= MAXLOOP)
		printk(KERN_ERR "viafb_wait_engine_idle: not syncing\n");
}
Commit	Line	Data
801b8a8c JC	1	/*
	2	* Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
	3	* Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
	4
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public
	7	* License as published by the Free Software Foundation;
	8	* either version 2, or (at your option) any later version.
	9
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
	12	* the implied warranty of MERCHANTABILITY or FITNESS FOR
	13	* A PARTICULAR PURPOSE.See the GNU General Public License
	14	* for more details.
	15
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc.,
	19	* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	20	*/
	21	#include "global.h"
	22
f1b99aa9 JC	23	/*
	24	* Figure out an appropriate bytes-per-pixel setting.
	25	*/
	26	static int viafb_set_bpp(void __iomem *engine, u8 bpp)
	27	{
	28	u32 gemode;
	29
	30	/* Preserve the reserved bits */
	31	/* Lowest 2 bits to zero gives us no rotation */
	32	gemode = readl(engine + VIA_REG_GEMODE) & 0xfffffcfc;
	33	switch (bpp) {
	34	case 8:
	35	gemode \|= VIA_GEM_8bpp;
	36	break;
	37	case 16:
	38	gemode \|= VIA_GEM_16bpp;
	39	break;
	40	case 32:
	41	gemode \|= VIA_GEM_32bpp;
	42	break;
	43	default:
	44	printk(KERN_WARNING "viafb_set_bpp: Unsupported bpp %d\n", bpp);
	45	return -EINVAL;
	46	}
	47	writel(gemode, engine + VIA_REG_GEMODE);
	48	return 0;
	49	}
	50
	51
c3e25673 FTS	52	static int hw_bitblt_1(void __iomem *engine, u8 op, u32 width, u32 height,
	53	u8 dst_bpp, u32 dst_addr, u32 dst_pitch, u32 dst_x, u32 dst_y,
	54	u32 *src_mem, u32 src_addr, u32 src_pitch, u32 src_x, u32 src_y,
	55	u32 fg_color, u32 bg_color, u8 fill_rop)
801b8a8c	56	{
c3e25673	57	u32 ge_cmd = 0, tmp, i;
f1b99aa9	58	int ret;
c3e25673 FTS	59
	60	if (!op \|\| op > 3) {
	61	printk(KERN_WARNING "hw_bitblt_1: Invalid operation: %d\n", op);
	62	return -EINVAL;
	63	}
	64
	65	if (op != VIA_BITBLT_FILL && !src_mem && src_addr == dst_addr) {
	66	if (src_x < dst_x) {
	67	ge_cmd \|= 0x00008000;
	68	src_x += width - 1;
	69	dst_x += width - 1;
	70	}
	71	if (src_y < dst_y) {
	72	ge_cmd \|= 0x00004000;
	73	src_y += height - 1;
	74	dst_y += height - 1;
	75	}
	76	}
	77
	78	if (op == VIA_BITBLT_FILL) {
	79	switch (fill_rop) {
	80	case 0x00: /* blackness */
	81	case 0x5A: /* pattern inversion */
	82	case 0xF0: /* pattern copy */
	83	case 0xFF: /* whiteness */
	84	break;
	85	default:
	86	printk(KERN_WARNING "hw_bitblt_1: Invalid fill rop: "
	87	"%u\n", fill_rop);
	88	return -EINVAL;
	89	}
	90	}
	91
f1b99aa9 JC	92	ret = viafb_set_bpp(engine, dst_bpp);
	93	if (ret)
	94	return ret;
c3e25673 FTS	95
	96	if (op != VIA_BITBLT_FILL) {
	97	if (src_x & (op == VIA_BITBLT_MONO ? 0xFFFF8000 : 0xFFFFF000)
	98	\|\| src_y & 0xFFFFF000) {
	99	printk(KERN_WARNING "hw_bitblt_1: Unsupported source "
	100	"x/y %d %d\n", src_x, src_y);
	101	return -EINVAL;
	102	}
	103	tmp = src_x \| (src_y << 16);
	104	writel(tmp, engine + 0x08);
	105	}
	106
	107	if (dst_x & 0xFFFFF000 \|\| dst_y & 0xFFFFF000) {
	108	printk(KERN_WARNING "hw_bitblt_1: Unsupported destination x/y "
	109	"%d %d\n", dst_x, dst_y);
	110	return -EINVAL;
	111	}
	112	tmp = dst_x \| (dst_y << 16);
	113	writel(tmp, engine + 0x0C);
	114
	115	if ((width - 1) & 0xFFFFF000 \|\| (height - 1) & 0xFFFFF000) {
	116	printk(KERN_WARNING "hw_bitblt_1: Unsupported width/height "
	117	"%d %d\n", width, height);
	118	return -EINVAL;
	119	}
	120	tmp = (width - 1) \| ((height - 1) << 16);
	121	writel(tmp, engine + 0x10);
	122
	123	if (op != VIA_BITBLT_COLOR)
	124	writel(fg_color, engine + 0x18);
	125
	126	if (op == VIA_BITBLT_MONO)
	127	writel(bg_color, engine + 0x1C);
	128
	129	if (op != VIA_BITBLT_FILL) {
	130	tmp = src_mem ? 0 : src_addr;
	131	if (dst_addr & 0xE0000007) {
	132	printk(KERN_WARNING "hw_bitblt_1: Unsupported source "
	133	"address %X\n", tmp);
	134	return -EINVAL;
	135	}
	136	tmp >>= 3;
	137	writel(tmp, engine + 0x30);
	138	}
	139
	140	if (dst_addr & 0xE0000007) {
	141	printk(KERN_WARNING "hw_bitblt_1: Unsupported destination "
	142	"address %X\n", dst_addr);
	143	return -EINVAL;
	144	}
	145	tmp = dst_addr >> 3;
	146	writel(tmp, engine + 0x34);
	147
	148	if (op == VIA_BITBLT_FILL)
	149	tmp = 0;
	150	else
	151	tmp = src_pitch;
	152	if (tmp & 0xFFFFC007 \|\| dst_pitch & 0xFFFFC007) {
	153	printk(KERN_WARNING "hw_bitblt_1: Unsupported pitch %X %X\n",
	154	tmp, dst_pitch);
	155	return -EINVAL;
	156	}
97922b54	157	tmp = VIA_PITCH_ENABLE \| (tmp >> 3) \| (dst_pitch << (16 - 3));
c3e25673 FTS	158	writel(tmp, engine + 0x38);
	159
	160	if (op == VIA_BITBLT_FILL)
	161	ge_cmd \|= fill_rop << 24 \| 0x00002000 \| 0x00000001;
	162	else {
	163	ge_cmd \|= 0xCC000000; /* ROP=SRCCOPY */
	164	if (src_mem)
	165	ge_cmd \|= 0x00000040;
	166	if (op == VIA_BITBLT_MONO)
	167	ge_cmd \|= 0x00000002 \| 0x00000100 \| 0x00020000;
	168	else
	169	ge_cmd \|= 0x00000001;
	170	}
	171	writel(ge_cmd, engine);
	172
	173	if (op == VIA_BITBLT_FILL \|\| !src_mem)
	174	return 0;
	175
	176	tmp = (width * height * (op == VIA_BITBLT_MONO ? 1 : (dst_bpp >> 3)) +
	177	3) >> 2;
	178
	179	for (i = 0; i < tmp; i++)
	180	writel(src_mem[i], engine + VIA_MMIO_BLTBASE);
	181
	182	return 0;
	183	}
	184
	185	static int hw_bitblt_2(void __iomem *engine, u8 op, u32 width, u32 height,
	186	u8 dst_bpp, u32 dst_addr, u32 dst_pitch, u32 dst_x, u32 dst_y,
	187	u32 *src_mem, u32 src_addr, u32 src_pitch, u32 src_x, u32 src_y,
	188	u32 fg_color, u32 bg_color, u8 fill_rop)
	189	{
	190	u32 ge_cmd = 0, tmp, i;
9ca43cf4	191	int ret;
c3e25673 FTS	192
	193	if (!op \|\| op > 3) {
	194	printk(KERN_WARNING "hw_bitblt_2: Invalid operation: %d\n", op);
	195	return -EINVAL;
	196	}
	197
	198	if (op != VIA_BITBLT_FILL && !src_mem && src_addr == dst_addr) {
	199	if (src_x < dst_x) {
	200	ge_cmd \|= 0x00008000;
	201	src_x += width - 1;
	202	dst_x += width - 1;
	203	}
	204	if (src_y < dst_y) {
	205	ge_cmd \|= 0x00004000;
	206	src_y += height - 1;
	207	dst_y += height - 1;
	208	}
	209	}
	210
	211	if (op == VIA_BITBLT_FILL) {
	212	switch (fill_rop) {
	213	case 0x00: /* blackness */
	214	case 0x5A: /* pattern inversion */
	215	case 0xF0: /* pattern copy */
	216	case 0xFF: /* whiteness */
	217	break;
	218	default:
	219	printk(KERN_WARNING "hw_bitblt_2: Invalid fill rop: "
	220	"%u\n", fill_rop);
	221	return -EINVAL;
	222	}
	223	}
	224
9ca43cf4 JC	225	ret = viafb_set_bpp(engine, dst_bpp);
	226	if (ret)
	227	return ret;
c3e25673 FTS	228
	229	if (op == VIA_BITBLT_FILL)
	230	tmp = 0;
	231	else
	232	tmp = src_pitch;
	233	if (tmp & 0xFFFFC007 \|\| dst_pitch & 0xFFFFC007) {
	234	printk(KERN_WARNING "hw_bitblt_2: Unsupported pitch %X %X\n",
	235	tmp, dst_pitch);
	236	return -EINVAL;
	237	}
	238	tmp = (tmp >> 3) \| (dst_pitch << (16 - 3));
	239	writel(tmp, engine + 0x08);
	240
	241	if ((width - 1) & 0xFFFFF000 \|\| (height - 1) & 0xFFFFF000) {
	242	printk(KERN_WARNING "hw_bitblt_2: Unsupported width/height "
	243	"%d %d\n", width, height);
	244	return -EINVAL;
	245	}
	246	tmp = (width - 1) \| ((height - 1) << 16);
	247	writel(tmp, engine + 0x0C);
	248
	249	if (dst_x & 0xFFFFF000 \|\| dst_y & 0xFFFFF000) {
	250	printk(KERN_WARNING "hw_bitblt_2: Unsupported destination x/y "
	251	"%d %d\n", dst_x, dst_y);
	252	return -EINVAL;
	253	}
	254	tmp = dst_x \| (dst_y << 16);
	255	writel(tmp, engine + 0x10);
	256
	257	if (dst_addr & 0xE0000007) {
	258	printk(KERN_WARNING "hw_bitblt_2: Unsupported destination "
	259	"address %X\n", dst_addr);
	260	return -EINVAL;
	261	}
	262	tmp = dst_addr >> 3;
	263	writel(tmp, engine + 0x14);
	264
	265	if (op != VIA_BITBLT_FILL) {
	266	if (src_x & (op == VIA_BITBLT_MONO ? 0xFFFF8000 : 0xFFFFF000)
	267	\|\| src_y & 0xFFFFF000) {
	268	printk(KERN_WARNING "hw_bitblt_2: Unsupported source "
	269	"x/y %d %d\n", src_x, src_y);
	270	return -EINVAL;
	271	}
	272	tmp = src_x \| (src_y << 16);
	273	writel(tmp, engine + 0x18);
	274
	275	tmp = src_mem ? 0 : src_addr;
	276	if (dst_addr & 0xE0000007) {
	277	printk(KERN_WARNING "hw_bitblt_2: Unsupported source "
	278	"address %X\n", tmp);
	279	return -EINVAL;
	280	}
	281	tmp >>= 3;
	282	writel(tmp, engine + 0x1C);
	283	}
	284
	285	if (op != VIA_BITBLT_COLOR)
	286	writel(fg_color, engine + 0x4C);
	287
	288	if (op == VIA_BITBLT_MONO)
	289	writel(bg_color, engine + 0x50);
	290
	291	if (op == VIA_BITBLT_FILL)
292	ge_cmd \|= fill_rop << 24 \| 0x00002000 \| 0x00000001;
293	else {
294	ge_cmd \|= 0xCC000000; /* ROP=SRCCOPY */
295	if (src_mem)
296	ge_cmd \|= 0x00000040;
297	if (op == VIA_BITBLT_MONO)
298	ge_cmd \|= 0x00000002 \| 0x00000100 \| 0x00020000;
299	else
300	ge_cmd \|= 0x00000001;
301	}
302	writel(ge_cmd, engine);
303
304	if (op == VIA_BITBLT_FILL \|\| !src_mem)
305	return 0;
306
307	tmp = (width * height * (op == VIA_BITBLT_MONO ? 1 : (dst_bpp >> 3)) +
308	3) >> 2;
309
310	for (i = 0; i < tmp; i++)
311	writel(src_mem[i], engine + VIA_MMIO_BLTBASE);
312
313	return 0;
314	}
315
31de59d5	316	int viafb_init_engine(struct fb_info *info)
c3e25673	317	{
31de59d5 FTS	318	struct viafb_par *viapar = info->par;
31de59d5 FTS	319	void __iomem *engine;
13178243	320	int highest_reg, i;
31de59d5 FTS	321	u32 vq_start_addr, vq_end_addr, vq_start_low, vq_end_low, vq_high,
	322	vq_len, chip_name = viapar->shared->chip_info.gfx_chip_name;
	323
	324	engine = ioremap_nocache(info->fix.mmio_start, info->fix.mmio_len);
	325	viapar->shared->engine_mmio = engine;
	326	if (!engine) {
	327	printk(KERN_WARNING "viafb_init_accel: ioremap failed, "
	328	"hardware acceleration disabled\n");
	329	return -ENOMEM;
	330	}
	331
13178243 JC	332	/* Initialize registers to reset the 2D engine */
	333	switch (viapar->shared->chip_info.twod_engine) {
	334	case VIA_2D_ENG_M1:
	335	highest_reg = 0x5c;
	336	break;
	337	default:
	338	highest_reg = 0x40;
	339	break;
	340	}
	341	for (i = 0; i <= highest_reg; i += 4)
	342	writel(0x0, engine + i);
	343
31de59d5	344	switch (chip_name) {
c3e25673 FTS	345	case UNICHROME_CLE266:
	346	case UNICHROME_K400:
	347	case UNICHROME_K800:
	348	case UNICHROME_PM800:
	349	case UNICHROME_CN700:
	350	case UNICHROME_CX700:
	351	case UNICHROME_CN750:
	352	case UNICHROME_K8M890:
	353	case UNICHROME_P4M890:
	354	case UNICHROME_P4M900:
31de59d5	355	viapar->shared->hw_bitblt = hw_bitblt_1;
c3e25673 FTS	356	break;
c3e25673 FTS	357	case UNICHROME_VX800:
3a324569	358	case UNICHROME_VX855:
31de59d5	359	viapar->shared->hw_bitblt = hw_bitblt_2;
c3e25673 FTS	360	break;
c3e25673 FTS	361	default:
31de59d5	362	viapar->shared->hw_bitblt = NULL;
c3e25673 FTS	363	}
c3e25673 FTS	364
31de59d5 FTS	365	viapar->fbmem_free -= CURSOR_SIZE;
	366	viapar->shared->cursor_vram_addr = viapar->fbmem_free;
	367	viapar->fbmem_used += CURSOR_SIZE;
801b8a8c	368
31de59d5 FTS	369	viapar->fbmem_free -= VQ_SIZE;
	370	viapar->shared->vq_vram_addr = viapar->fbmem_free;
	371	viapar->fbmem_used += VQ_SIZE;
801b8a8c	372
801b8a8c	373	/* Init AGP and VQ regs */
31de59d5	374	switch (chip_name) {
801b8a8c JC	375	case UNICHROME_K8M890:
801b8a8c JC	376	case UNICHROME_P4M900:
13178243 JC	377	case UNICHROME_VX800:
13178243 JC	378	case UNICHROME_VX855:
31de59d5 FTS	379	writel(0x00100000, engine + VIA_REG_CR_TRANSET);
	380	writel(0x680A0000, engine + VIA_REG_CR_TRANSPACE);
	381	writel(0x02000000, engine + VIA_REG_CR_TRANSPACE);
801b8a8c JC	382	break;
	383
	384	default:
31de59d5 FTS	385	writel(0x00100000, engine + VIA_REG_TRANSET);
	386	writel(0x00000000, engine + VIA_REG_TRANSPACE);
	387	writel(0x00333004, engine + VIA_REG_TRANSPACE);
	388	writel(0x60000000, engine + VIA_REG_TRANSPACE);
	389	writel(0x61000000, engine + VIA_REG_TRANSPACE);
	390	writel(0x62000000, engine + VIA_REG_TRANSPACE);
	391	writel(0x63000000, engine + VIA_REG_TRANSPACE);
	392	writel(0x64000000, engine + VIA_REG_TRANSPACE);
	393	writel(0x7D000000, engine + VIA_REG_TRANSPACE);
	394
	395	writel(0xFE020000, engine + VIA_REG_TRANSET);
	396	writel(0x00000000, engine + VIA_REG_TRANSPACE);
801b8a8c JC	397	break;
801b8a8c JC	398	}
801b8a8c	399
31de59d5 FTS	400	/* Enable VQ */
	401	vq_start_addr = viapar->shared->vq_vram_addr;
	402	vq_end_addr = viapar->shared->vq_vram_addr + VQ_SIZE - 1;
	403
	404	vq_start_low = 0x50000000 \| (vq_start_addr & 0xFFFFFF);
	405	vq_end_low = 0x51000000 \| (vq_end_addr & 0xFFFFFF);
	406	vq_high = 0x52000000 \| ((vq_start_addr & 0xFF000000) >> 24) \|
	407	((vq_end_addr & 0xFF000000) >> 16);
	408	vq_len = 0x53000000 \| (VQ_SIZE >> 3);
	409
	410	switch (chip_name) {
	411	case UNICHROME_K8M890:
	412	case UNICHROME_P4M900:
13178243 JC	413	case UNICHROME_VX800:
13178243 JC	414	case UNICHROME_VX855:
31de59d5 FTS	415	vq_start_low \|= 0x20000000;
	416	vq_end_low \|= 0x20000000;
	417	vq_high \|= 0x20000000;
	418	vq_len \|= 0x20000000;
	419
	420	writel(0x00100000, engine + VIA_REG_CR_TRANSET);
	421	writel(vq_high, engine + VIA_REG_CR_TRANSPACE);
	422	writel(vq_start_low, engine + VIA_REG_CR_TRANSPACE);
	423	writel(vq_end_low, engine + VIA_REG_CR_TRANSPACE);
	424	writel(vq_len, engine + VIA_REG_CR_TRANSPACE);
	425	writel(0x74301001, engine + VIA_REG_CR_TRANSPACE);
	426	writel(0x00000000, engine + VIA_REG_CR_TRANSPACE);
	427	break;
	428	default:
	429	writel(0x00FE0000, engine + VIA_REG_TRANSET);
	430	writel(0x080003FE, engine + VIA_REG_TRANSPACE);
	431	writel(0x0A00027C, engine + VIA_REG_TRANSPACE);
	432	writel(0x0B000260, engine + VIA_REG_TRANSPACE);
	433	writel(0x0C000274, engine + VIA_REG_TRANSPACE);
	434	writel(0x0D000264, engine + VIA_REG_TRANSPACE);
	435	writel(0x0E000000, engine + VIA_REG_TRANSPACE);
	436	writel(0x0F000020, engine + VIA_REG_TRANSPACE);
	437	writel(0x1000027E, engine + VIA_REG_TRANSPACE);
	438	writel(0x110002FE, engine + VIA_REG_TRANSPACE);
	439	writel(0x200F0060, engine + VIA_REG_TRANSPACE);
	440
	441	writel(0x00000006, engine + VIA_REG_TRANSPACE);
	442	writel(0x40008C0F, engine + VIA_REG_TRANSPACE);
	443	writel(0x44000000, engine + VIA_REG_TRANSPACE);
	444	writel(0x45080C04, engine + VIA_REG_TRANSPACE);
	445	writel(0x46800408, engine + VIA_REG_TRANSPACE);
	446
	447	writel(vq_high, engine + VIA_REG_TRANSPACE);
	448	writel(vq_start_low, engine + VIA_REG_TRANSPACE);
	449	writel(vq_end_low, engine + VIA_REG_TRANSPACE);
	450	writel(vq_len, engine + VIA_REG_TRANSPACE);
	451	break;
801b8a8c	452	}
801b8a8c	453
801b8a8c	454	/* Set Cursor Image Base Address */
31de59d5 FTS	455	writel(viapar->shared->cursor_vram_addr, engine + VIA_REG_CURSOR_MODE);
	456	writel(0x0, engine + VIA_REG_CURSOR_POS);
	457	writel(0x0, engine + VIA_REG_CURSOR_ORG);
	458	writel(0x0, engine + VIA_REG_CURSOR_BG);
	459	writel(0x0, engine + VIA_REG_CURSOR_FG);
	460	return 0;
801b8a8c JC	461	}
	462
	463	void viafb_show_hw_cursor(struct fb_info *info, int Status)
	464	{
31de59d5 FTS	465	struct viafb_par *viapar = info->par;
31de59d5 FTS	466	u32 temp, iga_path = viapar->iga_path;
801b8a8c	467
31de59d5	468	temp = readl(viapar->shared->engine_mmio + VIA_REG_CURSOR_MODE);
801b8a8c JC	469	switch (Status) {
	470	case HW_Cursor_ON:
	471	temp \|= 0x1;
	472	break;
	473	case HW_Cursor_OFF:
	474	temp &= 0xFFFFFFFE;
	475	break;
	476	}
	477	switch (iga_path) {
	478	case IGA2:
	479	temp \|= 0x80000000;
	480	break;
	481	case IGA1:
	482	default:
	483	temp &= 0x7FFFFFFF;
	484	}
31de59d5	485	writel(temp, viapar->shared->engine_mmio + VIA_REG_CURSOR_MODE);
801b8a8c JC	486	}
801b8a8c JC	487
31de59d5	488	void viafb_wait_engine_idle(struct fb_info *info)
801b8a8c	489	{
31de59d5	490	struct viafb_par *viapar = info->par;
801b8a8c	491	int loop = 0;
13178243	492	u32 mask;
801b8a8c	493
13178243 JC	494	switch (viapar->shared->chip_info.twod_engine) {
	495	case VIA_2D_ENG_H5:
	496	case VIA_2D_ENG_M1:
	497	mask = VIA_CMD_RGTR_BUSY_M1 \| VIA_2D_ENG_BUSY_M1 \|
	498	VIA_3D_ENG_BUSY_M1;
	499	break;
	500	default:
	501	while (!(readl(viapar->shared->engine_mmio + VIA_REG_STATUS) &
	502	VIA_VR_QUEUE_BUSY) && (loop < MAXLOOP)) {
	503	loop++;
	504	cpu_relax();
	505	}
	506	mask = VIA_CMD_RGTR_BUSY \| VIA_2D_ENG_BUSY \| VIA_3D_ENG_BUSY;
	507	break;
2bd8c475	508	}
801b8a8c	509
13178243	510	while ((readl(viapar->shared->engine_mmio + VIA_REG_STATUS) & mask) &&
2bd8c475 RK	511	(loop < MAXLOOP)) {
2bd8c475 RK	512	loop++;
801b8a8c	513	cpu_relax();
2bd8c475	514	}
801b8a8c	515
31de59d5 FTS	516	if (loop >= MAXLOOP)
31de59d5 FTS	517	printk(KERN_ERR "viafb_wait_engine_idle: not syncing\n");
801b8a8c	518	}