projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| d61e0bf3 JC |
1 | /* |
| 2 | * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved. | |
| 3 | * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved. | |
| 4 | ||
| 5 | * This program is free software; you can redistribute it and/or | |
| 6 | * modify it under the terms of the GNU General Public | |
| 7 | * License as published by the Free Software Foundation; | |
| 8 | * either version 2, or (at your option) any later version. | |
| 9 | ||
| 10 | * This program is distributed in the hope that it will be useful, | |
| 11 | * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even | |
| 12 | * the implied warranty of MERCHANTABILITY or FITNESS FOR | |
| 13 | * A PARTICULAR PURPOSE.See the GNU General Public License | |
| 14 | * for more details. | |
| 15 | ||
| 16 | * You should have received a copy of the GNU General Public License | |
| 17 | * along with this program; if not, write to the Free Software | |
| 18 | * Foundation, Inc., | |
| 19 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
| 20 | */ | |
| 21 | ||
| 22 | #ifndef __HW_H__ | |
| 23 | #define __HW_H__ | |
| 24 | ||
| 2a918392 FTS |
25 | #include <linux/seq_file.h> |
| 26 | ||
| dd73d686 | 27 | #include "viamode.h" |
| d61e0bf3 | 28 | #include "global.h" |
| 100e74a1 | 29 | #include "via_modesetting.h" |
| c3898748 FTS |
30 | |
| 31 | #define viafb_read_reg(p, i) via_read_reg(p, i) | |
| 32 | #define viafb_write_reg(i, p, d) via_write_reg(p, i, d) | |
| 33 | #define viafb_write_reg_mask(i, p, d, m) via_write_reg_mask(p, i, d, m) | |
| d61e0bf3 | 34 | |
| 18d9dc08 | 35 | /* VIA output devices */ |
| a2aa9f9f FTS |
36 | #define VIA_LDVP0 0x00000001 |
| 37 | #define VIA_LDVP1 0x00000002 | |
| 38 | #define VIA_DVP0 0x00000004 | |
| 18d9dc08 FTS |
39 | #define VIA_CRT 0x00000010 |
| 40 | #define VIA_DVP1 0x00000020 | |
| 41 | #define VIA_LVDS1 0x00000040 | |
| 42 | #define VIA_LVDS2 0x00000080 | |
| 43 | ||
| 6f9422d4 FTS |
44 | /* VIA output device power states */ |
| 45 | #define VIA_STATE_ON 0 | |
| 46 | #define VIA_STATE_STANDBY 1 | |
| 47 | #define VIA_STATE_SUSPEND 2 | |
| 48 | #define VIA_STATE_OFF 3 | |
| 49 | ||
| 7f0e153e FTS |
50 | /* VIA output device sync polarity */ |
| 51 | #define VIA_HSYNC_NEGATIVE 0x01 | |
| 52 | #define VIA_VSYNC_NEGATIVE 0x02 | |
| 53 | ||
| d61e0bf3 JC |
54 | /**********************************************************/ |
| 55 | /* Definition IGA2 Design Method of CRTC Shadow Registers */ | |
| 56 | /**********************************************************/ | |
| 57 | #define IGA2_HOR_TOTAL_SHADOW_FORMULA(x) ((x/8)-5) | |
| 58 | #define IGA2_HOR_BLANK_END_SHADOW_FORMULA(x, y) (((x+y)/8)-1) | |
| 59 | #define IGA2_VER_TOTAL_SHADOW_FORMULA(x) ((x)-2) | |
| 60 | #define IGA2_VER_ADDR_SHADOW_FORMULA(x) ((x)-1) | |
| 61 | #define IGA2_VER_BLANK_START_SHADOW_FORMULA(x) ((x)-1) | |
| 62 | #define IGA2_VER_BLANK_END_SHADOW_FORMULA(x, y) ((x+y)-1) | |
| 63 | #define IGA2_VER_SYNC_START_SHADOW_FORMULA(x) (x) | |
| 64 | #define IGA2_VER_SYNC_END_SHADOW_FORMULA(x, y) (x+y) | |
| 65 | ||
| d61e0bf3 JC |
66 | /* Define Register Number for IGA2 Shadow CRTC Timing */ |
| 67 | ||
| 68 | /* location: {CR6D,0,7},{CR71,3,3} */ | |
| 69 | #define IGA2_SHADOW_HOR_TOTAL_REG_NUM 2 | |
| 70 | /* location: {CR6E,0,7} */ | |
| 71 | #define IGA2_SHADOW_HOR_BLANK_END_REG_NUM 1 | |
| 72 | /* location: {CR6F,0,7},{CR71,0,2} */ | |
| 73 | #define IGA2_SHADOW_VER_TOTAL_REG_NUM 2 | |
| 74 | /* location: {CR70,0,7},{CR71,4,6} */ | |
| 75 | #define IGA2_SHADOW_VER_ADDR_REG_NUM 2 | |
| 76 | /* location: {CR72,0,7},{CR74,4,6} */ | |
| 77 | #define IGA2_SHADOW_VER_BLANK_START_REG_NUM 2 | |
| 78 | /* location: {CR73,0,7},{CR74,0,2} */ | |
| 79 | #define IGA2_SHADOW_VER_BLANK_END_REG_NUM 2 | |
| 80 | /* location: {CR75,0,7},{CR76,4,6} */ | |
| 81 | #define IGA2_SHADOW_VER_SYNC_START_REG_NUM 2 | |
| 82 | /* location: {CR76,0,3} */ | |
| 83 | #define IGA2_SHADOW_VER_SYNC_END_REG_NUM 1 | |
| 84 | ||
| 2d6e8851 | 85 | /* Define Fetch Count Register*/ |
| d61e0bf3 | 86 | |
| d61e0bf3 JC |
87 | /* location: {SR1C,0,7},{SR1D,0,1} */ |
| 88 | #define IGA1_FETCH_COUNT_REG_NUM 2 | |
| 89 | /* 16 bytes alignment. */ | |
| 90 | #define IGA1_FETCH_COUNT_ALIGN_BYTE 16 | |
| 91 | /* x: H resolution, y: color depth */ | |
| 92 | #define IGA1_FETCH_COUNT_PATCH_VALUE 4 | |
| 93 | #define IGA1_FETCH_COUNT_FORMULA(x, y) \ | |
| 94 | (((x*y)/IGA1_FETCH_COUNT_ALIGN_BYTE) + IGA1_FETCH_COUNT_PATCH_VALUE) | |
| 95 | ||
| d61e0bf3 JC |
96 | /* location: {CR65,0,7},{CR67,2,3} */ |
| 97 | #define IGA2_FETCH_COUNT_REG_NUM 2 | |
| 98 | #define IGA2_FETCH_COUNT_ALIGN_BYTE 16 | |
| 99 | #define IGA2_FETCH_COUNT_PATCH_VALUE 0 | |
| 100 | #define IGA2_FETCH_COUNT_FORMULA(x, y) \ | |
| 101 | (((x*y)/IGA2_FETCH_COUNT_ALIGN_BYTE) + IGA2_FETCH_COUNT_PATCH_VALUE) | |
| 102 | ||
| 103 | /* Staring Address*/ | |
| 104 | ||
| 105 | /* location: {CR0C,0,7},{CR0D,0,7},{CR34,0,7},{CR48,0,1} */ | |
| 106 | #define IGA1_STARTING_ADDR_REG_NUM 4 | |
| 107 | /* location: {CR62,1,7},{CR63,0,7},{CR64,0,7} */ | |
| 108 | #define IGA2_STARTING_ADDR_REG_NUM 3 | |
| 109 | ||
| 110 | /* Define Display OFFSET*/ | |
| 111 | /* These value are by HW suggested value*/ | |
| 112 | /* location: {SR17,0,7} */ | |
| 113 | #define K800_IGA1_FIFO_MAX_DEPTH 384 | |
| 114 | /* location: {SR16,0,5},{SR16,7,7} */ | |
| 115 | #define K800_IGA1_FIFO_THRESHOLD 328 | |
| 116 | /* location: {SR18,0,5},{SR18,7,7} */ | |
| 117 | #define K800_IGA1_FIFO_HIGH_THRESHOLD 296 | |
| 118 | /* location: {SR22,0,4}. (128/4) =64, K800 must be set zero, */ | |
| 119 | /* because HW only 5 bits */ | |
| 120 | #define K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 0 | |
| 121 | ||
| 122 | /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ | |
| 123 | #define K800_IGA2_FIFO_MAX_DEPTH 384 | |
| 124 | /* location: {CR68,0,3},{CR95,4,6} */ | |
| 125 | #define K800_IGA2_FIFO_THRESHOLD 328 | |
| 126 | /* location: {CR92,0,3},{CR95,0,2} */ | |
| 127 | #define K800_IGA2_FIFO_HIGH_THRESHOLD 296 | |
| 128 | /* location: {CR94,0,6} */ | |
| 129 | #define K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128 | |
| 130 | ||
| 131 | /* location: {SR17,0,7} */ | |
| 132 | #define P880_IGA1_FIFO_MAX_DEPTH 192 | |
| 133 | /* location: {SR16,0,5},{SR16,7,7} */ | |
| 134 | #define P880_IGA1_FIFO_THRESHOLD 128 | |
| 135 | /* location: {SR18,0,5},{SR18,7,7} */ | |
| 136 | #define P880_IGA1_FIFO_HIGH_THRESHOLD 64 | |
| 137 | /* location: {SR22,0,4}. (128/4) =64, K800 must be set zero, */ | |
| 138 | /* because HW only 5 bits */ | |
| 139 | #define P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 0 | |
| 140 | ||
| 141 | /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ | |
| 142 | #define P880_IGA2_FIFO_MAX_DEPTH 96 | |
| 143 | /* location: {CR68,0,3},{CR95,4,6} */ | |
| 144 | #define P880_IGA2_FIFO_THRESHOLD 64 | |
| 145 | /* location: {CR92,0,3},{CR95,0,2} */ | |
| 146 | #define P880_IGA2_FIFO_HIGH_THRESHOLD 32 | |
| 147 | /* location: {CR94,0,6} */ | |
| 148 | #define P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128 | |
| 149 | ||
| 150 | /* VT3314 chipset*/ | |
| 151 | ||
| 152 | /* location: {SR17,0,7} */ | |
| 153 | #define CN700_IGA1_FIFO_MAX_DEPTH 96 | |
| 154 | /* location: {SR16,0,5},{SR16,7,7} */ | |
| 155 | #define CN700_IGA1_FIFO_THRESHOLD 80 | |
| 156 | /* location: {SR18,0,5},{SR18,7,7} */ | |
| 157 | #define CN700_IGA1_FIFO_HIGH_THRESHOLD 64 | |
| 158 | /* location: {SR22,0,4}. (128/4) =64, P800 must be set zero, | |
| 159 | because HW only 5 bits */ | |
| 160 | #define CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 0 | |
| 161 | /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ | |
| 162 | #define CN700_IGA2_FIFO_MAX_DEPTH 96 | |
| 163 | /* location: {CR68,0,3},{CR95,4,6} */ | |
| 164 | #define CN700_IGA2_FIFO_THRESHOLD 80 | |
| 165 | /* location: {CR92,0,3},{CR95,0,2} */ | |
| 166 | #define CN700_IGA2_FIFO_HIGH_THRESHOLD 32 | |
| 167 | /* location: {CR94,0,6} */ | |
| 168 | #define CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128 | |
| 169 | ||
| 170 | /* For VT3324, these values are suggested by HW */ | |
| 171 | /* location: {SR17,0,7} */ | |
| 172 | #define CX700_IGA1_FIFO_MAX_DEPTH 192 | |
| 173 | /* location: {SR16,0,5},{SR16,7,7} */ | |
| 174 | #define CX700_IGA1_FIFO_THRESHOLD 128 | |
| 175 | /* location: {SR18,0,5},{SR18,7,7} */ | |
| 176 | #define CX700_IGA1_FIFO_HIGH_THRESHOLD 128 | |
| 177 | /* location: {SR22,0,4} */ | |
| 178 | #define CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 124 | |
| 179 | ||
| 180 | /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ | |
| 181 | #define CX700_IGA2_FIFO_MAX_DEPTH 96 | |
| 182 | /* location: {CR68,0,3},{CR95,4,6} */ | |
| 183 | #define CX700_IGA2_FIFO_THRESHOLD 64 | |
| 184 | /* location: {CR92,0,3},{CR95,0,2} */ | |
| 185 | #define CX700_IGA2_FIFO_HIGH_THRESHOLD 32 | |
| 186 | /* location: {CR94,0,6} */ | |
| 187 | #define CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128 | |
| 188 | ||
| 189 | /* VT3336 chipset*/ | |
| 190 | /* location: {SR17,0,7} */ | |
| 191 | #define K8M890_IGA1_FIFO_MAX_DEPTH 360 | |
| 192 | /* location: {SR16,0,5},{SR16,7,7} */ | |
| 193 | #define K8M890_IGA1_FIFO_THRESHOLD 328 | |
| 194 | /* location: {SR18,0,5},{SR18,7,7} */ | |
| 195 | #define K8M890_IGA1_FIFO_HIGH_THRESHOLD 296 | |
| 196 | /* location: {SR22,0,4}. */ | |
| 197 | #define K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 124 | |
| 198 | ||
| 199 | /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ | |
| 200 | #define K8M890_IGA2_FIFO_MAX_DEPTH 360 | |
| 201 | /* location: {CR68,0,3},{CR95,4,6} */ | |
| 202 | #define K8M890_IGA2_FIFO_THRESHOLD 328 | |
| 203 | /* location: {CR92,0,3},{CR95,0,2} */ | |
| 204 | #define K8M890_IGA2_FIFO_HIGH_THRESHOLD 296 | |
| 205 | /* location: {CR94,0,6} */ | |
| 206 | #define K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 124 | |
| 207 | ||
| 208 | /* VT3327 chipset*/ | |
| 209 | /* location: {SR17,0,7} */ | |
| 210 | #define P4M890_IGA1_FIFO_MAX_DEPTH 96 | |
| 211 | /* location: {SR16,0,5},{SR16,7,7} */ | |
| 212 | #define P4M890_IGA1_FIFO_THRESHOLD 76 | |
| 213 | /* location: {SR18,0,5},{SR18,7,7} */ | |
| 214 | #define P4M890_IGA1_FIFO_HIGH_THRESHOLD 64 | |
| 215 | /* location: {SR22,0,4}. (32/4) =8 */ | |
| 216 | #define P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 32 | |
| 217 | /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ | |
| 218 | #define P4M890_IGA2_FIFO_MAX_DEPTH 96 | |
| 219 | /* location: {CR68,0,3},{CR95,4,6} */ | |
| 220 | #define P4M890_IGA2_FIFO_THRESHOLD 76 | |
| 221 | /* location: {CR92,0,3},{CR95,0,2} */ | |
| 222 | #define P4M890_IGA2_FIFO_HIGH_THRESHOLD 64 | |
| 223 | /* location: {CR94,0,6} */ | |
| 224 | #define P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 32 | |
| 225 | ||
| 226 | /* VT3364 chipset*/ | |
| 227 | /* location: {SR17,0,7} */ | |
| 228 | #define P4M900_IGA1_FIFO_MAX_DEPTH 96 | |
| 229 | /* location: {SR16,0,5},{SR16,7,7} */ | |
| 230 | #define P4M900_IGA1_FIFO_THRESHOLD 76 | |
| 231 | /* location: {SR18,0,5},{SR18,7,7} */ | |
| 232 | #define P4M900_IGA1_FIFO_HIGH_THRESHOLD 76 | |
| 233 | /* location: {SR22,0,4}. */ | |
| 234 | #define P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 32 | |
| 235 | /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ | |
| 236 | #define P4M900_IGA2_FIFO_MAX_DEPTH 96 | |
| 237 | /* location: {CR68,0,3},{CR95,4,6} */ | |
| 238 | #define P4M900_IGA2_FIFO_THRESHOLD 76 | |
| 239 | /* location: {CR92,0,3},{CR95,0,2} */ | |
| 240 | #define P4M900_IGA2_FIFO_HIGH_THRESHOLD 76 | |
| 241 | /* location: {CR94,0,6} */ | |
| 242 | #define P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 32 | |
| 243 | ||
| 244 | /* For VT3353, these values are suggested by HW */ | |
| 245 | /* location: {SR17,0,7} */ | |
| 246 | #define VX800_IGA1_FIFO_MAX_DEPTH 192 | |
| 247 | /* location: {SR16,0,5},{SR16,7,7} */ | |
| 248 | #define VX800_IGA1_FIFO_THRESHOLD 152 | |
| 249 | /* location: {SR18,0,5},{SR18,7,7} */ | |
| 250 | #define VX800_IGA1_FIFO_HIGH_THRESHOLD 152 | |
| 251 | /* location: {SR22,0,4} */ | |
| 252 | #define VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 64 | |
| 253 | /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ | |
| 254 | #define VX800_IGA2_FIFO_MAX_DEPTH 96 | |
| 255 | /* location: {CR68,0,3},{CR95,4,6} */ | |
| 256 | #define VX800_IGA2_FIFO_THRESHOLD 64 | |
| 257 | /* location: {CR92,0,3},{CR95,0,2} */ | |
| 258 | #define VX800_IGA2_FIFO_HIGH_THRESHOLD 32 | |
| 259 | /* location: {CR94,0,6} */ | |
| 260 | #define VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128 | |
| 261 | ||
| 0306ab11 HW |
262 | /* For VT3409 */ |
| 263 | #define VX855_IGA1_FIFO_MAX_DEPTH 400 | |
| 264 | #define VX855_IGA1_FIFO_THRESHOLD 320 | |
| 265 | #define VX855_IGA1_FIFO_HIGH_THRESHOLD 320 | |
| 266 | #define VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 160 | |
| 267 | ||
| 268 | #define VX855_IGA2_FIFO_MAX_DEPTH 200 | |
| 269 | #define VX855_IGA2_FIFO_THRESHOLD 160 | |
| 270 | #define VX855_IGA2_FIFO_HIGH_THRESHOLD 160 | |
| 271 | #define VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 320 | |
| 272 | ||
| 51f4332b FTS |
273 | /* For VT3410 */ |
| 274 | #define VX900_IGA1_FIFO_MAX_DEPTH 400 | |
| 275 | #define VX900_IGA1_FIFO_THRESHOLD 320 | |
| 276 | #define VX900_IGA1_FIFO_HIGH_THRESHOLD 320 | |
| 277 | #define VX900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 160 | |
| 278 | ||
| 279 | #define VX900_IGA2_FIFO_MAX_DEPTH 192 | |
| 280 | #define VX900_IGA2_FIFO_THRESHOLD 160 | |
| 281 | #define VX900_IGA2_FIFO_HIGH_THRESHOLD 160 | |
| 282 | #define VX900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 320 | |
| 283 | ||
| d61e0bf3 JC |
284 | #define IGA1_FIFO_DEPTH_SELECT_REG_NUM 1 |
| 285 | #define IGA1_FIFO_THRESHOLD_REG_NUM 2 | |
| 286 | #define IGA1_FIFO_HIGH_THRESHOLD_REG_NUM 2 | |
| 287 | #define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM 1 | |
| 288 | ||
| 289 | #define IGA2_FIFO_DEPTH_SELECT_REG_NUM 3 | |
| 290 | #define IGA2_FIFO_THRESHOLD_REG_NUM 2 | |
| 291 | #define IGA2_FIFO_HIGH_THRESHOLD_REG_NUM 2 | |
| 292 | #define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM 1 | |
| 293 | ||
| 294 | #define IGA1_FIFO_DEPTH_SELECT_FORMULA(x) ((x/2)-1) | |
| 295 | #define IGA1_FIFO_THRESHOLD_FORMULA(x) (x/4) | |
| 296 | #define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x) (x/4) | |
| 297 | #define IGA1_FIFO_HIGH_THRESHOLD_FORMULA(x) (x/4) | |
| 298 | #define IGA2_FIFO_DEPTH_SELECT_FORMULA(x) (((x/2)/4)-1) | |
| 299 | #define IGA2_FIFO_THRESHOLD_FORMULA(x) (x/4) | |
| 300 | #define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x) (x/4) | |
| 301 | #define IGA2_FIFO_HIGH_THRESHOLD_FORMULA(x) (x/4) | |
| 302 | ||
| 303 | /************************************************************************/ | |
| 304 | /* LCD Timing */ | |
| 305 | /************************************************************************/ | |
| 306 | ||
| 307 | /* 500 ms = 500000 us */ | |
| 308 | #define LCD_POWER_SEQ_TD0 500000 | |
| 309 | /* 50 ms = 50000 us */ | |
| 310 | #define LCD_POWER_SEQ_TD1 50000 | |
| 311 | /* 0 us */ | |
| 312 | #define LCD_POWER_SEQ_TD2 0 | |
| 313 | /* 210 ms = 210000 us */ | |
| 314 | #define LCD_POWER_SEQ_TD3 210000 | |
| 315 | /* 2^10 * (1/14.31818M) = 71.475 us (K400.revA) */ | |
| 316 | #define CLE266_POWER_SEQ_UNIT 71 | |
| 317 | /* 2^11 * (1/14.31818M) = 142.95 us (K400.revB) */ | |
| 318 | #define K800_POWER_SEQ_UNIT 142 | |
| 319 | /* 2^13 * (1/14.31818M) = 572.1 us */ | |
| 320 | #define P880_POWER_SEQ_UNIT 572 | |
| 321 | ||
| 322 | #define CLE266_POWER_SEQ_FORMULA(x) ((x)/CLE266_POWER_SEQ_UNIT) | |
| 323 | #define K800_POWER_SEQ_FORMULA(x) ((x)/K800_POWER_SEQ_UNIT) | |
| 324 | #define P880_POWER_SEQ_FORMULA(x) ((x)/P880_POWER_SEQ_UNIT) | |
| 325 | ||
| 326 | /* location: {CR8B,0,7},{CR8F,0,3} */ | |
| 327 | #define LCD_POWER_SEQ_TD0_REG_NUM 2 | |
| 328 | /* location: {CR8C,0,7},{CR8F,4,7} */ | |
| 329 | #define LCD_POWER_SEQ_TD1_REG_NUM 2 | |
| 330 | /* location: {CR8D,0,7},{CR90,0,3} */ | |
| 331 | #define LCD_POWER_SEQ_TD2_REG_NUM 2 | |
| 332 | /* location: {CR8E,0,7},{CR90,4,7} */ | |
| 333 | #define LCD_POWER_SEQ_TD3_REG_NUM 2 | |
| 334 | ||
| 335 | /* LCD Scaling factor*/ | |
| 336 | /* x: indicate setting horizontal size*/ | |
| 337 | /* y: indicate panel horizontal size*/ | |
| 338 | ||
| 339 | /* Horizontal scaling factor 10 bits (2^10) */ | |
| 340 | #define CLE266_LCD_HOR_SCF_FORMULA(x, y) (((x-1)*1024)/(y-1)) | |
| 341 | /* Vertical scaling factor 10 bits (2^10) */ | |
| 342 | #define CLE266_LCD_VER_SCF_FORMULA(x, y) (((x-1)*1024)/(y-1)) | |
| 343 | /* Horizontal scaling factor 10 bits (2^12) */ | |
| 344 | #define K800_LCD_HOR_SCF_FORMULA(x, y) (((x-1)*4096)/(y-1)) | |
| 345 | /* Vertical scaling factor 10 bits (2^11) */ | |
| 346 | #define K800_LCD_VER_SCF_FORMULA(x, y) (((x-1)*2048)/(y-1)) | |
| 347 | ||
| 348 | /* location: {CR9F,0,1},{CR77,0,7},{CR79,4,5} */ | |
| 349 | #define LCD_HOR_SCALING_FACTOR_REG_NUM 3 | |
| 350 | /* location: {CR79,3,3},{CR78,0,7},{CR79,6,7} */ | |
| 351 | #define LCD_VER_SCALING_FACTOR_REG_NUM 3 | |
| 352 | /* location: {CR77,0,7},{CR79,4,5} */ | |
| 353 | #define LCD_HOR_SCALING_FACTOR_REG_NUM_CLE 2 | |
| 354 | /* location: {CR78,0,7},{CR79,6,7} */ | |
| 355 | #define LCD_VER_SCALING_FACTOR_REG_NUM_CLE 2 | |
| 356 | ||
| d61e0bf3 JC |
357 | struct io_register { |
| 358 | u8 io_addr; | |
| 359 | u8 start_bit; | |
| 360 | u8 end_bit; | |
| 361 | }; | |
| 362 | ||
| d61e0bf3 JC |
363 | /***************************************************** |
| 364 | ** Define IGA2 Shadow Display Timing **** | |
| 365 | *****************************************************/ | |
| 366 | ||
| 367 | /* IGA2 Shadow Horizontal Total */ | |
| 368 | struct iga2_shadow_hor_total { | |
| 369 | int reg_num; | |
| 370 | struct io_register reg[IGA2_SHADOW_HOR_TOTAL_REG_NUM]; | |
| 371 | }; | |
| 372 | ||
| 373 | /* IGA2 Shadow Horizontal Blank End */ | |
| 374 | struct iga2_shadow_hor_blank_end { | |
| 375 | int reg_num; | |
| 376 | struct io_register reg[IGA2_SHADOW_HOR_BLANK_END_REG_NUM]; | |
| 377 | }; | |
| 378 | ||
| 379 | /* IGA2 Shadow Vertical Total */ | |
| 380 | struct iga2_shadow_ver_total { | |
| 381 | int reg_num; | |
| 382 | struct io_register reg[IGA2_SHADOW_VER_TOTAL_REG_NUM]; | |
| 383 | }; | |
| 384 | ||
| 385 | /* IGA2 Shadow Vertical Addressable Video */ | |
| 386 | struct iga2_shadow_ver_addr { | |
| 387 | int reg_num; | |
| 388 | struct io_register reg[IGA2_SHADOW_VER_ADDR_REG_NUM]; | |
| 389 | }; | |
| 390 | ||
| 391 | /* IGA2 Shadow Vertical Blank Start */ | |
| 392 | struct iga2_shadow_ver_blank_start { | |
| 393 | int reg_num; | |
| 394 | struct io_register reg[IGA2_SHADOW_VER_BLANK_START_REG_NUM]; | |
| 395 | }; | |
| 396 | ||
| 397 | /* IGA2 Shadow Vertical Blank End */ | |
| 398 | struct iga2_shadow_ver_blank_end { | |
| 399 | int reg_num; | |
| 400 | struct io_register reg[IGA2_SHADOW_VER_BLANK_END_REG_NUM]; | |
| 401 | }; | |
| 402 | ||
| 403 | /* IGA2 Shadow Vertical Sync Start */ | |
| 404 | struct iga2_shadow_ver_sync_start { | |
| 405 | int reg_num; | |
| 406 | struct io_register reg[IGA2_SHADOW_VER_SYNC_START_REG_NUM]; | |
| 407 | }; | |
| 408 | ||
| 409 | /* IGA2 Shadow Vertical Sync End */ | |
| 410 | struct iga2_shadow_ver_sync_end { | |
| 411 | int reg_num; | |
| 412 | struct io_register reg[IGA2_SHADOW_VER_SYNC_END_REG_NUM]; | |
| 413 | }; | |
| 414 | ||
| d61e0bf3 JC |
415 | /* IGA1 Fetch Count Register */ |
| 416 | struct iga1_fetch_count { | |
| 417 | int reg_num; | |
| 418 | struct io_register reg[IGA1_FETCH_COUNT_REG_NUM]; | |
| 419 | }; | |
| 420 | ||
| 421 | /* IGA2 Fetch Count Register */ | |
| 422 | struct iga2_fetch_count { | |
| 423 | int reg_num; | |
| 424 | struct io_register reg[IGA2_FETCH_COUNT_REG_NUM]; | |
| 425 | }; | |
| 426 | ||
| 427 | struct fetch_count { | |
| 428 | struct iga1_fetch_count iga1_fetch_count_reg; | |
| 429 | struct iga2_fetch_count iga2_fetch_count_reg; | |
| 430 | }; | |
| 431 | ||
| 432 | /* Starting Address Register */ | |
| 433 | struct iga1_starting_addr { | |
| 434 | int reg_num; | |
| 435 | struct io_register reg[IGA1_STARTING_ADDR_REG_NUM]; | |
| 436 | }; | |
| 437 | ||
| 438 | struct iga2_starting_addr { | |
| 439 | int reg_num; | |
| 440 | struct io_register reg[IGA2_STARTING_ADDR_REG_NUM]; | |
| 441 | }; | |
| 442 | ||
| 443 | struct starting_addr { | |
| 444 | struct iga1_starting_addr iga1_starting_addr_reg; | |
| 445 | struct iga2_starting_addr iga2_starting_addr_reg; | |
| 446 | }; | |
| 447 | ||
| 448 | /* LCD Power Sequence Timer */ | |
| 449 | struct lcd_pwd_seq_td0 { | |
| 450 | int reg_num; | |
| 451 | struct io_register reg[LCD_POWER_SEQ_TD0_REG_NUM]; | |
| 452 | }; | |
| 453 | ||
| 454 | struct lcd_pwd_seq_td1 { | |
| 455 | int reg_num; | |
| 456 | struct io_register reg[LCD_POWER_SEQ_TD1_REG_NUM]; | |
| 457 | }; | |
| 458 | ||
| 459 | struct lcd_pwd_seq_td2 { | |
| 460 | int reg_num; | |
| 461 | struct io_register reg[LCD_POWER_SEQ_TD2_REG_NUM]; | |
| 462 | }; | |
| 463 | ||
| 464 | struct lcd_pwd_seq_td3 { | |
| 465 | int reg_num; | |
| 466 | struct io_register reg[LCD_POWER_SEQ_TD3_REG_NUM]; | |
| 467 | }; | |
| 468 | ||
| 469 | struct _lcd_pwd_seq_timer { | |
| 470 | struct lcd_pwd_seq_td0 td0; | |
| 471 | struct lcd_pwd_seq_td1 td1; | |
| 472 | struct lcd_pwd_seq_td2 td2; | |
| 473 | struct lcd_pwd_seq_td3 td3; | |
| 474 | }; | |
| 475 | ||
| 476 | /* LCD Scaling Factor */ | |
| 477 | struct _lcd_hor_scaling_factor { | |
| 478 | int reg_num; | |
| 479 | struct io_register reg[LCD_HOR_SCALING_FACTOR_REG_NUM]; | |
| 480 | }; | |
| 481 | ||
| 482 | struct _lcd_ver_scaling_factor { | |
| 483 | int reg_num; | |
| 484 | struct io_register reg[LCD_VER_SCALING_FACTOR_REG_NUM]; | |
| 485 | }; | |
| 486 | ||
| 487 | struct _lcd_scaling_factor { | |
| 488 | struct _lcd_hor_scaling_factor lcd_hor_scaling_factor; | |
| 489 | struct _lcd_ver_scaling_factor lcd_ver_scaling_factor; | |
| 490 | }; | |
| 491 | ||
| eb0536c5 FTS |
492 | struct pll_limit { |
| 493 | u16 multiplier_min; | |
| 494 | u16 multiplier_max; | |
| 1f844350 FTS |
495 | u8 divisor; |
| 496 | u8 rshift; | |
| 497 | }; | |
| 498 | ||
| d61e0bf3 JC |
499 | struct rgbLUT { |
| 500 | u8 red; | |
| 501 | u8 green; | |
| 502 | u8 blue; | |
| 503 | }; | |
| 504 | ||
| 505 | struct lcd_pwd_seq_timer { | |
| 506 | u16 td0; | |
| 507 | u16 td1; | |
| 508 | u16 td2; | |
| 509 | u16 td3; | |
| 510 | }; | |
| 511 | ||
| 512 | /* Display FIFO Relation Registers*/ | |
| 513 | struct iga1_fifo_depth_select { | |
| 514 | int reg_num; | |
| 515 | struct io_register reg[IGA1_FIFO_DEPTH_SELECT_REG_NUM]; | |
| 516 | }; | |
| 517 | ||
| 518 | struct iga1_fifo_threshold_select { | |
| 519 | int reg_num; | |
| 520 | struct io_register reg[IGA1_FIFO_THRESHOLD_REG_NUM]; | |
| 521 | }; | |
| 522 | ||
| 523 | struct iga1_fifo_high_threshold_select { | |
| 524 | int reg_num; | |
| 525 | struct io_register reg[IGA1_FIFO_HIGH_THRESHOLD_REG_NUM]; | |
| 526 | }; | |
| 527 | ||
| 528 | struct iga1_display_queue_expire_num { | |
| 529 | int reg_num; | |
| 530 | struct io_register reg[IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM]; | |
| 531 | }; | |
| 532 | ||
| 533 | struct iga2_fifo_depth_select { | |
| 534 | int reg_num; | |
| 535 | struct io_register reg[IGA2_FIFO_DEPTH_SELECT_REG_NUM]; | |
| 536 | }; | |
| 537 | ||
| 538 | struct iga2_fifo_threshold_select { | |
| 539 | int reg_num; | |
| 540 | struct io_register reg[IGA2_FIFO_THRESHOLD_REG_NUM]; | |
| 541 | }; | |
| 542 | ||
| 543 | struct iga2_fifo_high_threshold_select { | |
| 544 | int reg_num; | |
| 545 | struct io_register reg[IGA2_FIFO_HIGH_THRESHOLD_REG_NUM]; | |
| 546 | }; | |
| 547 | ||
| 548 | struct iga2_display_queue_expire_num { | |
| 549 | int reg_num; | |
| 550 | struct io_register reg[IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM]; | |
| 551 | }; | |
| 552 | ||
| 553 | struct fifo_depth_select { | |
| 554 | struct iga1_fifo_depth_select iga1_fifo_depth_select_reg; | |
| 555 | struct iga2_fifo_depth_select iga2_fifo_depth_select_reg; | |
| 556 | }; | |
| 557 | ||
| 558 | struct fifo_threshold_select { | |
| 559 | struct iga1_fifo_threshold_select iga1_fifo_threshold_select_reg; | |
| 560 | struct iga2_fifo_threshold_select iga2_fifo_threshold_select_reg; | |
| 561 | }; | |
| 562 | ||
| 563 | struct fifo_high_threshold_select { | |
| 564 | struct iga1_fifo_high_threshold_select | |
| 565 | iga1_fifo_high_threshold_select_reg; | |
| 566 | struct iga2_fifo_high_threshold_select | |
| 567 | iga2_fifo_high_threshold_select_reg; | |
| 568 | }; | |
| 569 | ||
| 570 | struct display_queue_expire_num { | |
| 571 | struct iga1_display_queue_expire_num | |
| 572 | iga1_display_queue_expire_num_reg; | |
| 573 | struct iga2_display_queue_expire_num | |
| 574 | iga2_display_queue_expire_num_reg; | |
| 575 | }; | |
| 576 | ||
| d61e0bf3 JC |
577 | struct iga2_shadow_crtc_timing { |
| 578 | struct iga2_shadow_hor_total hor_total_shadow; | |
| 579 | struct iga2_shadow_hor_blank_end hor_blank_end_shadow; | |
| 580 | struct iga2_shadow_ver_total ver_total_shadow; | |
| 581 | struct iga2_shadow_ver_addr ver_addr_shadow; | |
| 582 | struct iga2_shadow_ver_blank_start ver_blank_start_shadow; | |
| 583 | struct iga2_shadow_ver_blank_end ver_blank_end_shadow; | |
| 584 | struct iga2_shadow_ver_sync_start ver_sync_start_shadow; | |
| 585 | struct iga2_shadow_ver_sync_end ver_sync_end_shadow; | |
| 586 | }; | |
| 587 | ||
| d61e0bf3 | 588 | /* device ID */ |
| b72a5070 HW |
589 | #define CLE266_FUNCTION3 0x3123 |
| 590 | #define KM400_FUNCTION3 0x3205 | |
| d61e0bf3 JC |
591 | #define CN400_FUNCTION2 0x2259 |
| 592 | #define CN400_FUNCTION3 0x3259 | |
| 593 | /* support VT3314 chipset */ | |
| 594 | #define CN700_FUNCTION2 0x2314 | |
| 595 | #define CN700_FUNCTION3 0x3208 | |
| 596 | /* VT3324 chipset */ | |
| 597 | #define CX700_FUNCTION2 0x2324 | |
| 598 | #define CX700_FUNCTION3 0x3324 | |
| 599 | /* VT3204 chipset*/ | |
| 600 | #define KM800_FUNCTION3 0x3204 | |
| 601 | /* VT3336 chipset*/ | |
| 602 | #define KM890_FUNCTION3 0x3336 | |
| 603 | /* VT3327 chipset*/ | |
| 604 | #define P4M890_FUNCTION3 0x3327 | |
| 605 | /* VT3293 chipset*/ | |
| 606 | #define CN750_FUNCTION3 0x3208 | |
| 607 | /* VT3364 chipset*/ | |
| 608 | #define P4M900_FUNCTION3 0x3364 | |
| 609 | /* VT3353 chipset*/ | |
| 610 | #define VX800_FUNCTION3 0x3353 | |
| 0306ab11 HW |
611 | /* VT3409 chipset*/ |
| 612 | #define VX855_FUNCTION3 0x3409 | |
| 51f4332b FTS |
613 | /* VT3410 chipset*/ |
| 614 | #define VX900_FUNCTION3 0x3410 | |
| d61e0bf3 | 615 | |
| d61e0bf3 JC |
616 | struct IODATA { |
| 617 | u8 Index; | |
| 618 | u8 Mask; | |
| 619 | u8 Data; | |
| 620 | }; | |
| 621 | ||
| 622 | struct pci_device_id_info { | |
| 623 | u32 vendor; | |
| 624 | u32 device; | |
| 625 | u32 chip_index; | |
| 626 | }; | |
| 627 | ||
| 2a918392 FTS |
628 | struct via_device_mapping { |
| 629 | u32 device; | |
| 630 | const char *name; | |
| 631 | }; | |
| 632 | ||
| d61e0bf3 JC |
633 | extern int viafb_SAMM_ON; |
| 634 | extern int viafb_dual_fb; | |
| 635 | extern int viafb_LCD2_ON; | |
| 636 | extern int viafb_LCD_ON; | |
| 637 | extern int viafb_DVI_ON; | |
| d61e0bf3 JC |
638 | extern int viafb_hotplug; |
| 639 | ||
| 9864ca20 FTS |
640 | struct display_timing var_to_timing(const struct fb_var_screeninfo *var, |
| 641 | u16 cxres, u16 cyres); | |
| 532f9169 FTS |
642 | void viafb_fill_crtc_timing(const struct fb_var_screeninfo *var, |
| 643 | u16 cxres, u16 cyres, int iga); | |
| d61e0bf3 JC |
644 | void viafb_set_vclock(u32 CLK, int set_iga); |
| 645 | void viafb_load_reg(int timing_value, int viafb_load_reg_num, | |
| 646 | struct io_register *reg, | |
| 647 | int io_type); | |
| 2a918392 | 648 | void via_set_source(u32 devices, u8 iga); |
| 6f9422d4 | 649 | void via_set_state(u32 devices, u8 state); |
| 7f0e153e | 650 | void via_set_sync_polarity(u32 devices, u8 polarity); |
| 2a918392 FTS |
651 | u32 via_parse_odev(char *input, char **end); |
| 652 | void via_odev_to_seq(struct seq_file *m, u32 odev); | |
| d61e0bf3 JC |
653 | void init_ad9389(void); |
| 654 | /* Access I/O Function */ | |
| d61e0bf3 JC |
655 | void viafb_lock_crt(void); |
| 656 | void viafb_unlock_crt(void); | |
| d61e0bf3 JC |
657 | void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga); |
| 658 | void viafb_write_regx(struct io_reg RegTable[], int ItemNum); | |
| d61e0bf3 | 659 | void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active); |
| d61e0bf3 JC |
660 | void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\ |
| 661 | *p_gfx_dpa_setting); | |
| 662 | ||
| 91dc1be8 | 663 | int viafb_setmode(void); |
| 94715ba9 | 664 | void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, |
| 9864ca20 | 665 | const struct fb_videomode *mode); |
| f4ab2f7a FTS |
666 | void __devinit viafb_init_chip_info(int chip_type); |
| 667 | void __devinit viafb_init_dac(int set_iga); | |
| d61e0bf3 | 668 | int viafb_get_refresh(int hres, int vres, u32 float_refresh); |
| 726abbc7 | 669 | void viafb_update_device_setting(int hres, int vres, int bpp, int flag); |
| d61e0bf3 JC |
670 | |
| 671 | void viafb_set_iga_path(void); | |
| 415559fb FTS |
672 | void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue); |
| 673 | void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue); | |
| d61e0bf3 JC |
674 | void viafb_get_fb_info(unsigned int *fb_base, unsigned int *fb_len); |
| 675 | ||
| 676 | #endif /* __HW_H__ */ |